In-package antenna module

Abstract

An antenna-in-package (AiP) module according to one embodiment of the present invention includes a substrate, a first chip group embedded in the substrate, a second chip group disposed on the substrate, and a radiation unit electrically connected to the second chip group, in which the radiation unit is shaped as a cover covering the substrate.

Description

Technical Field

[0001] The present invention relates to an antenna-in-package (AiP) module, and more particularly, to an AiP module in which one of two chipsets is embedded and includes a covered antenna. Background Art

[0002] To improve the efficiency of electric vehicles, a battery management system (BMS) is installed on each battery pack to efficiently manage the electric vehicle battery.

[0003] A wireless battery management system (BMS) is being used to perform communication between BMSs using wireless communication instead of using existing wire harnesses to perform communication between BMSs. To perform wireless communication, an antenna must be installed on the wireless BMS. However, there is a problem in that the size of the BMS module increases according to the installation of the antenna.

[0004] There is a need to develop a module that can reduce the size of the wireless BMS module. Summary of the Invention

[0005] Technical Problem

[0006] The technical problem to be solved by the present invention is to provide an AiP module and a battery management system including the AiP module, the AiP module including a covered antenna in which one of two chipsets is embedded.

[0007] Technical Solution

[0008] To solve the above technical problem, an antenna-in-package (AiP) module according to an embodiment of the present invention includes: a substrate; a first chipset embedded in the substrate; a second chipset disposed on the substrate; and a radiating unit (emitting unit) electrically connected to the second chipset, wherein the radiating unit is formed to cover the substrate.

[0009] In addition, the radiating unit may include a radiating pattern (emitting pattern) formed to be spaced apart from the substrate.

[0010] In addition, the radiating unit may include at least one support to connect the radiating pattern and the substrate.

[0011] In addition, the first chipset includes a battery management IC (BMIC), and the second chipset may include a wireless communication chip.

[0012] In addition, the first chipset may be formed in a wafer shape.

[0013] In addition, at least a part of the first chipset and the second chipset may overlap each other in the vertical direction of the substrate.

[0014] In addition, a shielding layer may be included and disposed in the substrate region where the first chipset and the second chipset overlap each other.

[0015] In addition, vias may be included to electrically connect the second chipset and the ground layer of the substrate.

[0016] In addition, the substrate may include a shielding wall that extends in the vertical direction along the outer periphery of the first chipset.

[0017] To solve the above technical problems, a battery management system according to an embodiment of the present invention includes: a battery pack including battery cells; a first module mounted on the battery pack to control the operation of the battery cells and communicate with a battery control unit; and a battery control unit that controls the battery cells through communication with the first module, wherein the first module includes any one of the above AiP modules.

[0018] In addition, the battery pack includes a housing in which a space for embedding the battery cells is formed, and the first module may be disposed on a side surface portion of the housing.

[0019] In addition, the battery pack includes a plurality of battery groups, and at least two adjacent battery groups among the plurality of battery groups may be arranged such that their upper surfaces and lower surfaces face each other.

[0020] In addition, the plurality of battery groups may be stacked or arranged while being vertically erected with one side surface of the housing as the bottom surface.

[0021] Advantageous Effects

[0022] According to an embodiment of the present invention, compared with the existing antenna module, miniaturization can be achieved. In addition, the material cost can be reduced by using a wafer-type BMIC, and since the antenna using a shielding cover does not require a metal cutting area, the space can be utilized without additional space on the upper part of the substrate. In addition, when coupled to the battery pack, the space can be reduced, and a stacked structure of the battery pack can be achieved through the arrangement of the side surface portion. Description of the Drawings

[0023] Figure 1 An AiP module according to an embodiment of the present invention is shown.

[0024] Figure 2 The upper surface and the lower surface of an AiP module according to an embodiment of the present invention are shown.

[0025] Figure 3 An AiP module according to a comparative example of the present invention is shown.

[0026] Figure 4 Shows an AiP module according to an embodiment of the present invention.

[0027] Figure 5 Briefly shows a battery management system applying an AiP module according to an embodiment of the present invention.

[0028] Figure 6 Shows a battery management system according to a comparative example of the present invention.

[0029] Figure 7 and Figure 8 Shows a battery management system according to an embodiment of the present invention. Detailed Description

[0030] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0031] However, the technical idea of the present invention is not limited to some embodiments to be described, but can be implemented in various forms, and within the scope of the technical idea of the present invention, one or more of the constituent elements can be selectively combined or replaced between embodiments.

[0032] In addition, unless clearly defined and described, the terms (including technical terms and scientific terms) used in the embodiments of the present invention can be interpreted as the meanings that those skilled in the art can generally understand, and common terms can be interpreted in consideration of the meaning of the context of the related technology, such as the terms defined in a dictionary.

[0033] In addition, the terms used in this specification are for describing embodiments and are not intended to limit the present invention. In this specification, unless otherwise specified in a phrase, the singular form may include the plural form, and when described as "at least one (or more than one) of A, B, and C", it may include one or more combinations of all combinable ones of A, B, and C.

[0034] In addition, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used.

[0035] These terms are only intended to distinguish components from other components, and these terms do not limit the nature, order, or sequence of the components.

[0036] And when a component is described as "connected", "coupled", or "interconnected" to another component, the component not only directly connects, couples, or interconnects to the other component, but may also include the case of being "connected", "coupled", or "interconnected" due to the presence of another component between the other components.

[0037] In addition, when described as “formed on” or “disposed on” the “upper (above)” or “lower (below)” of each component, the “upper (above)” or “lower (below)” includes not only the case where two components are in direct contact, but also the case where one or more other components are formed or disposed between the two components. In addition, the expressions “upper (above)” or “lower (below)” not only refer to the upward direction relative to a certain component, but may also include the meaning of the downward direction.

[0038] A modified embodiment according to the present embodiment may simultaneously include some components of each embodiment and some components of other embodiments. That is to say, the modified embodiment may include one embodiment among various embodiments, but some components may be omitted, and some components of the corresponding other embodiments may be included. Or, vice versa. The features, structures, effects, etc. described in the embodiments are included in at least one embodiment, rather than being limited to one embodiment. In addition, the features, structures, effects, etc. illustrated in each embodiment can be combined, modified, and implemented by those of ordinary skill in the art to which the embodiments belong in other embodiments. Therefore, the content related to such combination and modification should be interpreted as being included within the scope of the embodiments.

[0039] Figure 1 An AiP module according to an embodiment of the present invention is shown; Figure 2 The upper surface and the lower surface of an AiP module according to an embodiment of the present invention are shown; Figure 3 An AiP module according to a comparative example of the present invention is shown; Figure 4 An AiP module according to an embodiment of the present invention is shown; Figure 5 A battery management system applying an AiP module according to an embodiment of the present invention is briefly shown; Figure 6 A battery management system according to a comparative example of the present invention is shown; Figure 7 and Figure 8 A battery management system according to an embodiment of the present invention is shown.

[0040] The AiP module 100 according to an embodiment of the present invention is configured with a substrate 110, a first chipset 120, a second chipset 130, and a radiation unit 140, and may include a shielding layer 171, a shielding wall 172, and a via 173.

[0041] The substrate 110 may be a planar printed circuit board. The substrate 110 may include multiple layers. The multiple layers may be laminated to form one substrate.

[0042] The first chipset 120 is embedded within the substrate 110. The first chipset 120 is embedded by being built into a space within the substrate 110. A cavity space is formed within the substrate 110 in which the first chipset 120 can be disposed, and the first chipset 120 can be embedded by being disposed within the cavity space. The substrate 110 is configured with multiple layers, and the cavity space can be formed within some of the multiple layers. The first chipset 120 can be embedded by being formed in a wafer shape. Here, a wafer refers to a circular plate configured with semiconductor integrated circuits.

[0043] The first chipset 120 is disposed within a space inside the substrate and can be electrically connected to the substrate 110 from above. The first chipset 120 can be electrically connected by contacting the upper part of the cavity space (i.e., the substrate 110). The first chipset 120 can be electrically connected to the substrate 110 in a ball grid array (BGA), pin grid array (PGA), or land grid array (LGA) manner. Additionally, it can be fixed within the cavity space by including one or more support structures supported within the cavity space.

[0044] The second chipset 130 is disposed on the substrate 110. The second chipset 130 can be disposed on the upper surface of the substrate 110 rather than inside the substrate 110. The second chipset 130 can be electrically connected to the substrate 110 by soldering. The second chipset 130 can be electrically connected to the substrate 110 in a ball grid array (BGA), pin grid array (PGA), or land grid array (LGA) manner.

[0045] The first chipset 120 can include a battery management IC (BMIC), and the second chipset 130 can include a wireless communication chip. The first chipset 120 can include a battery management chip that manages the battery performance of the batteries in a battery pack, such as the state of health (SOH) and state of charge (SOC). Battery management can be performed on one battery cell or multiple battery cells. For example, management can be performed on 16 series-connected battery cells.

[0046] The second chipset 130 includes a wireless communication chip, so the first chipset 120 can perform wireless communication to send and receive data with another battery management system or the external world. Here, the second chipset 130 can include an RF communication chip. The second chipset 130 can be a 2.4 GHz radio frequency chip or a 5 GHz radio frequency chip. The second chipset 130 can include a wireless communication chip that performs various wireless communications such as Bluetooth, Bluetooth Low Energy (BLE), and Wi-Fi.

[0047] The radiation unit 140 is electrically connected to the second chipset 130. The radiation unit 140 is electrically connected to the second chipset 130 and radiates (emits) the signal transmitted from the second chipset 130. The radiation unit 140 is formed in a cover shape covering the substrate 110. The radiation unit 140 is formed as a cover antenna and can radiate signals without requiring a separate space in the substrate 110. The radiation unit 140 functions as a shielding cover while radiating signals. For this purpose, the radiation unit 140 can be formed of metal. By being formed of metal, it can protect the first chipset 120 and the components on the substrate 110 and at the same time radiate signals. The second chipset 130 can be a 2.4 GHz radio frequency chip, and the radiation unit 140 can be a 2.4 GHz radio frequency antenna.

[0048] The radiation unit 140 is formed in a form covering the upper surface of the substrate 110 by being spaced apart from the upper surface of the substrate 110 by a predetermined distance so as to be formed in a cover shape. The radiation unit 140 can include a feeding section for receiving signals from the substrate 110 and a grounding section connected to the ground of the substrate 110 to radiate signals. A current is applied through the feeding section to input a signal, the current is output to the grounding section, and the signal is radiated through the radiation unit 140 forming a radiation pattern.

[0049] As Figure 2 shown, the radiation pattern of the radiation unit 140 can be formed in a pattern such as a meandering shape, or some areas are empty. The resonant frequency can vary according to the radiation pattern. The radiation unit 140 can include one or more supports welded to the substrate 110 to support the radiation unit 140 so as to maintain the shape of the cover. One of the supports is electrically connected to the first chipset 120, and the other support can be welded and connected to the substrate 110 and can be formed to be insulated rather than connected to a grounding member or other configurations.

[0050] As Figure 2 shown, a grounding portion can be formed on the lower surface of the substrate 110. The radiation unit 140 is connected to the outer periphery of the substrate 110 in the form of a cover and can be connected to the outer peripheral ground pattern 152 on the lower surface, and the embedded second chipset 130 can be connected to the internal ground pattern 151.

[0051] The radiation unit 140 is formed in the form of a cover for the substrate 110 so that it can simultaneously perform the functions of a cover for the substrate 110 and radiation. Thus, a separate radiation structure for signal radiation is not required, which is beneficial for miniaturization.

[0052] As Figure 3As shown, when forming a radiation element of the patterned antenna 14 on the substrate 11, it is necessary to cut and remove the metal of the substrate 11, such as copper, and other components cannot be arranged in the corresponding area, so there are limitations in space utilization. In addition, when forming the radiation element, there are space limitations, that is, other components cannot be arranged at a certain interval to avoid affecting radiation. However, by implementing the radiation element in the form of a cover of the substrate 110, space limitations can be reduced, and the degree of freedom in design can be increased.

[0053] As Figure 3 shown, when the first chipset 12, the second chipset 13, and the radiation element 14 are all formed on the substrate 11, the substrate size increases, and it becomes difficult to utilize the space where the radiation element 1 is formed. For miniaturization, the first chipset 120 can be embedded inside the substrate 110, and the second chipset 130 can be arranged on the upper part of the substrate to reduce the size of the substrate 110. The first chipset 120 and the second chipset 130 can at least partially overlap in the vertical direction of the substrate 110. The first chipset 120 and the second chipset 130 can overlap with each other while being aligned in the vertical direction of the substrate 110, and can be arranged to at least partially overlap with each other to reduce the size of the substrate 110. Areas where a large amount of frequency interference occurs can also be arranged not to overlap with each other.

[0054] At this time, the shielding units 171 and 172 shield the first chipset 120. The first chipset 120 is embedded in the substrate 110, and the second chipset 130 is arranged on the substrate 110, so they can affect each other. When the first chipset 120 and the second chipset 130 operate simultaneously, it may be difficult to ensure performance due to noise and frequency interference. The shielding unit shields the first chipset 120 to reduce the noise and frequency interference between the first chipset 120 and the second chipset 130, thereby ensuring performance.

[0055] The shielding unit may include a shielding layer 171, which is arranged in the substrate area where the first chipset 120 and the second chipset 130 overlap each other, and is located between the first chipset 120 and the second chipset 130. The first chipset 120 and the second chipset 130 overlap each other, the substrate 110 is inserted therebetween, and the first chipset 120 and the second chipset 130 face each other. Therefore, frequency interference may occur at the position where they overlap and face each other. To prevent this, a shielding layer 171 can be included, which is arranged in the substrate area where the first chipset 120 and the second chipset 130 overlap each other. The shielding layer 171 can be laminated in a flat shape on the upper part of the substrate 110. Or, it can be laminated inside the substrate 110. At this time, one of the multiple layers forming the substrate 110 can be formed as the shielding layer 171. The shielding layer 171 includes a non-magnetic material and may include an insulating layer.

[0056] The shielding unit may include a ground layer 150 laminated to the lower portion of the substrate 110. By including the ground layer 150 in the lower portion of the substrate 110, a ground layer for shielding can be formed. The ground layer 150 may form a ground connection (GND). The ground layer 150 may be laminated to the lower portion of the substrate 110 in a planar shape. Alternatively, it may be laminated inside the substrate 110. At this time, one of the multiple layers forming the substrate 110 is formed as the ground layer 150.

[0057] Herein, a via 173 may be included to electrically connect the shielding layer 171 and the ground layer 150 of the substrate. The via 173 may electrically connect the shielding layer 171 and the ground layer 150 by penetrating the substrate 110. The first chipset 120 or the second chipset 130 may be electrically connected to the ground layer 150 through the shielding layer 171 and the via 173.

[0058] Compared with the case of not including a shielding layer, in the case of including the shielding layer 171, the ground layer 150, and the via 173 connecting the shielding layer 171 and the ground layer 150, the shielding performance can exhibit a shielding performance of -17 dB and a surface current (S-current) performance of -40 A / m 2 of.

[0059] The shielding unit may include a shielding wall 172 that extends in the vertical direction of the substrate 110 along the outer periphery of the first chipset 120. As Figure 4 shown, the shielding wall 172 may extend in the vertical direction of the substrate 110 to divide the substrate 110 into an inner region and an outer region of the shielding wall 172. The shielding wall 172 may be formed along the outer peripheral shape of the first chipset 122 to shield the first chipset 120. The shielding wall 172 may be formed by cutting and removing a part of the substrate 110. The shielding wall 172 may be formed by cutting and removing the inside of the substrate (i.e., the metal part of each layer). Each layer of the substrate 110 may be coated with a metal (such as copper), and the coated metal may be removed at a predetermined gap to form the shielding wall 172. At this time, the thickness of the shielding wall 172 may be 0.1 mm.

[0060] By forming the shielding layer 171 that shields the first chipset 120 from top to bottom and the shielding wall 172 that shields the first chipset 120 from left to right, the noise and frequency interference between the first chipset 120 and the second chipset 130 can be minimized.

[0061] The shielding wall 172 can be arranged to be separated from the outer periphery of the first chipset 120, and the via 173 can be arranged between the first chipset 120 and the shielding wall 172. Even if the shielding layer 171 is formed, frequency interference will occur at the position of the via 173. Therefore, the via 173 can be arranged between the first chipset 120 and the shielding wall 172 such that the shielding wall 172 is arranged outside the via 173.

[0062] The shielding wall 172 can extend from the upper part of the substrate 110 to the upper part of the ground layer 150, and the ground layer 150 is laminated to the lower part of the substrate. The shielding wall 172 can extend to the shielding layer 171 such that the shielding layer 171 can also be divided into an inner region and an outer region of the shielding wall 172. Alternatively, the shielding layer 171 can be formed only in the inner region of the shielding wall 172.

[0063] The shielding performance of the communication module including the shielding layer 171, the ground layer 150, the via 173 connecting the shielding layer 171 and the ground layer 150, and the shielding wall 172 can exhibit a shielding performance of -27 dB and a surface current (S-current) performance of -50 A / m 2 in the near field.

[0064] In the upper part of the substrate 110, the peripheral components 161 and 162 of the chipset can be arranged in the area where the second chipset 130 is not arranged. These components include at least one of the active component 161 or the passive component 162, and some of these components can be embedded inside the substrate 110. The component 161 can be arranged along the shielding wall 172 in the outer region of the substrate 110. Thus, the influence on the first chipset 120 can be minimized.

[0065] The shielding wall 172 extends from the upper part of the substrate 110 to the ground layer 150 and divides the shielding layer 171 or the upper part of the substrate 110 into an inner region and an outer region. That is, the inner region and the outer region are separated in the upper part of the substrate 110, making it difficult to send and receive signals with other components 180 or externally. The via 173 can be formed to provide a bypass path for sending and receiving signals, including vias in the inner region of the shielding wall and vias in the outer region of the shielding wall. The first chipset 120 or the second chipset 130 is electrically connected to one of the multiple layers of the shielding layer 171 or the substrate 110 and is electrically connected to the ground layer 150 through a via in the inner region of the shielding wall, electrically connected to a via in the outer region of the shielding wall through the ground layer 150, and electrically connected to the component 161 or externally, thereby sending and receiving signals.

[0066] Thus, the space for the two chipsets can be effectively ensured, and the shielding performance can be enhanced by forming the shielding layer and the shielding wall, which shield the chipset embedded inside the substrate.

[0067] The AiP module 100 according to an embodiment of the present invention can be applied to the battery pack 410 of a battery management system as Figure 5 shown. Each battery pack 410 includes a BMIC for a wireless BMS and a 2.4GHz RF integrated embedded AiP module, so that wireless communication can be performed between BMS modules. The battery management system can be configured with an array of battery packs, a battery junction box (BJB) 420, and a battery control unit (BCU) 430. The BJB 420 and the BCU 430 can send and receive data through high-speed communication interfaces 421 and 431 and low-speed communication interfaces 422 and 432. Each BMIC and the 2.4GHz RF integrated embedded AiP module 410 for the wireless BMS can perform wireless communication through 2.4GHz RF communication.

[0068] A battery management system according to an embodiment of the present invention may include an AiP module to perform wireless communication between BMSs. The detailed description of the AiP module for a wireless BMS for a vehicle corresponds to Figures 1 to 5 the detailed description of the AiP module, and thus any repeated description will be omitted below.

[0069] A battery management system according to an embodiment of the present invention includes a battery pack 200, an AiP module 100, and a battery control unit 430. The battery pack 200 includes at least one battery cell, and the AiP module 100 is mounted on the battery pack 200 to control the operation of the battery cell and communicate with the battery control unit 430. The battery control unit 430 controls the battery cell through communication with the AiP module 100.

[0070] Here, the battery pack 200 includes a housing in which a space for embedding the battery cell is formed, and the AiP module 100 can be disposed on a side surface portion of the housing.

[0071] As Figure 3 implemented, the AiP module 10 is difficult to be mounted on the side surface of the battery pack and can be mounted on a wider first surface of the battery pack 20, as Figure 6 shown. Since the radiation unit 14 cannot be arranged to overlap with another battery pack for wireless communication, multiple battery packs can only be arranged in a planar form, as Figure 6 shown.

[0072] The AiP module 100 according to an embodiment of the present invention can be miniaturized and thus can be disposed on the side surface of the battery pack 200.

[0073] The battery pack 200 includes a plurality of battery packs, and at least two adjacent battery packs among the plurality of battery packs may be arranged such that their upper surfaces and lower surfaces face each other. In addition, the plurality of battery packs may be stacked or arranged while being vertically erected with one side surface of the housing as the bottom surface.

[0074] That is to say, as Figure 7 shown, by arranging the AiP module 100 on the side surface of the battery pack 200, the battery pack can be arranged while being vertically erected, or as Figure 8 shown, a stacked structure in which a plurality of battery packs are stacked can be arranged. In particular, when a plurality of battery packs are used for high-capacity batteries, various arrangements can be achieved, thereby increasing the degree of freedom in design and effectively utilizing space.

[0075] An AiP module includes a substrate, a first chipset embedded in the substrate, a second chipset arranged on the substrate, and a radiation unit electrically connected to the second chipset, wherein the radiation unit is formed in the form of a cover covering the substrate. In addition, the radiation unit may include a radiation pattern formed at a distance from the substrate, the radiation unit may include at least one or more supports connecting the radiation pattern and the substrate, the first chipset may include a battery management IC (BMIC), the second chipset may include a wireless communication chip, the first chipset may be formed in a wafer shape, the first chipset and the second chipset may at least partially overlap each other in the up-down direction of the substrate, a shielding layer is arranged in the substrate area where the first chipset and the second chipset overlap each other, may include vias connecting the second chipset and the ground layer of the substrate, and may include a shielding wall extending in the up-down direction of the substrate along the outer periphery of the first chipset.

[0076] Accordingly: miniaturization can be achieved compared with the existing antenna module; using a wafer-type BMIC can reduce the material cost; the antenna using the shielding cover can eliminate the need for a metal cutting area, thereby allowing the utilization of space without additional space at the top of the substrate; the space can be reduced when coupled with the battery pack; and a stacked structure of the battery pack can be achieved through the arrangement of the side surface portion.

[0077] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not limited to one embodiment. In addition, the features, structures, effects, etc. shown in each embodiment can be combined, modified, and implemented by those of ordinary skill in the art to which the embodiments belong in other embodiments. Therefore, the content related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0078] Those skilled in the art related to this embodiment will understand that the above description can be implemented in a modified form without departing from its basic features. Therefore, the disclosed method should be considered from an illustrative rather than a restrictive perspective. The scope of the present invention is indicated by the claims rather than the above description, and all differences within the scope equivalent thereto should be construed as being included in the present invention.

Claims

1. An AiP module, comprising: A substrate; A first chipset, embedded in the substrate; A second chipset, disposed on the substrate; And A radiation unit, electrically connected to the second chipset, wherein the radiation unit is shaped as a cover covering the substrate.

2. The AiP module according to claim 1, Among them, The radiation unit includes a radiation pattern formed at a distance from the substrate.

3. The AiP module according to claim 2, comprising: At least one support member for connecting the radiation pattern and the substrate.

4. The AiP module according to claim 1, Among them, The first chipset includes a battery management chip, and wherein the second chipset includes a wireless communication chip.

5. The AiP module according to claim 1, Among them, The first chipset is formed in a wafer shape.

6. The AiP module according to claim 1, Among them, At least a part of the first chipset and the second chipset overlap each other in the up and down direction of the substrate.

7. The AiP module according to claim 6, comprising: A shielding layer, disposed in the substrate area where the first chipset and the second chipset overlap each other.

8. The AiP module according to claim 7, comprising: A via for electrically connecting the second chipset and the ground layer of the substrate.

9. The AiP module according to claim 1, comprising: A shielding wall, extending in the up and down direction of the substrate along the outer periphery of the first chipset.

10. A battery management system, comprising: A battery pack, including battery cells; A first module, mounted on the battery pack to control the operation of the battery cells and communicate with a battery control unit; And A battery control unit, controlling the battery cells through communication with the first module, wherein the first module includes the AiP module according to any one of claims 1 to 9.

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