Gate driven charge pump circuit for dynamic bias control

Abstract

In an example, a system (400) includes a charge pump (142A). The system (400) includes a transistor (108A) coupled to a power supply terminal (134), the transistor (108A) gate coupled to a charge pump (142A) output. The system (400) includes current sense circuitry having a power input, a load input, and a sense output (410), where the power input is coupled to the power terminal (134), the current sense circuitry configured to provide a sense signal at the sense output (410), and the sense signal being representative of a polarity and magnitude of current at the load input. The system (400) includes a controller (148) having a sensing input (412) coupled to the sensing output (410) and a control output (414) coupled to a control input, where the controller (148) is configured to provide a control signal at the control output (414) in response to the sensing signal, and the charge pump (142A) is configured to adjust a voltage at an output of the charge pump (142A) in response to the control signal.

Description

Background Art

[0001] Batteries can power electronic circuits in various applications. A battery pack can include multiple batteries and a battery management system for controlling charging, discharging, and monitoring of the batteries. The performance and safety of the batteries can be monitored, for example, by monitoring voltage, current, temperature, cooling, history, the health of battery cells, the state of balance of battery cells, etc. Summary of the Invention

[0002] In at least one example of the present specification, a system includes a charge pump having a control input and a charge pump output. The system includes a transistor serially coupled to a power supply terminal, the transistor having a gate coupled to the charge pump output. The system further includes a current sensing circuitry having a power input, a load input, and a sense output, wherein the power input is coupled to the power supply terminal, the current sensing circuitry is configured to provide a sense signal at the sense output, and the sense signal represents the polarity and magnitude of the current at the load input. The system includes a controller having a sense input and a control output, wherein the sense input is coupled to the sense output, the control output is coupled to the control input, and the controller is configured to provide a control signal at the control output in response to the sense signal, and the charge pump is configured to adjust the voltage at the charge pump output in response to the control signal.

[0003] In at least one example of the present specification, a method includes measuring, by a control circuit, a load current of a transistor coupled to a power supply, wherein a gate of the transistor is coupled to a charge pump. The method further includes reducing, by the control circuit, an output voltage of the charge pump in response to a negative-polarity load current and the load current being below a threshold. The method includes increasing, by the control circuit, the output voltage of the charge pump in response to a negative-polarity load current and the load current being above a threshold. The method includes increasing, by the control circuit, the output voltage of the charge pump in response to a positive-polarity load current.

[0004] In at least one example of the present specification, a system includes a first charge pump having a first charge pump output coupled to the gate of a first n-channel transistor. The system further includes a second charge pump having a second charge pump output coupled to the gate of a second n-channel transistor, the second n-channel transistor being coupled in series with the first n-channel transistor. The system includes a power supply coupled to the first n-channel transistor and the second n-channel transistor. The system further includes current sensing circuitry configured to provide a sense signal representative of the polarity and magnitude of the current passing through the first n-channel transistor and the second n-channel transistor. The system includes a controller configured to provide a control signal in response to the sense signal, wherein the control signal is provided to the first charge pump and the second charge pump, and wherein the first charge pump and the second charge pump are configured to adjust the voltages at the first charge pump output and the second charge pump output, respectively, in response to the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of a system for dynamically controlling a gate drive charge pump circuit in various examples.

[0006] Figure 2 is a graph showing example transistor on-state resistance and gate leakage in various examples.

[0007] Figure 3 is a graph of charge pump output voltage versus time in various examples.

[0008] Figure 4 is a block diagram of a system for dynamically controlling a gate drive charge pump circuit in various examples.

[0009] Figure 5 is a flowchart of a method for dynamically controlling a gate drive charge pump circuit in various examples.

[0010] Figure 6 is a flowchart of a method for dynamically controlling a gate drive charge pump circuit in various examples.

[0011] Like reference numerals or other reference indicators are used in the drawings to denote (functionally and / or structurally) identical or similar features. DETAILED DESCRIPTION

[0012] The battery pack may include one or more batteries and an electronic device for monitoring and controlling the batteries. The electronic device for monitoring and controlling the batteries may be embodied in one or more integrated circuits (ICs) within a chip. The chip may drive two high-side external transistors, which may be N-channel field effect transistors (NFETs) in an example. One NFET charges the battery, and the other NFET discharges the battery. The protector IC may indirectly monitor the current carried by the NFETs using series sense resistors. The series sense resistors monitor the current, and if the charging current or charging voltage is too high, the charging NFET turns off. If the discharge current is too high (e.g., in the case of a short circuit), the discharge NFET turns off. If the battery is significantly discharged and the battery voltage is low, the discharge NFET turns off.

[0013] The charge pump circuit may provide a voltage higher than the supply voltage to turn on the NFETs. For each NFET, the voltage sensing regulation system monitors the gate-to-source voltage (V GS ) of the NFET to regulate the charge pump output voltage to a specific level. The V GS may be regulated by turning the clock source of the charge pump on and off. If V GS reaches the appropriate level, the clock source is turned off to temporarily turn off the charge pump. When the charge pump loses charge (via gate-to-source leakage of the NFETs, V GS safety resistors, leakage in the IC, etc.), the charge pump is turned back on. This type of regulation is referred to as hysteresis control or skip mode control.

[0014] If the device using the battery pack is in use, the NFETs can operate more efficiently at a higher charge pump voltage. When the charge pump voltage increases, the efficiency increases because the drain-to-source resistance of the NFETs decreases. However, if the device is not in use, the increased charge pump voltage causes an increased gate leakage current in the NFETs. In the examples herein, multiple operating modes of the charge pump are implemented. The current passing through the NFETs or through the sense resistors is measured, and the charge pump is placed in different modes in response to the current measurement. If the battery pack is being charged, the charge pump voltage is set to a high voltage. If the battery pack is discharging and the current is high, the device is in operation, and the charge pump voltage is set to a high voltage to increase the efficiency of the NFETs. If the battery pack is discharging and the current is low, the device is in standby or idle state, and the charge pump voltage is decreased to reduce the leakage current. In other examples, more than two charge pump voltage levels may be implemented and selected based on the current measurement.

[0015] Figure 1FIG. 0 is a block diagram of a system 100 for dynamically controlling a gate drive charge pump circuit in various examples herein. System 100 includes a main protector IC 102, a secondary protector IC 104, battery cells 106A, 106B, 106C (collectively battery cells 106), and NFETs 108A and 108B (collectively NFET 108). System 100 also includes a sense resistor 110, a resistor 112, ground (or common node) 114, a fuse 116, and a transistor 118. The main protector IC 102 includes a charge pin 120 (CHG), a discharge pin 122 (DSG), a temperature sensor (TS) pin 124, a sense resistor positive (SRP) pin 126, a sense resistor negative (SRN) pin 128, a serial data (SDA) pin 130, and a serial clock (SCL) pin 132. System 100 includes a node 134 where the battery cells 106 provide a CELL+ voltage and a node 136 where the battery cells 106 provide a CELL− voltage. System 100 also includes a PACK+ pin 138 and a PACK− pin 140.

[0016] The main protector IC 102 also includes a charge pump 142, a voltage sensing circuit 144, a clock 146, a controller 148, and an analog-to-digital converter (ADC) 150. The main protector IC 102 drives the NFETs 108A and 108B which, in this example, are high-side external FETs. In other examples, the NFET 108 can be internal to the IC. In this example, NFET 108A is a charge FET and NFET 108B is a discharge FET. NFET 108A charges the battery cells 106 and NFET 108B controls the discharge current of the battery cells 106. The main protector IC 102 controls the NFET 108 via signals from the charge pin 120 and the discharge pin 122.

[0017] In one example, the main protector IC 102 also monitors the voltage and / or current through the NFET 108 using the sense resistor 110. The main protector IC 102 uses the SRP pin 126 and the SRN pin 128 to monitor the current. If the current is higher than a threshold, the voltage across the NFET 108 is too high and the main protector IC 102 disconnects the charge NFET 108A via a signal from the charge pin 120. If the main protector IC 102 detects excessive discharge current (e.g., a short circuit situation), it disconnects the discharge NFET 108B via a signal from the discharge pin 122. And, if the battery is substantially discharged and the voltage is below a threshold, the discharge NFET 108B is disconnected.

[0018] The TS pin 124 can be a thermistor that monitors the temperature of the battery cell 106 in one example. If the battery cell 106 is too hot, the charging NFET 108A can be disconnected to protect the battery cell 106. Alternatively, the discharging NFET 108B can be disconnected to prevent the hot battery from operating. The secondary protector IC 104 monitors overcharging of the battery cell 106 and manages the fuse 116. The primary protector IC 102 can disconnect the NFET 108 in response to the battery voltage. If the NFET 108 is damaged, the primary protector IC 102 may not be able to prevent overcharging. The fuse 116 provides backup protection. The voltage threshold monitored by the primary protector IC 102 can be lower than the voltage threshold monitored by the secondary protector IC 104. If the primary protector IC 102 is unable to reduce the voltage by disconnecting the NFET 108, the secondary protector IC 104 can blow the fuse 116. In some examples, blowing the fuse 116 permanently deactivates the system 100.

[0019] In the examples herein, the primary protector IC 102 includes two charge pumps 142 that independently drive each of the NFETs 108. For the two NFETs 108, the voltage sensing circuit 144 monitors the gate-to-source voltage V across each NFET 108 GS to regulate the output voltage of each of the charge pumps 142. V can be regulated by turning the clock 146 on and off, GS which is the clock source for the charge pumps 142. If V GS reaches a predetermined level, the clock 146 can be turned off to temporarily disconnect the charge pumps 142. When the charge pumps 142 lose charge (via gate-to-source leakage of the NFETs 108, V GS safety resistor, leakage in the IC, etc.), the charge pumps 142 can be turned on by turning the clock 146 back on. The ADC 150 performs current sensing to determine which state to place the charge pumps 142 in. The controller 148 activates the charge pumps 142 and the clock 146 in response to the current sensing signal from the ADC 150.

[0020] As described herein, the system 100 dynamically adjusts the gate drive of the NFETs 108 in response to current sensing monitoring performed by the primary protector IC 102. As described above, multiple operating modes of the charge pumps 142 are implemented. If the battery cell 106 is charging, the charge pump 142 voltage is set to a high voltage. If the battery cell 106 is discharging and the current is high, the system 100 is in operation, and the charge pump 142 voltage is set to a high voltage to improve the efficiency of the NFETs 108. If the battery cell 106 is discharging and the current is low, the system 100 is in standby or idle state, and the charge pump 142 voltage is reduced to reduce leakage current. Below regardingFigure 4 Provide additional description of the operation of the circuitry within system 100.

[0021] Figure 2 Include graphs of the on-state resistance and gate leakage of the example NFETs in the various examples herein. In one example, graphs 200 and 250 can be graphs of NFET 108. Other FETs can be useful in other examples and can have on-state resistances and / or gate leakages different from those of graphs 200 and 250.

[0022] In one example, graph 200 is a graph of the source-to-source on-state resistance (in mΩ) of NFET 108 on the y-axis and the gate-to-source voltage V GS (in volts (V)) on the x-axis. NFET 108 can be produced and sold as a package, so the source-to-source on-state resistance is shown in graph 200. Graph 200 includes waveforms 202, 204, and 206. Waveform 202 shows the on-state resistance versus V GS at a temperature of 85°C. GS Waveform 204 shows the on-state resistance versus V GS at a temperature of 25°C. GS Waveform 206 shows the on-state resistance versus V GS at a temperature of -40°C. GS Graph 200 shows that as V GS increases on the x-axis, the on-state resistance decreases. This indicates that as V GS increases, NFET 108 becomes more efficient. However, this comes at the cost of the charge pump turning on more frequently and increasing the leakage current, as described below.

[0023] As an example, two positions are marked on waveform 202. Position 208 indicates that at 85°C and a V GS of 5 V, the on-state resistance is approximately 3.5 mΩ. Position 210 indicates that at 85°C and a V GS of 10 V, the on-state resistance is approximately 2.7 mΩ. As described above, the resistance decreases as V GS increases.

[0024] Graph 250 is a graph of the gate-to-source leakage current in amperes (A) on the x-axis and V GS (in V) on the y-axis. Graph 250 includes waveforms 252, 254, and 256. Waveform 252 shows the leakage current versus V GS at a temperature of 85°C. GS Waveform 254 shows the leakage current versus V GS at a temperature of 25°C. GS Waveform 256 shows the leakage current versus V GS at a temperature of -40°C. GSAs it increases on the x-axis, the leakage current also increases.

[0025] As an example, two positions are marked on waveform 252. Position 258 indicates that at 85 °C and a V of 5V, the leakage current is approximately 30 nanoamperes (nA). Position 260 indicates that at 85 °C and a V of 10V, the leakage current is approximately 150 nA. In this example, the change in V from 5V to 10V may have a five-fold impact on the magnitude of the leakage current. The gate leakage current shown in graph 250 can be one of the contributing factors to the maximum current consumption of system 100. Therefore, increasing V has both advantages (lower on-state resistance) and disadvantages (higher leakage current). GS GS GS GS

[0026] In the examples herein, as described above, multiple operating modes of charge pump 142 are implemented. In one example, if both charge pumps 142 are turned on, system 100 may consume 100 microamperes at a V of 10V. At a V of 5V, the current can be reduced to 20 microamperes. If system 100 is discharging a large amount of current (e.g., the load is being actively driven by system 100, such as powering a device), the battery cell 106 may only provide a runtime of 15 to 30 minutes. An example device with this type of runtime could be a power tool, such as an electric trimmer. During the runtime, the leakage current of charge pump 142 (e.g., graph 250) is mostly irrelevant to the operation of the device. In fact, the maximum efficiency of the device is more relevant (graph 200), and a higher V provides higher efficiency. Alternatively, if the device is not in use (e.g., a device that may not be used for days or weeks), the leakage current becomes more important because when the device is idle, a high leakage current can deplete battery cell 106. Therefore, the device has two different use cases. When system 100 is driving a load (e.g., the device is in use), high efficiency is important, which is achieved using a higher V. When the device is idle, a lower leakage current is important for conserving the charge in battery cell 106. As described herein, the current passing through NFET 108 or through sense resistor 110 is measured, and in response to the current measurement, charge pump 142 is placed in different modes (e.g., a V of 5V or 10V). GS GS GS GS GS

[0027] Figure 3 ​​​​​​​​​It is the graph 300 of the charge pump output voltage versus time in various examples in this article. The graph 300 shows the hysteresis control or skip mode control of the charge pump 142 as described above. The x-axis is the output voltage of the charge pump 142 in volts, and the y-axis is time.

[0028] The graph 300 includes two waveforms 302 and 304. The waveform 302 represents that the output voltage of the charge pump 142 is 10 V, with a 10-μA load and a 1-fold output voltage rise rate. In this example, the charge pump 142 has a duty cycle of approximately 20%. As shown in the waveform 302, the charge pump 142 is turned on as needed to generate a series of rising edges, and then the voltage slowly decreases over time before the next rising edge. This creates a slight ripple in the waveform 302. The ripple does not affect the output of the battery cell 106 or the system 100.

[0029] The waveform 304 represents that the output voltage of the charge pump 142 is 5 V, with a 5-μA load and a 2-fold rise rate. In this example, the waveform 304 has a duty cycle of approximately 5%. Similar to the waveform 302, the charge pump 142 is turned on as needed to generate a series of rising edges, and then the voltage slowly decreases over time before the next rising edge.

[0030] In the example of the waveform 302, the charge pump 142 is turned on more frequently than in the example of the waveform 304. The 20% duty cycle of the waveform 302 is higher than the 5% duty cycle of the waveform 304. Therefore, more power is saved in the waveform 304 example compared to the waveform 302 example. Thus, more power is saved if the output voltage of the charge pump 142 is 5 V compared to 10 V. As described above, if the system 100 is idle, the output voltage of the charge pump 142 can be reduced (e.g., from 10 V to 5 V) to reduce power consumption. The graph 300 shows an example of how to achieve a reduction in power consumption.

[0031] Figure 4 It is the block diagram of the system 400 for dynamically controlling the gate drive charge pump circuit in various examples in this article. The system 400 includes many components described above regarding Figure 1 the system 100 in, and the same numbers indicate the same components. The system 400 includes the main protector IC 102, the battery cell 106 (shown as one battery in this example), NFETs 108A and 108B, and the sense resistor 110. For simplicity, the secondary protector IC 104 is not shown in the figure. The system 400 includes nodes 134, 136, the PACK+ pin 138, and the PACK- pin 140. The system 400 also includes V GS safety resistors 402A and 402B (collectively referred to as V GS safety resistors 402). V GSThe safety resistor 402 is optional and may not be present in other instances.

[0032] The main protector IC 102 includes a charging pin 120, a discharging pin 122, charge pumps 142A and 142B, a voltage sensing circuit 144, a clock 146, a controller 148, and an ADC 150. In some instances, the ADC 150 may be replaced by a voltage comparator. The main protector IC 102 also includes a ground domain translation 404, which may not be present in other instances. The ground domain translation 404 provides an internal ground or a common potential rail for internal components of the main protector IC 102 (such as the charge pumps 142). The main protector IC 102 presents two current sensing options: a FET current sensing option 406 and a resistor current sensing option 408. In the examples herein, either current sensing option may be useful. In some instances, only one of the current sensing options 406 or 408 may be present. If the resistor current sensing option 408 is not present in some instances, the sense resistor 110 may also not be present.

[0033] Each current sensing option 406 or 408 includes any suitable current sensing circuitry having a power input and a load input. The power input and the load input may be provided to an ADC 150 having a sense output 410. A sensing signal representing the polarity and magnitude of the current at the load input is provided at the sense output 410. The sensing signal is provided to the controller 148 at a sense input 412. The controller 148 has a control output 414, and the controller 148 is configured to provide a control signal at the control output 414 in response to the sensing signal. As described below, the charge pumps 142 are configured to adjust the voltage at the charge pump 142 output in response to the control signal. In other instances, a control circuit or control circuitry may be used to perform the functions of the controller 148 as described herein.

[0034] In the system 400, the NFET 108 represents the high-side FET. The charge pump 142 provides the gate voltage to the NFET 108. To turn on the NFET 108A or 108B, the NFET 108 requires a gate voltage higher than its source voltage. For each NFET 108, the voltage sensing regulation system monitors V GS to regulate the output voltage of the charge pump 142 to a specific level. The V GS of each NFET 108 can be regulated by disconnecting the clock 146, which temporarily disconnects the charge pump 142. In response to the V GS reaching an appropriate level, the clock 146 is reconnected. If the charge pump 142 subsequently loses charge (via gate-to-source leakage of the NFET 108, V GSSafety resistors 402, leakage in the main protector IC 102, etc.), the charge pump 142 is reactivated. Each charge pump 142 has a charge pump output coupled to the NFET 108. As an example, the charge pump 142A has a charge pump output (e.g., the first charge pump output) coupled to the gate of the NFET 108A via the charge pin 120. The charge pump 142B has a charge pump output (e.g., the second charge pump output) coupled to the gate of the NFET 108B via the discharge pin 122. The NFETs 108 are each coupled between the charge pump 142 output and the power supply terminal. In one example, one power supply terminal may be the node 134, and the other power supply terminal may be the PACK+ 138.

[0035] In an example, the ADC 150 determines the operating mode of the charge pump 142 in response to current sensing. The ADC 150 may be a low-power ADC that operates periodically by turning on to check the current and then turning off. In one example, the ADC 150 uses the sense resistor 110 to measure the current (e.g., the resistor current sensing option 408), which indicates the current through the NFET 108. In some examples, the high-tolerance sense resistor 110 may occupy board space and increase cost. Thus, in other examples, the FET current sensing option 406 is useful. The FET current sensing option 406 senses the current by monitoring the voltage across the NFET 108. However, the resistance of the NFET 108 may depend on temperature and process, and thus may not be as accurate as the resistor current sensing option 408 in some examples. In other examples, the main protector IC 102 may determine the current by monitoring the CELL+ and PACK+ voltages ( Figure 4 not shown). Any suitable method for monitoring or measuring current may be applicable to the examples herein.

[0036] The ADC 150 generates an output signal based on the input voltage provided to the ADC 150 and the selected current sensing option. In one example, the output signal is a digital signal provided to the controller 148, and the controller 148 determines the magnitude and polarity of the sensed current based on the output signal from the ADC 150. The sensed current indicates the current passing through the NFET 108. In an example, the controller 148 can use any suitable software, hardware, algorithm, digital logic, or state machine to compare the output signal from the ADC 150 with one or more thresholds. Based on the comparison with one or more thresholds, the controller 148 provides a signal to the voltage sensing circuit 144. In response to the signal, the voltage sensing circuit 144 sets the output voltage level of the charge pump 142. The voltage sensing circuit 144 can set the charge pump output voltage level by turning the clock 146 on and off at an appropriate duty cycle as described above. In one example, the voltage sensing circuit 144 compares the gate-to-source voltage level of the charging NFET (e.g., NFET 108A) or the discharging NFET (e.g., NFET 108B) with a reference voltage via an internal comparator and determines whether the charge pump output voltage is above or below a threshold. If it is above the threshold, the voltage sensing circuit 144 turns off the clock 146. If the charge pump output voltage is below the threshold, the voltage sensing circuit 144 turns on the clock 146 to activate the charge pump 142. The clock 146 provides a signal to the control input of each charge pump 142. The voltage sensing circuit 144 can include any suitable controller, hardware, circuitry, or digital logic to perform the functions described herein.

[0037] As described herein, the current passing through the NFET 108 or through the sense resistor 110 is measured, and the charge pump 142 is placed in different modes in response to the current measurement. If the battery cell 106 is being charged, the charge pump 142 voltage is set to a high voltage. If the battery cell 106 is discharging and the current is high (e.g., above a predetermined threshold), the device is in operation, and the charge pump 142 voltage is set to a high voltage to increase the efficiency of the NFET 108 (e.g., 10V). If the battery cell 106 is discharging and the current is low (e.g., below a predetermined threshold), the device is in a standby or idle state, and the charge pump 142 voltage is reduced to reduce the leakage current of the NFET 108 (e.g., the charge pump 142 voltage is set to 5V). In other examples, more than two charge pump 142 voltage levels can be implemented and selected based on current sensing.

[0038] In some instances, one of the NFETs 108 may be optional and not present, where system 400 has only one NFET 108. In other instances, the discharging NFET 108 (e.g., NFET 108B) may be a high-side FET, and the charging NFET 108 (e.g., NFET 108A) may be a low-side FET. Some instances herein may include a single NFET 108 and a single charge pump 142. In the instances herein, the charge pump 142 is any suitable charge pump and may include any suitable circuitry. The clock 146 can be any appropriate clock circuitry or have any suitable topology. Also, any current sensing method with any suitable circuitry is useful.

[0039] Figure 5 is a flowchart of method 500 for dynamically controlling a gate drive charge pump circuit in various instances herein. The steps of method 500 can be performed in any suitable order. In some instances, the hardware components described above with respect to Figure 1 and 4 can perform method 500. In some instances, any suitable hardware, software, or digital logic can perform method 500.

[0040] Method 500 indicates how the main protector IC 102 determines which state to place the charge pump 142 in. Method 500 begins at 510, where the ADC 150 and the controller 148 measure the supply current and determine the polarity of the current (e.g., positive or negative). Any suitable current sensing can be useful in the instances herein. If a positive current is detected, method 500 proceeds to 520. A positive current indicates that the battery cell 106 is charging. If the battery cell 106 is charging, power savings is not a concern, so if a positive current is detected at 510, there is no need to determine the magnitude of the current.

[0041] At 520. As described above, a positive current has been detected. The battery cell 106 is charging, so the charge pump 142 can be set to a high (or highest) voltage level, and then method 500 returns to 510 to monitor the state of the current. Alternatively, the current is monitored at 520, and if a change in the current (e.g., a change in the polarity of the current) is detected, method 500 can return to 510.

[0042] If a negative current is detected at 510, method 500 proceeds to 530. The negative current indicates that battery cell 106 is discharging. If battery cell 106 is discharging, the magnitude of the current is measured to determine the state of the device or system. In this example, the magnitude of the current is determined to be high (above a threshold) or low (below a threshold), and thus charge pump 142 has two different operating voltages. However, in other examples, any number of operating states of charge pump 142 may be implemented. ADC 150 and controller 148 may quantize the current measurement into any number of levels and then implement different output voltage values of charge pump 142 for each level. In many examples, two output voltage levels of charge pump 142 are suitable for providing effective operation, but different numbers of output voltage levels may be useful in other examples. In some examples, the output voltage of charge pump 142 may change linearly with the current measurement.

[0043] At 530, the magnitude of the current is measured to determine whether the current is above or below a threshold. If the current is low (below the threshold), method 500 proceeds to 540. If the current is high (above the threshold), method 500 proceeds to 550.

[0044] At 540, the current is below the threshold. This state indicates that the current is discharging, but the current is low. If the current is low, the device is likely in an idle or standby state, and battery cell 106 is not actively driving a load. The output voltage of charge pump 142 is set to a low voltage (e.g., 5V). This may be referred to as a low-power mode. As shown in graph 250, the low voltage reduces the leakage current. After placing charge pump 142 in the low-power mode, method 500 may return to 510 to continue monitoring the current to determine the polarity and magnitude of the current. The current may be retested periodically by ADC 150 and controller 148 to determine if a mode change is needed.

[0045] If the current is high in step 530, method 500 proceeds to 550. At 550, a high current is discharging, which indicates that battery cell 106 is actively driving a load. Thus, the system or device is in use or in an active state. If the device is in use, the output voltage of charge pump 142 is set to a high voltage (e.g., 10V). This may be referred to as a high-power mode. The high voltage provides effective operation of NFET 108, as shown in graph 200. After placing charge pump 142 in the high-power mode, method 500 may return to 510 to continue monitoring the current to determine the polarity and magnitude of the current. The current may be retested periodically by ADC 150 and controller 148 to determine if another mode change is needed. Thus, method 500 provides an example of dynamic control of a gate drive charge pump circuit for more efficient operation.

[0046] Figure 6 is a flow chart of method 600 for dynamically controlling a gate drive charge pump circuit in various examples herein. The steps of method 600 may be performed in any suitable order. In some examples, the hardware components described above with respect to Figure 1 and 4 may perform method 600. In some examples, any suitable hardware, software, or digital logic may perform method 600.

[0047] Method 600 begins at 610, where a controller or control circuit measures a load current of a transistor coupled to a power supply, where the gate of the transistor is coupled to a charge pump. As described above, any suitable sensing circuitry may be used to measure the load current. A sensing signal may be provided to the controller, and the controller may act in response to the sensing signal.

[0048] Method 600 continues at 620, where in response to a negative load current and the load current being below a threshold, the charge pump reduces the output voltage. The controller or control circuit may send a control signal to reduce the output voltage of the charge pump to additional circuitry. In one example, a clock such as clock 146 may be disabled to reduce the output voltage of the charge pump. In other examples, any suitable technique may be used to reduce the output voltage of the charge pump. A negative load current and a current below the threshold indicate that the system is discharging current but may not be actively driving a load. Thus, the system may be in an idle state.

[0049] Method 600 continues at 630, where in response to a negative load current and the load current being above a threshold, the charge pump increases the output voltage. The controller or control circuit may send a control signal to increase the output voltage of the charge pump to additional circuitry. In one example, the output voltage may be increased by enabling a clock such as clock 146. Other techniques for increasing the output voltage of the charge pump may be useful in other examples. A negative load current and a current above the threshold indicate that the system is discharging current at a high rate and is likely actively driving a load. As described above, in this state or mode of operation, the efficiency of NFET 108 is more important than the leakage current, and thus the charge pump output voltage may be increased to reduce the on-resistance of NFET 108.

[0050] Method 600 continues at 640 where, in response to a positive load current, the charge pump increases the output voltage. A controller or control circuit may send a control signal that increases the output voltage of the charge pump to additional circuitry. In one example, the output voltage may be increased by turning on a clock such as clock 146. Other techniques for increasing the output voltage of the charge pump may be useful in other examples. The positive load current indicates that the battery is charging. As described above, in this state or operating mode, the efficiency of NFET 108 is more important than the leakage current, and thus the charge pump output voltage may be increased to reduce the on-resistance of NFET 108 while the battery is charging.

[0051] In the examples herein, multiple operating modes of a gate-driven charge pump are implemented. The current through the high-side NFET or through a sense resistor in the power supply application is measured, and the charge pump is placed in different modes in response to the current measurement. If the battery pack is charging, the charge pump output voltage is set to a high voltage. If the battery pack is discharging and the current is high, the device is in operation, and the charge pump output voltage is set to a high voltage to improve the efficiency of the NFET. If the battery pack is discharging and the current is low, the device is in a standby or idle state, and the charge pump output voltage is reduced to reduce the leakage current. In other examples, more than two charge pump output voltage levels may be implemented and selected based on the current measurement.

[0052] As described herein, the charge pump output voltage is dynamically adjusted based on the system load current polarity and magnitude. When efficiency is important, the on-resistance of the NFET may decrease with an increasing gate-to-source voltage at high load currents. In a low-power operating mode, the on-resistance may be increased by reducing the gate-to-source voltage and reducing the current consumption of the charge pump. The examples herein may provide extended battery or power supply life by reducing the current consumption of the charge pump that controls the operation of the NFET.

[0053] In this specification, the term "coupled" may cover connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first example, device A is directly connected to device B; or (b) in a second example, if an intermediate component C does not change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C, such that device B is controlled by device A via the control signal provided by device A.

[0054] A device “configured to” perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or can be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be performed by firmware and / or software programming of the device, by the construction and / or layout of hardware components, and the interconnection of the device or combinations thereof.

[0055] A circuit or device described herein as including certain components can alternatively be coupled to those components to form the described circuitry or device. By way of example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage source and / or current source) can in fact include only semiconductor elements within a single physical device (e.g., semiconductor die and / or integrated circuit (IC) package), and can be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by an end user and / or a third party.

[0056] Although certain components may be described herein as belonging to a particular process technology, those components can be exchanged with components of other process technologies. The circuits described herein can be reconfigured to include replacement components to provide functionality that is at least partially similar to the functionality available prior to the component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can instead be multiple resistors or capacitors respectively coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can instead be multiple resistors or capacitors respectively coupled in series between the same two nodes as a single resistor or capacitor.

[0057] The use of the phrase “ground” in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise noted, “about,” “approximately,” or “substantially” in front of a parameter means within + / - 10% of the stated parameter. Within the scope of the claims, modifications to the described examples are possible, and other examples are possible.

Claims

1. A system, comprising: A charge pump having a control input and a charge pump output; A transistor coupled in series with a power supply terminal, the transistor having a gate coupled to the charge pump output; A current sensing circuitry having a power supply input, a load input, and a sensing output, wherein the power supply input is coupled to the power supply terminal, the current sensing circuitry is configured to provide a sensing signal at the sensing output, and the sensing signal represents a polarity and a magnitude of a current at the load input; And A controller having a sensing input and a control output, wherein the sensing input is coupled to the sensing output, the control output is coupled to the control input, and the controller is configured to provide a control signal at the control output in response to the sensing signal, and the charge pump is configured to adjust a voltage at the charge pump output in response to the control signal.

2. The system according to claim 1, wherein the transistor is an n-channel field effect transistor (NFET).

3. The system according to claim 1, wherein the transistor is a first transistor, and the first transistor is coupled in series to a second transistor.

4. The system according to claim 3, wherein the first transistor is configured to discharge the power supply, and the second transistor is configured to charge the power supply.

5. The system according to claim 1, wherein the charge pump is configured to increase the voltage at the charge pump output in response to a positive polarity of the current.

6. The system according to claim 1, wherein the charge pump is configured to decrease the voltage at the charge pump output in response to a negative polarity of the current and the magnitude of the current being lower than a predetermined threshold.

7. The system according to claim 1, wherein the charge pump is configured to increase the voltage at the charge pump output in response to a negative polarity of the current and the magnitude of the current being higher than a predetermined threshold.

8. The system according to claim 1, wherein the current sensing circuitry includes a current sensing resistor coupled to the power supply terminal.

9. The system according to claim 1, wherein the sensing output is an output of an analog-to-digital converter.

10. The system according to claim 1, wherein the current sensing circuitry is coupled to the transistor.

11. The system according to claim 1, wherein the control input is configured to receive a signal from a clock.

12. The system according to claim 1, wherein the charge pump is a first charge pump, the charge pump output is a first charge pump output, the transistor is a first transistor, and the system further includes: A second charge pump having a second charge pump output; And A second transistor coupled to the second charge pump output, wherein the second transistor is coupled in series to the first transistor.

13. A method, comprising: Measuring, by a control circuit, a load current of a transistor coupled to a power supply, wherein a gate of the transistor is coupled to a charge pump; Reducing, by the control circuit, an output voltage of the charge pump in response to a negative polarity load current and the load current being lower than a threshold; In response to a negative load current and the load current being higher than a threshold, increase the output voltage of the charge pump via the control circuit; and In response to a positive load current, increase the output voltage of the charge pump via the control circuit.

14. The method according to claim 13, wherein the transistor is a first transistor, and the first transistor is coupled in series to a second transistor.

15. The method according to claim 13, wherein measuring the load current includes measuring the load current through a sense resistor.

16. The method according to claim 13, wherein increasing the output voltage of the charge pump increases the gate-to-source voltage of the transistor.

17. The method according to claim 13, wherein decreasing the output voltage of the charge pump decreases the gate-to-source voltage of the transistor.

18. A system, comprising: a first charge pump having a first charge pump output coupled to the gate of a first n-channel transistor; a second charge pump having a second charge pump output coupled to the gate of a second n-channel transistor, the second n-channel transistor being coupled in series to the first n-channel transistor; a power supply coupled to the first n-channel transistor and the second n-channel transistor; a current sensing circuitry configured to provide a sense signal indicative of the polarity and magnitude of the current through the first n-channel transistor and the second n-channel transistor; and a controller configured to provide a control signal in response to the sense signal, wherein the control signal is provided to the first charge pump and the second charge pump, and wherein the first charge pump and the second charge pump are configured to adjust the voltages at the first charge pump output and the second charge pump output, respectively, in response to the control signal.

19. The system according to claim 18, wherein the sense signal is provided by a current sense resistor.

20. The system according to claim 18, wherein the first n-channel transistor is configured to charge the power supply, and the second n-channel transistor is configured to discharge the power supply.

Images