Event sensor pixel with sensitivity and dynamic range optimization

Abstract

A pixel circuit for an event sensor is provided. In one embodiment, the pixel circuit includes: a photosensitive element configured to generate a current signal in response to a brightness of light irradiated on the photosensitive element; a first N-type transistor; a second N-type transistor; a first P-type transistor including a gate connected to a first bias voltage; a second P-type transistor including a gate connected to a second bias voltage, the second bias voltage being an adjustable DC bias voltage adjusted according to at least one of a sensing temperature of the pixel circuit or a manufacturing process change; and a voltage output that varies in response to brightness of light irradiated on the photosensitive element. Adjustment of the second bias voltage causes the DC level of the voltage output to shift up or down without changing the overall gain of the pixel circuit. The pixel circuit may also include one or more additional N-type transistors for improved performance by optimizing contrast sensitivity. The pixel circuit may further include a converter, a capacitor electrically coupled to the converter, and an amplifier electrically coupled to the capacitor. Further, the pixel circuitry may be implemented by stacking the wafer configuration and one or more interconnects between the wafers.

Description

Technical Field

[0001] The present disclosure generally relates to the field of sensors and pixel circuits for sensing and other applications. More specifically and without limitation, the present disclosure relates to pixel circuits with optimized sensitivity and dynamic range and associated architectures for implementing event-based vision sensors as well as other sensors and vision systems. The pixel circuits and features disclosed herein can be used in a variety of systems and applications such as security systems, production line monitoring applications, autonomous vehicles, navigation systems, and other systems and applications that benefit from optimized pixel sensitivity and dynamic range. Background Art

[0002] Pixel circuits can be used in a wide range of applications, including event vision sensors. Examples of such sensors include contrast detection sensors, temporal contrast event sensors, and dynamic vision sensors.

[0003] Pixel circuits used in event vision sensors typically include multiple circuit elements, including a photosensitive element (e.g., a photodiode) configured to generate a current signal in response to the luminance of light incident on the photosensitive element. Some of these circuits use transistors to convert the current signal generated by the photosensitive element into a voltage signal (V pr_out ) for further processing. FIGS. 1A and 1B illustrate exemplary state-of-the-art pixel front-end circuits used in temporal contrast event sensors.

[0004] When the contrast sensitivity of a pixel increases, temporal contrast event sensors generally achieve better application performance. This can be achieved by increasing the gain of the signal path between the photosensitive element and a comparator used to detect contrast events. For example, relative to the circuit shown in FIG. 1A, the existing circuit shown in FIG. 1B increases the gain of the current-voltage conversion by approximately 2 times.

[0005] The inventors of the present disclosure have found that it is beneficial to maintain contrast sensitivity over a wide illuminance range, and this can be achieved while avoiding signal saturation. The range of operation without saturation of illuminance is generally referred to as the dynamic range.

[0006] Event vision sensors fabricated using wafer stacking technology typically include a per-pixel hybrid bond interconnect between a top wafer and a bottom wafer. The top wafer can be fabricated using a dedicated CMOS image sensor (CIS) semiconductor manufacturing process, while the bottom wafer can be fabricated using a high-performance analog CMOS semiconductor manufacturing process.

[0007] Circuit elements can be formed in the same or different wafers compared to each other. The partitioning of the circuit elements of an event sensor pixel circuit between a CMOS wafer and a CIS wafer is typically implemented such that only the photodiode is on the CIS wafer. Another known partitioning option is to have the photodiode and one or more NMOS transistors on the same CIS wafer.

[0008] Placing an N-type (e.g., NMOS) transistor on the CIS wafer allows it to be removed from the already very dense CMOS wafer. Also, while implementing the NMOS transistor on the CIS wafer allows for a smaller pixel pitch, it also reduces the photosensitive area. The CIS wafer manufacturing process typically only allows the photodiode and NMOS transistor to be implemented on the CIS wafer at least within the pixel area. For process optimization, P-type (e.g., PMOS) transistors are generally not allowed. If the NMOS transistor connected to the photodiode is placed very close to the photodiode on the same wafer, it can be optimized to operate with the photodiode. Some CIS wafer manufacturing processes do allow the simultaneous implementation of N-type (e.g., NMOS) and P-type (e.g., PMOS) transistors within the pixel area. Figure 1C shows an example of the circuit of Figure 1A implemented via a stacked "CIS-on-CMOS" wafer manufacturing process, where the photodiode and all transistors of the front-end circuit are placed on the CIS layer. The hybrid bonding connection to the rest of the pixel circuit on the CMOS layer is represented by the cylindrical shape at the V pr_out node.

[0009] Existing pixel circuit implementations such as those discussed above may have one or more drawbacks. For example, they may exhibit an output voltage (V pr_out ) versus light (illuminance) relationship with low gain and thus exhibit less than ideal contrast sensitivity. As discussed above, one technique for boosting gain includes placing additional (e.g., NMOS) transistors in the photodiode branch to affect gain boost and thereby improve contrast sensitivity. However, because saturation may occur for higher temperatures closer to ground and lower temperatures closer to the power supply, the drawback of this gain-boosting technique is a reduced dynamic range. Another way to correct this drawback is to increase the power supply voltage, thereby increasing the available signal range without saturation. However, this approach requires higher power consumption and increases the likelihood of reliability issues.

[0010] Another problem with existing implementations of pixel circuits is low-light degradation at higher temperatures, which is manifested as a non-linear compression towards lower light in the "red" output voltage versus illuminance curve.

[0011] In view of the above and other disadvantages of the available technologies and implementations, there is a need for improved pixel circuits for sensing and other applications. For example, there is a need for improved event sensor pixel circuits with greater sensitivity and optimized dynamic range. The present disclosure includes embodiments for addressing these and other purposes, including novel pixel circuit arrangements and schemes to appropriately mitigate the dynamic range issues brought about by temperature and / or manufacturing processes, as further described below. Summary of the Invention

[0012] Embodiments of the present disclosure relate to pixel circuits having improved features and characteristics. Pixel circuits compliant with the present disclosure can be implemented for event-based vision sensors as well as other sensors and vision systems. Pixel circuits compliant with the present disclosure can be arranged using stacked or non-stacked configurations. Additionally, as disclosed herein, pixel circuits can be implemented using adjustable DC bias voltages. Advantageously, pixel circuits in accordance with embodiments of the present disclosure can provide greater pixel sensitivity and optimized dynamic range.

[0013] By way of example, a pixel circuit is provided that includes: a photosensitive element configured to generate a current signal in response to the luminance of light incident on the photosensitive element; a first N-type transistor; a second N-type transistor; a first P-type transistor including a gate connected to a first bias voltage; a second P-type transistor including a gate connected to a second bias voltage; and a voltage output that varies in response to the luminance of light incident on the photosensitive element. The second P-type transistor can affect gain boosting, such as boosting the gain by approximately two times. The pixel circuit can be arranged in a stacked configuration or a non-stacked configuration, as disclosed herein.

[0014] According to embodiments of the present disclosure, the second bias voltage of the pixel circuit can be an adjustable DC bias voltage. For example, the bias voltage can be adjusted to cause the DC level of the voltage output to shift up or down without changing the overall gain of the pixel circuit. Additionally, as disclosed herein, adjusting the bias voltage can increase the unsaturated operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit. Furthermore, pixel sensitivity can be optimized.

[0015] Embodiments of the present disclosure include a pixel circuit, wherein a second bias voltage (e.g., a DC bias voltage) is automatically adjusted in response to temperature fluctuations and / or statically adjusted according to manufacturing process parameter variations. In some embodiments, an on-chip temperature-sensitive bias circuit can be used to continuously sense the chip temperature and automatically adjust the bias voltage (e.g., the second bias voltage of the pixel circuit) in response to the chip temperature. As another example, the bias voltage can be statically adjusted (e.g., at a certain time or before use) to cope with manufacturing process parameter variations (e.g., global threshold voltage) and increase the non-saturation operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit. For example, in some embodiments, a bias circuit can be used, which is configured to sense the process parameters of the chip and adjust the bias voltage. The static type of bias voltage adjustment can provide compensation for the effects of manufacturing process parameters that vary between chips. As disclosed herein, a compensation voltage signal can be generated by the bias circuit and applied to adjust the bias voltage (e.g., the second bias voltage of the pixel circuit). In some embodiments, the temperature-sensitive bias circuit or the bias circuit configured to sense process parameters can include a third P-type transistor in series with a third N-type transistor, a programmable current source, and a programmable voltage source. And, in some embodiments, the third P-type transistor of the bias circuit can correspond to the P-type transistor of the connected pixel circuit, and / or the third N-type transistor of the bias circuit can correspond to the N-type transistor of the connected pixel circuit.

[0016] The above and other features can be provided. For example, the pixel circuit can further include a third N-type transistor, which includes a gate connected to a DC voltage, wherein the third N-type transistor provides leakage compensation at a low light level incident on the photosensitive element. In some embodiments of the pixel circuit, the second P-type transistor, the third N-type transistor, and one or more other components of the pixel circuit are implemented in a non-stacked configuration on a common wafer.

[0017] In some embodiments of the pixel circuit, the third N-type transistor is implemented on a common wafer together with the second P-type transistor and the first N-type transistor and the second N-type transistor. The common wafer can include a first CMOS wafer. In some embodiments, the photosensitive element is implemented in a second CMOS wafer, wherein the first CMOS wafer is stacked relative to the second CMOS wafer. There can be at least one intra-pixel interconnect between the first CMOS wafer and the second CMOS wafer. As a further example, the first N-type transistor, the second N-type transistor, the third N-type transistor, and the photosensitive element can be implemented on a common wafer. Moreover, the common wafer can include a CMOS image sensor (CIS) wafer. As a further example, the second P-type transistor can be implemented in a CMOS wafer, wherein the CMOS wafer is stacked relative to the CIS wafer. Further still, there can be one or more interconnects between the CMOS wafer and the CIS wafer.

[0018] In some embodiments, the pixel circuit may further include a converter configured to receive a current signal from a photosensitive element and generate a voltage signal based on the received current signal. For example, the converter may be implemented using a second P-type transistor and configured as a logarithmic current-voltage converter. The pixel circuit may further include a first capacitor serially electrically coupled to the converter and configured to receive the voltage signal from the converter. Moreover, the pixel circuit may include an amplifier serially electrically coupled to the first capacitor at an input and configured to generate an amplified signal at an output based on an output signal from the first capacitor. Also, in some embodiments, the photosensitive element may include a photodiode.

[0019] In some embodiments of the pixel circuit, the converter and the first capacitor are implemented in a CMOS wafer together with the second P-type transistor. Moreover, the pixel circuit may further include a second capacitor connected in parallel with the first capacitor, which is implemented in a CIS wafer and connected to the first capacitor by using at least two interconnections. The combination of the second capacitor and the first capacitor may increase the capacitance of the amplifier, and the combination with a third capacitor may increase the overall gain of the pixel circuit. A continuous adjustment of a second bias voltage (e.g., a DC bias voltage) in response to the chip temperature may increase the non-saturation operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit by increasing the voltage margin. As a further example, in some embodiments, an adjustment of the bias voltage in response to (multiple) manufacturing process variations (e.g., global threshold voltage variations, where a larger threshold may reduce the voltage margin and result in a reduced dynamic range; reducing the bias voltage in response to the variation may mitigate and counteract the impact of the manufacturing process variation) may increase the non-saturation operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit.

[0020] Embodiments of the present disclosure may further provide an event sensor having a plurality of pixels, each pixel including a pixel circuit that includes a photosensitive element configured to generate a current signal in response to the luminance of light incident on the photosensitive element. The pixel circuit may further include: a first N-type transistor; a second N-type transistor; a first P-type transistor including a gate connected to a first bias voltage; and a second P-type transistor including a gate connected to a second bias voltage, wherein the second bias voltage is an adjustable DC bias voltage. Moreover, the pixel circuit may include a voltage output that varies in response to the luminance of light incident on the photosensitive element. In some embodiments, the second P-type transistor affects gain boosting, such as boosting the gain by approximately two times. In some embodiments, adjustment of the second bias voltage causes the DC level of the voltage output to shift up or down without changing the overall gain of the pixel circuit. Additionally or alternatively, adjustment of the second bias voltage (e.g., the DC bias voltage) increases the non-saturation operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit.

[0021] In some embodiments, the second bias voltage is an adjustable bias voltage. For example, the bias voltage may be automatically adjusted according to temperature and / or statically adjusted according to manufacturing process parameter variations. In some embodiments, an on-chip temperature-sensitive bias circuit may be used to automatically adjust the bias voltage (e.g., the second bias voltage of the pixel circuit) in response to the chip temperature. As another example, the bias voltage may be statically adjusted (e.g., at a certain time or before using the pixel circuit) to account for manufacturing process parameter variations (e.g., global threshold voltage variations) and increase the non-saturation operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit. For example, in some embodiments, a bias circuit may be used that is configured to sense the process parameters of the chip or wafer of the pixel circuit and adjust the bias voltage. The static type of bias voltage adjustment may provide compensation for the effects of manufacturing process parameters that vary between chips. As disclosed herein, a compensation voltage signal may be generated by the bias circuit and applied to correct the bias voltage (e.g., the second bias voltage of the pixel circuit). In some embodiments, the temperature-sensitive bias circuit or the bias circuit configured to sense process parameters may include a third P-type transistor in series with a third N-type transistor, a programmable current source, and a programmable voltage source. And, in some embodiments, the third P-type transistor of the bias circuit may correspond to the P-type transistor of the connected pixel circuit, and / or the third N-type transistor of the bias circuit may correspond to the N-type transistor of the connected pixel circuit.

[0022] The above and other features may be provided. For example, the second P-type transistor of the pixel circuit and one or more other components may be implemented in a non-stacked common wafer. Moreover, the event sensor may further include a third N-type transistor, the third N-type transistor including a gate connected to a DC voltage, wherein the third N-type transistor provides leakage compensation at a low light level incident on the photosensitive element. The P-type transistor of the pixel circuit, the third N-type transistor, and one or more other components may be implemented in a non-stacked configuration in a common wafer. Moreover, the third N-type transistor may be implemented in a common wafer together with the second P-type transistor and the first N-type transistor and the second N-type transistor. The common wafer includes a first CMOS wafer.

[0023] In the above example, the photosensitive element may be implemented in a second CMOS wafer, wherein the second CMOS wafer is stacked relative to the first CMOS wafer. There may be at least one intra-pixel interconnect between the first CMOS wafer and the second CMOS wafer. As a further example, the first N-type transistor, the second N-type transistor, the third N-type transistor, and the photosensitive element may be implemented on a common wafer. Moreover, the common wafer may include a CMOS image sensor (CIS) wafer. As a further example, the second P-type transistor may be implemented in a CMOS wafer, wherein the CMOS wafer is stacked relative to the CIS wafer. Further still, there may be a plurality of interconnects between the CMOS wafer and the CIS wafer.

[0024] In some embodiments, the event sensor further includes a converter configured to receive a current signal from the photosensitive element and generate a voltage signal based on the received current signal. The converter may be implemented using the second P-type transistor. Examples of the converter include a logarithmic current-voltage converter. The event sensor may further include a first capacitor serially electrically coupled to the converter and configured to receive the voltage signal from the converter. Further, the event sensor may include an amplifier serially electrically coupled to the first capacitor at an input and configured to generate an amplified signal at an output based on the output signal from the first capacitor. In some embodiments, the photosensitive element may include a photodiode.

[0025] In some embodiments, the converter and the first capacitor are implemented in a CMOS wafer together with the second P-type transistor. Moreover, the event sensor may further include a second capacitor connected in parallel with the first capacitor, the second capacitor being implemented in the CIS wafer and connected to the first capacitor by using at least two interconnects. As an example, the second capacitor in combination with the first capacitor increases the capacitance of the amplifier, and in combination with a third capacitor increases the overall gain of the pixel circuit.

[0026] In some embodiments, the gate of the third N-type transistor is connected to a second bias voltage. Moreover, the pixel circuit may further include a fourth diode-connected N-type transistor at the voltage output.

[0027] Embodiments of the present disclosure may further include a pixel circuit for use with an event sensor, the pixel circuit including a photosensitive element configured to generate a current signal in response to the luminance of light incident on the photosensitive element. The pixel circuit may further include: a first N-type transistor; a second N-type transistor; a first P-type transistor including a gate connected to a first bias voltage; and a second P-type transistor including a gate connected to a second bias voltage, wherein the second bias voltage is an adjustable DC bias voltage. Moreover, the pixel circuit may include a voltage output that varies in response to the luminance of light incident on the photosensitive element. In some embodiments, the second P-type transistor may affect gain boosting, such as boosting the gain by approximately two times. In some embodiments, adjusting the second bias voltage may cause the DC level of the voltage output to shift up or down without changing the overall gain of the pixel circuit, and adjusting the second bias voltage may increase the unsaturated operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit. Additionally, or alternatively, adjusting the second bias voltage (e.g., the DC bias voltage) may increase the unsaturated operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit. For example, the bias voltage may be automatically adjusted in response to the chip temperature and / or statically adjusted according to manufacturing process parameter variations. In some embodiments, a temperature-sensitive bias circuit or a bias circuit configured to sense process parameters may provide an adjustable bias voltage to the pixel circuit. For example, the bias circuit may include a third P-type transistor in series with the third N-type transistor, a programmable current source, and a programmable voltage source. And, in some embodiments, the third P-type transistor of the bias circuit may correspond to the P-type transistor of the connected pixel circuit, and / or the third N-type transistor of the bias circuit may correspond to the N-type transistor of the connected pixel circuit.

[0028] As a further example, the pixel circuit may further include a converter configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal. The converter may be implemented using the second P-type transistor. Examples of the converter include logarithmic current-voltage converters. Moreover, a first capacitor may be provided, which is serially electrically coupled to the converter and configured to receive the voltage signal from the converter. In addition, an amplifier may be provided, which is serially electrically coupled to the first capacitor at the input and configured to generate an amplified signal at the output based on the output signal from the first capacitor.

[0029] In some embodiments, the pixel circuit further includes a third N-type transistor, the third N-type transistor including a gate connected to a DC voltage, wherein the third N-type transistor provides leakage compensation at a low light level incident on the photosensitive element.

[0030] It will be understood that the foregoing summary description and the following detailed description are merely exemplary and explanatory and do not limit the disclosed embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Reference will now be made to the drawings, which show exemplary embodiments of the present disclosure, in which:

[0032] FIG. 1A is a schematic representation of an example of a conventional pixel circuit.

[0033] FIG. 1B is a schematic representation of another example of a conventional pixel circuit.

[0034] FIG. 1C is a schematic representation of an example of a conventional stacked pixel circuit.

[0035] Figure 2A is a schematic representation of an example of a non-stacked pixel circuit according to an embodiment of the present disclosure.

[0036] Figure 2B is a schematic representation of an example of a stacked pixel circuit according to an embodiment of the present disclosure.

[0037] Figure 2C is a schematic representation of an example of another stacked pixel circuit according to an embodiment of the present disclosure.

[0038] Figure 2D is a schematic representation of an example of yet another stacked pixel circuit according to an embodiment of the present disclosure.

[0039] Figure 3A is a schematic representation of an example of another non-stacked pixel circuit according to an embodiment of the present disclosure.

[0040] Figure 3B is a schematic representation of an example of a stacked pixel circuit according to an embodiment of the present disclosure.

[0041] Figure 4A is a schematic representation of an example of other non-stacked pixel circuits according to an embodiment of the present disclosure.

[0042] Figure 4B is a schematic representation of an example of other stacked pixel circuits according to an embodiment of the present disclosure.

[0043] Figure 5A is a schematic representation of an example of yet another non-stacked pixel circuit according to an embodiment of the present disclosure.

[0044] Figure 5B Schematic representation of an example of another stacked pixel circuit according to an embodiment of the present disclosure.

[0045] Figure 6A Schematic representation of an example of another pixel circuit according to an embodiment of the present disclosure.

[0046] Figure 6B Schematic representation of an example of another pixel circuit having a stacked configuration according to an embodiment of the present disclosure and illustration of the arrangement of components associated with different wafers.

[0047] Figure 7A and Figure 7B Provide a schematic representation of an example of other pixel circuits according to an embodiment of the present disclosure.

[0048] Figure 8 Schematic representation of an example of another pixel circuit having additional components for implementing an event sensor according to an embodiment of the present disclosure.

[0049] Figure 9 Graphical representation of an example of the output voltage of a pixel circuit versus the contrast according to an embodiment of the present disclosure.

[0050] Figure 10 Graphical representation of an example of the bias voltage of a pixel circuit as a function of temperature according to an embodiment of the present disclosure.

[0051] Figure 11 Representation of an example of a stacked configuration of wafers having interconnects for implementing a pixel circuit according to an embodiment of the present disclosure.

[0052] Figure 12 Provide a schematic representation of an example of a bias circuit for adjusting the bias voltage of a pixel circuit according to an embodiment of the present disclosure.

[0053] Figures 13 to 20 Provide an illustration of the operation and impact of a bias circuit compliant with an embodiment of the present disclosure with respect to manufacturing parameter variations and temperature fluctuations. Figure 13 Shows an exemplary graph of V bias_fes versus I pr_out for different process corners under controlled V ph . Figure 14 Shows an exemplary graph of V bias_fes versus I pr_out for different process corners at constant V ph . Figure 15 Shows an exemplary graph of the variation of V bias_fes for different process corners. Figure 16 Shows an exemplary graph of V bias_fes versus Vref V with different settings pr_out for I ph Exemplary curves. Figure 17 Shows at a constant V bias_fes for different temperatures pr_out for I ph Exemplary curves. Figure 18 Shows at a controlled V bias_fes and I ref = 1 pA for different temperatures pr_out for I ph Exemplary curves. Figure 18 Shows at a controlled V bias_fes and I ref = 1 pA for different temperatures pr_out for I ph Exemplary curves. Figure 20 Shows for different temperatures bias_fes Exemplary curves of the change. Detailed implementation

[0054] Now, detailed reference will be made to the exemplary embodiments and aspects of the present disclosure, which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar components. The terms used in the descriptions presented herein are not intended to be construed in any restrictive or limiting manner merely because they are used in conjunction with the detailed descriptions of certain specific embodiments. Moreover, the described embodiments include several novel features, none of which alone is responsible for its desired properties or is essential for the pixel circuits, sensor systems, and arrangements described herein.

[0055] The disclosed embodiments relate to improved pixel circuits and architectures for sensing systems and applications, including asynchronous time-based event sensing. The disclosed embodiments also relate to systems and methods for implementing and using event-based vision sensors (referred to herein as "event sensors") having such pixel circuits. Advantageously, the exemplary embodiments can provide efficient sensing with greater contrast sensitivity and dynamic range. Other advantages of the present embodiments include the ability to optimally use advanced semiconductor manufacturing process technologies to implement vision sensors with competitive pixel sizes. Further, as will be understood from the present disclosure, the embodiments can be implemented and used in various applications and vision systems, such as security systems, autonomous vehicles, and other systems that benefit from rapid and efficient motion or event detection.

[0056] In existing image or video processing systems, an image sensor can acquire and process visual information to reconstruct an image. An image or video acquisition and processing system can include an array of optoelectronic sensors, where each optoelectronic sensor can acquire visual information to reconstruct an image representation of a visual scene. This process can be repeated at a predetermined rate.

[0057] An event-based vision sensor includes multiple pixel circuits and can detect, pixel by pixel, temporal contrasts exceeding a preset relative threshold to follow the temporal evolution of relative light changes (e.g., contrast detection, CD; temporal contrast, TC) and define sampling points for frameless pixel-level measurements of absolute intensity (e.g., exposure measurement, EM). Due to the temporal precision of the recorded data, the inherent suppression of temporal redundancy leading to reduced post-processing costs, and the ability to achieve wide dynamic range operation within a scene, event sensors have become popular in high-speed low-power machine vision applications. Information regarding temporal contrast can be encoded in the form of "events": data packets containing the X, Y coordinates, timestamp, and contrast polarity of the original pixel. To maximize the benefit of the ability of individual pixels to sample visual information with high temporal precision, early timestamping and high readout throughput are crucial for preserving event timing.

[0058] In some embodiments, for real-time artificial vision (also referred to herein as "computer vision" or "machine vision"), a vision acquisition and processing system can be configured to acquire and process only data representing changes in current visual information relative to previously acquired visual information. Such a sensor or vision system may not generate frames of an image. Such a vision sensor can include, for example, a temporal contrast (TC) sensor, a contrast detection (CD) sensor, or a dynamic vision sensor (DVS). Such sensors are referred to herein as "event-based vision sensors" or generally as "event sensors". Examples of such sensors are described in U.S. Patent Nos. 8,780,240, 10,721,432, 10,904,465, and 11,317,045, the disclosures of which are incorporated herein by reference in their entirety.

[0059] For example, a TC sensor does not record images frame by frame like existing image systems. Instead, each pixel of the TC sensor can determine the time derivative of the light it senses. In some embodiments, optionally, the pixel can further perform some processing on the time derivative. When the time derivative exceeds a preset threshold, the pixel can generate an "event" by outputting a signal. In the case of short latency, the pixel can further transmit data related to the event. In some embodiments, the transmitted data can include the position (e.g., x coordinate and y coordinate) of the pixel within the TC sensor (e.g., having a two-dimensional pixel matrix). In some embodiments, the transmitted data can include a sign bit representing the polarity (e.g., positive sign or negative sign) of the temporal evolution of the light intensity sensed by the pixel. In some embodiments, the transmitted data can include a timestamp of when the event occurred. In some embodiments, the transmitted data of the pixel can include a sequence of (x, y, s) values, where 'x' and 'y' represent the coordinates of the pixel, and's' represents the polarity. The value of's' can represent the relative change in the light intensity detected by the pixel, where the value of's' can represent the magnitude of the change, and the sign of's' can represent the direction of the change (e.g., increasing or decreasing). In some embodiments, the pixel circuits of the TC sensor can operate asynchronously, where the pixel circuits of the TC sensor are generally not quantized to a time reference (e.g., not timed). In other embodiments, the pixel circuits of the TC sensor can operate synchronously, where the pixel circuits of the TC sensor are quantized to a time reference (e.g., timed).

[0060] As described above, an event sensor can include a time contrast (TC) sensor, also known as a contrast detection (CD) sensor or a dynamic vision sensor (DVS). The event sensor can be implemented in many different ways, including with or without exposure measurement (EM), with or without other operations or components, including an analog-to-digital converter (ADC) or a digital-to-analog converter (DAC). The number of components can also vary (e.g., one EM versus multiple EMs), and the location of the components can also vary (e.g., within the pixel versus outside the pixel). Also, the components can work asynchronously or synchronously, or have a combination of both. The specific arrangement and type of operation typically depend on the application and requirements of the event sensor.

[0061] Embodiments of the present invention provide a pixel circuit and features that can be advantageously used in event-based vision sensors and other sensor systems. By way of example, and without limitation, an event sensor implemented using a TC sensor with a two-dimensional pixel matrix can incorporate embodiments of the present invention and their related features. As a further example, an event sensor using superpixels can incorporate embodiments of the present invention and their related features. It will be understood that the following description of the optimization of the sensitivity and dynamic range of event sensor pixels is merely exemplary, and other forms of sensors can also be employed with embodiments of the present invention. In fact, as noted above, embodiments of the present invention can be advantageously incorporated into any type of event-based vision sensor or other sensor system.

[0062] For embodiments of image sensors, it is beneficial to use modern wafer stacking technology, which is characterized by minimizing the distance between the interconnections between wafers, thus allowing for the presence of at least one interconnection per pixel. The term "wafer" as used herein generally refers to a semiconductor wafer used for manufacturing integrated circuits. Such wafers can be used to fabricate pixel circuits as described herein. By way of example, a wafer can be a CMOS wafer or a CMOS image sensor (CIS) wafer. The term "interconnection" as used herein generally refers to an electrical connection between individual wafers (e.g., a conductive bond). Techniques for implementing interconnections between wafers include, for example, direct metal-to-metal (i.e., Cu-Cu) bonding and "through-silicon vias" (TSVs). Using the direct metal-to-metal bonding technique, the upper wafer is oriented upside down, and the upper and lower wafers are connected "face-to-face" using the (multiple) interconnections that connect the top metals of the two wafers. "Through-silicon vias" (TSVs) can be used to connect two wafers that are not face-to-face oriented (i.e., the back side of the upper wafer is connected to the front side of the lower wafer). If more than two wafers are stacked, TSVs can be used. For example, to stack three wafers, face-to-face Cu-Cu bonding can be used to connect the top wafer and the middle wafer, and TSVs can be used as interconnections to connect the third wafer to the middle wafer below.

[0063] One or more interconnections can be used between the wafers of a pixel circuit, as further described herein. Using the above techniques, a stacked configuration can be achieved for the circuit elements implementing the pixels, such as a vertical stacked arrangement of two or more wafers, and different manufacturing processes can be used for different wafers. For example, in the case where the light-conducting or light-sensitive components are located on the upper wafer and other pixel circuits are located on the lower wafer, one manufacturing technique can be optimized for implementing the light-sensitive elements, while another manufacturing technique can be optimized for implementing other electrical components and elements. Such an arrangement helps to minimize the pixel size while maximizing the overall pixel density of the sensor.

[0064] In some embodiments, a stacked implementation is utilized such that the minimum interconnect distance (i.e., pitch) is significantly less than the target pixel pitch, and multiple interconnects can be placed and used in each pixel. Advantageously, multiple intra-pixel interconnects can be employed to achieve optimized pixel gain and contrast sensitivity.

[0065] Embodiments of the present disclosure also provide an event sensor that has increased temporal contrast pixel circuit gain while improving the dynamic range by avoiding pixel front-end saturation, particularly in the presence of temperature and / or manufacturing process variations. This is achieved by applying certain circuit design techniques and leveraging various manufacturing technology features, as described herein.

[0066] The circuit design techniques according to the present disclosure include a gain boosting mechanism that includes DC bias point adjustment capabilities. For example, in some embodiments, the DC bias point adjustment capabilities include an automatic dynamic adjustment of the bias voltage (e.g., DC bias voltage) of the pixel circuit in response to continuous sensing or determination of the chip temperature. A temperature-sensitive bias circuit configured to generate a temperature-dependent bias voltage signal that adjusts the bias voltage in response to fluctuations in the chip temperature can be used to determine the temperature of the pixel circuit. In some embodiments, a pixel circuit or event sensor that includes a stacked wafer technology (i.e., two or more wafers) includes a temperature-sensitive bias circuit placed on the bottom wafer (e.g., a CMOS wafer). In other embodiments that include a stacked wafer technology, the bias circuit can be placed on the top wafer (e.g., a CIS wafer). In other embodiments that include a stacked wafer technology, the bias circuit can be placed on both the top wafer and the bottom wafer. Alternatively, the bias circuit can be a shared bias circuit across both the top wafer and the bottom wafer.

[0067] Additionally or alternatively, the DC bias point adjustment capabilities can include a static adjustment of the bias voltage to compensate for the effects of manufacturing process parameters (e.g., global threshold voltage) that vary between chips. The static type of bias voltage adjustment can be achieved by using a bias circuit configured to sense the process parameters of the chip or wafer of the pixel circuit and provide a compensation voltage signal applied to correct or adjust the bias voltage. As disclosed herein, the adjustment of the bias voltage can prevent saturation and improve the dynamic range of the pixel circuit. In some embodiments, a pixel circuit or event sensor that includes a stacked wafer technology (i.e., two or more wafers) includes a bias circuit placed on the bottom wafer (e.g., a CMOS wafer). In other embodiments that include a stacked wafer technology, the bias circuit can be placed on the top wafer (e.g., a CIS wafer). In other embodiments that include a stacked wafer technology, the bias circuit can be placed on both the top wafer and the bottom wafer. Alternatively, the bias circuit can be a shared bias circuit across both the top wafer and the bottom wafer.

[0068] As a further alternative, the DC bias point adjustment capability may include an automatic dynamic adjustment of the bias voltage (e.g., DC bias voltage) of the pixel circuit in response to a continuous determination of the chip temperature, and a static adjustment of the bias voltage to compensate for the effects of manufacturing process parameters that vary between chips. An on-chip temperature-sensitive bias circuit configured to generate a temperature-dependent bias voltage signal may be used to sense the temperature of the pixel circuit, and the bias voltage is adjusted in response to fluctuations in the chip temperature. The static type of bias voltage adjustment may be implemented using the same bias circuit that is further configured to sense the process parameters of the chip or wafer of the pixel circuit and provide a compensation voltage signal that is further applied to correct or adjust the bias voltage. As disclosed herein, the adjustment of the bias voltage can prevent saturation and improve the dynamic range of the pixel circuit. In some embodiments of pixel circuits or event sensors that include stacked wafer technology (i.e., two or more wafers), the bias circuit may be placed on the bottom wafer (e.g., CMOS wafer). In other embodiments that include stacked wafer technology, the bias circuit may be placed on the top wafer (e.g., CIS wafer). In other embodiments that include stacked wafer technology, the bias circuit may be placed on both the top wafer and the bottom wafer. Alternatively, the bias circuit may be a shared bias circuit that spans both the top wafer and the bottom wafer.

[0069] The benefits associated with the bias point adjustment capability are independent of whether a stacked configuration or a non-stacked configuration is employed. However, in some embodiments, further benefits can be achieved by utilizing a stacked configuration. For example, in 3D stacked implementations, the pixel circuit performance is even further improved. In addition to any DC bias point adjustment capability, with the disclosed stacked implementations, performance can be improved by using multiple interconnects per pixel to optimally distribute circuit components between different wafers. These and other features will be described herein with reference to the illustrated example embodiments.

[0070] Figures 2A to 2D A schematic representation of an example of a pixel circuit 100 in accordance with embodiments of the present disclosure is provided. The pixel circuit 100 may be implemented in a non-stacked configuration (e.g., Figure 2A ) or a stacked configuration (e.g., Figure 2B , Figure 2C and Figure 2D ). Further, as disclosed herein, the pixel circuit 100 may be used to implement an event-based vision sensor or a similar vision system. According to these embodiments, the pixel circuit 100 may provide several advantages, including improved gain boosting characteristics and an automatic adjustment capability for the bias voltage.

[0071] In Figures 2A to 2DIn [description], the pixel circuit 100 includes a photosensitive element 101 configured to generate a current signal in response to the luminance of light incident on the photosensitive element 101. The pixel circuit 100 further includes: a first N-type transistor 107; a second N-type transistor 108; a first P-type transistor 110 including a gate connected to a first bias voltage (“bias_pr”) 103; and a second P-type transistor 102 (e.g., a PMOS transistor) including a gate connected to a second bias voltage (“bias_fes”) 104. The second bias voltage 104 may be an adjustable DC bias voltage. For example, the bias voltage may be automatically adjusted according to temperature and / or statically adjusted according to manufacturing process parameter variations.

[0072] For example, the second bias voltage may be a DC bias voltage that is automatically adjusted in response to fluctuations in the chip temperature. In some embodiments, an on-chip temperature-sensitive bias circuit may be used to continuously sense the chip temperature of the pixel circuit and automatically adjust the bias voltage (e.g., the second bias voltage of the pixel circuit) in response to the chip temperature. As another example, the bias voltage may be statically adjusted (e.g., at a certain time or before using the pixel circuit) to cope with manufacturing process parameter variations (e.g., global threshold voltage) and prevent saturation and / or improve the dynamic range of the pixel circuit. For example, in some embodiments, a bias circuit may be used that is configured to sense the process parameters of the chip or wafer of the pixel circuit and adjust the bias voltage. The static type of bias voltage adjustment may provide compensation for the effects of process parameters that vary between chips. According to yet another example, the bias voltage may be automatically and dynamically adjusted in response to continuous sensing or determination of the chip temperature, and may be statically adjusted to compensate for the effects of manufacturing process parameters that vary between chips. Thus, in some embodiments, a bias circuit may be used that is configured to continuously sense the chip temperature of the pixel circuit and automatically adjust the bias voltage in response to the chip temperature, and sense the process parameters of the chip or wafer of the pixel circuit and further adjust the bias voltage. As disclosed herein, a compensation voltage signal may be generated by the bias circuit and applied to adjust the bias voltage (e.g., the second bias voltage of the pixel circuit).

[0073] The first N-type transistor 107 may have a first terminal (e.g., source) connected to a first terminal (e.g., source) of the second P-type transistor 102. The first N-type transistor 107 may have a second terminal (e.g., drain) connected to a drain supply voltage (VDD). The second N-type transistor 108 may have a first terminal (e.g., drain) connected to the gate of the first N-type transistor 107. The second N-type transistor 108 may have a second terminal (e.g., source) connected to ground. The second N-type transistor 108 may have its gate connected to a second terminal (e.g., drain) of the second P-type transistor 102 and the photosensitive element 101.

[0074] As Figures 2A to 2D further shown, the pixel circuit 100 includes a voltage output (“Vpr_out”) 105 that varies in response to the luminance (i.e., illuminance) of light incident on the photosensitive element 101. When implemented in a stacked configuration, the pixel circuit 100 may also include one or more interconnections 106 between the wafers, as Figures 2B to 2D shown and described elsewhere in the present disclosure. For example, depending on the number and arrangement of circuit components, there may be (a) connection(s) between the top wafer and the bottom wafer. The top wafer (including, for example, the photosensitive element 101) may be fabricated using a specialized CMOS image sensor (CIS) semiconductor manufacturing process, while the bottom wafer (including, for example, the other components of the pixel circuit 100) may be fabricated using a high-performance analog CMOS semiconductor manufacturing process. In other embodiments, both the top wafer and the bottom wafer are CMOS wafers. Figure 2B An exemplary pixel circuit is shown, where the photosensitive element 101 is implemented on the top wafer and where the other components of the pixel circuit are implemented on the bottom wafer. Figure 2C Another exemplary pixel circuit is shown, where the photosensitive element 101, the first N-type transistor 107, and the second N-type transistor 108 are implemented on the top wafer and where the other components of the pixel circuit are implemented on the bottom wafer. In Figure 2C the example shown, the top wafer is a CIS wafer and the bottom wafer is a CMOS wafer, where the interconnection 106 provides an electrical connection between the top wafer and the bottom wafer. Figure 2D An exemplary pixel circuit is shown, where the photosensitive element 101, the first P-type transistor 110 with its gate connected to a first bias voltage (“bias_pr”) 103, the second P-type transistor 102 with its gate connected to a second bias voltage (“bias_fes”) 104, the first N-type transistor 107, and the second N-type transistor 108 are implemented on the top wafer and where the other components (e.g., the output voltage 105) are implemented on the bottom wafer. In Figure 2D the example shown, the interconnection 106 provides an electrical connection between the top wafer and the bottom wafer. It will be understood through the present disclosure that other configurations are possible and Figures 2A to 2D non-limiting examples are provided.

[0075] In Figures 2A to 2DIn an example pixel circuit embodiment, the second P-type transistor 102 affects the gain boost by approximately two times (e.g., in the range of 1.5 to 2.5). Further, the adjustment of the second bias voltage 104 causes the DC level of the voltage output 105 to shift up or down without changing the overall gain of the pixel circuit 100. For example, the adjustment of the second bias voltage 104 allows the output voltage potential to be shifted based on variations in temperature and / or manufacturing process, thereby preventing the pixel circuit from entering the lower saturation region and the upper saturation region. For example, as Figure 9 shown, when adjusting the second bias voltage ("bias_fes") 104 as a function of temperature, the output voltage ("Vpr_out") 105 vs. contrast ("In") curve shifts arbitrarily little with temperature. The latter adjustment is as Figure 10 shown.

[0076] Figures 3A to 3B A schematic representation of an example of another pixel circuit 200 in accordance with embodiments of the present disclosure is provided. The pixel circuit 200 can be implemented in a non-stacked configuration (e.g., Figure 3A ) or a stacked configuration (e.g., Figure 3B ). The pixel circuit 200 can be used to implement an event-based vision sensor or a similar vision system as described herein.

[0077] The pixel circuit 200 includes a photosensitive element 201 configured to generate a current signal in response to the luminance of light incident on the photosensitive element 101. The pixel circuit further includes: a first N-type transistor 207; a second N-type transistor 208; a first P-type transistor 210 including a gate connected to a first bias voltage ("bias_pr") 203; and a second P-type transistor 202 (e.g., a PMOS transistor) including a gate connected to a second bias voltage ("bias_fes") 204. The second bias voltage 204 can be an adjustable DC bias voltage. For example, the bias voltage can be automatically adjusted according to temperature and / or statically adjusted according to manufacturing process parameter variations. To adjust the second bias voltage, the same techniques described above for adjusting the Figures 2A to 2D second bias voltage can be implemented to adjust the Figures 6A to 6B second bias voltage. Figures 3A to 3B The pixel circuit 200 of Figures 2A to 2B also includes a voltage output ("Vpr_out") 205 that varies in response to the luminance of light incident on the photosensitive element 201. Further, compared to the pixel circuit 100 of Figures 3A to 3B , the pixel circuit 200 of Figures 3A to 3BIn the example, the gate of the third N-type transistor 211 is shown connected to the second bias voltage 204. However, it will be understood from the present disclosure that the gate of the transistor 211 can be connected to another DC voltage source. In Figures 3A to 3B the embodiment, the third N-type transistor 211 provides the advantage of leakage compensation at low light levels incident on the photosensitive element 201. This leakage compensation allows for better control and linearization of the gain boost from the second P-type transistor 202 at low light levels.

[0078] As Figure 3B shown, the pixel circuit 200 can be arranged in a stacked configuration. When implemented in a stacked configuration, the pixel circuit 200 can include one or more interconnections 206 between the wafers. For example, depending on the number and arrangement of the circuit components, there may be (multiple) interconnections between the top wafer and the bottom wafer. The top wafer (including, for example, the photosensitive element 201) can be fabricated using a dedicated CMOS image sensor (CIS) semiconductor manufacturing process, while the bottom wafer (including, for example, the other components of the pixel circuit 200) can be fabricated using a high-performance analog CMOS semiconductor manufacturing process. In other embodiments, both the top wafer and the bottom wafer are CMOS wafers. It will be understood from the present disclosure that other configurations are possible, and Figures 3A to 3B non-limiting examples are provided.

[0079] In some embodiments of the pixel circuit 200, the second P-type transistor 202, the third N-type transistor 211, and one or more other components of the pixel circuit 200 are implemented in a non-stacked configuration in a common wafer (e.g., a CMOS wafer).

[0080] Figures 4A to 4B A schematic representation of another example of a pixel circuit 300 according to an embodiment of the present disclosure is provided. Figures 4A to 4B The embodiment can be implemented in a non-stacked configuration (e.g., Figure 4A ) or a stacked configuration (e.g., Figure 4B ). Further, Figures 4A to 4B the pixel circuit 300 can be used to implement an event-based vision sensor or a similar vision system as described herein.

[0081] Figures 4A to 4BThe pixel circuit 300 includes: a photosensitive element 301 configured to generate a current signal in response to the luminance of light incident on the photosensitive element 301; a first N-type transistor 307; a second N-type transistor 308; a first P-type transistor 310 having a gate connected to a first bias voltage (“bias_pr”) 303; and a second P-type transistor 302 (i.e., a PMOS transistor) including a gate connected to a bias voltage (“bias_fes”) 304. In some embodiments, the second bias voltage 304 is an adjustable DC bias voltage. For example, the bias voltage may be adjusted automatically according to temperature and / or statically adjusted according to manufacturing process parameter variations. To adjust the second bias voltage, the same techniques described above for adjusting Figures 2A to 2D the second bias voltage of Figures 6A to 6B can be implemented to adjust the second bias voltage of Figures 4A to 4B The pixel circuit 300 further includes a voltage output (“Vpr_out”) 305 that varies in response to the luminance of light incident on the photosensitive element 301 and a diode-connected N-type transistor 313 (e.g., an NMOS transistor) at the output voltage 305. In Figures 4A to 4B embodiments, the diode-connected N-type transistor 313 at the output voltage 305 allows for compensation of the body effect, thereby increasing the gain of any subsequent stage that receives the voltage output 305.

[0082] As Figure 4B further shown, the pixel circuit 300 can be arranged in a stacked configuration. When implemented in a stacked configuration, the pixel circuit 300 may include one or more interconnections 306 between wafers. For example, depending on the number and arrangement of circuit components, there may be (a) interconnection(s) between the top wafer and the bottom wafer. The top wafer (including, for example, the photosensitive element 301) may be fabricated using a specialized CMOS image sensor (CIS) semiconductor manufacturing process, while the bottom wafer (including, for example, the other components of the pixel circuit 300) may be fabricated using a high-performance analog CMOS semiconductor manufacturing process. In other embodiments, both the top wafer and the bottom wafer are CMOS wafers. It will be understood by this disclosure that other configurations are possible, and Figures 4A to 4B non-limiting examples are provided.

[0083] In some embodiments of the pixel circuit 300, the second P-type transistor 302 of the pixel circuit 300, the diode-connected N-type transistor 311 at the output voltage 305, and one or more other components are implemented in a common wafer in a non-stacked configuration.

[0084] Figures 5A to 5B A schematic representation of another example of a pixel circuit 400 according to an embodiment of the present disclosure is provided. Depending on the vision system and application (e.g., an event-based vision sensor, etc.), Figures 5A to 5BThe pixel circuit 400 can be implemented in various configurations. In some embodiments, the pixel circuit 400 is implemented as a non-stacked configuration (e.g., Figure 5A ) or a stacked configuration (e.g., Figure 5B ). Other configurations are possible, and it will be understood that Figures 5A to 5B non-limiting examples are provided.

[0085] The pixel circuit 400 includes: a photosensitive element 401 configured to generate a current signal in response to the luminance of light incident on the photosensitive element 401; a first N-type transistor 407; a second N-type transistor 408; a first P-type transistor 410 having a gate connected to a first bias voltage (“bias_pr”) 403; and a P-type transistor 402 (e.g., a PMOS transistor) having a gate connected to a bias voltage (“bias_fes”) 404. By way of example, the bias voltage 404 is an adjustable DC bias voltage. For example, the bias voltage can be automatically adjusted according to temperature and / or statically adjusted according to manufacturing process parameter variations. To adjust the second bias voltage, the same techniques described above for adjusting Figures 2A to 2D the second bias voltage of Figures 5A to 5B can be implemented to adjust the second bias voltage of

[0086] As Figures 5A to 5B further shown, the first N-type transistor 407 can have its gate connected to the first terminal (e.g., the drain) of the second N-type transistor 408. The second N-type transistor 408 can have a second terminal (e.g., the source) connected to ground. The second N-type transistor 408 can have its gate connected to the first terminal (e.g., the drain) of the second P-type transistor 402 and the first terminal (e.g., the drain) of a third N-type transistor 411. The first N-type transistor 407 can have a first end (e.g., the source) connected to the second end (e.g., the source) of the second P-type transistor 402, and the first N-type transistor 407 can have a second end (e.g., the drain) connected to a drain supply voltage (VDD).

[0087] The pixel circuit 400 further includes a voltage output (“Vpr_out”) 405 that varies in response to the luminance of light incident on the photosensitive element 401, a third N-type transistor 411 (e.g., an NMOS transistor) having a gate connected to a DC voltage (e.g., the bias voltage 404), and an additional diode-connected N-type transistor 413 at the output voltage 404. In Figures 5A to 5BIn the embodiment, the third N-type transistor 411 provides leakage compensation at the low light level incident on the photosensitive element 401. This leakage compensation allows for better control and linearization of the gain boost from the second P-type transistor 402 at the low light level. Additionally, the diode-connected N-type transistor 413 at the output voltage 405 allows for compensation of the body effect, thereby enhancing the gain of any subsequent stage receiving the voltage output 405.

[0088] As Figure 5B Further shown, the pixel circuit 400 may be arranged in a stacked configuration. When implemented in a stacked configuration, the pixel circuit 400 may include one or more interconnections 406 between the wafers. For example, depending on the number and arrangement of the circuit components, there may be (a) connection(s) between the top wafer and the bottom wafer. The top wafer (including, for example, the photosensitive element 401) may be fabricated using a dedicated CMOS image sensor (CIS) semiconductor manufacturing process, while the bottom wafer (including, for example, the other components of the pixel circuit 400) may be fabricated using a high-performance analog CMOS semiconductor manufacturing process. In other embodiments, both the top wafer and the bottom wafer are CMOS wafers. It will be understood from this disclosure that other configurations are possible, and Figures 5A to 5B non-limiting examples are provided.

[0089] In some embodiments of the pixel circuit 400, the third N-type transistor 411 is implemented in a common wafer together with the second P-type transistor 402 and any optional additional N-type transistors (such as transistors 407, 408, 413) and / or the photosensitive element 401. In some embodiments of the pixel circuit 400, the first N-type transistor 407, the second N-type transistor 408, the third N-type transistor 411, the diode-connected N-type transistor 413 at the output voltage 405, and the photosensitive element 401 are implemented on a common wafer. In some embodiments of the pixel circuit 400, the second P-type transistor 402 and one or more of the transistors 407, 408, 413 and / or the photosensitive element 401 are implemented in a non-stacked configuration in a common wafer. By way of example, the common wafer may be a first CMOS wafer or a CMOS image sensor (CIS) wafer. In some embodiments, the photosensitive element 401 in the pixel circuit 400 is implemented in a second CMOS wafer, and the first CMOS wafer is stacked relative to the second CMOS wafer. In some embodiments, the second P-type transistor 402 is implemented in a CMOS wafer, and this CMOS wafer is stacked relative to another CMOS wafer or relative to a CIS wafer.

[0090] As previously discussed, one or more interconnections may be provided between the wafers. For example, referring to the embodiment of the pixel circuit 400, at least one intra-pixel interconnection 406 may be provided between the first CMOS wafer and the second CMOS wafer. In some embodiments, there is more than one intra-pixel interconnection 406 between the first CMOS wafer and the second CMOS wafer. Alternatively, or additionally, a plurality of interconnections 406 may be provided between the first CMOS wafer and the second CMOS wafer. Other configurations with interconnections are possible and are within the scope of the present disclosure.

[0091] Figures 6A to 6B A schematic representation of an example of a further pixel circuit 500 according to an embodiment of the present disclosure is provided. Depending on the vision system and application (e.g., event-based vision sensors, etc.), Figures 6A to 6B the pixel circuit 500 may be implemented in various configurations. In Figures 6A to 6B the illustrated embodiment, the pixel circuit 500 is implemented in a stacked configuration with interconnections 506, as further described below.

[0092] The pixel circuit 500 includes: a photosensitive element 501 configured to generate a current signal in response to the luminance of light incident on the photosensitive element 501 (e.g., a photodiode); a first N-type transistor 507; a second N-type transistor 508; a first P-type transistor 510 having a gate connected to a first bias voltage (“bias_pr”) 503; and a second P-type transistor 502 (e.g., a PMOS transistor) having a gate connected to a second bias voltage (“bias_fes”) 504. By way of example, the second bias voltage 504 may be an adjustable DC bias voltage. For example, the bias voltage may be automatically adjusted according to temperature and / or statically adjusted according to manufacturing process parameter variations. To adjust the second bias voltage, the same techniques described above for adjusting Figures 2A to 2C the second bias voltage may be implemented to adjust Figures 6A to 6B the second bias voltage. Figures 6A to 6B The pixel circuit 500 of

[0093] also includes a voltage output (“Vpr_out”) 505 that varies in response to the luminance of light incident on the photosensitive element 501, a third N-type transistor 511 (e.g., an NMOS transistor) having a gate connected to a DC voltage (e.g., the second bias voltage 504), and a diode-connected N-type transistor 513 (i.e., a fourth N-type transistor) at the output voltage 505.

[0093] As Figures 6A to 6BFurther shown, the pixel circuit 500 can be implemented with a stacked configuration of interconnects 506. In some embodiments, a plurality of interconnects 506 are provided between wafers (e.g., an upper wafer and a lower wafer, or a CIS wafer and a CMOS wafer). The number and arrangement of the interconnects 506 can depend on the position and arrangement of the components of the pixel circuit 500 relative to each other and / or the wafers. For example, as Figure 6B shown in the exemplary embodiment of, the photosensitive element 501 and the N-type transistors 507, 508, 511, and 513 are located on the CIS wafer, while the P-type transistors 502 and 510, the bias voltages 504 and 503, and the voltage output 505 are located on one or more CMOS wafers, with four interconnects 506 positioned between the CMOS wafer and the CIS wafer.

[0094] The exemplary pixel circuit 500 can provide several advantages, including leakage compensation at low light levels incident on the photosensitive element 501, thereby better controlling and linearizing the gain boost from the second P-type transistor 502 at low light levels (due to the third N-type transistor 511). Additionally, the pixel circuit 500 can provide compensation for the body effect, thereby increasing the gain of any subsequent stage receiving the voltage output 505 (due to the diode-connected N-type transistor 513), and increasing the processing power generated by the first N-type transistor 507 and the second N-type transistor 508. Embodiments of the pixel circuit 500 also provide the opportunity to use different manufacturing processes for different wafers to minimize the pixel size while maximizing the overall pixel density (due to the stacked implementation). With the pixel circuit 500, the pixel gain and contrast sensitivity can also be further optimized due to the multiple pixel interconnects 506.

[0095] Figures 7A to 7B A schematic representation of an example of other pixel circuits according to embodiments of the present disclosure is provided.

[0096] Reference Figure 7A, an example pixel circuit 600 is disclosed. The pixel circuit 600 and any of the above example embodiments of the pixel circuit can be used alone or in combination with other components to implement the front-end circuit of an event-based vision sensor. For example, the pixel circuit 600 includes a current-voltage (I / V) converter, which includes an amplifier 611, a transistor 602, and a feedback transistor 607, and is configured to receive a current signal from a photosensitive element 601 and generate a voltage signal (at "Vpr_out") 605 based on the received current signal. The amplifier 611 itself includes one or more N-type transistors (e.g., transistor 508 and optionally transistor 513) and a P-type transistor having a gate connected to a bias voltage (e.g., transistor 510 and bias voltage 503). The pixel circuit 600 further includes: a first capacitor 612, which is serially electrically coupled to the converter (via a buffer 603) and is configured to receive the voltage signal (at "Vpr_out") 605 from the converter; and an amplifier 616, which is serially electrically coupled to the first capacitor 612 at the input and is configured to generate an amplified signal at the output based on the output signal from the first capacitor 612.

[0097] In Figures 7A to 7B the embodiment, the gate of the transistor 602 is connected to a bias voltage 604, such as a DC bias voltage ("bias_fes"). For example, the bias voltage 604 can be an adjustable DC bias voltage. For example, the bias voltage can be automatically adjusted according to temperature and / or statically adjusted according to manufacturing process variations. To adjust the bias voltage, the same techniques described above for adjusting Figures 2A to 2D the second bias voltage can be implemented to adjust Figures 7A to 7B the bias voltage 604.

[0098] The pixel circuit 600 can be implemented using various configurations, including a stacked arrangement with one or more interconnects. For example, according to Figure 7A the embodiment, the I / V converter (including the amplifier 611, the transistor 602, and the feedback transistor 607) and the first capacitor 612 can be implemented in a CMOS wafer together with the buffer 603, the amplifier 616, and / or other components. Additionally, the CIS wafer can be provided with the remaining components of the pixel circuit 600, such as the photosensitive element 601.

[0099] Now referring to Figure 7B , another embodiment of the pixel circuit 600 is provided, which employs a stacked configuration with an interconnect 606. For example, as Figure 7BAs shown, the pixel circuit 600 may include a second capacitor 614 in parallel with the first capacitor 612. The second capacitor 614 may be implemented together with the photosensitive element 601 in one or more CIS wafers and connected to the first capacitor 612 in the CMOS wafer through at least two interconnections 606 between two or more wafers.

[0100] According to embodiments of the present disclosure, a stacked wafer implementation of the pixel circuit (100 - 600) may provide many benefits. For example, a stacked implementation of the pixel circuit: (i) may reduce the pixel size by placing the pixel circuit under the photosensitive element while also maximizing the photosensitive area (i.e., maximizing the fill factor of the pixel), and (ii) enables the use of optimized manufacturing process technologies that may vary for each part of the stacked implementation. One or more interconnections per pixel may be used to implement such a stacked implementation. If only one interconnection is provided per pixel, adding a P-type transistor (e.g., Figures 2A to 2D the P-type transistor 102 in Figures 6A to 6B in Figure 7B the interconnection 606 in

[0101] in the pixel circuit will result in a partitioning requirement that places the photosensitive element only on the upper wafer (e.g., the CIS wafer). In the case of multiple interconnections per pixel (e.g., two or more interconnections per pixel, such as Figures 6A to 6B the interconnection 506 in Figures 6A to 6B or Figure 11 the interconnection 606 in Figure 11 ), this partitioning requirement is eliminated.

[0102] Referring again to Figures 6A to 6B where the pixel circuit 500 shown includes a combination of two P-type transistors 502, 510 and four N-type transistors 507, 508, 511, and 513. The pixel circuit 500 may be implemented using a stacked configuration of wafers. For example, the photosensitive element 501 and the four N-type transistors 507, 508, 511, and 513 may be located on the CIS wafer, and multiple interconnections 506 (e.g., four interconnections) may be provided between the CMOS wafer and the CIS wafer (as Figure 11The wafers 1001 and 1002). In this configuration, the adjustable second bias voltage 504, P-type transistors 502, 510, and the output voltage 505 can be located on the CMOS wafer.

[0103] If multiple interconnections per pixel are available, the photodiodes or other photosensitive elements and all N-type transistors can be located on a common wafer such as a CIS wafer. The main advantage of this partitioning is that the CIS N-type devices can be optimized for joint operation with the photosensitive elements. With this architecture, the photosensitive elements and the connected N-type transistors can share the same diffusion, and the photosensitive elements can avoid direct connection to the large parasitic capacitances associated with hybrid bonding and the transition from one wafer to another. Figure 6B The exemplary partitioning shown places the photosensitive element 501 and four N-type transistors 507, 508, 511, and 513 in the CIS wafer and places the P-type transistors 502, 510 in the CMOS wafer, as described above.

[0104] In Figure 7B In an embodiment, more than one interconnection 606 is provided per pixel, so the area and metal available on the CIS wafer can be used to increase the capacitance of the downstream part of the full pixel circuit (i.e., the combined capacitors 612 and 614). Increasing this capacitance also increases the overall pixel gain, thereby improving the contrast sensitivity. Specifically, as Figure 7B shown, the pixel circuit 600 includes a first capacitor 612 in parallel with a second capacitor 614. The second capacitor 614 can be implemented in the CIS wafer and connected to the first capacitor 612 implemented on the CMOS wafer through at least two interconnections 606. The combination of the first capacitor 612 and the second capacitor 614 increases the capacitance of, for example, the downstream amplifier 616, thereby increasing the overall gain of the pixel circuit 600.

[0105] Referring to Figure 8 , a schematic representation of an example of another pixel circuit 700 according to an embodiment of the present disclosure is provided. Figure 8 The arrangement of the components of the pixel circuit 700 is shown. For example, the pixel circuit 700 includes: an I / V converter including an amplifier 711, a transistor 702, and a feedback transistor 707; a second amplifier 716; comparators 726 and 728; a first capacitor 717; a second capacitor 712; and a logic block (e.g., implemented using latches) 738, all of which are located on a common wafer such as a CMOS wafer. The pixel circuit 700 also includes a photosensitive element 701 and a third capacitor 714 implemented on another wafer such as a CIS wafer. Using Figure 8The pixel circuit 700 can achieve increased pixel gain by using multiple interconnections 706 between wafers (e.g., between a CMOS wafer and a CIS wafer) and adding capacitance via a third capacitor 714. It will be understood from this disclosure that other configurations and arrangements are also possible, and Figure 8 are non-limiting examples.

[0106] In Figure 8 an embodiment, the gate of transistor 702 is connected to a bias voltage 704, such as a DC bias voltage ("bias_fes"). By way of example, the bias voltage 704 can be an adjustable DC bias voltage. For example, the bias voltage can be automatically adjusted according to temperature and / or statically adjusted according to manufacturing process variations. To adjust the bias voltage, the same techniques described above for adjusting Figures 2A to 2C the second bias voltage can be implemented to adjust Figure 8 the bias voltage 704.

[0107] In Figure 8 an example pixel circuit embodiment, the P-type transistor 702 can provide a gain boost of approximately two times (e.g., in the range of 1.5 to 2.5). Adjusting the bias voltage 704 applied to the gate of transistor 702 can cause the DC level of the voltage output 705 ("pr_out") to shift up or down without changing the overall gain of the pixel circuit 700. For example, adjusting the bias voltage 704 allows the potential of the output voltage 705 to be shifted based on temperature or variations in the manufacturing process employed. This shift in the output voltage potential can prevent the pixel from entering the upper saturation region or the lower saturation region. As Figure 9 shown by curve 810 in Figure 8 , by adjusting the bias voltage ("bias_fes") as a function of temperature (e.g., 704 in Figure 10 and the bias voltages in other example pixel circuits herein), the shift of the output voltage ("Vpr_out") versus illumination ("In") curve based on temperature can be made arbitrarily small.

[0108] In embodiments of the pixel circuits described herein, adjusting the bias voltage (e.g., 704 in Figure 8 ) applied to a second P-type transistor (e.g., 702 in Figure 8 ) as a function of temperature can prevent entry into the upper saturation region or the lower saturation region, thereby improving the dynamic range of the pixel circuit. Advantageously, capacitor 714 in combination with capacitor 712 increases the capacitance stage of the second amplifier 716, and in combination with capacitor 717 further increases the overall gain of the pixel circuit 700. Figure 9The curve 810 shows any small offset of the output voltage contrast curve due to temperature changes, and as a result, any part of the curve does not enter the upper saturation region and the lower saturation region. Any small offset of the output voltage contrast curve and the non-entry into the upper saturation region and the lower saturation region form an optimization of the dynamic range of the pixel circuit, which is in line with the embodiments of the present disclosure. Moreover, the gain boost of approximately twice (e.g., in the range of 1.5 to 2.5) achieved by the second P-type transistor, the N-type transistor, and the pixel not entering the upper saturation region and the lower saturation region results in an increased contrast sensitivity of the pixel circuit.

[0109] In some embodiments of any pixel circuit described herein, depending on manufacturing process variations, the adjustment of the bias voltage (e.g., Figure 8 704 in Figure 8 ), implemented via the second P-type transistor (e.g.,

[0110] Figure 11 Figure 1000 shows an exemplary 3D stacked configuration for implementing a pixel circuit in accordance with the disclosed embodiments. As Figure 11 shown, the stacked configuration includes four interconnections 1006 between a top wafer 1001 (e.g., a CIS wafer) and a bottom wafer 1002 (e.g., a CMOS wafer). As disclosed herein, such a stacked implementation of the pixel circuit can provide at least two advantages: (i) it can reduce the pixel size by placing the pixel circuit under the photosensitive element while also maximizing the photosensitive area (i.e., maximizing the fill factor of the pixel), and (ii) it enables the use of optimized manufacturing process technologies that can be different for each part of the stacked implementation. One or more interconnections per pixel can be used to implement such a stacked implementation. If only one interconnection is provided per pixel, adding a second P-type transistor (e.g., Figure 8 the P-type transistor 702 in

[0111] Figure 12 Figure 1000 shows a configuration for dynamically and / or statically adjusting a pixel circuit (e.g., Figure 2AAn example bias circuit 1200 for a bias voltage (e.g., of the pixel circuit described herein or other exemplary pixel circuits). The bias circuit 1200 can be configured to generate a bias voltage (“bias_fes”) 1204 as an output supplied to the pixel circuit. By setting appropriate values for the current reference “Iref” (i.e., a programmable current source) and the voltage reference “Vref” (i.e., a programmable voltage source), the bias voltage 1204 can be statically set and / or adjusted for the manufacturing process parameters associated with the pixel circuit. Additionally, or alternatively, the bias voltage 1204 can be automatically adjusted in response to the chip temperature of the pixel circuit. As disclosed herein, this can provide dynamic adjustment of the bias voltage to account for temperature fluctuations within the pixel circuit. Thus, the bias circuit 1200 can be implemented to supply a bias voltage to the pixel circuit to ensure that, for a given photocurrent, the variability of the output voltage (“Vpr_out”) of the pixel circuit due to variations in manufacturing process parameters and / or temperature fluctuations is minimized. Adjustment of the bias voltage increases the unsaturated operating range of pixel circuit saturation, thereby improving pixel sensitivity and / or the dynamic range of the pixel circuit.

[0112] For example, manufacturing process parameters can vary based on whether the combination of P-type and N-type transistors in a given pixel circuit includes fast or slow transistors, such as fast NMOS / fast PMOS (FnFp), fast NMOS / slow PMOS (FnSp), slow NMOS / fast PMOS (SnFp), and slow NMOS / slow PMOS (SnSp). Compared to values of a typical manufacturing process, slow transistors are associated with an increase in threshold voltage, while fast transistors are associated with a decrease in threshold voltage compared to values of a typical manufacturing process. Due to the various combinations of transistors and their different effects on the threshold voltage, variations in the output voltage can occur based on the specific transistors fabricated within the pixel circuit. By ensuring that the P-type and N-type transistors in the pixel circuit correspond to the P-type and N-type transistors in the bias circuit 1200, the bias circuit includes P-type and N-type transistors having the same manufacturing parameters as the P-type and N-type transistors in the pixel circuit. Thus, the bias circuit 1200 is capable of applying an appropriate adjustment to the bias voltage supplied to the connected pixel circuit to handle variations in manufacturing parameters, thereby minimizing variations in the output voltage of the connected pixel circuit by canceling or accounting for the voltage effects of the connected pixel circuit due to its specific manufacturing parameters. See Figures 13 to 20 , for further description and examples of the operation and effects of a bias circuit in accordance with the disclosed embodiments with respect to variations in manufacturing parameters.

[0113] In addition to the effects of varying manufacturing parameters, the output voltage of the exemplary pixel circuits disclosed herein may also be dependent on the temperature of the pixel circuits due to the thermal voltage associated with the pixel circuits. Due to this dependence on the chip temperature, the bias circuit 1200 can also be used to adjust the bias voltage provided to the pixel circuits in response to temperature fluctuations. For example, by adjusting the bias voltage (“bias_fes”) 1204 in response to temperature, the bias circuit 1200 can be configured to cause an upward shift in the output voltage of the pixel circuits for higher temperatures and a downward shift in the output voltage of the pixel circuits for lower temperatures. Thus, the maximum amount of variation in the output voltage of the pixel circuits can be further reduced. Moreover, by ensuring that the P-type and N-type transistors in the pixel circuits correspond in type to the P-type and N-type transistors in the bias circuit 1200, the bias circuit is configured to include P-type and N-type transistors having the same thermal characteristics as the P-type and N-type transistors in the pixel circuits. Thus, the bias circuit 1200 is able to sense the same temperature fluctuations as the connected pixel circuits experience. By setting appropriate values for the current reference “Iref” (i.e., the programmable current source) and the voltage reference “Vref” (i.e., the programmable voltage source), the bias circuit 1200 can automatically adjust the bias voltage 1204 provided to the connected pixel circuits to handle temperature fluctuations. The effect of such adjustment is to minimize the variation in the output voltage of the connected pixel circuits by canceling or accounting for the variation in the voltage of the connected pixel circuits due to chip temperature fluctuations. See Figures 13 to 20 , for a further description and examples of the operation and effects of a bias circuit in accordance with the disclosed embodiments with respect to temperature fluctuations.

[0114] Referring more specifically to Figure 12 the example embodiment of, the bias circuit 1200 can include a P-type transistor 1202 in diode configuration (i.e., the gate and source of the transistor are connected) and an N-type transistor 1207 in diode configuration. As Figure 12 shown, the P-type transistor 1202 and the N-type transistor 1207 can be arranged in series. Further in accordance with the above description, the transistors 1202 and 1207 can correspond (e.g., in type or kind) to the P-type and N-type transistors in the connected pixel circuits, respectively. For example, the P-type transistor 1202 can correspond to the P-type transistor 102 of the exemplary pixel circuit 100 as Figure 2A shown, while the N-type transistor 1207 can correspond to the Figure 2Acorresponds to the N-type transistor 107 of the exemplary pixel circuit 100 shown. Additionally, to set and / or further adjust the bias voltage 1204, the bias circuit 1200 may include a programmable voltage source 1240 (“Vref”) and a programmable current source 1250 (“Iref”). For example, the programmable voltage source or programmable current source may be implemented by one or more DACs (digital-to-analog converters) configured to convert a digital input or literal into an analog signal (e.g., a target voltage or current). Further, to set and / or program the programmable voltage and / or current source, one or more registers may be used in combination with one or more DACs, where the (multiple) registers store values in a digital format corresponding to analog values. As an example, for the programmable voltage source, a linear relationship between the digital input and the analog voltage output may be used. As another example, for the programmable current source, a logarithmic relationship between the digital input and the analog current output may be used (due to a wider range). In some embodiments, the programmable voltage source and programmable current source may remain constant in response to a temperature change.

[0115] As an example, the voltage output of the bias circuit may be set to a value for which, within the specified operating range of the connected pixel circuit (e.g., a temperature range of -25 degrees Celsius to 85 degrees Celsius and an illumination range of, for example, 1 fA to 1 nA), the output voltage of the pixel circuit will never be lower than a certain voltage with respect to ground (GND) (e.g., 0.1 V above GND). This is the case for the entire operating range of the pixel circuit, even for the most severe manufacturing process parameter variations. In some embodiments, the current source “I ref ” may be set or programmed in a first step to achieve a preferred intercept point of the “V pr_out (I ph , temperature)” curve (see, for example, Figure 18 and Figure 19 ), and in a second step, the voltage source “V ref” may be set or programmed to offset the voltage output of the bias circuit to meet the desired conditions for the output voltage of the pixel circuit (e.g., the conditions discussed above related to the output voltage of the pixel circuit with respect to ground (GND)).

[0116] In some embodiments, the programmable voltage source 1240 may be set or adjusted based on the voltage supply (VDD) of the connected pixel circuit (e.g., Figure 2A the exemplary pixel circuit 100 shown or other example pixel circuits disclosed herein) to additionally automatically adjust the output voltage of the connected pixel circuit based on an offset of the voltage supply of the connected pixel circuit. In some embodiments, a voltage buffer (e.g., a low output impedance voltage buffer — Figure 12(not shown) can also be positioned between the output voltage 1204 of the bias circuit and the corresponding input of the connected pixel circuit to provide an improved bias voltage supply to the connected pixel circuit.

[0117] According to an embodiment of the present invention, the bias voltage V of a bias circuit (such as the bias circuit 1200 of the exemplary embodiment of the present application) Figure 12 can be calculated as: bias_fes

[0118] V b"#$_fe$ = V (ef - V GS,n,b - V SG,-,b (1), where the gate-source voltage V of the N-type transistor and the source-gate voltage V of the P-type transistor are used. See, for example, GS,n SG,p Figure 12

[0119] In some embodiments, for an N-type transistor in the saturated subthreshold operation region, the dependence of the drain current (I D ) on the voltage V GS can be described as:

[0120]

[0121] where the width W n and length L n of the transistor, the subthreshold slope n n , the carrier mobility μ n , the gate oxide capacitance C ox , the thermal voltage V T and the threshold voltage V th are used.

[0122] In some embodiments, for an N-type transistor in a given pixel circuit, the main effect of the variation of the manufacturing process parameters may be related to the variation ΔV th of the threshold voltage. From Equation 2, the following can be obtained:

[0123]

[0124] where there can also be the following relationship:

[0125]

[0126] Equation 3 can also be expressed as:

[0127]

[0128] Thus, for a P-type transistor, Equation 5 can correspond to:

[0129]

[0130] In some embodiments, the output voltage V in the pixel circuit pr_out can be calculated as follows:

[0131] V pr_out = V bias + V GS,n,p + V SG,p,p (7).

[0132] Substituting the relationships of Equation 5 and Equation 6 into Equation 7 gives the following:

[0133]

[0134] where I ph is the photocurrent inside the pixel circuit.

[0135] Similarly, substituting the relationships of Equation 5 and Equation 6 into Equation 1 gives the following:

[0136]

[0137] By substituting the value of V bias_fes in Equation 9 into Equation 8, the P-type and N-type transistors in the bias circuit (related to the similar P-type and N-type transistors in the connected pixel circuit) can cause the variation of the threshold voltage caused by the change of manufacturing process parameters (i.e., process corner) to be eliminated for the output voltage V pr_out of the pixel circuit, as shown below:

[0138]

[0139] Figure 13 Shows a graph of V ph as a function of the photocurrent I pr_out ranging from 1 fA to 1 nA extracted from circuit simulation, where the controlled V bias_fes is for different process corners. In the Figure 13 example, V ref is set to 0.85 V, I ref = 1 pA, and T = 25 C. Figure 13 The 5 curves shown in the graph of th represent 5 process corners (i.e., fast nmos / fast pmos (FnFp), fast nmos / slow pmos (FnSp), slow nmos / fast pmos (SnFp), slow nmos / slow pmos (SnSp)) and typical process parameters. Compared with the values of the typical process, "slow" means an increase in the threshold voltage (+ΔV th ), while "fast" means a decrease in the threshold voltage (-ΔVth )。

[0140] In Figure 13 the example of pr_out for a given photocurrent I ph the maximum variation within 6 decimal places is only 32 mV.

[0141] In contrast, Figure 14 shows the results of simulations performed for different process corners at a constant bias voltage V bias_fes of 0.55 V. In both simulations, the value of 0.55 V is the same for V pr_out (I ph ) with typical process parameters. V pr_out In Figure 14 the example of Figure 13 the maximum variation is 196 mV, which is much larger than the value of the controlled bias voltage example of

[0142] Figure 15 shows the variation of V Figure 12 of a bias circuit (such as the bias circuit 1200 illustrated in bias_fes ) as described by Equation 9 depending on the process corner.

[0143] According to Equation 9 and Equation 10, V ref can be used to offset V bias_fes and V pr_out respectively. Figure 16 shows the V ref at 0.85 V, 0.95 V, and 1.05 V, typical process parameters, I pr_out (I ph ) curve graph at = 1 pA and T = 25°C. If V ref is referenced to VDD, it allows ensuring a minimum voltage difference between the maximum value of V pr_out and VDD independent of VDD to avoid circuit saturation at high photocurrents for low VDD values.

[0144] According to Equation 8, the value of V pr_out as a function of I ph and the slope of the curve shows a strong temperature dependence due to the thermal voltage V T . The thermal voltage is defined as V T = kT / q, where the Boltzmann constant k, the elementary charge q, and the temperature T are used. Figure 17 shows at a constant voltage V bias_fes (0.55 V) and typical process parameters (ΔV 日At (V = 0), for three different temperatures: -25 degrees Celsius, 25 degrees Celsius, and 75 degrees Celsius, V pr_out as a function of photocurrent I from 1 fA to 1 nA ph graph. In this example, V pr_out for a given photocurrent I ph has a maximum change of up to 595 mV, while for low photocurrents, V pr_out enters saturation near 0 V, which prevents the pixel circuit from operating correctly.

[0145] A bias circuit (such as Figure 12 the bias circuit 1200 shown) shifts the V pr_out curve upward for higher temperatures and shifts the curve V pr_out downward for lower temperatures. Thus, the overall maximum change in V pr_out may be reduced. Since similar P-type and N-type transistors in the pixel circuit and the bias circuit have the same thermal characteristics, according to Equation 10, this reduction in the change of V pr_out can be achieved by applying an appropriate value for I ref One option is to select I ref to set the intercept point of the curve to near the middle value of the photocurrent range. Figure 18 shows at I ref = 1 pA and typical process parameters (ΔV th = 0), for three different temperatures: -25 degrees Celsius, 25 degrees Celsius, and 75 degrees Celsius, V pr_out as a function of photocurrent I from 1 fA to 1 nA ph graph. Compared to a scheme including a constant bias voltage V bias_fes , the maximum change in V pr_out is 280 mV, which is lower. Additionally, any saturation at low light can be avoided. The intercept point of the curve is near I ph = 1 pA. I ref can also be used to shift the intercept point of the curve to achieve specific behavior.

[0146] Figure 19 shows at I ref = 100 pA and typical process parameters (ΔV th = 0), for three different temperatures: -25 degrees Celsius, 25 degrees Celsius, and 75 degrees Celsius, V pr_out as a function of photocurrent I from 1 fA to 1 nA ph graph. In this example, the intercept point moves to I ph = 100 pA, which on one hand increases the maximum change in V pr_out for low photocurrents, but on the other hand also significantly reduces Vpr_out Variations for higher photocurrent. In Figure 19 the example of ref V changes from 0.85V to 1.2V to achieve the same value of V ref (I ref = 1pA and I pr_out (I ph ) at T = 25C in both simulations.

[0147] Figure 20 Shows the change of V bias_fes depending on temperature for V ref = 0.85V and I ref = 1pA as described in Equation 9.

[0148] Although illustrative embodiments have been described herein, the scope includes any and all embodiments having equivalent elements, modifications, omissions, combinations, adaptations and / or alterations (e.g., aspects of various embodiments) based on the present disclosure. Elements in the claims will be construed broadly based on the language employed in the claims and not limited solely to the examples described in the specification or during the prosecution of the application, which examples are to be construed as non-exclusive. Further, the steps of the disclosed methods may be modified in any way, including reordering steps and / or inserting or deleting steps.

[0149] The features and advantages of the present disclosure become apparent from the detailed description, and thus the appended claims are intended to cover all systems and methods within the true spirit and scope of the present disclosure. As used herein, the indefinite articles "a" and "an" mean "one or more". Similarly, the use of plural terms does not necessarily indicate plurality unless it is unambiguous in a given context. Words such as "and" or "or" mean "and / or" unless specifically stated otherwise. Further, since many modifications and variations will be readily apparent by studying the present disclosure, it is not intended to limit the present disclosure to the exact construction and operation shown and described, and thus all suitable modifications and equivalent forms may be subsumed within the scope of the present disclosure.

[0150] Other embodiments will be apparent to those skilled in the art in view of the specification and practice of the embodiments disclosed herein. The architectures and circuit arrangements shown in the figures are intended for illustrative purposes only and are not intended to be limited to the specific arrangements and circuit arrangements described and shown in the figures. The specification and examples should also be considered only exemplary, and the true scope and spirit of the invention are indicated by the following claims.

Claims

1. A pixel circuit for use with an event sensor, the pixel circuit comprising: A photosensitive element configured to generate a current signal in response to the luminance of light incident on the photosensitive element; A first N-type transistor; A second N-type transistor; A first P-type transistor, the first P-type transistor including a gate connected to a first bias voltage; A second P-type transistor, the second P-type transistor including a gate connected to a second bias voltage, the second bias voltage being a DC bias voltage adjusted in response to at least one of the chip temperature or manufacturing process variations of the pixel circuit; And A voltage output that varies in response to the luminance of light incident on the photosensitive element; Wherein, the adjustment of the second bias voltage increases the non-saturation operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit.

2. The pixel circuit according to claim 1, wherein, The adjustment of the second bias voltage causes the DC level of the voltage output to shift upward or downward without changing the overall gain of the pixel circuit.

3. The pixel circuit according to claim 1 or 2, wherein, The second P-type transistor affects the gain boost by approximately two times.

4. The pixel circuit according to any one of the preceding claims, comprising a temperature-sensitive bias circuit configured to continuously sense the chip temperature of the pixel circuit for automatically adjusting the second bias voltage.

5. The pixel circuit according to claim 4, wherein, The temperature-sensitive bias circuit comprises: A third P-type transistor in series with a third N-type transistor; A programmable current source; and A programmable voltage source; Wherein, the third P-type transistor corresponds to the second P-type transistor; and Wherein, the third N-type transistor corresponds to the first N-type transistor.

6. The pixel circuit according to any one of the preceding claims, comprising a bias circuit, and wherein, The manufacturing process variations include global threshold variations detected by the bias circuit and used for static adjustment of the second bias voltage.

7. The pixel circuit according to claim 6, wherein, The bias circuit comprises: A third P-type transistor in series with a third N-type transistor; A programmable current source; and A programmable voltage source; Wherein, the third P-type transistor corresponds to the second P-type transistor; and Wherein, the third N-type transistor corresponds to the first N-type transistor.

8. The pixel circuit according to any one of the preceding claims, wherein, The second P-type transistor, the first N-type transistor, the second N-type transistor, and one or more other components of the pixel circuit are implemented in a non-stacked configuration on a common wafer.

9. The pixel circuit according to any one of claims 1 to 7, wherein, The pixel circuit is implemented in a stacked configuration, wherein at least the photosensitive element is implemented on a first wafer, and wherein at least the first P-type transistor and the second P-type transistor are implemented on a second wafer.

10. The pixel circuit according to any one of the preceding claims, further comprising an N-type transistor at the voltage output.

11. The pixel circuit according to any one of the preceding claims, further comprising a third N-type transistor, the third N-type transistor including a gate connected to a DC voltage, wherein, The third N-type transistor provides leakage compensation at low light levels incident on the photosensitive element.

12. The pixel circuit according to claim 11, wherein, The third N-type transistor is implemented in a common wafer together with the first P-type transistor, the second P-type transistor, the first N-type transistor, and the second N-type transistor.

13. The pixel circuit according to claim 12, wherein, The common wafer comprises a first CMOS wafer.

14. The pixel circuit according to claim 13, wherein, The photosensitive element is implemented in the second CMOS wafer, and the first CMOS wafer is stacked relative to the second CMOS wafer.

15. The pixel circuit according to claim 14, wherein, There is at least one intra-pixel interconnection between the first CMOS wafer and the second CMOS wafer.

16. The pixel circuit according to any one of claims 11 to 15, wherein, The first N-type transistor, the second N-type transistor, the third N-type transistor, and the photosensitive element are implemented on a common wafer.

17. The pixel circuit according to claim 16, wherein, The common wafer includes a CMOS image sensor (CIS) wafer.

18. The pixel circuit according to claim 17, wherein, The first P-type transistor and the second P-type transistor are implemented in a CMOS wafer, and the CMOS wafer is stacked relative to the CIS wafer.

19. The pixel circuit according to claim 18, wherein, There are a plurality of interconnections between the CMOS wafer and the CIS wafer.

20. The pixel circuit according to any one of the preceding claims, further comprising: A converter, which is composed of the first P-type transistor and is configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; A first capacitor, which is serially electrically coupled to the converter and is configured to receive the voltage signal from the converter; And An amplifier, which is serially electrically coupled to the first capacitor at the input and is configured to generate an amplified signal at the output based on the output signal from the first capacitor.

21. The pixel circuit according to claim 20, wherein, The converter and the first capacitor are implemented in a CMOS wafer together with the second P-type transistor.

22. The pixel circuit according to any one of claims 17 to 19, further comprising a second capacitor connected in parallel with the first capacitor, the second capacitor is implemented in the CIS wafer and is connected to the first capacitor by using at least two interconnections between the CMOS wafer and the CIS wafer.

23. The pixel circuit according to claim 22, wherein, The second capacitor is combined with the first capacitor to increase the capacitance of the amplifier and increase the overall gain of the pixel circuit.

24. An event sensor having a plurality of pixels, each pixel including a pixel circuit, the pixel circuit comprising: A photosensitive element, which is configured to generate a current signal in response to the brightness of light incident on the photosensitive element; A first N-type transistor; A second N-type transistor; A first P-type transistor, the first P-type transistor includes a gate connected to a first bias voltage; A second P-type transistor, the second P-type transistor includes a gate connected to a second bias voltage, and the second bias voltage is a DC bias voltage adjusted in response to at least one of the chip temperature or manufacturing process variation of the pixel circuit; And A voltage output, which varies in response to the brightness of light incident on the photosensitive element; Wherein, the adjustment of the second bias voltage increases the non-saturation operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit.

25. The event sensor according to claim 24, wherein, The adjustment of the second bias voltage causes the DC level of the voltage output to shift up or down without changing the overall gain of the pixel circuit.

26. The event sensor according to claim 24 or 25, wherein The second P-type transistor affects the gain boost by approximately two times.

27. The event sensor according to any one of claims 24 to 26, comprising a temperature-sensitive bias circuit configured to continuously sense the chip temperature of the pixel circuit for automatically adjusting the second bias voltage.

28. The event sensor according to claim 27, wherein, The bias circuit includes: a third P-type transistor in series with a third N-type transistor; a programmable current source; and a programmable voltage source; wherein the third P-type transistor corresponds to the second P-type transistor; and wherein the third N-type transistor corresponds to the first N-type transistor.

29. The event sensor according to any one of claims 24 to 28, wherein, The manufacturing process variations include global threshold variations detected by the bias circuit and used for static adjustment of the bias voltage.

30. The event sensor according to claim 29, wherein, The bias circuit includes: a third P-type transistor in series with a third N-type transistor; a programmable current source; and a programmable voltage source; wherein the third P-type transistor corresponds to the second P-type transistor; and wherein the third N-type transistor corresponds to the first N-type transistor.

31. The event sensor according to any one of claims 24 to 30, wherein The photosensitive element, the second P-type transistor, and one or more other components of the pixel circuit are implemented in a non-stacked common wafer.

32. The event sensor according to any one of claims 24 to 31, further comprising a third N-type transistor, the third N-type transistor including a gate connected to a DC voltage, wherein, The third N-type transistor provides leakage compensation at a low light level incident on the photosensitive element.

33. The event sensor according to claim 32, wherein, The second P-type transistor, the third N-type transistor, and one or more other components of the pixel circuit are implemented in a non-stacked configuration in a common wafer.

34. The event sensor according to claim 32 or 33, wherein The event sensor is implemented in a stacked configuration, wherein at least the photosensitive element is implemented on a first wafer, and wherein at least the first P-type transistor and the second P-type transistor are implemented on a second wafer.

35. The event sensor according to any one of claims 32 to 34, wherein, The third N-type transistor is implemented in a common wafer together with the second P-type transistor, the first N-type transistor, and the second N-type transistor.

36. The event sensor according to claim 35, wherein, The common wafer includes a first CMOS wafer.

37. The event sensor according to claim 36, wherein, The photosensitive element is implemented in a second CMOS wafer stacked relative to the first CMOS wafer.

38. The event sensor according to claim 37, wherein, There is at least one intra-pixel interconnect between the first CMOS wafer and the second CMOS wafer.

39. The event sensor according to any one of claims 32 to 38, wherein, The first N-type transistor, the second N-type transistor, the third N-type transistor, and the photosensitive element are implemented on a common wafer.

40. The event sensor according to claim 39, wherein, The common wafer includes a CMOS image sensor (CIS) wafer.

41. The event sensor according to claim 40, wherein, The second P-type transistor is implemented in a CMOS wafer stacked relative to the CIS wafer.

42. The event sensor according to claim 41, wherein, There are a plurality of interconnects between the CMOS wafer and the CIS wafer.

43. The event sensor according to any one of claims 24 to 42, further comprising: a converter composed of the second P-type transistor and configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a first capacitor serially electrically coupled to the converter and configured to receive the voltage signal from the converter; and An amplifier that is electrically coupled in series to the first capacitor at an input and is configured to generate an amplified signal at an output based on an output signal from the first capacitor.

44. The event sensor according to claim 43, wherein, The converter and the first capacitor are implemented in a CMOS wafer together with the second P-type transistor.

45. The event sensor according to claim 44, further comprising a second capacitor connected in parallel to the first capacitor, the second capacitor being implemented in a CIS wafer and connected to the first capacitor by using at least two interconnects.

46. The event sensor according to claim 45, wherein, The second capacitor combines with the first capacitor to increase the capacitance of the amplifier and increase the overall gain of the pixel circuit.

47. The event sensor according to any one of claims 24 to 46, further comprising an N-type transistor at the voltage output.

48. A pixel circuit for use with an event sensor, the pixel circuit comprising: A photosensitive element configured to generate a current signal in response to the brightness of light incident on the photosensitive element; A first N-type transistor; A second N-type transistor; A P-type transistor comprising a gate connected to a bias voltage, the bias voltage being a DC bias voltage adjusted in response to at least one of the chip temperature or manufacturing process variations of the pixel circuit; And A voltage output that varies in response to the brightness of light incident on the photosensitive element; wherein the adjustment of the bias voltage causes the DC level of the voltage output to shift up or down without changing the overall gain of the pixel circuit; and wherein the adjustment of the bias voltage increases the non-saturation operating range of the pixel circuit, thereby improving the dynamic range of the pixel circuit.

49. The pixel circuit according to claim 48, further comprising a first P-type transistor, the first P-type transistor including a gate connected to a first bias voltage, and wherein, The P-type transistor is a second P-type transistor, the second P-type transistor comprising a gate connected to a second bias voltage, the second bias voltage comprising the DC bias voltage adjusted to prevent saturation and improve the dynamic range of the pixel circuit.

50. The pixel circuit according to claim 49, wherein, The second P-type transistor affects a gain boost of approximately two times.

51. The pixel circuit according to claim 48, comprising a temperature-sensitive bias circuit configured to continuously sense the chip temperature of the pixel circuit for automatically adjusting the bias voltage.

52. The pixel circuit according to claim 51, wherein, The bias circuit comprises: A third P-type transistor in series with a third N-type transistor; A programmable current source; and A programmable voltage source; wherein the third P-type transistor corresponds to the second P-type transistor; and wherein the third N-type transistor corresponds to the first N-type transistor.

53. The pixel circuit according to any one of claims 48 to 52, wherein, The manufacturing process variations include global threshold variations detected by the bias circuit and used for static adjustment of the bias voltage.

54. The pixel circuit according to claim 53, wherein, The bias circuit comprises: A third P-type transistor in series with a third N-type transistor; A programmable current source; and A programmable voltage source; wherein the third P-type transistor corresponds to the second P-type transistor; and wherein the third N-type transistor corresponds to the first N-type transistor.

55. The pixel circuit according to any one of claims 48 to 54 further includes a third N-type transistor, the third N-type transistor including a gate connected to a DC voltage, wherein, The third N-type transistor provides leakage compensation at a low light level incident on the photosensitive element.

56. The pixel circuit according to any one of claims 48 to 55, further comprising: a converter composed of the P-type transistor and configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a first capacitor serially electrically coupled to the converter and configured to receive the voltage signal from the converter; and an amplifier serially electrically coupled to the first capacitor at an input and configured to generate an amplified signal at an output based on an output signal from the first capacitor.

57. The pixel circuit according to claim 56, wherein, The converter and the first capacitor are implemented in a CMOS wafer together with the P-type transistor.

58. The pixel circuit according to claim 56, further comprising a second capacitor connected in parallel with the first capacitor, the second capacitor being implemented in a CIS wafer and connected to the first capacitor by using at least two interconnections.

59. A pixel circuit, comprising: a photosensitive element configured to generate a current signal in response to the brightness of light incident on the photosensitive element; a converter configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a first capacitor serially electrically coupled to the converter and configured to receive the voltage signal from the converter, wherein the converter and the first capacitor are implemented on a CMOS wafer; an amplifier serially electrically coupled to the first capacitor at an input and configured to generate an amplified signal at an output based on an output signal from the first capacitor; and a second capacitor connected in parallel with the first capacitor, the second capacitor being implemented in a CIS wafer and connected to the first capacitor by using at least two interconnections between the CMOS wafer and the CIS wafer.

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