Semiconductor device, memory device, and electronic apparatus

Abstract

A semiconductor device having a high storage density is used. One embodiment of the present invention is a semiconductor device including a first layer and a first insulator. The first layer includes a first oxide semiconductor, first to ninth conductors, and second to fifth insulators. The first layer is on the first insulator, and the first oxide semiconductor is over the first insulator. The first conductor and the sixth conductor are respectively arranged on the top surface and the side surface of the first oxide semiconductor and the top surface of the first insulator. In addition, each of the second and fourth conductors is located on the top surface of the first oxide semiconductor. The second insulator and the third conductor are located between the first conductor and the second conductor, the third insulator and the fifth conductor are located between the second conductor and the fourth conductor, and the fourth insulator and the seventh conductor are located between the fourth conductor and the sixth conductor. The fifth insulator and the eighth conductor are sequentially located on the first conductor in a region that does not overlap the first oxide. In addition, the ninth conductor is located on the second conductor.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a storage device, and an electronic device.

[0002] In addition, one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a working method, or a manufacturing method. In addition, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, specifically, examples of the technical field of one aspect of the present invention disclosed in this specification may include a semiconductor device, a display device (including a liquid crystal display device), a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a sensor, a processor, an electronic device, a system, their driving methods, their manufacturing methods, or their inspection methods. 1 Background Art

[0003] In recent years, with the increase in the amount of data used, a storage device with a larger storage capacity has been required. In order to increase the storage capacity per unit area, stacking storage units, such as a 3D NAND type storage device, is effective (see Patent Documents 1 to 3). By stacking storage units, the storage capacity per unit area can be increased corresponding to the number of stacked layers of the storage units. [Prior Art Documents] [Patent Documents]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2011 / 0065270 [Patent Document 2] U.S. Patent Application Publication No. 2016 / 0149004 [Patent Document 3] U.S. Patent Application Publication No. 2013 / 0069052 Summary of the Invention Technical Problem to be Solved by the Invention

[0005] One of the objects of one aspect of the present invention is to provide a semiconductor device with a large storage capacity. In addition, one of the objects of one aspect of the present invention is to provide a semiconductor device with a high storage density. In addition, one of the objects of one aspect of the present invention is to provide a novel semiconductor device. In addition, one of the objects of one aspect of the present invention is to provide a novel storage device including the above semiconductor device. In addition, one of the objects of one aspect of the present invention is to provide a novel electronic device including the above storage device.

[0006] Note that the object of one embodiment of the present invention is not limited to the above object. The above-listed objects do not preclude the existence of other objects. In addition, other objects are those that are not mentioned above and will be described in the following description. Those skilled in the art can derive and appropriately extract the objects not mentioned above from the description of the specification, drawings, etc. In addition, one embodiment of the present invention achieves at least one of the above objects and other objects. In addition, one embodiment of the present invention does not need to achieve all of the above objects and other objects. Means for Solving Technical Problems (1) One embodiment of the present invention is a semiconductor device including a first layer and a first insulator. The first layer includes a first oxide semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a second insulator, a third insulator, a fourth insulator, and a fifth insulator.

[0008] The first layer is located on the first insulator. The first oxide semiconductor is located above the first insulator. The first conductor is located on the top surface and side surface of the first oxide semiconductor and on the top surface of the first insulator. The second conductor is located on the top surface of the first oxide semiconductor. The second insulator is located between the first conductor and the second conductor when viewed in cross section and on the top surface of the first oxide semiconductor. The third conductor is located on the top surface of the second insulator. The fourth conductor is located on the top surface of the first oxide semiconductor. The third insulator is located between the second conductor and the fourth conductor when viewed in cross section and on the top surface of the first oxide semiconductor. The fifth conductor is located on the top surface of the third insulator. The sixth conductor is located on the top surface and side surface of the first oxide semiconductor and on the top surface of the first insulator. The fourth insulator is located between the fourth conductor and the sixth conductor when viewed in cross section and on the top surface of the first oxide semiconductor. The seventh conductor is located on the top surface of the fourth insulator. The fifth insulator is located on the first conductor in a region that does not overlap with the first oxide semiconductor but overlaps with the first insulator. The eighth conductor is located on the fifth insulator. And the ninth conductor is located on the second conductor. (2) In addition, one embodiment of the present invention may also have the following structure: in the above (1), the first layer includes a second oxide semiconductor, a tenth conductor, an eleventh conductor, a twelfth conductor, a thirteenth conductor, and a sixth insulator. In particular, preferably, the second oxide semiconductor is located above the first insulator, the tenth conductor is located on the top surface and side surfaces of the second oxide semiconductor and the top surface of the first insulator, and the eleventh conductor is located on the top surface of the second oxide semiconductor. In addition, preferably, the sixth insulator is located between the tenth conductor and the eleventh conductor when viewed in cross section and on the top surface of the second oxide semiconductor, and the twelfth conductor is located on the sixth insulator. Further, the thirteenth conductor is preferably located on the first conductor and the twelfth conductor. (3) In addition, one embodiment of the present invention may also have the following structure: in the above (2), a second layer and a seventh insulator are further included. In particular, the second layer preferably includes a third oxide semiconductor, a fourteenth conductor, a seventh insulator, and an eighth insulator. In addition, preferably, the seventh insulator is located on the first layer, and the second layer is located on the seventh insulator. In addition, preferably, the third oxide semiconductor includes a region overlapping with the eighth conductor and the thirteenth conductor, the eighth insulator overlaps with the eighth conductor and is located on the top surface of the third oxide semiconductor, and the fourteenth conductor is located on the eighth insulator. (4) In addition, one embodiment of the present invention may also have the following structure: in the above (3), the first oxide semiconductor, the second oxide semiconductor, and the third oxide semiconductor each contain one or more selected from indium, zinc, and element M.

[0012] Note that element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony. (5) In addition, one embodiment of the present invention is a storage device including the semiconductor device according to any one of the above (1) to (4) and a drive circuit. In addition, the first insulator is located above the drive circuit. (6) In addition, one embodiment of the present invention is an electronic device including the storage device according to the above (5) and a housing. (7) In addition, one embodiment of the present invention is a semiconductor device including a first layer, a second layer, a first insulator, a second insulator, and a first conductor. Further, each of the first layer and the second layer includes a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator. Further, the first layer is on the first insulator, the second insulator is on the first layer, and the second layer is on the second insulator.

[0016] In each of the first layer and the second layer, the second conductor is on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, and the third conductor is on the top surface of the first oxide semiconductor. The fourth insulator is between the second conductor and the third conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and the fourth conductor is on the top surface of the fourth insulator. The fifth conductor is on the top surface of the first oxide semiconductor, the fifth insulator is between the third conductor and the fifth conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and the sixth conductor is on the top surface of the fifth insulator. The seventh conductor is on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, the sixth insulator is between the fifth conductor and the seventh conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and the eighth conductor is on the top surface of the sixth insulator. The seventh insulator is in a region of the top surface of the seventh conductor that does not overlap with the first oxide semiconductor, the ninth conductor is on the top surface of the seventh insulator, and the tenth conductor is on the top surface of the fifth conductor.

[0017] The second insulator has an opening, and the first conductor is in the opening. Further, the first conductor is on the top surface of the fourth conductor of the first layer, and a part of the seventh conductor of the second layer is on the top surface of the first conductor. (8) In addition, one embodiment of the present invention is a semiconductor device including a first layer, a second layer, a third layer, a first insulator, a second insulator, a third insulator, and a first conductor. Further, each of the first layer, the second layer, and the third layer includes a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator. Further, the first layer is on the first insulator, the second insulator is on the first layer, the second layer is on the second insulator, the third insulator is on the second layer, and the third layer is on the third insulator.

[0019] In each of the first layer, the second layer, and the third layer, a second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, and a third conductor is located on the top surface of the first oxide semiconductor. A fourth insulator is located between the second conductor and the third conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and a fourth conductor is located on the top surface of the fourth insulator. A fifth conductor is located on the top surface of the first oxide semiconductor, a fifth insulator is located between the third conductor and the fifth conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and a sixth conductor is located on the top surface of the fifth insulator. A seventh conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, a sixth insulator is located between the fifth conductor and the seventh conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and an eighth conductor is located on the top surface of the sixth insulator. A seventh insulator is located in a region of the top surface of the seventh conductor that does not overlap with the first oxide semiconductor, a ninth conductor is located on the top surface of the seventh insulator, and a tenth conductor is located on the top surface of the fifth conductor.

[0020] The second insulator has an opening, and the first conductor is located in the opening. In addition, the first conductor is located on the top surface of the fourth conductor in the first layer, and a part of the seventh conductor in the second layer is located on the top surface of the first conductor. In addition, the ninth conductor in the second layer is located in a region overlapping with the eighth conductor in the third layer. (9) In addition, one aspect of the present invention is a semiconductor device including a first layer, a second layer, a first insulator, a second insulator, and a first conductor, and having a structure different from that of the above (7). The first layer and the second layer each include a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator. The first layer is located on the first insulator, the second insulator is located on the first layer, and the second layer is located on the second insulator.

[0022] In each of the first layer and the second layer, a second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, and a third conductor is located on the top surface of the first oxide semiconductor. A fourth insulator is located between the second conductor and the third conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and a fourth conductor is located on the top surface of the fourth insulator. A fifth conductor is located on the top surface of the first oxide semiconductor, a fifth insulator is located between the third conductor and the fifth conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and a sixth conductor is located on the top surface of the fifth insulator. A seventh conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, a sixth insulator is located between the fifth conductor and the seventh conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and an eighth conductor is located on the top surface of the sixth insulator. A seventh insulator is located in a region of the top surface of the seventh conductor that does not overlap with the first oxide semiconductor, a ninth conductor is located on the top surface of the seventh insulator, and a tenth conductor is located on the top surface of the fifth conductor.

[0023] The second insulator has an opening, and the first conductor is located in the opening. Further, the first conductor is located on the top surface of the sixth conductor of the first layer, and a part of the seventh conductor of the second layer is located on the top surface of the first conductor. (10) Further, one aspect of the present invention is a semiconductor device including a first layer, a second layer, a third layer, a first insulator, a second insulator, a third insulator, and a first conductor, and having a structure different from that of the above (8). Further, each of the first layer, the second layer, and the third layer includes a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator. Further, the first layer is located on the first insulator, the second insulator is located on the first layer, the second layer is located on the second insulator, the third insulator is located on the second layer, and the third layer is located on the third insulator.

[0025] In each of the first layer, the second layer, and the third layer, a second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, and a third conductor is located on the top surface of the first oxide semiconductor. A fourth insulator is located between the second conductor and the third conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and a fourth conductor is located on the top surface of the fourth insulator. A fifth conductor is located on the top surface of the first oxide semiconductor, a fifth insulator is located between the third conductor and the fifth conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and a sixth conductor is located on the top surface of the fifth insulator. A seventh conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, a sixth insulator is located between the fifth conductor and the seventh conductor when viewed in cross section and on the top surface of the first oxide semiconductor, and an eighth conductor is located on the top surface of the sixth insulator. A seventh insulator is located in a region of the top surface of the seventh conductor that does not overlap with the first oxide semiconductor, a ninth conductor is located on the top surface of the seventh insulator, and a tenth conductor is located on the top surface of the fifth conductor.

[0026] The second insulator has an opening, and the first conductor is located in the opening. In addition, the first conductor is located on the top surface of the sixth conductor in the first layer, and a part of the seventh conductor in the second layer is located on the top surface of the first conductor. In addition, the ninth conductor in the second layer is located in a region overlapping with the eighth conductor in the third layer. (11) In addition, one embodiment of the present invention may have the following structure: in any one of the above (7) to (10), the first oxide semiconductor contains one or more selected from indium, zinc, and element M.

[0028] Note that element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony. (12) In addition, one embodiment of the present invention is a storage device including the semiconductor device and the drive circuit of the above (11). In addition, the first insulator is located above the drive circuit. (13) In addition, one embodiment of the present invention is an electronic device including the storage device of the above (12) and a housing. Advantages of the Invention

[0031] According to one aspect of the present invention, a semiconductor device with a large storage capacity can be provided. In addition, according to one aspect of the present invention, a semiconductor device with a high storage density can be provided. In addition, according to one aspect of the present invention, a novel semiconductor device can be provided. In addition, according to one aspect of the present invention, a novel storage device including the above semiconductor device can be provided. In addition, according to one aspect of the present invention, a novel electronic device including the above storage device can be provided.

[0032] Note that the effects of one aspect of the present invention are not limited to the above effects. The above-listed effects do not prevent the existence of other effects. In addition, other effects are effects that are not mentioned above and will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned above from the descriptions in the specification or drawings, etc. In addition, one aspect of the present invention has at least one of the above effects and other effects. Therefore, one aspect of the present invention may sometimes not have the above-listed effects depending on the circumstances. Brief Description of the Drawings

[0033] Figure 1 is a circuit diagram showing a structural example of a semiconductor device. Figure 2 is a cross-sectional schematic diagram showing a structural example of a semiconductor device. Figure 3 is a cross-sectional schematic diagram showing a structural example of a semiconductor device. Figure 4 is a perspective schematic diagram showing a structural example of a semiconductor device. Figure 5 is a cross-sectional schematic diagram showing a structural example of a semiconductor device. Figure 6 is a perspective schematic diagram showing a structural example of a semiconductor device. Figure 7 is a layout diagram showing a structural example of a semiconductor device. Figure 8A is a plan schematic diagram showing a structural example of a semiconductor device, Figures 8B to 8D is a cross-sectional schematic diagram showing a structural example of a semiconductor device. Figure 9A is a plan schematic diagram showing an example of a manufacturing method of a semiconductor device, Figures 9B to 9D is a cross-sectional schematic diagram showing an example of a manufacturing method of a semiconductor device. Figure 10A is a plan schematic diagram showing an example of a manufacturing method of a semiconductor device, Figures 10B to 10D is a cross-sectional schematic diagram showing an example of a manufacturing method of a semiconductor device. Figure 11Ais a plan view showing an example of a method for manufacturing a semiconductor device, Figures 11B to 11D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 12A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 12B to 12D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 13A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 13B to 13D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 14A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 14B to 14D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 15A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 15B to 15D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 16A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 16B to 16D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 17A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 17B to 17D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 18A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 18B to 18D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 19A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 19B to 19D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 20A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 20B to 20D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 21A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 21B to 21D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 22A is a plan view showing an example of a method for manufacturing a semiconductor device, Figures 22B to 22D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 23It is a circuit diagram showing an example of the structure of a semiconductor device. Figure 24 It is a schematic cross-sectional view showing an example of the structure of a semiconductor device. Figure 25 It is a schematic cross-sectional view showing an example of the structure of a semiconductor device. Figure 26 It is a three-dimensional schematic view showing an example of the structure of a semiconductor device. Figure 27 It is a schematic cross-sectional view showing an example of the structure of a semiconductor device. Figure 28 It is a schematic cross-sectional view showing an example of the structure of a semiconductor device. Figure 29A and Figure 29B It is a schematic cross-sectional view showing an example of the manufacturing method of a semiconductor device. Figure 30A and Figure 30B It is a schematic cross-sectional view showing an example of the manufacturing method of a semiconductor device. Figure 31 It is a schematic cross-sectional view showing an example of the manufacturing method of a semiconductor device. Figure 32A It is a three-dimensional view illustrating an example of the structure of a storage device, Figure 32B It is a block diagram illustrating an example of the structure of a semiconductor device. Figure 33 It is a block diagram illustrating an example of the structure of a storage device. Figure 34 It is a schematic cross-sectional view illustrating an example of the structure of a storage device. Figure 35A and Figure 35B It is a diagram showing an example of an electronic component. Figure 36A and Figure 36B It is a diagram showing an example of an electronic device, Figures 36C to 36E It is a diagram showing an example of a mainframe computer. Figure 37 It is a diagram showing an example of a space device. Figure 38 It is a diagram showing an example of a storage system that can be used in a data center. Figure 39A It is a graph showing the breakdown voltage characteristics between the source and drain of a transistor, Figure 39B It is a graph showing the gate breakdown voltage characteristics of a transistor. Figure 40 It is a circuit diagram illustrating the storage cell of an embodiment. Figure 41 It is a circuit diagram illustrating the storage device of an embodiment. Figure 42It is a timing diagram illustrating an operation example of the storage device according to the embodiment. Figure 43 It is a top view photograph of a memory die including the storage device. Figure 44A It is a graph showing the relationship between the voltage written to the storage device and the voltage read from the storage device. Figure 44B It is a graph showing the relationship between the voltage written to the storage device and three times the standard deviation σ of the voltage read from the storage device. Figure 45A and Figure 45B It is a schematic diagram of the threshold voltage distribution of the write voltage to the storage device. Figure 46A It is a graph showing the change in the read voltage that occurs as the holding time elapses in the storage device with the write voltage. Figure 46B It is a graph showing the relationship between the initial read voltage and the change amount of the read voltage after a certain time in the storage device with the write voltage. Figure 47A and Figure 47B It is a schematic diagram of the threshold voltage distribution of the write voltage to the storage device. Mode for Carrying Out the Invention

[0034] In this specification and the like, a semiconductor device refers to a device that utilizes semiconductor characteristics, including a circuit of semiconductor elements (e.g., transistors, diodes, photodiodes) and a device including such a circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip having an integrated circuit, and an electronic component in which a chip is housed in a package are all examples of semiconductor devices. In addition, for example, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device may sometimes be a semiconductor device itself, or may sometimes include a semiconductor device.

[0035] In addition, in this specification and the like, when it is described that "X is connected to Y", it means that the following cases are disclosed in this specification and the like: the case where X is electrically connected to Y; the case where X is functionally connected to Y; and the case where X is directly connected to Y. Therefore, it is not limited to the connection relationship specified such as the connection relationship shown in the drawings or the text. Connection relationships other than the connection relationship shown in the drawings or the text are also considered to be those described in the drawings or the text. X and Y are objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films or layers).

[0036] As an example of the case where X and Y are electrically connected, one or more components capable of electrically connecting X and Y (such as switches, transistors, capacitors, inductors, resistors, diodes, display devices, light-emitting devices, loads) can be connected between X and Y. In addition, the switch has the function of controlling on or off. In other words, whether current flows is controlled by making the switch in the conducting state (on state) or the non-conducting state (off state).

[0037] In addition, in the case where both a component and a power supply line (such as VDD (high power supply potential), VSS (low power supply potential), GND (ground potential) or a wiring supplying a desired potential) are arranged between X and Y, it cannot be said that X and Y are electrically connected. In addition, in the case where only a power supply line is arranged between X and Y, there are no other components between X and Y, so it can be said that X and Y are directly connected. Therefore, in the case where only a power supply line is arranged between X and Y, it can also be said that "X and Y are electrically connected". However, in the case where both a component and a power supply line are arranged between X and Y, it can be said that X is electrically connected to the power supply line (through the component) and Y is electrically connected to the power supply line, but it cannot be said that X and Y are electrically connected. In addition, in the case where the gate and source of a transistor are interposed between X and Y, it cannot be said that X and Y are electrically connected. In addition, in the case where the gate and drain of a transistor are interposed between X and Y, it cannot be said that X and Y are electrically connected. That is, regarding a transistor, in the case where the drain and source of the transistor are interposed between X and Y, it can be said that X and Y are electrically connected. In addition, in the case where a capacitor is arranged between X and Y, sometimes it can be said that X and Y are electrically connected, and sometimes it cannot be said that X and Y are electrically connected. For example, in the structure of a digital circuit or a logic circuit, in the case where a capacitor is arranged between X and Y, sometimes it cannot be said that X and Y are electrically connected. On the other hand, for example, in the structure of an analog circuit, in the case where a capacitor is arranged between X and Y, sometimes it can be said that X and Y are electrically connected.

[0038] As an example of the case where X and Y are functionally connected, for example, one or more circuits capable of functionally connecting X and Y (such as logic circuits (such as inverters, NAND circuits, NOR circuits), signal conversion circuits (such as digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits), potential level conversion circuits (such as power supply circuits such as boost circuits and buck circuits, level shift circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (such as circuits capable of increasing the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits), signal generation circuits, storage circuits, control circuits) can be connected between X and Y. Note that, for example, even if there are other circuits between X and Y, when the signal output from X is transmitted to Y, it can be said that X and Y are functionally connected.

[0039] In addition, when it is explicitly described as "X is electrically connected to Y", it includes the following cases: the case where X is electrically connected to Y (in other words, the case where X and Y are connected with other elements or other circuits interposed therebetween); and the case where X and Y are directly connected (in other words, the case where X and Y are connected without other elements or other circuits interposed therebetween).

[0040] In addition, for example, it can be expressed as "X, Y, the source of the transistor (sometimes alternatively referred to as one of the first terminal and the second terminal) and the drain of the transistor (sometimes alternatively referred to as the other of the first terminal and the second terminal) are electrically connected to each other, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence". Or, it can be expressed as "the source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence". Or, it can be expressed as "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are arranged to be connected to each other in sequence". By specifying the connection order in the circuit structure using the same expression method as these examples, the source and drain of the transistor can be distinguished and the technical scope can be determined. Note that this expression method is an example and is not limited to the above expression method. Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films or layers).

[0041] In addition, even when independent components on a circuit diagram are electrically connected to each other, sometimes one component has the functions of multiple components. For example, when a part of the wiring is used as an electrode, one conductive film has the two functions of wiring and electrode. Therefore, the case where one conductive film has the functions of multiple components is also included within the scope of "electrically connected" in this specification.

[0042] In this specification and the like, a "resistor" can be, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, a "resistor" includes a wiring having a resistance value, a transistor through which current flows between the source and the drain, a diode, or a coil. Therefore, a "resistor" can sometimes be alternatively referred to as "resistance", "load", or "region having a resistance value". In contrast, "resistance", "load", or "region having a resistance value", etc. can sometimes be alternatively referred to as "resistor". As the resistance value, for example, it is preferably 1 mΩ or more and 10Ω or less, more preferably 5 mΩ or more and 5Ω or less, and further preferably 10 mΩ or more and 1Ω or less. In addition, for example, it can also be 1Ω or more and 1×10 9 Ω or less.

[0043] In the present specification and the like, a "capacitor" may be, for example, a circuit element having an electrostatic capacitance value higher than 0 F, a region of a wiring having an electrostatic capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, a "capacitor", a "parasitic capacitance", or a "gate capacitance" may sometimes be interchangeably referred to as a "capacitance". In contrast, a "capacitance" may sometimes be interchangeably referred to as a "capacitor", a "parasitic capacitance", or a "gate capacitance". In addition, a "capacitance" (including a "capacitance" having three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Thus, the "pair of conductors" of a "capacitance" may be interchangeably referred to as a "pair of electrodes", a "pair of conductive regions", a "pair of regions", or a "pair of terminals". In addition, "one of the pair of terminals" and "the other of the pair of terminals" are sometimes referred to as a first terminal and a second terminal, respectively. In addition, the electrostatic capacitance value may be, for example, 0.05 fF or more and 10 pF or less. In addition, for example, it may also be 1 pF or more and 10 μF or less.

[0044] In the present specification and the like, a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal for controlling the conduction state of the transistor. The two terminals used as the source or the drain are the input / output terminals of the transistor. Depending on the conductivity type (n-channel type, p-channel type) of the transistor and the magnitudes of the potentials applied to the three terminals of the transistor, one of the two input / output terminals serves as the source and the other serves as the drain. Thus, in the present specification and the like, the source and the drain may sometimes be interchanged with each other. In the present specification and the like, when explaining the connection relationship of a transistor, the expressions "one of the source and the drain" (first electrode or first terminal) and "the other of the source and the drain" (second electrode or second terminal) are used. In addition, depending on the structure of the transistor, sometimes in addition to the above three terminals, it also includes a back gate. In this case, in the present specification and the like, sometimes one of the gate and the back gate of the transistor is referred to as a first gate, and the other of the gate and the back gate of the transistor is referred to as a second gate. And, in the same transistor, sometimes the "gate" and the "back gate" can be interchanged with each other. In addition, when a transistor includes three or more gates, in the present specification and the like, sometimes each gate is referred to as a first gate, a second gate, a third gate, and the like.

[0045] For example, in the present specification and the like, as an example of a transistor, a multi-gate structure transistor having two or more gate electrodes can be adopted. When the multi-gate structure is adopted, since the channel formation regions are connected in series, a structure in which a plurality of transistors are connected in series is formed. Therefore, by adopting the multi-gate structure, the off-state current can be reduced, and the breakdown voltage of the transistor (reliability improvement) can be increased. Alternatively, by using the multi-gate structure, when the transistor operates in the saturation region, even if the voltage between the drain and the source changes, the change in the drain-source current is not very large, so that a voltage-current characteristic with a flat slope angle can be obtained. When using the voltage-current characteristic with a flat slope angle, an ideal current source circuit or an active load with an extremely high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0046] In addition, the case where a circuit diagram shows one circuit element sometimes includes the case where the circuit element has a plurality of circuit elements. For example, the case where a circuit diagram shows one resistor includes the case where two or more resistors are connected in series. In addition, for example, the case where a circuit diagram shows one capacitor includes the case where two or more capacitors are connected in parallel. In addition, for example, the case where a circuit diagram shows one transistor includes the case where two or more transistors are connected in series and the gates of the respective transistors are electrically connected to each other. Similarly, for example, the case where a circuit diagram shows one switch includes the case where the switch has two or more transistors, the two or more transistors are connected in series or in parallel, and the gates of the respective transistors are electrically connected to each other.

[0047] In addition, in the present specification and the like, a node can also be renamed as a terminal, a wiring, an electrode, a conductive layer, a conductor, or an impurity region according to the circuit structure, the device structure, and the like. In addition, a terminal, a wiring, etc. can also be renamed as a node.

[0048] In addition, in the present specification and the like, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from a reference potential. For example, when the reference potential is the ground potential (grounded potential), "voltage" can also be referred to as "potential". The ground potential does not necessarily mean 0V. In addition, potential is relative, and the potential supplied to the wiring, the potential applied to the circuit, the potential output from the circuit, etc. also change according to the change of the reference potential.

[0049] In addition, in the present specification and the like, "high-level potential" and "low-level potential" do not mean specific potentials. For example, in the case where two wirings are both described as "wiring for supplying a high-level potential", the high-level potentials supplied by the two wirings can also be different from each other. Similarly, in the case where two wirings are both described as "wiring for supplying a low-level potential", the low-level potentials supplied by the two wirings can also be different from each other.

[0050] In addition, "electric current" refers to the phenomenon of charge migration (electric conduction). For example, the description "electric conduction of a positively charged object occurs" can be replaced with the description "electric conduction of a negatively charged object occurs in the opposite direction". Therefore, in this specification and the like, unless otherwise specified, "electric current" refers to the phenomenon of charge migration (electric conduction) during carrier migration. Here, examples of carriers include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). In addition, the "direction of electric current" in wiring, etc. is the direction of migration of positively charged carriers, and is recorded as a positive electric current amount. In other words, the direction of migration of negatively charged carriers is opposite to the direction of electric current, and is recorded as a negative electric current amount. Therefore, in this specification and the like, unless otherwise specified, regarding the positive and negative of electric current (or the direction of electric current), the description "electric current flows from element A to element B" can be replaced with the description "electric current flows from element B to element A". In addition, the description "input electric current to element A" can be replaced with the description "output electric current from element A".

[0051] In addition, in this specification and the like, ordinal numbers such as "first", "second", "third", etc. are added to avoid confusion of components. Therefore, this ordinal number does not limit the number of components. In addition, this ordinal number does not limit the order of components. For example, in this specification and the like, the "first" component in one embodiment may be referred to as the "second" component in other embodiments or claims. In addition, for example, in this specification and the like, the component referred to as "first" in one embodiment may be omitted in other embodiments or claims.

[0052] In this specification and the like, for convenience, phrases indicating configuration such as "above" and "below" are sometimes used to describe the positional relationship of components with reference to the drawings. In addition, the positional relationship of components is appropriately changed according to the directions for describing each component. Therefore, without being limited to the phrases described in the specification and the like, the phrases can be appropriately changed according to the circumstances. For example, for the expression "an insulator located on the top surface of a conductor", by rotating the direction of the shown drawing by 180 degrees, it can be changed to "an insulator located on the bottom surface of a conductor".

[0053] In addition, terms such as "upper" or "lower" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessarily required that electrode B is formed in direct contact on insulating layer A, and it may also include the case where other components are included between insulating layer A and electrode B. Similarly, for example, in the expression "electrode B above insulating layer A", it is not necessarily required that electrode B is formed in direct contact on insulating layer A, and it may also include the case where other components are included between insulating layer A and electrode B. Similarly, for example, in the expression "electrode B below insulating layer A", it is not necessarily required that electrode B is formed in direct contact under insulating layer A, and it may also include the case where other components are included between insulating layer A and electrode B.

[0054] In addition, in this specification and the like, phrases such as "row" and "column" are sometimes used to describe the components configured in a matrix and their positional relationships. In addition, the positional relationships of the components are appropriately changed according to the directions for describing the components. Therefore, not limited to the phrases described in the specification and the like, the phrases can be appropriately changed according to the situation. For example, by rotating the direction of the drawing by 90 degrees, the expression "row direction" can sometimes be changed to the "column direction".

[0055] In addition, in this specification and the like, according to the situation, phrases such as "film" and "layer" can be interchanged with each other. For example, "conductive layer" can sometimes be changed to "conductive film". In addition, "insulating film" can sometimes be changed to "insulating layer". In addition, according to the situation or circumstances, other phrases can be used instead of phrases such as "film" and "layer". For example, "conductive layer" or "conductive film" can sometimes be changed to "conductor". In addition, for example, "insulating layer" or "insulating film" can sometimes be changed to "insulator".

[0056] Note that in this specification and the like, the phrases "electrode", "wiring", and "terminal" do not functionally limit their components. For example, "electrode" is sometimes used as part of "wiring", and vice versa. Furthermore, phrases such as "electrode" or "wiring" also include the case where a plurality of "electrodes" or "wirings" are formed integrally. In addition, for example, "terminal" is sometimes used as part of "wiring" or "electrode", and vice versa. Furthermore, the phrase "terminal" also includes the case where one or more selected from "electrode", "wiring", and "terminal" are formed integrally. Therefore, for example, "electrode" can be part of "wiring" or "terminal", and for example, "terminal" can be part of "wiring" or "electrode". In addition, the phrases such as "electrode", "wiring", or "terminal" are sometimes replaced with phrases such as "region" according to the situation.

[0057] In this specification and the like, depending on the situation or circumstances, terms such as "wiring", "signal line", or "power line" can be interchanged with each other. For example, sometimes "wiring" can be changed to "signal line". In addition, for example, sometimes "wiring" can be changed to "power line". Vice versa, sometimes terms such as "signal line" or "power line" can be changed to "wiring". Sometimes "power line" and the like can be changed to "signal line". Vice versa, sometimes terms such as "signal line" can be changed to "power line" and the like. In addition, depending on the situation or circumstances, sometimes the "potential" applied to the wiring can be changed to "signal" with each other. Vice versa, sometimes "signal" can be changed to "potential".

[0058] In addition, in this specification and the like, sometimes the operation method of the semiconductor device is described with reference to a timing chart. In addition, the timing chart used in this specification and the like shows an ideal operation example, and without special explanation, it is not limited to the period, the magnitude of the signal (for example, potential or current), and the timing shown in the timing chart. In the timing chart of this specification and the like, the magnitude and timing of the signal (for example, potential or current) input to each wiring (including nodes) in the timing chart can be changed according to the situation. For example, even if two periods with equal intervals are shown in the timing chart, the lengths of the two periods are sometimes not the same. In addition, for example, even if one of the two periods is shown to be long and the other is short, the lengths of the two periods can sometimes be the same, or sometimes one of the two periods can be made short and the other can be made long.

[0059] In this specification and the like, metal oxide refers to the oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, which can also be abbreviated as OS), etc. For example, when a metal oxide is included in the channel formation region of a transistor, sometimes the metal oxide is referred to as an oxide semiconductor. In other words, when a metal oxide can form the channel formation region of a transistor having at least one of an amplification function, a rectification function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, an OS transistor can be alternatively referred to as a transistor including a metal oxide or an oxide semiconductor.

[0060] In addition, in this specification and the like, sometimes a metal oxide containing nitrogen is also referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen can also be referred to as a metal oxynitride.

[0061] In addition, in this specification and the like, for example, impurities in a semiconductor refer to substances other than the main components constituting the semiconductor film. For example, an element with a concentration lower than 0.1 at.% is an impurity. When impurities are included, for example, one or more of the following may occur: an increase in the density of defect states in the semiconductor, a decrease in the carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, examples of impurities that change the semiconductor characteristics include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components. In particular, for example, there are hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, examples of impurities that change the semiconductor characteristics include Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (note that oxygen and hydrogen may not be included in some cases).

[0062] In this specification and the like, a switch refers to an element that has a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element that has a function of selecting and switching current paths. Therefore, a switch sometimes includes two or more terminals through which current flows in addition to the control terminals. As an example of a switch, an electrical switch or a mechanical switch, etc. can be used. In other words, as long as a switch can control current, it is not limited to a specific element.

[0063] Examples of electrical switches include transistors (such as bipolar transistors or MOS transistors), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, metal-insulator-semiconductor (MIS) diodes, or diode-connected transistors), or logic circuits that combine these elements. When a transistor is used as a switch, the "conductive state" of the transistor, for example, refers to a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited or a state in which current can flow between the source electrode and the drain electrode. In addition, the "non-conductive state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When only using a transistor as a switch, there is no particular limitation on the polarity (conductivity type) of the transistor.

[0064] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is -10° or more and 10° or less. Therefore, it also includes a state in which the angle is -5° or more and 5° or less. "Substantially parallel" refers to a state in which the angle formed by two straight lines is -30° or more and 30° or less. In addition, "perpendicular" refers to a state in which the angle between two straight lines is 80° or more and 100° or less. Therefore, it also includes a state in which the angle is 85° or more and 95° or less. "Substantially perpendicular" refers to a state in which the angle formed by two straight lines is 60° or more and 120° or less.

[0065] In addition, in this specification and the like, the structures shown in each embodiment can be appropriately combined with the structures shown in other embodiments to form one embodiment of the present invention. Further, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0066] In addition, the content (or a part thereof) described in a certain embodiment can be applied / combined / replaced with at least one of the content (or a part thereof) described in other content (or a part thereof) described in this embodiment and the content (or a part thereof) described in another or multiple other embodiments.

[0067] Note that the content described in the embodiments refers to the content described by using various drawings in each embodiment or the content described by using the articles recorded in the specification.

[0068] In addition, by combining the drawing (or a part thereof) shown in a certain embodiment with at least one of the other parts of this drawing, the other drawings (or a part thereof) shown in this embodiment, and the drawings (or a part thereof) shown in another or multiple other embodiments, more drawings can be formed.

[0069] The embodiments described in this specification will be described with reference to the drawings. However, those of ordinary skill in the art can easily understand the fact that the embodiments can be implemented in multiple different forms, and their forms and details can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the embodiments. Note that in the structure of the invention in the embodiments, sometimes the same reference numerals are used in different drawings to represent the same parts or parts having the same functions, and repeated descriptions are omitted. In perspective views and the like, for the sake of clarity, sometimes the illustration of some constituent elements is omitted.

[0070] In this specification and the like, when multiple elements use the same reference numeral and it is necessary to distinguish them, sometimes symbols for identification such as “_1”, “[n]”, “[m, n]”, etc. are attached to the reference numeral. In addition, in the drawings and the like, in the case where symbols for identification such as “_1”, “[n]”, “[m, n]”, etc. are attached to the reference numeral, if it is not necessary to distinguish them in this specification and the like, sometimes the symbols for identification are not attached.

[0071] In the drawings of this specification, for the sake of clear illustration, sometimes the sizes, the thicknesses of layers, or regions are exaggerated. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and are not limited to the shapes, values, etc. shown in the drawings. For example, it may include unevenness of signals, voltages, or currents caused by noise, timing deviations, etc.

[0072] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described.

[0073] <Example of circuit structure of semiconductor device> Figure 1 It is a circuit diagram showing an example of the structure of a semiconductor device DEV according to one aspect of the present invention. As an example, the semiconductor device DEV includes a storage layer ALYa and a storage layer ALYb. Further, in Figure 1 the storage layer ALYb is located above the storage layer ALYa.

[0074] Each of the storage layer ALYa and the storage layer ALYb includes a plurality of storage units. In particular, as an example, each of the storage layer ALYa and the storage layer ALYb includes a plurality of storage units arranged in a matrix. In Figure 1 as an example, the storage layer ALYa includes storage units MCa arranged in a matrix of m rows and n columns (m is an integer of 1 or more, and n is an integer of 1 or more). Similarly, in Figure 1 as an example, the storage layer ALYb includes storage units MCb arranged in a matrix of m rows and n columns (m is an integer of 1 or more, and n is an integer of 1 or more).

[0075] Further, in this specification and the drawings, for example, the storage unit located at the first row and the first column in the matrix of the storage layer ALYa is denoted as the storage unit MCa[1, 1], and the storage unit located at the m-th row and the n-th column in the matrix of the storage layer ALYb is denoted as the storage unit MCb[m, n]. For example, Figure 1 shows the storage unit MCa[i, j] located at the i-th row and the j-th column (i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n - 1 or less) in the matrix of the storage layer ALYa and the storage unit MCa[i, j + 1] located at the i-th row and the j + 1-th column. In addition, the storage unit MCb[i, j] located at the i-th row and the j-th column in the matrix of the storage layer ALYb and the storage unit MCb[i, j + 1] located at the i-th row and the j + 1-th column are also shown.

[0076] In addition, in Figure 1 the storage unit MCa and the storage unit MCb have the same circuit structure as each other. Therefore, in this specification and the drawings, when describing matters common to the storage unit MCa and the storage unit MCb, the storage unit MCa and the storage unit MCb are described as the storage unit MC.

[0077] Note that the number of rows and columns of the matrix of the storage layer ALYa and the number of rows and columns of the matrix of the storage layer ALYb may be the same as or different from each other.

[0078] In addition,Figure 1 The memory cell MC shown is an example of a memory cell called a gain cell, and includes a transistor M1, a transistor M2, a transistor M3, and a capacitor C1. In particular, in this specification and the like, the structure of the memory cell MC in which OS transistors are used for the transistors M1 to M3 is sometimes referred to as NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor Random Access Memory).

[0079] As an example, it is preferable to use OS transistors for the transistors M1 to M3. In particular, as the metal oxide contained in the channel formation region of the OS transistor, for example, indium oxide, gallium oxide, and zinc oxide can be cited. In addition, the metal oxide preferably contains one or more selected from indium, element M, and zinc. Note that element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony. In particular, element M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

[0080] In particular, as the metal oxide for the semiconductor layer, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also denoted as IGZO). Alternatively, it is preferable to use an oxide containing indium (In), tin (Sn), and zinc (Zn) (also denoted as ITZO (registered trademark)). Alternatively, it is preferable to use an oxide containing indium (In), gallium (Ga), tin (Sn), and zinc (Zn). Alternatively, it is preferable to use an oxide containing indium (In), aluminum (A1), and zinc (Zn) (also called IAZO). Alternatively, it is preferable to use an oxide containing indium (In), aluminum (A1), gallium (Ga), and zinc (Zn) (also called IAGZO). In addition, the OS transistor will be described when explaining an example of the cross-sectional structure of the semiconductor device.

[0081] In addition, transistors other than OS transistors can also be applied to the transistors M1 to M3. For example, the transistors M1 to M3 can be applied to transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors). In addition, as the silicon, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon (including low temperature polycrystalline silicon) can be used.

[0082] In addition, as the transistors M1 to M3, in addition to OS transistors and Si transistors, for example, transistors in which the channel formation region contains germanium, transistors in which the channel formation region contains a compound semiconductor such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium, transistors in which the channel formation region contains carbon nanotubes, or transistors in which the channel formation region contains an organic semiconductor can be used.

[0083] In addition, although Figure 1 the transistors M1 to M3 shown are n-channel transistors, they can also be p-channel transistors depending on the situation or circumstances. In addition, when replacing the n-channel transistors with p-channel transistors, it is necessary to appropriately change the potential input to the memory cell MC so that the memory cell MC operates normally. This applies not only to Figure 1 but also to the transistors described in other parts of the specification and the transistors shown in other drawings. In addition, in the present embodiment, the transistors M1 to M3 are described as n-channel transistors to explain the structure of the memory cell MC.

[0084] In addition, the transistors M1 to M3 preferably operate in the saturation region when in the on state. For example, when the gate-source voltage of any one of the transistors M1 to M3 is constant, the current flowing between the source and drain of any one of the transistors is greater than the current when any one of the transistors operates in the linear region. Thus, by increasing the current amount, the signal transmission speed becomes faster, and as a result, the operating speed of the circuit can be increased.

[0085] In addition, depending on the situation, one or more selected from the transistors M1 to M3 can also operate in the linear region. In addition, one or more selected from the transistors M1 to M3 can also operate in the subthreshold region.

[0086] As an example, the transistor M1 uses a transistor including a pair of gates across the channel, and the transistor M1 includes a first gate and a second gate. As an example, for convenience, the first gate is denoted as the gate (sometimes denoted as the front gate), and the second gate is denoted as the back gate for distinction, but the first gate and the second gate can be swapped with each other. Specifically, the connection structure of "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" can be swapped with the connection structure of "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring".

[0087] In addition, the transistors M2 and M3 can also be transistors without a back gate.

[0088] In addition, the description of the above transistors can be applied not only to transistors M1 to M3, but also to the transistors described in other parts of the specification and the transistors shown in the drawings in the same manner.

[0089] Next, the circuit structures of the memory cells MCa[i, j] and MCa[i, j + 1] will be described.

[0090] In the memory cells MCa[i, j] and MCa[i, j + 1] of the memory layer ALYa, the first terminal of transistor M1 is electrically connected to the gate of transistor M2 and the first terminal of capacitor C1. In addition, the first terminal of transistor M2 is electrically connected to the first terminal of transistor M3.

[0091] In the memory cell MCa[i, j] of the memory layer ALYa, the second terminal of transistor M1 is electrically connected to the wiring WRBLa[j], the second terminal of transistor M2 is electrically connected to the wiring SLa[j], and the second terminal of transistor M3 is electrically connected to the wiring WRBLa[j + 1]. In addition, the gate of transistor M1 is electrically connected to the wiring WWLa[i], the second terminal of capacitor C1 is electrically connected to the wiring CLa[i], and the gate of transistor M3 is electrically connected to the wiring RWLa[i].

[0092] In the memory cell MCa[i, j + 1] of the memory layer ALYa, the second terminal of transistor M1 is electrically connected to the wiring WRBLa[j + 1], the second terminal of transistor M2 is electrically connected to the wiring SLa[j + 1], and the second terminal of transistor M3 is electrically connected to the wiring WRBLa[j + 2]. In addition, the gate of transistor M1 is electrically connected to the wiring WWLa[i], the second terminal of capacitor C1 is electrically connected to the wiring CLa[i], and the gate of transistor M3 is electrically connected to the wiring RWLa[i].

[0093] In each of the memory cells MCa[i, j] and MCa[i, j + 1] in the memory layer ALYa, the back gate of transistor M1 can also be electrically connected to a wiring (not shown) extending and disposed below the memory layer ALYa, for example.

[0094] The wiring WWLa[i] is used as a write word line for the memory cells MCa[i, j] and MCa[i, j + 1] included in the memory layer ALYa, for example. That is, the wiring WWLa[i] is used as a wiring for transmitting a selection signal (sometimes referred to as a current, variable potential, or pulse voltage) for selecting the memory cell MCa to be written. In addition, the wiring WWLa[i] can also be used as a wiring for supplying a constant potential depending on the situation.

[0095] The wiring RWLa[i] is used, for example, as a readout word line for the memory cells MCa[i,j] and MCa[i,j+1] included in the memory layer ALYa. That is to say, the wiring RWLa[i] is used as a wiring for transmitting a selection signal (sometimes referred to as current, variable potential, or pulse voltage) for selecting the memory cell MCa to be read out. In addition, the wiring RWLa[i] can also be used as a wiring for supplying a constant potential according to the situation.

[0096] The wiring WRBLa[j] is used, for example, as a write bit line for the memory cell MCa[i,j] included in the memory layer ALYa. That is to say, the wiring WRBLa[j] is used as a wiring for transmitting write data to the selected memory cell MCa[i,j]. In addition, the wiring WRBLa[j+1] is used as a write bit line for the memory cell MCa[i,j+1] included in the memory layer ALYa. That is to say, the wiring WRBLa[j+1] is used as a wiring for transmitting write data to the selected memory cell MCa[i,j+1].

[0097] In addition, the wiring WRBLa[j+1] is also used, for example, as a read bit line for the memory cell MCa[i,j] included in the memory layer ALYa. That is to say, the wiring WRBLa[j+1] is used as a wiring for transmitting read data from the selected memory cell MCa[i,j]. In addition, the wiring WRBLa[j+2] is used as a write bit line for the memory cell MCa[i,j+1] included in the memory layer ALYa. That is to say, the wiring WRBLa[j+2] is used as a wiring for transmitting read data from the selected memory cell MCa[i,j+1].

[0098] Note that the wiring WRBLa[j] is used, for example, as a read bit line for the memory cell MCa[i,j-1] ( Figure 1 not shown in the figure. In addition, at this time, j is an integer of 2 or more). In addition, the wiring WRBLa[j+1] is used, for example, as a write bit line for the memory cell MCa[i,j+2] ( Figure 1 not shown in the figure. In addition, at this time, j is an integer of n-2 or less).

[0099] That is to say, the wiring WRBLa is used as a write bit line for one of the memory cells adjacent to each other across the wiring WRBLa, and is used as a read bit line for the other of the memory cells adjacent to each other across the wiring WRBLa.

[0100] In addition, the wirings WRBLa[j] to WRBLa[j+2] can also be used as wirings for supplying a constant potential according to the situation.

[0101] The wiring SLa[j] is used, for example, as a wiring for supplying a constant potential to the memory cells MCa[i, j] included in the memory layer ALYa. Further, the wiring SLa[j + 1] is used, for example, as a wiring for supplying a constant potential to the memory cells MCa[i, j + 1] included in the memory layer ALYa. In addition, the wiring SLa[j] and the wiring SLa[j + 1] may also be used as wirings for supplying a variable potential depending on the situation.

[0102] The wiring CLa[i] is used, for example, as a wiring for supplying a constant potential to the memory cells MCa[i, j] and the memory cells MCa[i, j + 1] included in the memory layer ALYa. In addition, the wiring CLa[i] may also be used as a wiring for supplying a variable potential depending on the situation.

[0103] Note that, as Figure 1 shown, the structure of the memory layer ALYb may be the same as that of the memory layer ALYa. Therefore, the structure of the memory cell MCb may be as follows: in the description of the structure of the above-mentioned memory cell MCa, the wiring WWLa[i] is replaced with the wiring WWLb[i], the wiring RWLa[i] is replaced with the wiring RWLb[i], the wirings WRBLa[j] to WRBLa[j + 2] are replaced with the wirings WRBLb[j] to WRBLb[j + 2], the wirings SLa[j] and SLa[j + 1] are replaced with the wirings SLb[j] and SLb[j + 1], and the wiring CLa[i] is replaced with the wiring CLb[i].

[0104] In addition, the back gates of the transistors M1 included in the memory cells MCb[i, j] and the memory cells MCb[i, j + 1] disposed in the memory layer ALYb may also be electrically connected to the wiring CLa extending and disposed in the memory layer ALYa, for example. In addition, the second terminals of the capacitors C1 included in the memory cells MCb[i, j] and the memory cells MCb[i, j + 1] disposed in the memory layer ALYb may also be electrically connected to the wiring of the memory layer extending and disposed above the memory layer ALYb (not shown), for example.

[0105] Next, the Figure 1 data writing to the memory cell MC and the data reading from the memory cell MC of the semiconductor device DEV shown will be described. Here, as an example, the data writing to the memory cell MCa[i, j] of the memory layer ALYa of the semiconductor device DEV and the data reading from the memory cell MCa[i, j] will be described.

[0106] In order to Figure 1Data is written to the memory cell MCa[i, j] of the semiconductor device DEV shown. For example, first, a first potential (e.g., ground potential) is supplied to the wiring CLa[i]. Next, a high-level potential is supplied to the wiring WWLa[i] so that the transistor M1 included in the memory cell MCa[i, j] is turned on, and low-level potentials are supplied to the wirings WWLa[1] to WWLa[m] other than the wiring WWLa[i] so that the transistors M1 included in the memory cells MCa on the first row to the m-th row other than the i-th row are turned off. In addition, low-level potentials are supplied to the wirings RWLa[1] to RWLa[m] so that the transistor M3 included in the memory cell MCa[i, j] is turned off.

[0107] Then, write data is sent to the wiring WRBLa[j], whereby a potential corresponding to the data is written to the first terminal of the capacitor C1 of the memory cell MCa[i, j]. After writing data to the first terminal of the capacitor C1 of the memory cell MCa[i, j], a low-level potential is supplied to the wiring WWLa[i] so that the transistor M1 included in the memory cell MCa[i, j] is turned off. Thus, the data writing operation for the memory cell MCa[i, j] is completed.

[0108] When reading data from Figure 1 the memory cell MCa[i, j] of the semiconductor device DEV shown, for example, first, a second potential (e.g., a high-level potential higher than the first potential) is supplied to the wiring WRBLa[j + 1]. Next, a high-level potential is supplied to the wiring RWLa[i] so that the transistor M3 included in the memory cell MCa[i, j] is turned on. At this time, when the transistor M2 in the memory cell MCa[i, j] operates in the saturation region, a current corresponding to the gate-source voltage of the transistor M2 (the potential difference between the potential of the gate of the transistor M2 and the potential of the wiring SLa[j]) flows. Thus, this current flows from the wiring WRBLa[j + 1] through the transistor M2 to the wiring SLa[j]. By inputting the current flowing through the wiring WRBLa[j + 1] to the readout circuit, the data written to the memory cell MCa[i, j] can be read out. Note that here, the data written to the memory cell MCa[i, j] is read out according to the amount of current, but the data written to the memory cell MCa[i, j] can also be read out according to the voltage change of the wiring WRBLa[j + 1].

[0109] In addition, regarding writing data to other memory cells MCa or reading data from other memory cells MCa, the same operations as described above can also be performed.

[0110] In addition, the circuit structure of the semiconductor device according to one aspect of the present invention is not limited toFigure 1 The structure. The circuit structure of the semiconductor device can also be changed according to the situation.

[0111] For example, in Figure 1 In the semiconductor device DEV shown, the wirings SLa[j] and SLa[j + 1] are arranged to extend in the column direction of the matrix of the storage layer ALYa, but the wirings SLa[j] and SLa[j + 1] can also be arranged to extend in the row direction of the matrix of the storage layer ALYa. Similarly, a wiring extending in one of the row direction and the column direction can be changed to a wiring extending in the other of the row direction and the column direction.

[0112] <Example of the cross-sectional structure of the semiconductor device> Next, an example of the structure of the semiconductor device DEV will be described.

[0113] Figure 2 is a cross-sectional schematic diagram showing an example of the structure of the semiconductor device DEV as one embodiment of the present invention. In Figure 2 In the semiconductor device DEV shown, in addition to the storage layers ALYa and ALYb, a storage layer ALYc above the storage layer ALYb is also provided. In addition, the storage layer ALYc includes a storage cell MCc having the same structure as the storage cells MCa and MCb. In addition, in Figure 2 the semiconductor device DEV has a structure in which storage layers are respectively provided below the storage layer ALYa and above the storage layer ALYc.

[0114] In addition, Figure 3 is a cross-sectional schematic diagram focusing on Figure 2 the storage layers ALYa and ALYb in the example of the structure of the semiconductor device DEV, Figure 3 and symbols of the constituent elements of the storage layers ALYa and ALYb are shown as an example in the cross-sectional schematic diagram.

[0115] Note that Figure 3 shows an example of a structure in which the storage layer ALYa is provided on the insulator 122a, the insulator 122b is provided on the storage layer ALYa, and the storage layer ALYb is provided on the insulator 122b. In addition, details of the insulator 122a and the insulator 122b will be described later.

[0116] In addition, Figures 2 to 22D the X direction shown is parallel to the channel length directions of the transistors M1, M2, and M3, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X direction and the Y direction. In addition, Figures 2 to 22D the X direction, Y direction, and Z direction shown are a right-handed system.

[0117] In addition,Figure 4 is a three-dimensional schematic diagram showing a partial structure example of the storage layer ALYa of the semiconductor device DEV shown in Figure 3 . Note that in Figure 4 , in order to easily observe the structure of the storage layer ALYa, the insulators 122b, 180, 180_0, and 175 are not shown. Note that the details of the insulators 122b, 180, 180_0, and 175 will be described later.

[0118] In Figure 4 's storage layer ALYa, as an example, the conductors 160_0, 160_1, 160_2, 160_3, 160_4, 170_2, 170_4, and 170_5 described later are arranged to extend in the Y direction.

[0119] To simply explain the structure example of the semiconductor device DEV, first focus on Figure 3 's storage layer ALYa.

[0120] In the storage layer ALYa, the memory cell MCa is provided on the insulator 122a.

[0121] As described in the circuit structure example, the memory cell MCa includes transistors M1, M2, M3, and a capacitor C1. As an example, Figure 3 the OS transistors are shown as transistors M1 to M3. That is, the semiconductor layers of transistors M1 to M3 each contain a metal oxide.

[0122] In Figure 3 , transistors M1 to M3 each include an insulator 124 and an oxide 130. Transistor M1 includes conductors 142a, 142d, 160_2, 170_0, 160_0, insulators 153_2, and 154_2. Transistor M2 includes conductors 142b, 142c, 160_3, insulators 153_3, and 154_3. Transistor M3 includes conductors 142c, 142d, 160_4, insulators 153_4, and 154_4. Capacitor C1 includes conductors 142a, 160_1, insulators 153_1, and 154_1.

[0123] As an example, the conductors 160_2 to 160_4 are each arranged so as to overlap with the oxide 130. Note that the conductors 160_2 to 160_4 are arranged in sequence in the X direction without overlapping each other. The conductor 160_2 is used as the gate of the transistor M1, the conductor 160_3 is used as the gate of the transistor M2, and the conductor 160_4 is used as the gate of the transistor M3. Note that each gate is sometimes referred to as the first gate. In addition, in this specification and the like, the conductors 160_2 to 160_4 are sometimes referred to as gate electrodes or first gate electrodes. In addition, the conductor 160_2 is used as, for example, Figure 1 the wiring WWLa[i] in Figure 1 In addition, the conductor 160_4 is used as, for example,

[0124] The insulators 153_2 and 154_2 are used as the first gate insulating film in the transistor M1. In addition, the insulators 153_3 and 154_3 are used as the first gate insulating film in the transistor M2. In addition, the insulators 153_4 and 154_4 are used as the first gate insulating film of the transistor M3.

[0125] The insulator 124 is provided on the insulator 122a. In addition, the insulators 122a and 124 are used as the second gate insulating film in the transistor M1.

[0126] As an example, the oxide 130 is provided on the insulator 124. In addition, the oxide 130 is used as the semiconductor included in the channel formation regions of the transistors M1 to M3.

[0127] The conductors 160_0 and 170_0 are used as the back gate (sometimes referred to as the second gate) of the transistor M1. Therefore, in this specification and the like, the conductors 160_0 and 170_0 are sometimes referred to as back gate electrodes or second gate electrodes. In addition, the conductors 160_0 and 170_0 are also used as one of a pair of electrodes of a capacitor included in a memory cell of a memory layer located below the memory layer ALYa.

[0128] In addition, Figure 3 shows the insulators 153_0, 154_0 formed around the conductor 160_0 in the memory layer located below the memory layer ALYa, and the insulator 180_0 (sometimes referred to as a planarization film or an interlayer film) embedding them.

[0129] In addition, in the transistor M1, as an example, the conductor 142a is disposed on the top surface and side surfaces of the oxide 130 and in a region not overlapping with the oxide 130. Specifically, the conductor 142a is disposed on a part of the oxide 130 and a part of the insulator 122a. In addition, as an example, the conductor 142d is disposed on a part of the oxide 130. In particular, the conductor 142a and the conductor 142d are physically separated from each other by the insulator 153_2 and the insulator 154_2. The conductor 142a is used as one of the source and drain in the transistor M1, and the conductor 142d is used as the other of the source and drain in the transistor M1. Therefore, in this specification and the like, the conductor 142a is sometimes referred to as one of the source electrode and the drain electrode, and the conductor 142d is sometimes referred to as the other of the source electrode and the drain electrode. In addition, the conductor 142d is used, for example, as Figure 1 any one of the wirings WRBLa[j], WRBLa[j + 1], and WRBLa[j + 2] or a conductor electrically connected to the wiring. In addition, an insulator 175 for preventing oxygen from diffusing into the conductor 142a and the conductor 142d is provided on the conductor 142a and the conductor 142d.

[0130] In addition, in the transistor M2, as an example, the conductor 142b is disposed on the top surface and side surfaces of the oxide 130 and in a region not overlapping with the oxide 130. Specifically, the conductor 142b is disposed on a part of the oxide 130 and a part of the insulator 122a. Similarly, as an example, the conductor 142c is disposed on a part of the oxide 130. In particular, the conductor 142b and the conductor 142c are physically separated from each other by the insulator 153_3 and the insulator 154_3. The conductor 142b is used as one of the source and drain in the transistor M2, and the conductor 142c is used as the other of the source and drain in the transistor M2. In addition, the conductor 142b is used, for example, as Figure 1 one of the wirings SLa[j] and SLa[j + 1] or a conductor electrically connected to the wiring SLa. In addition, an insulator 175 for preventing oxygen from diffusing into the conductor 142b and the conductor 142c is provided on the conductor 142b and the conductor 142c.

[0131] In addition, in transistor M3, as an example, conductor 142c is disposed on a part of oxide 130. Similarly, as an example, conductor 142d is disposed on a part of oxide 130. In particular, conductor 142c and conductor 142d are physically separated from each other by insulator 153_4 and insulator 154_4. Conductor 142a is used as one of the source and drain in transistor M2, and conductor 142d is used as the other of the source and drain in transistor M3.

[0132] In a region of the top surface of conductor 142a that does not overlap with oxide 130, insulator 153_1, insulator 154_1, and conductor 160_1 are sequentially disposed. In particular, capacitor C1 is formed in a region where conductor 142a and conductor 160_1 overlap with each other with insulator 153_1 and insulator 154_1 interposed therebetween. In other words, a part of conductor 142a is used as one of a pair of electrodes of capacitor C1, and a part of conductor 160_1 is used as the other of a pair of electrodes of capacitor C1. In addition, a part of insulator 153_1 and a part of insulator 154_1 are used as the dielectric of capacitor C1.

[0133] In addition, conductors 160_1 to 160_4 can be formed by different processes or can be formed simultaneously by the same process.

[0134] In addition, storage layer ALYa includes insulator 180 that serves as a planarization film or an interlayer film. Insulator 180 is formed so as to cover transistors M1 to M3. In addition, conductors 160_1 to 160_4 are formed so as to be embedded in insulator 180.

[0135] In addition, insulator 180_0 and insulator 180 can use the same insulating material. In addition, specific insulating materials that can be applied to insulator 180_0 and insulator 180 will be described later.

[0136] In addition, insulator 180 has a first opening in a region that overlaps with conductor 142a and does not overlap with oxide 130. Conductor 170_3 is disposed inside the first opening and on a part of insulator 180. In addition, conductor 170_3 is electrically connected to conductor 160_3.

[0137] In addition, insulator 180 has a second opening in a region that overlaps with conductor 142d. In addition, conductor 170_5 is disposed inside the second opening and on a part of insulator 180. In addition, conductor 170_5 is used as, for example, Figure 1 any one of wirings WRBLa[j], WRBLa[j + 1], and WRBLa[j + 2].

[0138] In addition, a conductor 170_1 is provided on the insulator 180, the insulator 153_1, the insulator 154_1, and the conductor 160_1. The conductor 170_1 or the conductor 160_1 is used as, for example, Figure 1 the wiring CLa[i] in

[0139] In addition, a conductor 170_2 is provided on the insulator 180, the insulator 153_2, the insulator 154_2, and the conductor 160_2. The conductor 170_2 or the conductor 160_2 is used as, for example, Figure 1 the wiring WWLa[i] in

[0140] In addition, a conductor 170_4 is provided on the insulator 180, the insulator 153_4, the insulator 154_4, and the conductor 160_4. The conductor 170_4 or the conductor 160_4 is used as, for example, Figure 1 the wiring RWLa[i] in

[0141] In addition, the conductors 170_1 to 170_5 can be formed by different processes or can be formed simultaneously by the same process.

[0142] In addition, an insulator 122b is provided above the insulator 180 and the conductors 170_1 to 170_5.

[0143] In addition, the insulator 122a and the insulator 122b can use the same insulating material. Specific insulating materials applicable to the insulator 122a and the insulator 122b will be described later.

[0144] A storage layer ALYb is provided on the insulator 122b.

[0145] In Figure 2 and Figure 3 the storage layer ALYb can be formed in the same manner as the storage layer ALYa. In particular, the storage layer ALYb is formed in such a way that the conductor 170_1 overlaps with the gate electrode of the transistor M1 of the storage layer ALYb (corresponding to the conductor 160_2 in the storage layer ALYa). Note that in Figure 2 and Figure 3 the cross-sectional structure of the storage layer ALYb is a structure in which the cross-sectional structure of the storage layer ALYa is inverted 180 degrees in the X-Y plane.

[0146] As in Figure 2 and Figure 3As shown, by forming the semiconductor device DEV, a conductor serving as the back gate electrode of the transistor M1 corresponding to the storage layer ALYb and a conductor serving as the other of the pair of electrodes of the capacitor C1 corresponding to the storage layer ALYa can be formed simultaneously. That is, by adopting Figure 2 and Figure 3 the structure shown, the following effects can be obtained: compared with the prior art, the number of photomasks used to manufacture the semiconductor device DEV can be reduced; and the manufacturing process of the semiconductor device DEV can be shortened.

[0147] In addition, the structure of the semiconductor device DEV of Figure 2 can also be changed according to the situation. For example, Figure 2 the semiconductor device DEV shown includes a plurality of storage layers, but the semiconductor device DEV as one aspect of the present invention may also include only one storage layer.

[0148] In addition, for example, Figure 2 ( Figure 3 ) the structure of the semiconductor device DEV can also be changed to Figure 5 the structure of the semiconductor device DEV shown. Figure 5 The semiconductor device DEV of Figure 2 ( Figure 3 ) is different from the semiconductor device DEV of Figure 2 ( Figure 3 ) in that the conductor 170_1 is not provided on the conductor 160_1 (the conductor 170_0 is not provided on the conductor 160_0). As described above, in Figure 2 ( Figure 3 ), the conductor 170_1 (the conductor 170_0) is used as the back gate electrode of the transistor M1, but in the case where only the conductor 160_1 (the conductor 160_0) is also used as the back gate electrode of the transistor M1, as in Figure 5 the structure of the semiconductor device DEV, the conductor 170_1 (the conductor 170_0) may not be provided.

[0149] In addition, for example, Figure 4 the storage layer ALYa of Figure 6 can also be changed to the structure of the storage layer ALYa shown. Figure 4 The storage layer ALYa of Figure 6 has a structure in which the conductor 160_1 extends in the Y direction, but in the storage layer ALYa of Figure 6 , it is not the conductor 160_1 that extends in the Y direction but the conductor 170_1 that extends in the Y direction. In addition, in Figure 6 the storage layer ALYa, the insulator 153_1, the insulator 154_1, and the conductor 160_1 are formed inside the opening of the insulator 180 (not shown) that overlaps with the insulator 122a.

[0150] As Figure 2 and Figure 3 shown, as an example, by arranging one of a pair of electrodes of capacitor C1 that commonly uses storage layer ALYa and the back gate electrode of transistor M1 of storage layer ALYb, the occupied area of storage cell MC can be reduced. As a result, miniaturization or high integration of the semiconductor device can be achieved, and thus, the storage density can be increased.

[0151] In addition, as Figure 2 and Figure 3 shown, by forming three transistors in one oxide 130, the occupied area of the transistors can be reduced. Specifically, the three transistors commonly use oxide 130, the second terminals of transistor M1 and transistor M3 commonly use conductor 142d, and the first terminals of transistor M2 and transistor M3 commonly use conductor 142c. As a result, transistors M1 to M3 can be formed in an area smaller than the area of the three transistors (for example, an area equivalent to 2.5 transistors). In addition, when electrically connecting multiple transistors, it is necessary to provide wirings such as gates, sources, and drains (sometimes referred to as electrodes or terminals) and contact holes (sometimes referred to as vias) for electrically connecting to the wirings. For example, when electrically connecting the source of the first transistor and the drain of the second transistor, a first contact hole is formed in the wiring corresponding to the source of the first transistor, a second contact hole is formed in the wiring corresponding to the drain of the second transistor, and a wiring for electrically connecting the first contact hole and the second contact hole is formed. On the other hand, as Figure 2 and Figure 3 shown, by forming three transistors in one oxide 130, the above-mentioned contact holes, etc. can be reduced. As a result, the occupied area of the storage cell can be reduced, and miniaturization or high integration of the semiconductor device can be achieved, and thus, the storage density can be increased.

[0152] <Layout Example of Semiconductor Device> Next, the layout of the storage layer included in semiconductor device DEV will be described.

[0153] As an example, Figure 7 is a layout diagram (top view) showing the circuit structure of storage layer ALYa of semiconductor device DEV shown Figure 6 in. In particular, Figure 7 the abstract shows a part of storage cells MCa[i, j], MCa[i + 1, j], MCa[i, j - 1], MCa[i + 1, j - 1], MCa[i, j + 1], MCa[i + 1, j + 1] and their peripheries. Note that for convenience,Figure 7 Also shown is a wiring (conductor 170_0) extending and disposed below the storage layer ALYa. In addition, Figure 7 the insulator included in the semiconductor device DEV is not shown.

[0154] In Figure 7 the top view shown, a conductor 170_0 is disposed below the storage layer ALYa. In addition, an oxide 130 is disposed on the region including the conductor 170_0. In addition, a conductor 142a and a conductor 142d are disposed so as to cover a part of the oxide 130. In addition, a conductor 160_2 is disposed above the region including the range where the conductor 170_0 and the oxide 130 overlap between the conductor 142a and the conductor 142d. Thus, a transistor M1 is formed. In addition, a conductor 170_2 is disposed on the conductor 160_2.

[0155] In addition, an opening PLa provided in an interlayer film (not shown) is located on the conductor 142a. In addition, an opening PLd provided in the interlayer film is located on the conductor 142d. A conductor 170_3 is embedded in the opening PLa, and a conductor 170_5 is embedded in the opening PLd. Thus, the conductor 170_3 embedded in the opening PLa and the conductor 170_5 embedded in the opening PLd are used as wirings or plugs. In particular, the conductor 170_5 extends and is disposed along the Y direction.

[0156] In addition, Figure 7 in the top view shown, a conductor 142b and a conductor 142c are disposed so as to cover a part of the oxide 130. In addition, a conductor 160_3 is disposed in the region where the conductor 142b and the conductor 142c overlap with the oxide 130. Thus, a transistor M2 is formed. In addition, a conductor 170_3 is disposed on the conductor 160_3.

[0157] In addition, Figure 7 in the top view shown, a conductor 160_4 is disposed in the region where the conductor 142c and the conductor 142d overlap with the oxide 130. Thus, a transistor M3 is formed. In addition, a conductor 170_4 is disposed on the conductor 160_4.

[0158] In addition, Figure 7 in the top view shown, an insulator (not shown) is disposed on a part of the conductor 142a, and a conductor 160_1 is disposed on the insulator. By using this insulator as a dielectric, a capacitor C1 is formed with each of a part of the conductor 142a and the conductor 160_1 as a pair of electrodes. In addition, a conductor 170_1 is disposed on the conductor 160_1.

[0159] In addition, the conductor 170_1 included in the storage layer ALYa is also used as the back gate electrode of the transistor M1 in the storage layer ALYb.

[0160] In addition, in Figure 7 the top view, in the storage layer ALYa, the conductors 142e, 142f, and 142g are arranged to extend in the row direction. In addition, the conductor 142a of the transistor M1 also includes a region arranged to extend in the row direction. In addition, the conductors 142e, 142f, and 142g can be formed simultaneously with the conductors 142a, 142b, 142c, and 142d.

[0161] In addition, an opening PLc provided in an interlayer film (not shown) is located on the conductor 142e. In addition, a conductor 170_4 is embedded in the opening PLc. Thus, the conductor 170_4 embedded in the opening PLc is used as a wiring or a plug. Therefore, the conductor 142e and the conductor 160_4 of the transistor M3 are electrically connected to each other.

[0162] In addition, an opening PLb provided in an interlayer film (not shown) is located on the conductor 142f. In addition, a conductor 170_2 is embedded in the opening PLb. Thus, the conductor 170_2 embedded in the opening PLb is used as a wiring or a plug. Therefore, the conductor 142f and the conductor 160_2 of the transistor M1 are electrically connected to each other.

[0163] In addition, an opening PLe provided in an interlayer film (not shown) is located on the conductor 142g. In addition, a conductor 170_1 is embedded in the opening PLe. Thus, the conductor 170_1 embedded in the opening is used as a wiring or a plug. Therefore, the conductor 142g and the conductor 160_1 of the capacitor C1 are electrically connected to each other.

[0164] As Figure 7 shown, the conductor 142e is used as the wiring RWLa[i] or the wiring RWLa[i + 1] arranged to extend in the row direction.

[0165] In addition, as Figure 7 shown, the conductor 142f is used as the wiring WWLa[i] or the wiring WWLa[i + 1] arranged to extend in the row direction.

[0166] As Figure 7 shown, the conductor 142g is used as the wiring CLa[i] or the wiring CLa[i + 1] arranged to extend in the row direction.

[0167] In Figure 1In [the figure], although the wirings SLa[j] and SLa[j + 1] are wirings extending in the column direction, the wiring SLa can also extend in the row direction without extending in the column direction. For example, as Figure 7 shown, the conductor 142b of the transistor M2 can also be used as the wirings SLa[i] and SLa[i + 1] extending in the row direction.

[0168] In addition, as Figure 7 shown, the conductor 170_5 is used as the wirings WRBLa[j] and WRBLa[j + 1] extending in the column direction.

[0169] The oxide 130, the conductors 142a, 142b, 142c, 142d, 142e, 142f, 142g, the conductors 160_1 to 160_4, and the conductors 170_1 to 170_5 can be formed, for example, by lithography. Specifically, for example, in the case of forming the conductor 142a, a conductive material that will become the conductor 142a is formed by using one or more methods selected from sputtering, CVD (Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), and ALD (Atomic Layer Deposition), and then a desired pattern is formed by lithography. In addition, the oxide 130, the conductors 142b, 142c, 142d, 142e, 142f, 142g, the conductors 160_1 to 160_4, and the conductors 170_1 to 170_5 can also be formed by the same method as described above.

[0170] In addition, for example, insulators are provided between the oxide 130 and the conductors 160_2, between the oxide 130 and the conductors 160_3, and between the oxide 130 and the conductors 160_4. In particular, this insulator is sometimes used as a first gate insulating film (sometimes referred to as a gate insulating film or a front gate insulating film).

[0171] In addition, in the process of forming the storage layer ALYa, in order to make the heights of the surfaces of the films formed with one or more selected from insulators, conductors, and semiconductors uniform, planarization can also be performed by using a planarization process such as chemical mechanical polishing (CMP: Chemical Mechanical Polishing).

[0172] Examples of the Structure of the Memory Cell Next, explain Figure 3An example of the structure of the storage layer ALYa of the semiconductor device DEV shown.

[0173] Figures 8A to 8D is Figure 3 A plan view and a cross-sectional view of the storage layer ALYa including the transistor M1, the transistor M2, the transistor M3, and the capacitor C1 in the semiconductor device DEV. Figure 8A is a plan view of the storage layer ALYa. In addition, Figures 8B to 8D is a cross-sectional view of the storage layer ALYa. Here, Figure 8B is a cross-sectional view of the portion along the dotted line A1 - A2 shown in Figure 8A , and is also a cross-sectional view in the channel length direction of the transistor M1. In addition, Figure 8C is a cross-sectional schematic view of the portion along the dotted line A3 - A4 shown in Figure 8A , and is also a cross-sectional schematic view in the channel width direction of the transistor M1. In addition, Figure 8D is a cross-sectional view of the portion along the dotted line A5 - A6 shown in Figure 8A , and is also a cross-sectional view of the capacitor C1. Note that in the top view of Figure 8A , some constituent elements are omitted for clarity of the drawing.

[0174] The storage layer located below the storage layer ALYa includes the insulator 180_0, the insulator 153_0, the insulator 154_0, and the conductor 160_0 on a substrate (not shown). In addition, Figure 8B The first gate electrode and the first gate insulating film of the transistor included in the storage layer located below the storage layer ALYa are also shown.

[0175] In addition, the semiconductor device DEV includes the conductor 170_0 in a part on the conductor of the storage layer located below the storage layer ALYa and in a part on the insulator 180_0. In addition, the semiconductor device DEV includes the insulator 122a covering the insulator 180_0, the conductor located on the insulator 180_0, the insulator 153_0, the insulator 154_0, the conductor 160_0, and the conductor 170_0.

[0176] The storage layer ALYa includes: insulator 124 on insulator 122a in a region including a range overlapping with conductor 160_0; oxide 130 (oxide 130a and oxide 130b) on the top surface of insulator 124; conductor 142a (conductor 142a1 and conductor 142a2) on the top surface and side surfaces of oxide 130; conductor 142b (conductor 142b1 and conductor 142b2) on the top surface and side surfaces of oxide 130; conductor 142c (conductor 142c1 and conductor 142c2) on the top surface of oxide 130; and conductor 142d (conductor 142d1 and conductor 142d2) on the top surface of oxide 130. In addition, the storage layer ALYa includes insulator 175 on the top surfaces of insulator 122a, conductor 142a, conductor 142b, conductor 142c, and conductor 142d and insulator 180 on the top surface of insulator 175.

[0177] In addition, the storage layer ALYa includes an insulator 153_2 located on the top surface and side surfaces of the oxide 130, an insulator 154_2 located on the top surface of the insulator 153_2, and a conductor 160_2 (conductor 160a_2 and conductor 160b_2) located on the top surface of the insulator 154_2. In addition, the storage layer ALYa includes a conductor 170_2 (conductor 170a_2 and conductor 170b_2) located on the top surfaces of the insulator 153_2, the insulator 154_2, the conductor 160_2, and the insulator 180. In addition, the storage layer ALYa includes an insulator 153_3 located on the top surface and side surfaces of the oxide 130, an insulator 154_3 located on the top surface of the insulator 153_3, and a conductor 160_3 (conductor 160a_3 and conductor 160b_3) located on the top surface of the insulator 154_3. In addition, the storage layer ALYa includes a conductor 170_3 (conductor 170a_3 and conductor 170b_3) located on the top surfaces of the insulator 153_3, the insulator 154_3, the conductor 160_3, and the insulator 180. In addition, the storage layer ALYa includes an insulator 153_4 located on the top surface and side surfaces of the oxide 130, an insulator 154_4 located on the top surface of the insulator 153_4, and a conductor 160_4 (conductor 160a_4 and conductor 160b_4) located on the top surface of the insulator 154_4. In addition, the storage layer ALYa includes a conductor 170_4 (conductor 170a_4 and conductor 170b_4) located on the top surfaces of the insulator 153_4, the insulator 154_4, the conductor 160_4, and the insulator 180. In addition, the storage layer ALYa includes an insulator 153_1 located in a region overlapping with the insulator 122a and not overlapping with the oxide 130, an insulator 154_1 located on the top surface of the insulator 153_1, and a conductor 160_1 (conductor 160a_1 and conductor 160b_1) located on the top surface of the insulator 154_1. In addition, the storage layer ALYa includes a conductor 170_1 (conductor 170a_1 and conductor 170b_1) located on the top surfaces of the insulator 153_1, the insulator 154_1, the conductor 160_1, and the insulator 180.

[0178] In addition, in the storage layer ALYa, the insulator 180 has an opening in a region overlapping with the conductor 142a and not overlapping with the oxide 130. In addition, the conductor 170_3 (the conductor 170a_3 and the conductor 170b_3) is located inside the opening and on the top surface of the insulator 180. In addition, in the storage layer ALYa, the insulator 180 also has an opening in a region overlapping with the conductor 142d. In addition, the conductor 170_5 (the conductor 170a_5 and the conductor 170b_5) is located inside the opening and on the top surface of the insulator 180.

[0179] In particular, the transistor M1, the transistor M2, the transistor M3, and the capacitor C1 are embedded in the insulator 180.

[0180] In the region where the transistor M1 is formed, an opening 158_2 reaching the oxide 130b is provided in the insulator 180 and the insulator 175. That is to say, the opening 158_2 includes a region overlapping with the oxide 130b; the insulator 175 has an opening overlapping with the opening of the insulator 180. That is to say, the opening 158_2 includes the opening of the insulator 180 and the opening of the insulator 175.

[0181] In addition, an insulator 153_2, an insulator 154_2, and a conductor 160_2 are arranged inside the opening 158_2. That is to say, the conductor 160_2 includes a region overlapping with the oxide 130b with the insulator 153 and the insulator 154 in between. In addition, in the channel length direction of the transistor M1 (or the transistor M2), a conductor 160_2, an insulator 153_2, and an insulator 154_2 are provided between the conductor 142a and the conductor 142b. The insulator 154_2 includes a region in contact with the side surface of the conductor 160_2 and a region in contact with the bottom surface of the conductor 160_2. In addition, as Figure 8C shown, in the region of the opening 158_2 that does not overlap with the oxide 130, the insulator 122a is in contact with the insulator 153_2.

[0182] Note that although in Figures 8A to 8DAlthough not shown in the figures, in the region where the transistor M2 is formed, openings 158_3 reaching the oxide 130b are provided in the insulator 180 and the insulator 175. In the region where the transistor M3 is formed, openings 158_4 reaching the oxide 130b are provided in the insulator 180 and the insulator 175. Similar to the opening 158_2, it can be said that the openings 158_3 and 158_4 include the openings of the insulator 180 and the openings of the insulator 175. In addition, similar to the opening 158_2, an insulator 153_3, an insulator 154_3, and a conductor 160_3 are disposed in the opening 158_3, and an insulator 153_4, an insulator 154_4, and a conductor 160_4 are disposed in the opening 158_4. Note that the channel width structure of the transistor M2 and the transistor M3 can be referred to Figure 8C to the cross-sectional view of the channel width of the transistor M1 shown

[0183] The oxide 130 preferably includes an oxide 130a disposed on the insulator 124 and an oxide 130b disposed on the oxide 130a. When the oxide 130a is included under the oxide 130b, diffusion of impurities from the structure formed under the oxide 130a to the oxide 130b can be suppressed.

[0184] In addition, although the oxide 130 is shown to have a stacked structure of two layers, the oxide 130a and the oxide 130b, in the transistors M1 to M3, the present invention is not limited thereto. For example, it may have a single layer or a stacked structure of three or more layers of the oxide 130b, or may have a structure in which the oxide 130a and the oxide 130b each have a stacked structure.

[0185] In Figures 8A to 8D the transistor M1 includes an oxide 130 serving as a semiconductor layer, a conductor 160_2 serving as a first gate (also referred to as a gate, a top gate, or a front gate) electrode, a conductor 170_0 serving as a second gate (also referred to as a back gate) electrode, a conductor 142a serving as one of a source electrode and a drain electrode, and a conductor 142d serving as the other of the source electrode and the drain electrode. In addition, it further includes an insulator 153_2 and an insulator 154_2 serving as a first gate insulator. In addition, it further includes an insulator 122a and an insulator 124 serving as a second gate insulator. In addition, the gate insulator is sometimes referred to as a gate insulating layer or a gate insulating film. In addition, at least a part of the region of the oxide 130 overlapping with the conductor 160_2 is used as a channel formation region.

[0186] The first gate electrode and the first gate insulating film are disposed in the opening 158_2 formed in the insulator 180 and the insulator 175. That is, the conductor 160_2, the insulator 154_2, and the insulator 153_2 are disposed in the opening 158_2.

[0187] In addition, transistor M2 includes an oxide 130 serving as a semiconductor layer, a conductor 160_3 serving as a gate (also referred to as a top gate or front gate) electrode, a conductor 142b serving as one of a source electrode and a drain electrode, and a conductor 142c serving as the other of the source electrode and the drain electrode. In addition, insulators 153_3 and 154_3 serving as gate insulators are included. Further, insulators 122a and 124 are included. Additionally, at least a part of the region of the oxide 130 overlapping with the conductor 160_3 is used as a channel formation region.

[0188] In addition, transistor M3 includes an oxide 130 serving as a semiconductor layer, a conductor 160_4 serving as a gate (also referred to as a top gate or front gate) electrode, a conductor 142c serving as one of a source electrode and a drain electrode, and a conductor 142d serving as the other of the source electrode and the drain electrode. In addition, insulators 153_4 and 154_4 serving as gate insulators are included. Further, insulators 122a and 124 are included. Additionally, at least a part of the region of the oxide 130 overlapping with the conductor 160_4 is used as a channel formation region.

[0189] Capacitor C1 includes a conductor 142a serving as a lower electrode, insulators 153_1 and 154_1 serving as a dielectric, and a conductor 160_1 serving as an upper electrode. That is, capacitor C1 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0190] The upper electrode and the dielectric of capacitor C1 are disposed within an opening 159 formed in insulators 180 and 175. That is, the conductor 160_1, the insulator 153_1, and the insulator 154_1 are disposed within the opening 159.

[0191] In addition, an opening of insulators 175 and 180 reaching the conductor 142a is provided in a region of the conductor 142b that does not overlap with the insulator 124 and the oxide 130b. A conductor 170_3 (conductor 170a_3 and conductor 170b_3) is disposed within the opening. The conductor 170_3 is used as a wiring or a plug.

[0192] In addition, as described above, the conductor 170_3 is also located on the insulator 180, the insulator 153_3, the insulator 154_3, and the conductor 160_3. Therefore, the conductor 170_3 and the conductor 160_3 are electrically connected to each other.

[0193] In addition, an opening reaching the insulators 175 and 180 of the conductor 142d is provided on the top surface of the conductor 142d. A conductor 170_5 (conductors 170a_5 and 170b_5) is disposed within the opening. The conductor 170_5 is used as a wiring or a plug.

[0194] In addition, as described above, the conductor 170_2 is located on the insulator 180, the insulator 153_2, the insulator 154_2, and the conductor 160_2. Therefore, the conductor 170_2 and the conductor 160_2 are electrically connected to each other. In addition, the conductor 170_2 is used as a wiring or a plug.

[0195] Similarly, as described above, the conductor 170_4 is located on the insulator 180, the insulator 153_4, the insulator 154_4, and the conductor 160_4. Therefore, the conductor 170_4 and the conductor 160_4 are electrically connected to each other. In addition, the conductor 170_4 is used as a wiring or a plug.

[0196] The storage layer ALYa including the transistors M1, M2, M3, and the capacitor C1 shown in this embodiment can be used in a storage device.

[0197] <<Example of a method for manufacturing a semiconductor device>> Next, an example of a method for manufacturing the storage layer ALYa of the semiconductor device DEV shown in Figures 8A to 8D will be described. In addition, the description of the example of the manufacturing method uses Figures 9A to 22D .

[0198] In Figures 9A to 22D , each of the drawings A is a plan schematic view. In addition, each of the drawings B is a cross-sectional schematic view of a portion along the dotted line A1 - A2 shown in the drawing A, and is also a cross-sectional schematic view in the channel length direction of the transistors M1 to M3. In addition, each of the drawings C is a cross-sectional schematic view of a portion along the dotted line A3 - A4 shown in the drawing A, and is also a cross-sectional schematic view in the channel width direction of the transistor M1. In addition, each of the drawings D is a cross-sectional schematic view of a portion along the dotted line A5 - A6 shown in the drawing A. In addition, in the plan schematic view of each of the drawings A, some of the constituent elements are omitted in order to clearly show the drawings.

[0199] Hereinafter, by appropriately using deposition methods such as sputtering method, CVD method, MBE (Molecular Beam Epitaxy) method, PLD method, or ALD method, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be deposited.

[0200] First, prepare a substrate (not shown), and form a storage layer below the storage layer ALYa on this substrate. For example, form insulator 180_0, insulator 153_0, insulator 154_0, conductor 160_0, conductor 170_0, and insulator 122a on this substrate (refer to Figures 9A to 9D ). In addition, in Figures 9A to 9D , in addition to insulator 180_0, insulator 153_0, insulator 154_0, conductor 160_0, conductor 170_0, and insulator 122a, the first gate electrodes and the first gate insulating films of each of transistors M1 to M3 included in the storage layer below the storage layer ALYa are also shown.

[0201] For example, deposit insulator 180_0 on this substrate, and then form openings in the regions where insulator 153_0, insulator 154_0, and conductor 160_0 are to be formed for insulator 180_0. After forming the openings, sequentially deposit a first insulating film that becomes insulator 153_0, a second insulating film that becomes insulator 154_0, and a first conductive film that becomes conductor 160_0 in the openings, and then perform a planarization process such as chemical mechanical polishing to remove a part of each of the first insulating film, the second insulating film, and the first conductive film, so that insulator 180_0 is exposed. Thus, insulator 153_0, insulator 154_0, and conductor 160_0 can be formed only in the openings formed in insulator 180_0.

[0202] Note that for the formation methods of insulator 180_0, insulator 153_0, insulator 154_0, and conductor 160_0 respectively, refer to the formation methods of insulator 180, insulator 153_1 to insulator 153_4, insulator 154_1 to insulator 154_4, and conductor 160_1 to conductor 160_4 described later (refer to Appendix Figures 14A to 19D ).

[0203] In addition, the first gate electrodes and the first gate insulating films included in each of transistors M1 to M3 included in the storage layer below the storage layer ALYa can also be formed in the same manner as described above. In addition, the first gate insulating films of each of transistors M1 to M3 can be formed simultaneously with insulator 153_0 and insulator 154_0. In addition, the first gate electrodes of each of transistors M1 to M3 can be formed simultaneously with conductor 160_0.

[0204] Then, a second conductive film that becomes the conductor 170_0 is deposited on the top surfaces of the insulator 180_0, the insulator 153_0, the insulator 154_0, and the conductor 160_0, and the second conductive film is processed using lithography technology, whereby the conductor 170_0 can be formed. Note that, regarding the formation of the conductor 170_0, refer to the formation methods of the conductors 170_1 to 170_5 described later (refer to Figures 20A to 22D ).

[0205] Next, an insulator 122a is formed on the insulator 180_0, the insulator 153_0, the insulator 154_0, the conductor 160_0, and the conductor 170_0 (refer to Figures 9A to 9D ). As the insulator 122a, an insulator containing an oxide of one or both of aluminum and hafnium can be used. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. Alternatively, a hafnium zirconium oxide is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 122a has a barrier property against hydrogen and water, it is possible to suppress hydrogen and water contained in the structure provided around the transistors M1 to M3 from diffusing into the inside of the transistors M1 to M3 through the insulator 122a, and thus it is possible to suppress the generation of oxygen vacancies in the oxide 130.

[0206] The insulator 122a is deposited by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the present embodiment, hafnium oxide is deposited as the insulator 122a using the ALD method. In particular, a method for forming hafnium oxide with a reduced hydrogen concentration is preferably used.

[0207] In addition, as the insulating material for the insulator 122a, a high-k material with a high relative dielectric constant can also be used. As the high-k material with a high relative dielectric constant, for example, in addition to the above-mentioned hafnium oxide, metal oxides containing one or more selected from aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be cited. Alternatively, as the insulator 122a, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing an oxide of one or both of aluminum and hafnium, can also be used. Alternatively, as the insulator 122a, a material that can be used for the insulators 153_1 to 153_4 or the insulators 154_1 to 154_4 described later can also be used. In addition, the insulator 122a can also have a stacked structure containing two or more selected from the above-mentioned materials.

[0208] Next, a heat treatment is preferably performed. The temperature of the heat treatment is preferably 250 °C or higher and 650 °C or lower, more preferably 300 °C or higher and 500 °C or lower, and further preferably 320 °C or higher and 450 °C or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the proportion of oxygen gas is preferably set to about 20%. In addition, the heat treatment can also be performed under a reduced pressure state. Alternatively, the heat treatment can be performed in a nitrogen gas or inert gas atmosphere, and then, in order to replenish the oxygen that has escaped, the heat treatment can be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more.

[0209] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment can be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed by the insulator 122a as much as possible.

[0210] In the present embodiment, as the heat treatment, after depositing the insulator 122a, a treatment is performed at a temperature of 400 °C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. By performing this heat treatment, impurities such as water or hydrogen contained in the insulator 122a can be removed. In addition, when using a hafnium-containing oxide as the insulator 122a, sometimes a part of the insulator 122a is crystallized by performing this heat treatment. In addition, the heat treatment can also be performed at the timing after depositing the insulator 124 or the like.

[0211] In addition, in subsequent processes, transistors M1 to M3 and capacitor C1 are formed on the insulator 122a. Therefore, it is preferable to perform a planarization treatment such as the CMP method on the insulator 122a.

[0212] Next, an insulating film 124Af is deposited on the insulator 122a (refer to Figures 10A to 10D ). The insulating film 124Af can be deposited by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the present embodiment, silicon oxide is deposited as the insulating film 124Af by the sputtering method. By using the sputtering method that does not require a molecule containing hydrogen for the deposition gas, the hydrogen concentration in the insulating film 124Af can be reduced. Since the insulating film 124Af comes into contact with the oxide 130a in a later process, it is preferable that the hydrogen concentration is reduced in this way.

[0213] In addition, as the insulating film 124Af, in addition to silicon oxide, for example, an insulating material such as silicon oxynitride can also be used.

[0214] In this specification and the like, "oxynitride" refers to a material in which the oxygen content is more than the nitrogen content in its composition, and "nitroxide" refers to a material in which the nitrogen content is more than the oxygen content in its composition. For example, when it is described as silicon oxynitride, this refers to a material in which the oxygen content is more than the nitrogen content in its composition, and when it is described as silicon nitroxide, this refers to a material in which the nitrogen content is more than the oxygen content in its composition.

[0215] Next, an oxide film 130Af and an oxide film 130Bf are sequentially deposited on the insulating film 124Af (refer to Figures 10A to 10D ). Note that it is preferable to continuously deposit the oxide film 130Af and the oxide film 130Bf without being exposed to the atmospheric environment. By depositing the oxide film without being exposed to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 130Af and the oxide film 130Bf, and it is possible to keep the vicinity of the interface between the oxide film 130Af and the oxide film 130Bf clean.

[0216] The oxide film 130Af and the oxide film 130Bf can be deposited by deposition methods such as sputtering method, CVD method, MBE method, PLD method, or ALD method. In the present embodiment, the sputtering method is used as the formation method of the oxide film 130Af and the oxide film 130Bf.

[0217] For example, in the case of forming the oxide film 130Af and the oxide film 130Bf by the sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. In addition, in the case of forming the above-mentioned oxide film by the sputtering method, the above-mentioned In-M-Zn oxide target or the like can be used.

[0218] In particular, when depositing the oxide film 130Af, sometimes a part of the oxygen contained in the sputtering gas is supplied to the insulating film 124Af. Therefore, the proportion of oxygen contained in the sputtering gas is preferably 70% or more, preferably 80% or more, and more preferably 100%.

[0219] In addition, in the case of forming the oxide film 130Bf by sputtering, an oxygen-excess type oxide semiconductor can be formed by performing deposition under the condition that the proportion of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less. A transistor using the oxygen-excess type oxide semiconductor for the channel formation region can have relatively high reliability. Note that one embodiment of the present invention is not limited to this. In the case of forming the oxide film 130Bf by sputtering, when deposition is performed under the condition that the proportion of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient type oxide semiconductor can be formed. A transistor using the oxygen-deficient type oxide semiconductor for the channel formation region can have a high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by performing deposition while heating the substrate.

[0220] In the present embodiment, as an example, the oxide film 130Af is formed by sputtering using an oxide target of In:Ga:Zn = 1:3:4 [atomic ratio]. In addition, the oxide film 130Bf is deposited by sputtering using an oxide target of In:Ga:Zn = 4:2:4.1 [atomic ratio], an oxide target of In:Ga:Zn = 1:1:1 [atomic ratio], an oxide target of In:Ga:Zn = 1:1:1.2 [atomic ratio], or an oxide target of In:Ga:Zn = 1:1:2 [atomic ratio]. Note that each oxide film is preferably formed by appropriately selecting the deposition conditions and the atomic ratio according to the characteristics required for the oxide 130a and the oxide 130b.

[0221] Note that it is preferable to form the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf by sputtering in a manner not exposed to the atmosphere. For example, a deposition apparatus using a multi-chamber method can be used. Thereby, the entry of hydrogen into the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf between the respective deposition processes can be reduced.

[0222] Note that the oxide film 130Af and the oxide film 130Bf can also be deposited by ALD. By depositing the oxide film 130Af and the oxide film 130Bf by ALD, a film with a uniform thickness can be formed even for a groove or an opening with a large aspect ratio. In addition, by using the PEALD (Plasma-Enhanced Atomic Layer Deposition) method, the oxide film 130Af and the oxide film 130Bf can be formed at a lower temperature compared with the thermal ALD method.

[0223] Next, a heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide films 130Af and 130Bf are not polycrystallized, and this temperature is 250°C or higher and 650°C or lower, preferably 400°C or higher and 600°C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, the proportion of oxygen gas may be set to about 20%. In addition, the heat treatment may also be performed under a reduced pressure state. Alternatively, after performing the heat treatment in an atmosphere of nitrogen gas or an inert gas, in order to fill in the oxygen that has escaped, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more.

[0224] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed by the oxide films 130Af and 130Bf as much as possible.

[0225] In the present embodiment, as the heat treatment, a treatment is performed for 1 hour under the conditions of a flow ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 400°C. By such a heat treatment including oxygen gas, impurities such as carbon, water, or hydrogen in the oxide films 130Af and 130Bf can be reduced. By reducing the impurities in the film in this way, the crystallinity of the oxide film 130Bf is improved, and a denser structure with a higher density can be achieved. Therefore, the crystalline regions in the oxide films 130Af and 130Bf can be increased, and the in-plane non-uniformity of the crystalline regions in the oxide films 130Af and 130Bf can be reduced. Therefore, the in-plane non-uniformity of the electrical characteristics of the transistors M1 to M3 can be reduced.

[0226] In addition, by performing the heat treatment, hydrogen in the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf moves to the insulator 122a and is absorbed by the insulator 122a. In other words, hydrogen in the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf diffuses to the insulator 122a. Therefore, although the hydrogen concentration in the insulator 122a increases, the hydrogen concentration in each of the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf decreases.

[0227] In particular, the insulating film 124Af is used as a gate insulator of the transistor M1. In addition, depending on the situation, the insulating film 124Af is sometimes used as a gate insulator of the transistor M2 and the transistor M3. In addition, the oxide film 130Af and the oxide film 130Bf are used as channel formation regions of the transistors M1 to M3. Therefore, the transistors M1 to M3 including the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf in which the hydrogen concentration is reduced have high reliability and are therefore preferred.

[0228] Next, the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf are processed into stripes by using a lithography technique, thereby forming the insulating layer 124A, the oxide layer 130A, and the oxide layer 130B (see Figures 11A to 11D Here, the insulating layer 124A, the oxide layer 130A, and the oxide layer 130B are parallel to the dotted line A3-A4 (the channel width direction of the transistor M1 or the channel width direction of the transistor M1). Figure 11A In addition, the insulating layer 124A, the oxide layer 130A, and the oxide layer 130B are formed in a manner extending in the Y direction (as shown). In addition, the insulating layer 124A, the oxide layer 130A, and the oxide layer 130B are formed in a manner that at least a portion thereof overlaps with the conductor 160_0. As the above-mentioned processing, a dry etching method or a wet etching method can be used. Processing using the dry etching method is suitable for micro-processing. In addition, the processing of the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf can also be performed under different conditions. In addition, the insulating film 124Af, the oxide film 130Af, and the oxide film 130Bf can also be processed into other shapes other than strips.

[0229] Note that in lithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, the conductor, semiconductor, insulator, etc. are processed into the desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. In addition, a liquid immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above light. Note that when an electron beam or an ion beam is used, a mask is not required. In addition, the resist mask can be removed by performing a dry etching process such as an ashing process, performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

[0230] Furthermore, a hard mask made of an insulator or a conductor may also be used under the resist mask. When using the hard mask, an insulating film or a conductive film that will be the hard mask material is formed on the oxide film 130Bf, and a resist mask is formed thereon, and then the hard mask material is etched, whereby a hard mask having a desired shape can be formed. The etching of the oxide film 130Bf or the like can be performed either after removing the resist mask or without removing the resist mask. In the latter case, the resist mask sometimes disappears during etching. The hard mask can also be removed by etching after the etching of the oxide film 130Bf or the like. On the other hand, when the hard mask material does not affect the subsequent processes or can be used in the subsequent processes, it is not necessarily required to remove the hard mask.

[0231] Next, a conductive film 142Af and a conductive film 142Bf are sequentially deposited on the insulator 122a and the oxide layer 130B (see Figures 12A to 12D ). The conductive film 142Af and the conductive film 142Bf can be deposited by deposition methods such as sputtering, CVD, MBE, PLD, ALD, etc. For example, tantalum nitride can be deposited as the conductive film 142Af by sputtering, and tungsten can be deposited as the conductive film 142Bf. Note that a heat treatment may also be performed before forming the conductive film 142Af. This heat treatment can also be performed under reduced pressure, and the conductive film 142Af is continuously formed in a manner not exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide layer 130B can be removed, and the moisture concentration and hydrogen concentration in the oxide layer 130A and the oxide layer 130B can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In the present embodiment, the temperature of the heat treatment is set to 200°C.

[0232] In addition, as the conductive film 142Af, in addition to tantalum nitride, for example, conductive materials such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, and nitrides containing titanium and aluminum can also be used. In addition, for example, conductive materials such as ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel can also be used. These materials are conductive materials that are not easily oxidized or maintain conductivity even when absorbing oxygen, so they are preferred.

[0233] In addition, as the conductive film 142Bf, in addition to tungsten, for example, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing the above metal elements as components, or alloys combining the above metal elements and other conductive materials can also be used. For example, conductive materials such as titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel can also be used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred.

[0234] In addition, the conductive film 142Af and the conductive film 142Bf can also use materials that can be mutually applied. In addition, the conductive film 142Af and the conductive film 142Bf can also use the same material. That is to say, in the memory cell MCa, the conductor 142a1 and the conductor 142a2 can also be one conductor. Similarly, the conductor 142b1 and the conductor 142b2 can also be one conductor. In addition, similarly, the conductor 142c1 and the conductor 142c2 can also be one conductor. In addition, similarly, the conductor 142d1 and the conductor 142d2 can also be one conductor.

[0235] Next, the insulating layer 124A, the oxide layer 130A, the oxide layer 130B, the conductive film 142Af, and the conductive film 142Bf are processed using lithography technology to form a stacked body of island-shaped insulators 124, oxides 130a, and oxides 130b, and conductive layers 142A and 142B located on the stacked body and on the insulator 122a (refer to Figures 13A to 13D ). For example, the insulating layer 124A, the oxide layer 130A, the oxide layer 130B, the conductive film 142Af, and the conductive film 142Bf are processed to form island-shaped insulators 124, oxides 130a, and oxides 130b, and conductive layers 142A and 142B extending in the direction parallel to the dotted line A1 - A2 (the channel length direction of the transistor M1 or Figure 13A the X direction shown), and then the conductive layers 142A and 142B are processed to form island-shaped conductive layers 142A and 142B.

[0236] Here, an insulator 124, an oxide 130a, an oxide 130b, a conductive layer 142A, and a conductive layer 142B are formed in such a manner that at least a part thereof overlaps with a conductor 160_0. In addition, openings formed in the conductive layer 142A and the conductive layer 142B are formed at positions that do not overlap with the oxide 130b. As the above processing, a dry etching method or a wet etching method can be used. Processing using the dry etching method is suitable for microfabrication. In addition, the insulating layer 124A, the oxide layer 130A, the oxide layer 130B, the conductive film 142Af, and the conductive film 142Bf can also be processed under respective different conditions.

[0237] In addition, as Figures 13B to 13D shown, the side surface shapes of the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B may also be conical shapes. For example, the side surfaces of the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B may be formed such that the cone angle is 60° or more and less than 90°. In this way, when the side surface has a conical shape, the coverage of the insulator 175 and the like formed in the subsequent process is improved, and defects such as voids can be reduced.

[0238] Note that in this specification and the like, the conical shape means a shape in which at least a part of the side surface of the component is inclined with respect to the substrate surface. In addition, the angle formed by the inclined side surface and the substrate surface is called the cone angle. In particular, in this specification and the like, a conical shape having a cone angle of more than 0° and 90° or less is called a positive conical shape, and a conical shape having a cone angle of more than 90° and less than 180° is called a negative conical shape.

[0239] However, without being limited thereto, a structure in which the side surfaces of the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B are substantially perpendicular to the top surface of the insulator 122a may also be adopted. By adopting such a structure, miniaturization and high density can be achieved when a plurality of transistors M1, a plurality of transistors M2, and a plurality of transistors M3 are provided.

[0240] In addition, sometimes by-products generated in the above etching process are formed in a layer on the side surfaces of the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B. In this case, the layer-like by-products are formed between the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, the conductive layer 142B, and the insulator 175. Therefore, it is preferable to remove the layer-like by-products that contact the top surface of the insulator 122a.

[0241] In addition, the shapes of the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B are not limited to Figures 13A to 13D the shapes shown, and can also be processed into other shapes.

[0242] Next, an insulator 175 is deposited so as to cover the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B (refer to Figures 14A to 14D ). Here, the insulator 175 preferably contacts the top surface of the insulator 122a and the side surface of the insulator 124. The insulator 175 can be deposited by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 175 is preferably an insulating film having a function of suppressing oxygen permeation. For example, silicon nitride can be deposited as the insulator 175 by the ALD method. Alternatively, aluminum oxide can be deposited as the insulator 175 by the sputtering method, and silicon nitride can be deposited thereon by the PEALD method. When the insulator 175 has such a stacked structure, the function of suppressing the diffusion of impurities such as water or hydrogen and oxygen is sometimes improved.

[0243] In this way, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B can be covered by the insulator 175 having a function of suppressing oxygen diffusion. Thereby, it is possible to suppress oxygen from directly diffusing into the insulator 124, the oxide 130a, the oxide 130b, the conductive layer 142A, and the conductive layer 142B from the insulator 180 formed later in subsequent processes.

[0244] Next, an insulating film that becomes the insulator 180 is deposited on the insulator 175 (refer to Figures 14A to 14D ). This insulating film can be deposited by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, a silicon oxide film can be deposited as this insulating film by the sputtering method. By depositing this insulating film by the sputtering method in an oxygen-containing atmosphere, an insulator 180 containing excess oxygen can be formed. Note that the excess oxygen here refers to, for example, oxygen that has detached from the insulator 180 due to heat treatment of the insulator 180. In addition, by using a sputtering method that does not require a hydrogen-containing molecule as a deposition gas, the hydrogen concentration in the insulator 180 can be reduced. In addition, a heat treatment can also be performed before depositing this insulating film. This heat treatment can also be performed under reduced pressure, and the insulating film can be continuously deposited without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 175, etc. can be removed, and the moisture concentration and hydrogen concentration in the oxide 130a, the oxide 130b, and the insulator 124 can be reduced. This heat treatment can adopt the conditions of the above heat treatment.

[0245] In addition, as the insulating film that will become the insulator 180, a material with a low dielectric constant is preferably used. Specifically, as materials with a low dielectric constant, for example, in addition to silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be cited. In addition, as materials with a low dielectric constant, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide containing pores can also be cited.

[0246] Next, by performing a planarization process such as the CMP method on the insulating film that becomes the insulator 180, an insulator 180 with a flat top surface is formed (refer to Figures 14A to 14D ). In addition, silicon nitride can be deposited on the insulator 180 by, for example, sputtering until it reaches the insulator 180, and the silicon nitride can be subjected to CMP processing.

[0247] Next, in a region that does not overlap with the insulator 124 and the oxide 130 and overlaps with a part of the conductive layer 142A and a part of the conductive layer 142B, a part of the insulator 180 and a part of the insulator 175 are processed to form an opening 159 that reaches the conductive layer 142B (refer to Figures 15A to 15D ).

[0248] In addition, a part of the insulator 180 and a part of the insulator 175 can be processed by a dry etching method or a wet etching method. In addition, this processing can be performed under different conditions. For example, a part of the insulator 180 can be processed by a dry etching method, and a part of the insulator 175 can be processed by a wet etching method.

[0249] The opening 159 is preferably formed to extend in a direction parallel to Figure 15A the dotted line A5 - A6 shown (the channel width direction of the transistor or Figure 15D the Y direction shown). By forming the opening 159 as described above, the conductor 160_1 formed later can be arranged to extend in the above direction and used as a wiring.

[0250] Next, in a region where the conductor 160_0 overlaps with the oxide 130, a part of the insulator 180, a part of the insulator 175, a part of the conductive layer 142A, and a part of the conductive layer 142B are processed to form an opening 158_2 that reaches the oxide 130b. In addition, in a region including the oxide 130, a part of the insulator 180, a part of the insulator 175, a part of the conductive layer 142A, and a part of the conductive layer 142B are processed to form openings 158_3 and 158_4 that reach the oxide 130b and are different from the opening 158_2.

[0251] By forming openings 158_2 to 158_4, conductors 142a1, 142b1, 142c1, and 142d1 can be formed from conductive layer 142A, and conductors 142a2, 142b2, 142c2, and 142d2 can be formed from conductive layer 142B (see Figures 16A to 16D ).

[0252] Note that when forming opening 159, conductive layer 142A and conductive layer 142B are hardly processed, and when forming openings 158_2 to 158_4, conductive layer 142A and conductive layer 142B are processed. That is, the conditions for forming opening 159 and the conditions for forming openings 158_2 to 158_4 are preferably different from each other. Specifically, for example, when forming opening 159, an etching method with a high selectivity to conductor 142 (the etching method using conductor 142 as the stop film) is preferably used, and when forming openings 158_2 to 158_4, an etching method with a high selectivity to oxide 130b (the etching method using oxide 130b as the stop film) is preferably used.

[0253] In addition, processing using a dry etching method is suitable for microfabrication. In addition, this processing can be performed under different conditions. For example, a part of insulator 180 can be processed by a dry etching method, a part of insulator 175 can be processed by a wet etching method, and a part of conductor 142 can be processed by a dry etching method.

[0254] Openings 158_2 to 158_4 are preferably formed extending in a direction parallel to Figure 16A the dash-dotted line A3 - A4 shown (the channel width direction of the transistor or Figure 16A the Y direction shown). By forming openings 158_2 to 158_4 as described above, conductors 160_2 to 160_4 formed later can be arranged to extend in the above direction and used as wirings. In particular, opening 158_2 is preferably formed so as to overlap conductor 160_0.

[0255] The widths of each of the openings 158_2 to 158_4 are reflected in the channel lengths of the transistors M1 to M3, respectively, and thus are preferably small. For example, the width of each of the openings 158_2 to 158_4 is preferably 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less and 1 nm or more or 5 nm or more. Additionally, depending on the situation, the width of each of the openings 158_2 to 158_4 may also be 1 μm or less, 0.6 μm or less, 0.5 μm or less, 0.4 μm or less, 0.3 μm or less, 0.2 μm or less, or 0.1 μm or less and 10 nm or more or 50 nm or more. Thus, in order to perform microfabrication on each of the openings 158_2 to 158_4, it is preferable to use a lithography technique using light with a short wavelength such as EUV light or an electron beam.

[0256] When performing microfabrication on the openings 158_2 to 158_4, it is preferable to process a part of the insulator 180, a part of the insulator 175, a part of the conductive layer 142B, and a part of the conductive layer 142A using anisotropic etching. In particular, processing using a dry etching method is suitable for microfabrication and is thus preferable. Additionally, this processing can be performed under different conditions for each.

[0257] By processing the insulator 180, the insulator 175, the conductive layer 142B, and the conductive layer 142A using anisotropic etching, for example, in the transistor M1, the opposing sides of the conductor 142a and the conductor 142d can be formed substantially perpendicular to the top surface of the oxide 130b. By adopting such a structure, a so-called Loff region can be formed in the region of the oxide 130 near the end of the conductor 142a and in the region of the oxide 130 near the end of the conductor 142d. Thereby, the frequency characteristics of the transistor M1 can be improved to increase the operating speed of the semiconductor device according to one aspect of the present invention. Note that although the transistor M1 is described above, the same can be said for the transistors M2 and M3.

[0258] Note that not limited to the above structure, the side shapes of the insulator 180, the insulator 175, and the conductor 142 (e.g., the conductor 142a and the conductor 142d) may sometimes be a tapered shape. Additionally, the taper angle of the insulator 180 may sometimes be greater than the taper angle of the conductor 142. Furthermore, when forming the openings 158_2 to 158_4, the top of the oxide 130b may sometimes be removed.

[0259] Due to the above-mentioned etching process, impurities sometimes adhere to the sides of the oxide 130a, the top and sides of the oxide 130b, the sides of the conductors 142a to 142d, and the sides of the insulator 180, etc., or the impurities diffuse into their interiors. A process for removing these impurities can be performed. Additionally, sometimes a damaged region is formed on the surface of the oxide 130b due to the above-mentioned dry etching. Such a damaged region can also be removed. Examples of such impurities include impurities resulting from components such as the insulator 180, the insulator 175, the conductive layer 142B, and the conductive layer 142A; components contained in the members used in the apparatus for forming the above-mentioned opening; components contained in the gas or liquid used for etching, etc. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, or chlorine.

[0260] In particular, impurities such as aluminum and silicon sometimes cause a decrease in the crystallinity of the oxide 130b. Therefore, it is preferable to remove impurities such as aluminum and silicon on and near the surface of the oxide 130b. In addition, it is preferable to reduce the concentration of such impurities. For example, the concentration of aluminum atoms on and near the surface of the oxide 130b can be 5.0 at.% or less, preferably 2.0 at.% or less, more preferably 1.5 at.% or less, further preferably 1.0 at.% or less, and even more preferably less than 0.3 at.%.

[0261] Note that in a region where the crystallinity of the oxide 130b is low due to impurities such as aluminum or silicon, the density of the crystal structure decreases, so a large number of V O H (V O represents an oxygen vacancy, and V O H represents hydrogen entering the defect in V O ) are generated, and the transistor is likely to have a normally-on characteristic (a characteristic in which a channel exists even when no voltage is applied to the gate electrode and current flows through the transistor). Therefore, it is preferable to reduce or remove V O H in the region where the crystallinity of the oxide 130b is low.

[0262] In contrast, the oxide 130b preferably has a layered CAAC structure. Particularly preferably, the lower end portion of the drain of the oxide 130b also has a CAAC structure. Here, in the transistor M1, the conductor 142a or the conductor 142b and its vicinity are used as the drain. In other words, the oxide 130b near the lower end portion of the conductor 142a (conductor 142d) preferably has a CAAC structure. In this way, by removing the region where the crystallinity of the oxide 130b is low at the drain end portion, which has a significant impact on the drain breakdown voltage, and making it have a CAAC structure, the variation in the electrical characteristics of the transistor M1 can be further suppressed. In addition, the reliability of the transistor M1 can be improved.

[0263] In order to remove impurities and the like adhering to the surface of the oxide 130b in the above etching process, a washing process is performed. As the washing method, there are wet washing using a washing liquid or the like (which may also be referred to as wet etching treatment), plasma treatment using plasma, washing using heat treatment, etc., and the above washings may be appropriately combined. Note that sometimes the above-described groove portion becomes deeper by performing this washing process.

[0264] As the wet washing, an aqueous solution diluted with carbonated water or pure water from one or more selected from ammonia water, oxalic acid, phosphoric acid, or hydrofluoric acid can be used. Alternatively, the wet washing can also be performed using pure water or carbonated water. Alternatively, ultrasonic washing can be performed using the above aqueous solution, pure water, or carbonated water. Alternatively, the above washings can be appropriately combined.

[0265] Note that in this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water is sometimes referred to as dilute hydrofluoric acid and an aqueous solution obtained by diluting ammonia water with pure water is sometimes referred to as dilute ammonia water. In addition, the concentration, temperature, etc. of this aqueous solution can be appropriately adjusted according to the impurities to be removed, the structure of the semiconductor device to be washed, etc. The ammonia concentration of the dilute ammonia water is set to 0.01% or more and 5% or less, and preferably set to 0.1% or more and 0.5% or less. In addition, the hydrogen fluoride concentration of the dilute hydrofluoric acid is set to 0.01 ppm or more and 100 ppm or less, and preferably set to 0.1 ppm or more and 10 ppm or less.

[0266] In addition, as the ultrasonic washing, a frequency of 200 kHz or more is preferably used, and a frequency of 900 kHz or more is more preferably used. By using this frequency, the damage to the oxide 130b and the like can be reduced.

[0267] In addition, the above washing process can be performed multiple times, and the washing liquid can be changed for each washing process. For example, a process using dilute hydrofluoric acid or dilute ammonia water can be performed as the first washing process, and a process using pure water or carbonated water can be performed as the second washing process.

[0268] As the above washing process, in this embodiment, wet washing is performed using dilute ammonia water. By performing this washing process, impurities adhering to the surfaces of the oxide 130a and the oxide 130b and the like or diffused into their interiors can be removed. And the crystallinity of the oxide 130b and the like can be improved.

[0269] Heat treatment can also be performed after the above-mentioned etching or the above-mentioned washing. The heat treatment is carried out at 100 °C or higher and 450 °C or lower, preferably at 350 °C or higher and 400 °C or lower. Note that the heat treatment is carried out in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably carried out in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 130a and the oxide 130b to reduce oxygen vacancies. In addition, by performing the above heat treatment, the crystallinity of the oxide 130b can be improved. In addition, the heat treatment can also be carried out under a reduced pressure state. Alternatively, the heat treatment can be carried out in an oxygen atmosphere and then continuously carried out in a nitrogen atmosphere without exposure to the atmosphere.

[0270] In addition, regarding the formation order of the openings 158_2 to 158_4 and the opening 159, the opening 159 can also be formed after the openings 158_2 to 158_4 are formed first. Alternatively, one or more openings selected from the openings 158_2 to 158_4 and the opening 159 can be formed first, and then the other openings can be formed. In addition, the openings 158_2 to 158_4 are preferably formed such that the bottom of each exposes the oxide 130b, and the opening 159 is preferably formed such that its bottom exposes the conductor 142a. Therefore, it is preferable to use processing methods with different conditions to form the openings 158_2 to 158_4 and the opening 159.

[0271] Next, an insulating film 153A (see Figures 17A to 17D ) is formed. The insulating film 153A is an insulating film that will become the insulators 153_1 to 153_4 in the subsequent process. The insulating film 153A can be deposited by a deposition method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating film 153A is preferably deposited by the ALD method. In particular, the insulating film 153A is preferably deposited thinly, and it is necessary to suppress the thickness non-uniformity to be small. In this regard, the ALD method is a deposition method in which a precursor and a reactant (for example, an oxidizing agent) are alternately introduced, and since the film thickness can be adjusted according to the number of times of repeating this cycle, the thickness can be precisely adjusted. In addition, as Figure 17B and Figure 17CAs shown, the insulating film 153A needs to be deposited with high coverage on the bottom and side surfaces of each of the openings 158_2 to 158_4 and the opening 159. In the openings 158_2 to 158_4, the insulating film 253A is preferably deposited with high coverage on the top and side surfaces of the oxide 130. In addition, in the opening 159, the insulating film 153A is preferably deposited with high coverage on the top and side surfaces of the conductor 142a and the top surface of the insulator 122a. By using the ALD method, since atomic layers of each layer can be deposited on the bottom and side surfaces of each of the openings 158_2 to 158_4, the insulating film 153A can be formed with high coverage in each opening.

[0272] In addition, when forming the insulating film 153A by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc. can be used as the oxidant. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as the oxidant, the hydrogen diffusing into the oxide 130b can be reduced.

[0273] In this embodiment, hafnium oxide is deposited as the insulating film 153A by the thermal ALD method.

[0274] Alternatively, as the insulating material for the insulating film 153A, a high-k material with a high relative dielectric constant can also be used. As the high-k material with a high relative dielectric constant, for example, in addition to the above-mentioned hafnium oxide, metal oxides containing one or more metals selected from aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be cited. Alternatively, as the insulating film 153A, alumina, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium, can also be used.

[0275] In addition, as the insulating film 153A, insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide can be used. Alternatively, as the insulating film 153A, an insulating material can be used. As this insulating material, for example, silicon oxide added with fluorine or silicon oxide added with carbon can be cited. Alternatively, as the insulating film 153A, silicon oxide added with carbon and nitrogen can be used. Alternatively, as the insulating film 153A, silicon oxide containing voids can be used. In particular, silicon oxide and silicon oxynitride have thermal stability, so they are preferred. Alternatively, the insulating film 153A can also have a laminated structure containing two or more of the above-mentioned materials.

[0276] Next, it is preferable to perform microwave treatment in an oxygen-containing atmosphere (refer to Figures 17A to 17D)。Here, the microwave treatment refers to, for example, a treatment using a device including a power source for generating a high-density plasma with microwaves. Additionally, in this specification and the like, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Note that when the insulating film 153A has a stacked structure, the microwave treatment can also be performed at the stage of forming a part of the insulating film 153A. For example, when the insulating film 153A includes a silicon oxide film or a silicon oxynitride film, this microwave treatment can also be performed at the stage of depositing the silicon oxide film or the silicon oxynitride film.

[0277] Figures 17B to 17D The dotted arrows in [figure number] indicate high-frequency waves such as microwaves or RF, oxygen plasma, oxygen radicals, etc. The microwave treatment preferably uses, for example, a microwave treatment device including a power source for generating a high-density plasma with microwaves. Here, the frequency of the microwave treatment device is set to 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, and for example, 2.45 GHz is sufficient. By using a high-density plasma, a high density of oxygen radicals can be generated. Additionally, the power of the power source for applying microwaves in the microwave treatment device is 1000 W or more and 10000 W or less, and preferably 2000 W or more and 5000 W or less. Furthermore, the microwave treatment device can also include a power source for applying RF to one side of the substrate. In addition, by applying RF to one side of the substrate, oxygen ions generated from the high-density plasma can be efficiently introduced into the oxide 130b. Through the action of plasma, microwaves, etc., V O H contained in the region of the oxide 130 that does not overlap with the conductors 142a to 142d can be separated to remove hydrogen in this region. In other words, V O H contained in this region can be reduced. Thereby, the oxygen vacancies and V O H in this region can be reduced, and the carrier concentration can be decreased. In addition, by supplying oxygen radicals generated in the above oxygen plasma to the oxygen vacancies formed in this region, the oxygen vacancies in this region can be further reduced, and the carrier concentration can be decreased.

[0278] In addition, as Figures 17B to 17D shown, the conductors 142a to 142d shield the action of high-frequency waves such as microwaves or RF, oxygen plasma, etc., so this action does not affect the region of the oxide 130b that overlaps with the conductors 142a to 142d. Thereby, a decrease in V O H and an excessive supply of oxygen do not occur in this region through the microwave treatment, so a decrease in the carrier concentration can be prevented.

[0279] In addition, an insulating film 153A is provided in contact with the side surfaces of the conductors 142a to 142d. Further, the insulating film 153A preferably has, for example, oxygen barrier properties. Therefore, formation of an oxidized film on the side surfaces of the conductors 142a to 142d due to microwave treatment can be suppressed.

[0280] In addition, the film quality of the insulator 153A can be improved by the above-described process, whereby the reliability of the transistors M1 to M3 is improved.

[0281] As described above, oxygen vacancies and V O H can be selectively removed in the region of the oxide 130 that does not overlap with the conductors 142a to 142d to make this region an i-type or substantially i-type. Also, supply of excessive oxygen to the region of the oxide 130 that overlaps with the conductors 142a to 142d and serves as a source region or a drain region can be suppressed to maintain conductivity. Thereby, variation in the electrical characteristics of the transistors M1 to M3 can be suppressed, and non-uniformity in the electrical characteristics of the transistors M1 to M3 within the substrate surface can be suppressed.

[0282] Note that in microwave treatment, sometimes thermal energy is directly transferred to the oxide 130b due to the electromagnetic interaction between microwaves and molecules in the oxide 130b. Sometimes the oxide 130b is heated by this thermal energy. Sometimes this heat treatment is referred to as microwave annealing. By performing microwave treatment in an oxygen-containing atmosphere, sometimes the same effect as oxygen annealing can be obtained. Further, it is considered that when the oxide 130b contains hydrogen, the above-described thermal energy is transferred to the hydrogen in the oxide 130b and the activated hydrogen is released from the oxide 130b.

[0283] In addition, microwave treatment can also be performed before forming the insulating film 153A without performing microwave treatment after forming the insulating film 153A.

[0284] In addition, a heat treatment can also be performed while maintaining a reduced pressure state after performing microwave treatment after forming the insulating film 153A. By performing such treatment, hydrogen in the insulating film 153A, the oxide 130b, and the oxide 130a can be efficiently removed. In addition, a part of the hydrogen is sometimes gettered by the conductor 142 (conductors 142a to 142d). Alternatively, the step of performing a heat treatment while maintaining a reduced pressure state after performing microwave treatment can be repeated. By repeating the heat treatment, hydrogen in the insulating film 153A, the oxide 130b, and the oxide 130a can be further efficiently removed. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower. In addition, the above-described microwave treatment, i.e., microwave annealing, can also serve as this heat treatment. When the oxide 130b and the like are sufficiently heated by microwave annealing, this heat treatment may not be performed.

[0285] In addition, by performing microwave treatment to modify the film quality of the insulating film 153A, the diffusion of impurities such as hydrogen or water can be suppressed. Thereby, the diffusion of impurities such as hydrogen or water through the insulator 153 into the oxide 130b, oxide 130a, etc. due to subsequent processes such as the deposition of the conductive films that will become the conductors 160_1 to 160_4 or post-treatment such as heat treatment can be suppressed.

[0286] Next, an insulating film 154A that will become the insulators 154_1 to 154_4 is deposited ( Figures 18A to 18D refer to). The insulating film 154A can be deposited by a deposition method such as sputtering, CVD method, MBE method, PLD method, or ALD method. The insulating film 154A is preferably formed by the ALD method in the same manner as the insulating film 153A. By using the ALD method, the insulating film 154A can be formed with high coverage and a small thickness. In the present embodiment, silicon nitride is deposited as the insulating film 154A using the PEALD method.

[0287] In addition, as the insulating film 154A, an insulating material applicable to the insulating film 153A can also be used.

[0288] In addition, the insulating film 154A can also use the same material as the insulating film 153A. That is, in the memory cell MCa, each of the insulators 153_1 to 153_4 and the insulators 154_1 to 154_4 can be one insulator.

[0289] Next, a conductive film 160A that will become the conductors 160a_1 to 160a_4 and a conductive film 160B that will become the conductors 160b_1 to 160b_4 are sequentially deposited (refer to Figures 18A to 18D ). The conductive film 160A and the conductive film 160B can be deposited by a deposition method such as sputtering, CVD method, MBE method, PLD method, or ALD method. In the present embodiment, titanium nitride is deposited as the conductive film 160A using the CVD method or the ALD method, and tungsten is deposited as the conductive film 160B using the CVD method.

[0290] In addition, as the conductive film 160A, in addition to titanium nitride, conductive materials such as tantalum, tantalum nitride, titanium, ruthenium, or ruthenium oxide can also be used. Alternatively, the conductive film 160A can also have a stacked structure including two or more selected from the above materials. In addition, as the conductive film 160B, in addition to tungsten, conductive materials such as copper or aluminum can also be used. In addition, the conductive film 160B can also have a stacked structure including two or more selected from the above materials.

[0291] Next, the insulating film 153A, the insulating film 154A, the conductive film 160A, and the conductive film 160B are polished by performing a planarization process such as a CMP method until the insulator 180 is exposed. In other words, the portions of the insulating film 153A, the insulating film 154A, the conductive film 160A, and the conductive film 160B exposed from the opening 158_2 to the opening 158_4 and the opening 159 are removed. Thus, the insulator 153_2, the insulator 154_2, and the conductor 160_2 (conductor 160a_2 and conductor 160b_2) are formed in the opening 158_2, the insulator 153_3, the insulator 154_3, and the conductor 160_3 (conductor 160a_3 and conductor 160b_3) are formed in the opening 158_3, and the insulator 153_4, the insulator 154_4, and the conductor 160_4 (conductor 160a_4 and conductor 160b_4) are formed in the opening 158_4. In addition, the insulator 153_1, the insulator 154_1, and the conductor 160_1 (conductor 160a_1 and conductor 160b_1) are formed in the opening 159 (see Figures 19A to 19D ).

[0292] Thus, the insulator 153_2 is provided in contact with the inner wall and side surface of the opening 158_2 overlapping the oxide 130b, and the conductor 160_2 is arranged in such a manner as to be embedded in the opening 158_2 via the insulator 153_2 and the insulator 154_2. Thus, the transistor M1 is formed. Similarly, the insulator 153_3 is provided in contact with the inner wall and side surface of the opening 158_3 overlapping the oxide 130b, and the conductor 160_3 is arranged in such a manner as to be embedded in the opening 158_3 via the insulator 153_3 and the insulator 154_3. Thus, the transistor M2 is formed. In addition, similarly, the insulator 153_4 is provided in contact with the inner wall and side surface of the opening 158_4 overlapping the oxide 130b, and the conductor 160_4 is arranged in such a manner as to be embedded in the opening 158_4 via the insulator 153_4 and the insulator 154_4. Thus, the transistor M3 is formed.

[0293] In addition, the insulator 153_1 is provided so as to be in contact with the inner wall and side surface of the opening 159 overlapping the conductor 142a, and the conductor 160_1 is arranged so as to be embedded in the opening 159 via the insulator 153_1 and the insulator 154_1. Thus, the capacitor C1 is formed.

[0294] Next, heat treatment can also be performed under the same conditions as the above heat treatment. In the present embodiment, the treatment is performed at a temperature of 400°C for 1 hour in a nitrogen atmosphere. By this heat treatment, the moisture concentration and hydrogen concentration in the insulator 180 can be reduced. In addition, after the above heat treatment, the formation of the conductors 170_1 to 170_5 described below can be continuously performed without being exposed to the atmosphere.

[0295] Next, in a region overlapping with the conductor 142a and not overlapping with the insulator 124 and the oxide 130, a part of the insulator 180 and a part of the insulator 175 are processed to form an opening 157_3 reaching the conductor 142a. Similarly, in a region overlapping with the conductor 142d, a part of the insulator 180 and a part of the insulator 175 are processed to form an opening 157_5 reaching the conductor 142d (see Figures 20A to 20D ).

[0296] In addition, a part of the insulator 180 and a part of the insulator 175 can be processed by a dry etching method or a wet etching method. Processing using the dry etching method is suitable for microfabrication. In addition, this processing can be performed under different conditions. For example, a part of the insulator 180 can be processed by the dry etching method, and a part of the insulator 175 can be processed by the wet etching method.

[0297] In addition, as a method for forming one or both of the opening 157_3 and the opening 157_5, a processing method capable of forming the openings 158_2 to 158_4 or the opening 159 can also be used.

[0298] Next, a conductive film 170A that will become the conductors 170a_1 to 170a_5 and a conductive film 170B that will become the conductors 170b_1 to 170b_5 are sequentially formed on the insulators 153_1 to 153_4, the insulators 154_1 to 154_4, and the conductors 160_1 to 160_4 (see Figures 21A to 21D ). The conductive film 170A and the conductive film 170B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In particular, the conductive film 170A is preferably formed with high coverage on the bottom surface and side surfaces of the opening 157_3 and the opening 157_5. Therefore, as an example, the CVD method or the ALD method is preferably used to form the conductive film 170A. In addition, as an example, the CVD method is preferably used to form the conductive film 170B.

[0299] In addition, as the conductive film 170A, a material applicable to the conductive film 160A can be used. In addition, as the conductive film 170B, a material applicable to the conductive film 160B can be used. Note that since the conductive films 170A and 170B are processed in subsequent processes, the materials applied to the conductive films 170A and 170B are preferably different from those of the conductive films 160A and 160B. Specifically, for example, in the case where an etching process is used as the processing treatment, a material with an etching rate faster than that of the conductor 160_2 is preferably used as the material applied to the conductive films 170A and 170B.

[0300] Next, the conductive films 170A and 170B are processed using lithography to form island-shaped conductors 170_1 (conductors 170a_1 and 170b_1), conductors 170_2 (conductors 170a_2 and 170b_2), conductors 170_3 (conductors 170a_3 and 170b_3), conductors 170_4 (conductors 170a_4 and 170b_4), and conductors 170_5 (conductors 170a_5 and 170b_5) (see Figures 22A to 22D ). In particular, through this processing, the conductor 170_3 becomes a wiring that makes the conductor 142a of the transistor M1 and the conductor 160_3 of the transistor M3 in a conductive state.

[0301] Next, an insulator 122b is deposited on the insulator 180, insulators 153_1 to 153_4, insulators 154_1 to 154_4, conductors 160_1 to 160_4, and conductors 170_1 to 170_5 (see Figures 8A to 8D ). The insulator 122b can be deposited using a deposition method such as sputtering, CVD, MBE, PLD, or ALD. As the insulator 122b, for example, hafnium oxide with a reduced hydrogen concentration is preferably deposited using the ALD method in the same manner as the insulator 122a.

[0302] Note that for other materials and other formation methods of the insulator 122b, the description of the insulator 122a can be referred to.

[0303] In addition, in subsequent processes, transistors M1, M2, M3, and capacitor C1 included in the storage layer ALYb are sometimes formed on the insulator 122b. Therefore, it is preferable to perform a planarization process such as CMP on the insulator 122b.

[0304] Through the above processes, a Figure 2 or Figure 3 semiconductor device including the memory cell MCa as shown can be manufactured. As Figures 9A to 22DAs shown, by using the method for manufacturing a semiconductor device according to the present embodiment, the capacitor C1, transistors M1 to M3 can be manufactured in the same process. Thus, the manufacturing process of the semiconductor device including the capacitor C1, transistors M1 to M3 can be reduced.

[0305] In addition, a semiconductor device including Figure 2 or Figure 3 the memory cell MCa shown can reduce the occupied area of the memory cell. That is, the storage density of the semiconductor device can be increased.

[0306] In addition, the method for manufacturing a semiconductor device according to one aspect of the present invention is not limited to Figures 8A to 22D the method shown. The method for manufacturing a semiconductor device can change materials and processes according to the situation.

[0307] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in the present embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments of the present invention and used.

[0308] (Embodiment 2) In the present embodiment, a semiconductor device having a structure different from that of the semiconductor device described in the above embodiment will be described.

[0309] <Example of the circuit structure of the semiconductor device> Figure 23 is a circuit diagram showing an example of the structure of a semiconductor device DEVA according to one aspect of the present invention. As an example, the semiconductor device DEVA includes a plurality of memory layers. In addition, in Figure 23 as an example of the plurality of memory layers, a memory layer ALYa, a memory layer ALYb, and a memory layer ALYc are shown. In addition, the memory layer ALYb is located above the memory layer ALYa, and the memory layer ALYc is located above the memory layer ALYb. In addition, a memory layer different from the memory layer ALYb and the memory layer ALYc can be located below the memory layer ALYa, and a memory layer different from the memory layer ALYa and the memory layer ALYb can be located above the memory layer ALYc.

[0310] The semiconductor device DEVA includes a plurality of memory cells. In particular, the memory layer ALYa and the memory layer ALYb share a plurality of memory cells MCA, and the memory layer ALYb and the memory layer ALYc share a plurality of memory cells MCB. In addition, the memory layer ALYa and the memory layer located below the memory layer ALYa share a plurality of memory cells MCZ, and the memory layer ALYc and the memory layer located above the memory layer ALYc share a plurality of memory cells MCC. Note that in Figure 23Among them, as an example, as the storage unit MCA, the storage units MCA[i, j] and MCA[i, j + 2] are shown. As the storage unit MCB, the storage unit MCB[i, j + 1] is shown. As the storage unit MCZ, the storage unit MCZ[i, j + 1] is shown. And as the storage unit MCC, the storage units MCC[i, j] and MCC[i, j + 2] are shown. Note that i and j will be described later.

[0311] As an example, a plurality of storage units MCA are arranged in a matrix in the storage layers ALYa and ALYb. For example, in Figure 23 Among them, the storage units MCA are arranged in a matrix with N (where N is an integer of 1 or more) in the row direction and M (where M is an integer of 1 or more) in the column direction, that is, arranged in a matrix of M×N. Similarly, in the storage layers ALYb and ALYc, as an example, a plurality of storage units MCB are arranged in a matrix of M×N. In the storage layer ALYc and the storage layer above the storage layer ALYc, as an example, a plurality of storage units MCC are arranged in a matrix of M×N. And in the storage layer ALYa and the storage layer below the storage layer ALYa, as an example, a plurality of storage units MCZ are arranged in a matrix of M×N.

[0312] Here, the storage unit MCA is the storage unit in the i-th row and the (2k - 1)-th column (k is an integer of 1 or more and N or less) in the storage layers ALYa and ALYb. In addition, the storage unit MCB is the storage unit in the i-th row and the 2k-th column in the storage layers ALYb and ALYc. In addition, the storage unit MCC is the storage unit in the i-th row and the (2k - 1)-th column in the storage layer ALYc and the storage layer above the storage layer ALYc. In addition, the storage unit MCZ is the storage unit in the i-th row and the 2k-th column in the storage layer ALYa and the storage layer below the storage layer ALYa.

[0313] Note that in Figure 23 Among them, i is an integer of 1 or more and M or less. In addition, j is a number that satisfies 2k - 1 = j or 2k - 1 = j + 2. At this time, Figure 23 The j shown is an odd number of 1 or more and 2N - 3 or less. At this time, 2k = j + 1 is satisfied. Figure 23 The j + 1 shown is an even number of 2 or more and 2N - 2 or less.

[0314] The transistors M2 and M3 are arranged in the (2k - 1)-th column of the i-th row in the storage layer ALYa. That is, in Figure 23In [context], a transistor M2 and a transistor M3 are respectively arranged at the j-th column and the (j + 2)-th column of the i-th row of the storage layer ALYa. In addition, a transistor M1 and a capacitor C1 are arranged at the (2k - 1)-th column of the i-th row of the storage layer ALYb. That is to say, in Figure 23 In [context], a transistor M1 and a capacitor C1 are respectively arranged at the j-th column and the (j + 2)-th column of the i-th row of the storage layer ALYb.

[0315] Summarizing the above content, in the storage layer ALYa and the storage layer ALYb, the memory cell MCA[i, j] includes the transistor M2 and the transistor M3 at the j-th column of the i-th row of the storage layer ALYa and the transistor M1 and the capacitor C1 at the j-th column of the i-th row of the storage layer ALYb. In addition, the memory cell MCA[i, j + 2] includes the transistor M2 and the transistor M3 at the (j + 2)-th column of the i-th row of the storage layer ALYa and the transistor M1 and the capacitor C1 at the (j + 2)-th column of the i-th row of the storage layer ALYb.

[0316] In addition, a transistor M2 and a transistor M3 are arranged at the 2k-th column of the i-th row of the storage layer ALYb. That is to say, in Figure 23 In [context], a transistor M2 and a transistor M3 are arranged at the (j + 1)-th column of the i-th row of the storage layer ALYb. In addition, a transistor M1 and a capacitor C1 are arranged at the 2k-th column of the i-th row of the storage layer ALYc. That is to say, in Figure 23 In [context], a transistor M1 and a capacitor C1 are arranged at the (j + 1)-th column of the i-th row of the storage layer ALYc.

[0317] In short, in the storage layer ALYb and the storage layer ALYc, the memory cell MCB[i, j + 1] includes the transistor M2 and the transistor M3 at the (j + 1)-th column of the i-th row of the storage layer ALYb and the transistor M1 and the capacitor C1 at the (j + 1)-th column of the i-th row of the storage layer ALYc.

[0318] Similarly, in the storage layer ALYc and the storage layer above the storage layer ALYc, the memory cell MCC includes the transistor M2 and the transistor M3 arranged in the storage layer ALYc and the transistor M1 and the capacitor C1 arranged in the storage layer above the storage layer ALYc. In addition, similarly, in the storage layer ALYa and the storage layer below the storage layer ALYa, the memory cell MCC includes the transistor M1 and the capacitor C1 arranged in the storage layer ALYa and the transistor M2 and the transistor M3 arranged in the storage layer below the storage layer ALYa.

[0319] Note that, regarding Figure 23 the transistors M1 to M3 and the capacitor C1 included in the semiconductor device DEVA, reference may be made to the transistors M1 to M3 and the capacitor C1 described in Embodiment 1.

[0320] In Figure 23 each of the memory cells MCA, MCB, MCC, and MCZ included in the semiconductor device DEVA, the first terminal of the transistor M1 is electrically connected to the gate of the transistor M2 and the first terminal of the capacitor C1. Further, the first terminal of the transistor M2 is electrically connected to the first terminal of the transistor M3.

[0321] That is to say, Figure 23 the memory cells MCA, MCB, MCC, and MCZ included in the semiconductor device DEVA all have the structure of the gain cell called NOSRAM (registered trademark) described in Embodiment 1.

[0322] In Figure 23 , the wiring SLa is provided to extend on the 2k - 1-th column of the memory layer ALYa. Specifically, in the memory layer ALYa, the wiring SLa[j] is provided to extend on the j-th column, and the wiring SLa[j + 2] is provided to extend on the j + 2-th column. Further, the wiring SLb is provided to extend on the 2k-th column of the memory layer ALYb. Specifically, the wiring SLb[j + 1] is provided to extend on the j + 1-th column of the memory layer ALYb. In addition, the wiring SLc is provided to extend on the 2k - 1-th column of the memory layer ALYc. Specifically, the wiring SLc[j] is provided to extend on the j-th column of the memory layer ALYc, and the wiring SLc[j + 2] is provided to extend on the j + 2-th column.

[0323] In addition, in Figure 23 , the wiring WRBLa is provided to extend on the 2k-th column of the memory layer ALYa. Specifically, the wiring WRBLa[j + 1] is provided to extend on the j + 1-th column of the memory layer ALYa. Further, the wiring WRBLb is provided to extend on the 2k - 1-th column of the memory layer ALYb. Specifically, in the memory layer ALYb, the wiring WRBLb[j] is provided to extend on the j-th column, and the wiring WRBLb[j + 2] is provided to extend on the j + 2-th column. In addition, the wiring WRBLc is provided to extend on the 2k-th column of the memory layer ALYc. Specifically, the wiring WRBLc[j + 1] is provided to extend on the j + 1-th column of the memory layer ALYc. Note that in Figure 23 , for convenience, the wiring WRBLa[j + 3] is provided to extend in the memory layer ALYa, and the wiring WRBLc[j + 3] is provided to extend in the memory layer ALYc.

[0324] In addition, in Figure 23Among them, wiring WWLa[i], wiring RWLa[i], and wiring CLa[i] are arranged to extend on the i-th row of the storage layer ALYa. In addition, wiring WWLb[i], wiring RWLb[i], and wiring CLb[i] are arranged to extend on the i-th row of the storage layer ALYb. In addition, wiring WWLc[i], wiring RWLc[i], and wiring CLc[i] are arranged to extend on the i-th row of the storage layer ALYc.

[0325] In Figure 23 Among them, wiring WWLa is used as the write word line for the memory cell MCZ, wiring WWLb is used as the write word line for the memory cell MCA, and wiring WWLc is used as the write word line for the memory cell MCB. In addition, wiring RWLa is used as the read word line for the memory cell MCA, wiring WWLb is used as the read word line for the memory cell MCB, and wiring WWLc is used as the read word line for the memory cell MCC. In addition, wiring WRBLa is used as the write bit line for the memory cell MCZ and the read bit line for the memory cell MCA. Wiring WRBLb is used as the write bit line for the memory cell MCA and the read bit line for the memory cell MCB. Wiring WRBLc is used as the write bit line for the memory cell MCB and the read bit line for the memory cell MCC.

[0326] In addition, for the description of the signals (such as potential or current) respectively sent to wiring WWLa to wiring WWLc, wiring RWLa to wiring RWLc, and wiring WRBLa to wiring WRBLc, reference can be made to the description of the signals respectively sent to wiring WWLa and wiring WWLb, wiring RWLa and wiring RWLb, and wiring WRBLa and wiring WRBLb described in Embodiment 1.

[0327] In addition, in Figure 23 Among them, wiring SLa is used as the wiring for supplying a fixed potential to the memory cell MCA and the memory cell MCZ, wiring SLb is used as the wiring for supplying a fixed potential to the memory cell MCA and the memory cell MCB, and wiring SLc is used as the wiring for supplying a fixed potential to the memory cell MCB and the memory cell MCC.

[0328] Note that wiring CLa to wiring CLc can also be used as the wiring for supplying variable potential according to the situation.

[0329] In the storage cell MCA[i, j], the second terminal of the transistor M1 is electrically connected to the wiring WRBLb[j], the gate of the transistor M1 is electrically connected to the wiring WWLb[i], and the back gate of the transistor M1 is electrically connected to the wiring CLa[i]. The second terminal of the capacitor C1 is electrically connected to the wiring CLb[i]. The second terminal of the transistor M2 is electrically connected to the wiring SLa[j]. The second terminal of the transistor M3 is electrically connected to the wiring WRBLa[j + 1], and the gate of the transistor M3 is electrically connected to the wiring RWLa[i].

[0330] Similarly, in the storage cell MCB[i, j + 1], the second terminal of the transistor M1 is electrically connected to the wiring WRBLc[j + 1], the gate of the transistor M1 is electrically connected to the wiring WWLc[i], and the back gate of the transistor M1 is electrically connected to the wiring CLb[i]. The second terminal of the capacitor C1 is electrically connected to the wiring CLc[i]. The second terminal of the transistor M2 is electrically connected to the wiring SLb[j + 1]. The second terminal of the transistor M3 is electrically connected to the wiring WRBLb[j + 2], and the gate of the transistor M3 is electrically connected to the wiring RWLb[i].

[0331] Next, an explanation will be given regarding Figure 23 writing data to and reading data from the storage cells MCA to MCC and the storage cell MCZ in the semiconductor device DEVA shown. Here, as an example, an explanation will be given regarding writing data to the storage cell MCA[i, j] in the storage layers ALYa and ALYb of the semiconductor device DEVA and reading data from the storage cell MCA[i, j].

[0332] When writing data to Figure 23 the storage cell MCA[i, j] of the semiconductor device DEVA shown, for example, first a first potential (e.g., a ground potential) is supplied to the wiring CLb[i]. Next, a high-level potential is supplied to the wiring WWLb[i] such that the transistor M1 included in the storage cell MCA[i, j] is in an ON state, and a low-level potential is supplied to the wirings WWLb[1] to WWLb[m] other than the wiring WWLb[i] such that the transistors M1 included in the storage cells MCA on the first to mth rows other than the ith row are in an OFF state. Further, a low-level potential is supplied to the wirings RWLa[1] to RWLa[m] such that the transistors M3 included in all the storage cells MCA are in an OFF state.

[0333] Then, write data to the wiring WRBLb[j], thereby writing a potential corresponding to the data to the first terminal of the capacitor C1 of the memory cell MCA[i, j]. After writing data to the first terminal of the capacitor C1 of the memory cell MCA[i, j], supply a low-level potential to the wiring WWLb[i] so that the transistor M1 included in the memory cell MCA[i, j] is in the off state. Thus, the data writing operation for the memory cell MCA[i, j] ends.

[0334] When reading data from the memory cell MCA[i, j] of the semiconductor device DEV shown in Figure 23 For example, first, supply a second potential (e.g., a high-level potential higher than the first potential) to the wiring WRBLa[j + 1]. Then, supply a high-level potential to the wiring RWLa[i] so that the transistor M3 included in the memory cell MCA[i, j] is in the on state. At this time, when the transistor M2 in the memory cell MCA[i, j] operates in the saturation region, a current corresponding to the gate-source voltage of the transistor M2 (the potential difference between the potential of the gate of the transistor M2 and the potential of the wiring SLa[j]) flows. Thus, this current flows from the wiring WRBLa[j + 1] through the transistor M2 to the wiring SLa[j]. By inputting the current flowing through the wiring WRBLa[j + 1] to the readout circuit, the data written in the memory cell MCA[i, j] can be read out. Note that here, the data written in the memory cell MCA[i, j] is read according to the amount of current, but the data written in the memory cell MCA[i, j] can also be read according to the voltage change of the wiring WRBLa[j + 1].

[0335] Note that regarding writing data to or reading data from other memory cells MCA, MCB, MCC, and MCZ, the same operations as described above can also be performed.

[0336] Note that the circuit structure of the semiconductor device according to one aspect of the present invention is not limited to Figure 23 the structure. The circuit structure of the semiconductor device can also be changed according to the situation.

[0337] For example, in Figure 23Among them, the numbers of the memory cells MCA, MCB, MCC, and MCZ are each M×N, but the numbers of the memory cells MCA and MCC can also be each M×N, and the numbers of the memory cells MCB and MCC can be each M×N - 1. Specifically, the number of columns of the memory cell MCA can be N columns in the memory layers ALYa and ALYb, the number of columns of the memory cell MCC can be N columns in the memory layer ALYc and the memory layer above the memory layer ALYc, the number of columns of the memory cell MCB can be N - 1 columns in the memory layers ALYb and ALYc, and the number of columns of the memory cell MCZ can be N - 1 columns in the memory layer ALYa and the memory layer below the memory layer ALYa.

[0338] <Example of cross-sectional structure of semiconductor device> Next, an example of the structure of the semiconductor device DEVA will be described.

[0339] Figure 24 It is a cross-sectional schematic view showing an example of the structure of the semiconductor device DEVA as one embodiment of the present invention. In Figure 24 In the shown semiconductor device DEVA, in addition to the memory layers ALYa, ALYb, and ALYc, memory layers are also provided above the memory layer ALYc and below the memory layer ALYa.

[0340] In addition, Figure 25 is Figure 24 A cross-sectional schematic view focusing on the memory layers ALYa and ALYb in the example of the structure of the semiconductor device DEVA, and symbols of the respective components of the memory layers ALYa, ALYb, and ALYc are shown as an example in Figure 25 the cross-sectional schematic view.

[0341] In addition, Figure 25 An example of the structure is shown: a memory layer ALYa is provided on the insulator 122a, an insulator 122b is provided on the memory layer ALYa, a memory layer ALYb is provided on the insulator 122b, an insulator 122c is provided on the memory layer ALYb, and a memory layer ALYc is provided on the insulator 122c. Note that the insulators 122a to 122c can refer to the insulators 122a and 122b described in Embodiment 1.

[0342] In addition, Figures 24 to 31 The shown X direction is parallel to the channel length directions of the transistors M1, M2, and M3 respectively, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X direction and the Y direction. In addition, Figures 24 to 31 the shown X direction, Y direction, and Z direction are a right-handed system.

[0343] In addition, Figure 26 is a perspective schematic diagram showing Figure 24 a structural example of a part of the storage layer ALYa and the storage layer ALYb of the semiconductor device DEV. Note that in Figure 26 , in order to easily see the structures of the storage layer ALYa and the storage layer ALYb, the insulators 180 and 175 are not shown. Note that for the details of each of the insulators 180 and 175, reference can be made to the insulators 180 and 175 described in Embodiment 1.

[0344] In Figure 26 's storage layer ALYa, as an example, the conductors 160_1, 160_2, 160_3, 160_4, and 170_5 described later are arranged to extend in the Y direction.

[0345] In Figure 24 and Figure 25 's storage layer ALYa and storage layer ALYb shown, the memory cell MCA is arranged above the insulator 122a.

[0346] As described in the circuit structure example, the memory cell MCA includes the transistors M1, M2, M3, and the capacitor C1. In particular, the transistors M2 and M3 are arranged above the insulator 122a, and the transistors M1 and the capacitor C1 are arranged above the insulator 122b. Note that, as an example, Figure 24 and Figure 25 show the OS transistor as the transistors M1 to M3. That is, the semiconductor layers of the transistors M1 to M3 each contain a metal oxide.

[0347] Next, the components of the semiconductor device DEVA will be described. Note that for simplicity, attention is focused here on Figure 25 's storage layer ALYa. In addition, descriptions of content that is repetitive with the semiconductor device DEV shown in Figure 2 and Figure 3 described in Embodiment 1 may sometimes be omitted.

[0348] In Figure 24 and Figure 25In the storage layer ALYa shown, each of the transistors M1 to M3 includes an insulator 124 and an oxide 130. In addition, transistor M1 includes a conductor 142a, a conductor 142d, a conductor 160_2, an insulator 153_2, and an insulator 154_2. In addition, transistor M2 includes a conductor 142b, a conductor 142c, a conductor 160_3, an insulator 153_3, and an insulator 154_3. In addition, transistor M3 includes a conductor 142c, a conductor 142d, a conductor 160_4, an insulator 153_4, and an insulator 154_4. In addition, capacitor C1 includes a conductor 142a, a conductor 160_1, an insulator 153_1, and an insulator 154_1.

[0349] In addition, transistor M1 includes a conductor 171_1 embedded in insulator 122a.

[0350] As an example, conductors 160_2 to 160_4 are arranged to overlap with the region including oxide 130. Conductor 160_2 is used as the gate of transistor M1, conductor 160_3 is used as the gate of transistor M2, and conductor 160_4 is used as the gate of transistor M3. Note that each gate is sometimes referred to as the first gate. In addition, in this specification and the like, conductors 160_2 to 160_4 are sometimes referred to as gate electrodes or first gate electrodes. In addition, conductor 160_2 is used as, for example, Figure 23 the wiring WWLa[i] in. In addition, conductor 160_4 is used as, for example, Figure 23 the wiring RWLa[i] in.

[0351] Insulators 153 and 154_2 are used as the first gate insulating film in transistor M1. In addition, insulators 153_3 and 154_3 are used as the first gate insulating film in transistor M2. In addition, insulators 153_4 and 154_4 are used as the first gate insulating film in transistor M3.

[0352] Insulator 124 is provided on insulator 122a. In addition, insulators 122a and 124 are used as the second gate insulating film in transistor M1.

[0353] As an example, oxide 130 is provided on insulator 124. In addition, conductors 160_2 to 160_4 are each arranged to overlap with the region including oxide 130. Oxide 130 is used as the semiconductor included in the channel formation regions of transistors M1 to M3.

[0354] The conductor 171_1 embedded in the insulator 122a is used as a back gate (sometimes referred to as a second gate) in the transistor M1. Thus, in this specification and the like, the conductor 171_1 is sometimes referred to as a back gate electrode or a second gate electrode. Further, the conductor 171_1 is also used as one of a pair of electrodes of a capacitor included in a memory cell of a memory layer located below the memory layer ALYa.

[0355] Note that, in Figure 25 , similar to the memory layer ALYa, the memory layer located below the memory layer ALYa is provided with conductors 160_2 to 160_4, insulators 153 (insulators 153_2 to 153_4), insulators 154 (insulators 154_2 to 154_4), and an insulator 180. Further, in the memory layer located below the memory layer ALYa, the conductors 160_2 to 160_4, the insulator 153, and the insulator 154 are embedded in the insulator 180. In particular, the conductor 160_1, the insulator 153_1, and the insulator 154_1 are located below the conductor 171_1 embedded in the insulator 122a.

[0356] Regarding the conductor 142a, the conductor 142b, the conductor 142c, the conductor 142d, and the insulator 175, reference can be made to the conductor 142a, the conductor 142b, the conductor 142c, the conductor 142d, and the insulator 175 described in Embodiment 1.

[0357] In particular, a conductor 170_5 is provided on the conductor 142d. The conductor 170_5 is used, for example, as Figure 23 the wiring WRBLa[j + 1] or the wiring WRBLa[j + 3] in

[0358] Further, the conductor 142b is used, for example, as Figure 23 the wiring SLa[j], the wiring SLa[j + 2], or a conductor electrically connected to the wiring SLa in

[0359] The conductor 171_3 embedded in the insulator 122a is located below a region that overlaps with the conductor 142a and does not overlap with the oxide 130. The conductor 171_3 embedded in the insulator 122a is used as a wiring that electrically connects the insulator 122a included in the memory layer ALYa and the conductor 160_3 included in the memory layer located below the memory layer ALYa.

[0360] In addition, an insulator 153_1, an insulator 154_1, and a conductor 160_1 are sequentially provided in a region that overlaps with the conductor 142a and does not overlap with the oxide 130. In particular, a capacitor C1 is formed in a region where the conductor 142a overlaps with the conductor 160_1. In other words, a part of the conductor 142a is used as one of a pair of electrodes of the capacitor C1, and a part of the conductor 160_1 is used as the other of the pair of electrodes of the capacitor C1.

[0361] In addition, the conductor 171_1 is located above the conductor 160_1. In particular, the conductor 171_1 is embedded in the insulator 122b. The conductor 171_1 embedded in the insulator 122b is also used as a back gate electrode of the transistor M1 included in the storage layer ALYb.

[0362] Note that, in Figure 25 the conductor 171_1 embedded in the insulator 122b is also located above the insulator 153_1 and the insulator 154_1, but the conductor 171_1 embedded in the insulator 122b may also be located above the conductor 160_1 and not above the insulator 153_1 and the insulator 154_1.

[0363] In addition, the conductor 171_3 is located above the conductor 160_3. In particular, the conductor 171_3 is embedded in the insulator 122b. The conductor 171_3 embedded in the insulator 122b is used as a wiring for electrically connecting the conductor 160_3 included in the storage layer ALYa and the conductor 142a included in the storage layer ALYb.

[0364] In addition, in Figure 25 the conductor 171_1 embedded in the insulator 122b may also be located above the insulator 153_1 and the insulator 154_1.

[0365] The conductor 171_1 and the conductor 171_3 may use the same conductive material. Note that specific conductive materials that can be used for the conductor 171_1 and the conductor 171_3 will be described later.

[0366] In addition, the conductor 171_1 and the conductor 171_3 may be formed by different processes or may be formed by the same process.

[0367] As Figure 24 and Figure 25 shown, a semiconductor device DEVA can be formed such that a conductor serving as a back gate electrode of the transistor M1 equivalent to the storage layer ALYb and a conductor serving as the other of a pair of electrodes of the capacitor C1 equivalent to the storage layer ALYa are formed simultaneously. That is, by adopting Figure 24 and Figure 25The structure shown can achieve the following effects: compared with the prior art, the number of photomasks used to manufacture the semiconductor device DEVA can be reduced; and the manufacturing process of the semiconductor device DEVA can be shortened.

[0368] In addition, the structure of the semiconductor device DEVA can also be changed according to the situation. Figure 24 of the semiconductor device DEVA.

[0369] For example, Figure 24 ( Figure 25 ) the semiconductor device DEVA can also be changed to Figure 27 the structure of the semiconductor device DEVA shown. Figure 27 The semiconductor device DEVA of Figure 24 ( Figure 25 ) is different from the semiconductor device DEVA of Figure 27 in that, for example, the conductor 160_3 included in the storage layer ALYb and 171_3 embedded in the insulator 122c do not overlap with the conductor 160_1 of the storage layer ALYc. That is to say, in the semiconductor device DEVA of Figure 27 , the transistor M2 of the lower storage layer does not overlap with the capacitor C1 of the upper storage layer. By adopting the structure of the semiconductor device DEVA of Figure 24 ( Figure 25 ), compared with the semiconductor device DEVA of

[0370] In addition, for example, Figure 24 ( Figure 25 ) the semiconductor device DEVA can also be changed to Figure 28 the structure of the semiconductor device DEVA shown. Figure 28 The semiconductor device DEVA of Figure 24 ( Figure 25 ) is different from the semiconductor device DEVA of Figure 28 in that, for example, the conductor 160_4 included in the storage layer ALYb and 171_3 embedded in the insulator 122c overlap with the conductor 160_1 of the storage layer ALYc. That is to say, Figure 24 ( Figure 25 ) the semiconductor device DEVA has a structure in which the positions of the transistors M2 and M3 formed in the oxide 130 are swapped with each other. In addition, Figure 28 the semiconductor device DEVA of Figure 23 has a structure in which the transistors M2 and M3 are swapped in the circuit diagram of Figure 28 . In the structure of the semiconductor device DEVA of Figure 24 ( Figure 25Similarly, data writing and reading can also be performed for the semiconductor device DEVA.

[0371] As Figure 24 and Figure 25 shown, as an example, by setting in such a way that another of a pair of electrodes of the capacitor C1 that shares the storage layer ALYa is used in common with the back gate electrode of the transistor M1 of the storage layer ALYb, the occupied area of the memory cell MCA (memory cell MCB, memory cell MCC, and memory cell MCZ) can be reduced. As a result, miniaturization or high integration of the semiconductor device can be achieved, and as a result, the storage density can be increased.

[0372] In addition, as Figure 24 and Figure 25 shown, by forming three transistors in one oxide 130, the occupied area of the transistors can be reduced. That is, the occupied area of the memory cell can be reduced, and as a result, miniaturization or high integration of the semiconductor device can be achieved, and as a result, the storage density can be increased.

[0373] "Manufacturing Method of Semiconductor Device" Next, an example of the manufacturing method of the storage layer ALYa of the semiconductor device DEVA shown in Figure 24 and Figure 25 will be described. Note that the description of the example of the manufacturing method uses Figures 29A to 31 .

[0374] Figures 29A to 31 Each shows a cross-sectional schematic diagram. In particular, Figures 29A to 31 shows a cross-sectional schematic diagram in the channel length direction of the transistors M1 to M3.

[0375] Note that in the manufacturing method of the semiconductor device DEVA shown in Figure 24 and Figure 25 , the description of the content that is repeated with the manufacturing method of the semiconductor device DEV shown in Figure 2 and Figure 3 described in Embodiment 1 may sometimes be omitted.

[0376] First, prepare a substrate (not shown), and form a storage layer below the storage layer ALYa on the substrate. For example, form an insulator and a conductor included in the storage layer below the storage layer ALYa on the substrate. Note that the insulator and the conductor can use the same materials as the insulator 180, insulators 153_1 to 153_4, insulators 154_1 to 154_4, conductors 160_1 to 160_4, conductor 170_5, insulator 122a, conductors 171_1 and 171_3 included in the storage layer ALYa. In addition, by forming the insulator and the conductor, transistors M1 to M3 and capacitor C1 are formed in the storage layer below the storage layer ALYa.

[0377] Next, form an insulating film that becomes the insulator 122a so as to cover the insulator and the conductor. Then, in the insulating film, an opening reaching the gate electrode is provided in a region overlapping with the gate electrode of the transistor M2, and an opening reaching the upper electrode is provided in a region overlapping with the upper electrode of a pair of electrodes of the capacitor C1, thereby forming the insulator 122a (refer to Figure 29A ). Note that for the insulator 122a, reference can be made to the description of the insulator 122a in Embodiment 1.

[0378] In addition, the conductor 171_3 is embedded in the opening of the insulator 122a overlapping with the gate electrode of the transistor M2. In addition, the conductor 171_1 is embedded in the opening of the insulator 122a overlapping with the upper electrode of a pair of electrodes of the capacitor C1 (refer to Figure 29A ). Note that the conductors 171_1 and 171_3 will be described later.

[0379] Next, refer to Figures 10A to 19D the manufacturing method shown to form transistors M1 to M3 and capacitor C1 on the insulator 122a, conductor 171_1 and conductor 171_3 (refer to Figure 29B ).

[0380] In addition, refer to Figures 20A to 20D the manufacturing method shown to provide an opening reaching the conductor 142d in a region of the insulator 180 overlapping with the conductor 142d (corresponding to the opening 157_5 in Figure 20B ).

[0381] In addition, refer to Figures 21A to 22D the manufacturing method shown to form the conductor 170_5 in the above opening (refer to Figure 29B ). Note that as shown in Figure 29B , the conductor 170_5 can also be formed on a part of the insulator 180.

[0382] Then, an insulating film 122B that becomes the insulator 122b is formed so as to cover the insulators 153_1 to 153_4, the insulators 154_1 to 154_4, the conductors 160_1 to 160_4, the insulator 180, and the conductor 170_5 (see Figure 29B ). Note that for the method of forming the insulating film 122B, reference can be made to the description of the insulator 122b in Embodiment 1.

[0383] Next, the insulating film 122B is processed to form the insulator 122b, which has openings in the regions overlapping with the conductor 160_1 included in the storage layer ALYa and in the regions overlapping with the conductor 160_3 included in the storage layer ALYa (see Figure 30A ). Note that as the above processing, a dry etching method or a wet etching method can be used.

[0384] In addition, a conductive film 171A and a conductive film 171B are sequentially formed on the insulator 122b and inside the openings of the insulator 122b (see Figure 30B ). Note that it is preferable to continuously deposit the conductive film 171A and the conductive film 171B without being exposed to the atmospheric environment. By depositing in a manner not exposed to the atmospheric environment, impurities or moisture from the atmospheric environment can be prevented from adhering to the conductive film 171A and the conductive film 171B, and the vicinity of the interface between the conductive film 171A and the conductive film 171B can be kept clean.

[0385] The conductive film 171A and the conductive film 171B can be deposited by deposition methods such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the present embodiment, the conductive film 171A and the conductive film 171B are formed using the CVD method.

[0386] In addition, for example, materials that can be used for the conductors 160a_1 to 160a_4 can be used for the conductive film 171A. In addition, for example, materials that can be used for the conductors 160b_1 to 160b_4 can be used for the conductive film 171B.

[0387] In addition, materials that can be mutually applied can also be used for the conductive film 171A and the conductive film 171B. In addition, the same material can also be used for the conductive film 171A and the conductive film 171B. That is to say, the conductive film 171A and the conductive film 171B can also be one conductor.

[0388] Next, the conductive film 171A and the conductive film 171B are polished by a planarization process such as CMP until the insulator 122b is exposed. That is, the portions of the conductive film 171A and the conductive film 171B that are exposed from the opening of the insulator 122b are removed. As a result, a conductor 171_3 is formed in the opening of the insulator 122b that overlaps with the conductor 160_3 included in the storage layer ALYa, and a conductor 171_1 is formed in the opening of the insulator 122b that overlaps with the conductor 160_1 included in the storage layer ALYa (see Figure 31 ).

[0389] In addition, after the conductor 171_1 and the conductor 171_3 are formed, the heat treatment described in Embodiment 1 may be performed.

[0390] As described above, by performing the Figures 29A to 31 manufacturing method, the storage layer ALYa of the semiconductor device DEVA can be formed. In addition, when forming the storage layer ALYb on the insulator 122b, the transistors M1 to M3 and the capacitor C1 may be formed with reference to the Figures 29A to 31 manufacturing method.

[0391] Note that the manufacturing method of the semiconductor device according to one aspect of the present invention is not limited to the Figures 29A to 31 shown method. The manufacturing method of the semiconductor device may change materials and processes according to circumstances.

[0392] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments and used.

[0393] (Embodiment 3) In this embodiment, a structural example of a storage device including the semiconductor device described in the above embodiment is described.

[0394] Figure 32A is a perspective schematic view showing a structural example of the storage device 100. Figure 32B is a block diagram showing a structural example of the storage device 100. The storage device 100 includes a drive circuit layer 50 and an N-layer (N is an integer of 1 or more) storage layer 60. In addition, each layer of the storage layer 60 includes a plurality of storage units 10 arranged in a matrix of m rows and n columns. In addition, Figure 32BAn example is shown in which the storage layer 60_k is configured with storage cells 10[1,1], storage cells 10[m,1] (where m is an integer greater than or equal to 1), storage cells 10[1,n] (where n is an integer greater than or equal to 1), storage cells 10[m,n], and storage cells 10[i,j] (where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n).

[0395] In addition, the storage layer 60 corresponds to the storage layer ALYa, the storage layer ALYb, or the storage layer ALYc described in Embodiment 1. In addition, the storage cell 10 corresponds to the storage cell MCa or the storage cell MCb described in Embodiment 1. In addition, the plurality of storage layers 60 may also include the storage layer ALYa to the storage layer ALYc described in Embodiment 2.

[0396] The N-layer storage layer 60 is provided on the drive circuit layer 50. By providing the N-layer storage layer 60 on the drive circuit layer 50, the occupied area of the storage device 100 can be reduced. In addition, the storage capacity per unit area can be increased.

[0397] In the present embodiment and the like, the first-layer storage layer 60 is denoted as the storage layer 60_1, the second-layer storage layer 60 is denoted as the storage layer 60_2, and the third-layer storage layer 60 is denoted as the storage layer 60_3. In addition, the k-th layer (k is an integer greater than or equal to 1 and less than or equal to N) of the storage layer 60 is denoted as the storage layer 60_k, and the N-th layer of the storage layer 60 is denoted as the storage layer 60_N. In the present embodiment and the like, when explaining matters related to the entire N-layer storage layer 60 or showing matters common to the respective layers of the N-layer storage layer 60, it is sometimes simply denoted as "storage layer 60".

[0398] <Structural example of the drive circuit layer 50> The drive circuit layer 50 includes a PSW22 (power switch), a PSW23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0399] In the storage device 100, the above-described respective circuits, signals, and voltages can be appropriately selected and discarded as needed. Alternatively, other circuits or other signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and the signal RDA is a signal output to the outside. The signal CLK is a clock signal.

[0400] In addition, signal BW, signal CE, and signal GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are signals for power gating control. In addition, signals PON1 and PON2 can also be generated in control circuit 32.

[0401] Control circuit 32 is a logic circuit having a function of controlling the overall operation of storage device 100. For example, control circuit performs a logical operation on signal CE, signal GW, and signal BW to determine the operation mode of storage device 100 (e.g., write operation, read operation). Alternatively, control circuit 32 generates a control signal for peripheral circuit 41 to execute the above operation mode.

[0402] Voltage generation circuit 33 has a function of generating a negative voltage. Signal WAKE has a function of controlling the input of signal CLK to voltage generation circuit 33. For example, when a signal of H level is applied to signal WAKE, signal CLK is input to voltage generation circuit 33, and voltage generation circuit 33 generates a negative voltage.

[0403] Peripheral circuit 41 is a circuit for writing and reading data to / from memory cell 10. Peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0404] Row decoder 42 and column decoder 44 have a function of decoding signal ADDR. Row decoder 42 is a circuit for specifying a row to be accessed, and column decoder 44 is a circuit for specifying a column to be accessed.

[0405] Row driver 43 has a function of selecting a write and read word line (e.g., any one of wirings WL[1] to WL[m] described later) specified by row decoder 42. Figure 33 shown).

[0406] Column driver 45 has the following functions: a function of writing data to memory cell 10; a function of reading data from memory cell 10; and a function of holding the read data. Column driver 45 has a function of selecting a write and read bit line (e.g., wirings BL[1] to BL[n] described later) specified by column decoder 44. Figure 33 shown).

[0407] The input circuit 47 has the function of holding the signal WDA. The data held in the input circuit 47 (the first data in the above-described embodiment) is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written into the memory cell 10. The data (Dout) read out from the memory cell 10 by the column driver 45 is output to the output circuit 48. In the above-described embodiment, the read-out data (Dout) is processed as the data of the operation result. The output circuit 48 has the function of holding Dout. In addition, the output circuit 48 has the function of outputting Dout to the outside of the storage device 100. The data output from the output circuit 48 is the signal RDA.

[0408] The PSW22 has the function of controlling the supply of VDD to the peripheral circuit 31. The PSW23 has the function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the storage device 100 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage used to make the word line high level, and it is higher than VDD. The on-state and off-state of the PSW22 are switched by the signal PON1, and the on-state and off-state of the PSW23 are switched by the signal PON2. In Figure 32B , the number of power supply domains supplied with VDD in the peripheral circuit 31 is 1, but it can also be multiple. At this time, a power switch can be set for each power supply domain.

[0409] Next, the electrical connection between the peripheral circuit 41 and the storage layer 60 will be described.

[0410] Figure 33 is a block diagram showing a structural example of the peripheral circuit 41 and the storage layer 60_k. In Figure 33 , the row decoder 42 and the row driver 43 are electrically connected to each of the wirings WL[1] to WL[m], and the column decoder 44, the column driver 45, and the sense amplifier 46 are electrically connected to each of the wirings BL[1] to BL[n].

[0411] In addition, the wirings WL[1] to WL[m] correspond to the wirings WWLa[i], RWLa[i], WWLb[i], and RWLb[i] described in Embodiment 1. That is, the wirings WL[1] to WL[m] are used as word lines.

[0412] In addition, the wirings BL[1] to BL[n] correspond to the wirings WRBLa[j], WRBLa[j + 1], WRBLa[j + 2], WRBLb[j], WRBLb[j + 1], and WRBLb[j + 2] described in Embodiment 1. That is, the wirings BL[1] to BL[n] are used as bit lines.

[0413] The memory cell 10 [i, j] arranged in the i-th row and the j-th column is electrically connected to the wiring WL [i] and the wiring BL [j].

[0414] like Figure 33 As shown, by electrically connecting the memory layer 60_k and the peripheral circuit 41, data can be written to the memory layer 60_k and data can be read from the memory layer 60_k.

[0415] then, Figure 34 An example of a cross-sectional structure of a storage device 100 according to one embodiment of the present invention is shown. Figure 34 The memory device 100 shown includes a multi-layer memory layer 60 (described in Embodiment 1) above a drive circuit layer 50. Figure 2 In order to avoid repeated description, the description of the storage layer 60 is omitted in this embodiment.

[0416] also, Figure 34 The transistor 400 included in the driving circuit layer 50 is shown. The transistor 400 is provided on the substrate 311 and includes a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 including a portion of the substrate 311, a low resistance region 314a used as one of the source region and the drain region, and a low resistance region 314b used as the other of the source region and the drain region. The transistor 400 can be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate can be used.

[0417] Here, in Figure 34 In the transistor 400 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, the conductor 316 can use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 400 is also referred to as a FIN-type transistor. In addition, an insulator having a mask for forming a convex portion in a manner that contacts the upper surface of the convex portion may also be provided. In addition, although a portion of the semiconductor substrate is processed to form a convex portion is shown here, an SOI (Silicon On Insulator) substrate may also be processed to form a semiconductor film having a convex shape.

[0418] Notice, Figure 34 The structure of the transistor 400 shown is just an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0419] A wiring layer including an interlayer film, wirings, and plugs may also be provided between the respective structural bodies. In addition, the wiring layer may be provided in multiple layers according to the design. In addition, in this specification and the like, a wiring and a plug electrically connected to the wiring may also be one constituent element. That is to say, a part of the conductor may be used as a wiring, and a part of the conductor may be used as a plug.

[0420] For example, on the transistor 400, insulators 320, 301, 324, and 326 are sequentially stacked as an interlayer film. In addition, conductors 328 and the like are embedded in the insulators 320 and 301. In addition, conductors 330 and the like are embedded in the insulators 324 and 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0421] In addition, the insulator used as the interlayer film may also be used as a planarization film covering the uneven shape below it. For example, in order to improve the flatness of the top surface of the insulator 301, planarization may also be achieved by a planarization process such as chemical mechanical polishing (CMP) method.

[0422] In addition, a wiring layer may also be provided on the insulator 326 and the conductor 330. For example, in Figure 34 , an insulator 350, an insulator 357, and an insulator 352 are sequentially stacked on the insulator 326 and the conductor 330. Conductors 356 are formed in the insulator 350, the insulator 357, and the insulator 352. The conductor 356 is used as a contact plug or a wiring. For example, the transistor 400 is electrically connected to the wiring WL or the wiring BL through the conductor 356, the conductor 330, and the like.

[0423] This embodiment can be appropriately combined with other embodiments shown in this specification and the like.

[0424] (Embodiment 4) In this embodiment, a transistor (OS transistor) in which an oxide semiconductor is contained in a channel formation region is described. In addition, in the description of the OS transistor, a comparison with a transistor in which silicon is contained in the channel formation region (also referred to as a Si transistor) is simply described.

[0425] [0S Transistor] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration in the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Hereinafter, it is preferably less than 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , further preferably less than 1×1013 cm -3 and more preferably less than 1×10 10 cm -3 and is 1×10 -9 cm -3 or more. In the case of aiming to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the density of defect states. In the present specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0426] Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has a low density of defect states, it sometimes has a low density of trap states. In addition, it takes a long time for the charge trapped in the trap states of the oxide semiconductor to disappear and sometimes acts like a fixed charge. Therefore, the electrical characteristics of a transistor formed in an oxide semiconductor with a high density of trap states are sometimes unstable.

[0427] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, nitrogen, etc. Note that impurities in the oxide semiconductor refer to elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration lower than 0.1 atomic% can be said to be an impurity.

[0428] In an OS transistor, when impurities and oxygen vacancies are present in the channel formation region of the oxide semiconductor, the electrical characteristics are likely to vary and the reliability may decrease. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), and electrons that become carriers may be generated. In addition, when V O H is formed in the channel formation region, the donor concentration in the channel formation region sometimes increases. As the donor concentration in the channel formation region increases, the threshold voltage sometimes becomes uneven. Therefore, when the channel formation region of the oxide semiconductor contains oxygen vacancies, the transistor is always on (becomes a state where a channel exists even without applying a voltage to the gate electrode and current flows through the transistor). Thus, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H.

[0429] In addition, the bandgap of the oxide semiconductor is preferably larger than the bandgap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more. By using an oxide semiconductor having a larger bandgap than silicon, the off-state current (also referred to as off-state leakage current or Ioff) of the transistor can be reduced.

[0430] In addition, in Si transistors, as the miniaturization of transistors progresses, the short-channel effect (Short Channel Effect: also referred to as SCE) appears. Therefore, it is difficult to miniaturize Si transistors. One of the reasons for the occurrence of the short-channel effect can be attributed to the relatively small bandgap of silicon. On the other hand, in OS transistors, an oxide semiconductor having a large bandgap is used as the semiconductor material, so the short-channel effect can be suppressed. In other words, OS transistors are transistors with no short-channel effect or very little short-channel effect.

[0431] Note that the short-channel effect refers to the degradation of electrical characteristics that occurs as transistors are miniaturized (reduction in channel length). Specific examples of the short-channel effect include a decrease in the threshold voltage, an increase in the subthreshold swing value (sometimes denoted as the S value), and an increase in the leakage current. Here, the S value refers to the change in the gate voltage in the subthreshold region where the drain current value changes by one order of magnitude with a fixed drain voltage.

[0432] In addition, as an index of the tolerance to the short-channel effect, the characteristic length is widely used. The characteristic length is an index of the curvature of the potential in the channel formation region. The smaller the characteristic length, the steeper the potential rises, so it can be said that the ability to resist the short-channel effect is high.

[0433] OS transistors are accumulation-mode transistors, and Si transistors are inversion-mode transistors. Therefore, compared with Si transistors, the characteristic lengths between the source region and the channel formation region and between the drain region and the channel formation region in OS transistors are smaller. Therefore, the ability of OS transistors to resist the short-channel effect is higher than that of Si transistors. That is to say, when trying to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0434] Even when the carrier concentration of the oxide semiconductor is reduced to the extent that the channel formation region is i-type or substantially i-type, in short-channel transistors, due to the Conduction-Band-Lowering (CBL) effect, the conduction band bottom of the channel formation region also becomes lower. Therefore, the energy difference between the conduction band bottoms of the source region or the drain region and the channel formation region may be reduced to more than 0.1 eV and less than 0.2 eV. Thus, OS transistors can be regarded as having n + / n - / n+ The accumulation-type junction-less transistor structure or n + / n - / n + The accumulation-type non-junction transistor structure, where the channel formation region is an n - type region, and the source region and the drain region are n + type regions.

[0435] When the above structure is adopted as an OS transistor, good electrical characteristics can be achieved even when the semiconductor device is miniaturized or highly integrated. For example, even when the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less and 1 nm or more, 3 nm or more, or 5 nm or more, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of 20 nm or less or 15 nm or less because of the short-channel effect. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region during the operation of the transistor, and is also the width of the bottom surface of the gate electrode when looking down at the transistor.

[0436] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cut-off frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cut-off frequency of the transistor can be 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more.

[0437] As described above, the OS transistor has excellent effects compared with Si transistors, such as a small off-state current and the ability to manufacture transistors with a small channel length.

[0438] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. For example, the components, structures, methods, etc. shown in this embodiment can be appropriately combined with the components, structures, methods, etc. shown in other embodiments and used.

[0439] (Embodiment 5) In this embodiment, electronic components, electronic devices, mainframe computers, space devices, and data centers (Data_Center: also referred to as DC) that can use the semiconductor device described in the above embodiment are described. Electronic components, electronic devices, mainframe computers, space devices, and data centers using the semiconductor device according to one aspect of the present invention are effective for realizing high performance such as low power consumption.

[0440] [Electronic Components] Figure 35A A perspective view showing a substrate (printed circuit board 704) on which an electronic component 700 is mounted. Figure 35A The illustrated electronic component 700 includes a semiconductor device 710 within a mold 711. Figure 35A In, a part of the electronic component 700 is omitted from the description to show its interior. The electronic component 700 includes bonding pads (lands) 712 outside the mold 711. The bonding pads 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 through leads 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. By combining a plurality of such electronic components and electrically connecting them to the printed circuit board 702 respectively, the printed circuit board 704 is thus completed.

[0441] In addition, the semiconductor device 710 includes a drive circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the drive circuit layer 715 and the storage layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding are not required to connect between the layers. When the drive circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0442] In addition, by adopting the on-chip memory structure, compared with the technology using through electrodes such as TSV, the size of connection wirings and the like can be reduced, and thus the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, and thereby the bandwidth of the memory (also referred to as memory bandwidth) can be improved.

[0443] In addition, preferably, a plurality of memory cell arrays in the storage layer 716 are formed using OS transistors, and the plurality of memory cell arrays are stacked in a monolithic manner. When the plurality of memory cell arrays are stacked in a monolithic manner, one or both of the bandwidth of the memory and the access latency of the memory can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between access and the start of data exchange. When Si transistors are used in the storage layer 716, it is more difficult to realize a monolithic stacked structure compared with OS transistors. Therefore, in the monolithic stacked structure, OS transistors are superior to Si transistors.

[0444] In addition, the semiconductor device 710 may be referred to as a die. In this specification and the like, a die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also referred to as a wafer) or the like in the manufacturing process of a semiconductor chip and cutting it into rectangular small pieces. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon die.

[0445] Next, Figure 35B A perspective view of the electronic component 730 is shown. The electronic component 730 is an example of a SiP (System in Package) or an MCM (MultiChip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0446] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM: High Bandwidth Memory). In addition, the semiconductor device 735 can be used for integrated circuits such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0447] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0448] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different electrode pitch. The plurality of wirings are composed of a single layer or multiple layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuits provided on the interposer 731 with the electrodes provided on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or an "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through this through electrode. In addition, in the case of using a silicon interposer, TSV can also be used as the through electrode.

[0449] In HBM, in order to achieve a wide memory bandwidth, many wirings need to be connected. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0450] In addition, in SiP and MCM using a silicon interposer, it is not easy for the reliability to decrease due to the difference in the coefficient of thermal expansion between the integrated circuit and the interposer. Further, since the surface flatness of the silicon interposer is high, it is not easy for a connection failure to occur between the integrated circuit provided on the silicon interposer and the silicon interposer. It is particularly preferable to use the silicon interposer for 2.5D packaging (2.5D mounting), in which a plurality of integrated circuits are arranged horizontally and disposed on the interposer.

[0451] On the other hand, when a plurality of integrated circuits having different terminal pitches are electrically connected using a silicon interposer and TSVs, a space such as the width of the terminal pitch is required. Therefore, when it is desired to reduce the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it is sometimes difficult to provide a large number of wirings required to achieve a wide memory bandwidth. Thus, as described above, the structure of a single-layer stack using OS transistors is preferable. Alternatively, a composite structure in which a memory cell array stacked using TSVs and a memory cell array stacked in a single-chip manner are combined may be employed.

[0452] In addition, a heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 730. In the case where the heat sink is provided, it is preferable that the heights of the integrated circuits provided on the interposer 731 be the same. For example, in the electronic component 730 shown in the present embodiment, it is preferable that the heights of the semiconductor device 710 and the semiconductor device 735 be the same.

[0453] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 35B An example of forming the electrodes 733 using solder balls is shown. By arranging the solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. In addition, the electrodes 733 may be formed using conductive pins. By arranging the conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0454] The electronic component 730 can be mounted on another substrate by various mounting methods, not limited to BGA and PGA. As mounting methods, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package) can be cited.

[0455] [Electronic device] Next, Figure 36A A perspective view of the electronic device 6500 is shown. Figure 36A The illustrated electronic device 6500 is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be used for the display unit 6502, the control device 6509, and the like.

[0456] Figure 36B The illustrated electronic device 6600 is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control device 6616. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be used for the display unit 6615, the control device 6616, and the like. In addition, by using a semiconductor device according to one aspect of the present invention for the control device 6509 and the control device 6616, power consumption can be reduced, which is therefore preferable.

[0457] [Mainframe computer] Next, Figure 36C A perspective view of the mainframe computer 5600 is shown. In Figure 36C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. In addition, the mainframe computer 5600 may also be referred to as a supercomputer.

[0458] The computer 5620 may, for example, have Figure 36D the structure of the perspective view shown. In Figure 36D this, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals, etc. A personal computer card 5621 is inserted into the slot 5631. And the personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0459] Figure 36EThe personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 36E Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For the description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0460] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the specifications of the connection terminal 5629 include PCIe, etc.

[0461] The connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for supplying power to the personal computer card 5621 or inputting signals, etc. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, etc. Examples of the specifications of each of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA: Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), etc. In addition, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the specifications include HDMI (registered trademark), etc.

[0462] The semiconductor device 5626 includes terminals (not shown) for inputting and outputting signals. By inserting these terminals into a socket (not shown) included in the board 5622, the semiconductor device 5626 and the board 5622 can be electrically connected.

[0463] The semiconductor device 5627 includes a plurality of terminals. For example, by soldering these terminals to the wiring included in the board 5622 by reflow soldering, the semiconductor device 5627 and the board 5622 can be electrically connected. Examples of the semiconductor device 5627 include an FPGA, a GPU, a CPU, etc. As the semiconductor device 5627, for example, the electronic component 730 can be used.

[0464] The semiconductor device 5628 includes a plurality of terminals. For example, by soldering the terminals to the wiring included in the board 5622 by reflow soldering, the semiconductor device 5628 and the board 5622 can be electrically connected. As the semiconductor device 5628, for example, a storage device or the like can be cited. As the semiconductor device 5628, for example, the electronic component 700 can be used.

[0465] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0466] [Space equipment] A semiconductor device according to one aspect of the present invention can be used as a device for processing and storing information in space equipment.

[0467] A semiconductor device according to one aspect of the present invention may include an OS transistor. The change in electrical characteristics of the OS transistor due to irradiation with radiation is small. In other words, since the resistance to radiation is high, it can be appropriately used even in an environment where radiation may be incident. For example, the OS transistor can be appropriately used when used in space.

[0468] In Figure 37 , as an example of space equipment, a satellite 6800 is shown. The satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In addition, Figure 37 An example of a planet 6804 in space is shown. Note that space, for example, refers to an altitude of 100 km or more, but the space shown in this specification may also include the thermosphere, the mesosphere, and the stratosphere.

[0469] In addition, although Figure 37 not shown in the figure, a battery management system (also referred to as BMS) or a battery control circuit may be provided in the secondary battery 6805. When the OS transistor is used in the above battery management system or battery control circuit, the power consumption is low, and high reliability can be achieved even in space, so it is preferable.

[0470] In addition, space is an environment where the radiation dose is 100 times or more that of the ground. As radiation, for example, electromagnetic waves (electromagnetic radiation) represented by X-rays and γ-rays; and particle radiation represented by α-rays, β-rays, neutron rays, proton rays, heavy ion rays, meson rays, etc. can be cited.

[0471] When sunlight shines on the solar panel 6802, the power required for the operation of the artificial satellite 6800 is generated. However, for example, when sunlight does not shine on the solar panel or when the amount of sunlight shining on the solar panel is small, the amount of generated power decreases. Therefore, it is possible that the power required for the operation of the artificial satellite 6800 is not generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar panel is sometimes referred to as a solar cell module.

[0472] The artificial satellite 6800 can generate a signal. This signal is transmitted through the antenna 6803 and can be received by, for example, a receiver on the ground or another artificial satellite. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver that receives the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0473] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is constituted by, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, it is preferable to use a semiconductor device according to one aspect of the present invention. Compared with Si transistors, OS transistors have less change in electrical characteristics due to irradiation with radiation. That is, OS transistors have high reliability even in an environment where radiation may be incident and can be used appropriately.

[0474] In addition, the artificial satellite 6800 may include sensors. For example, by including a visible light sensor, the artificial satellite 6800 can have a function of detecting sunlight reflected by an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have a function of detecting thermal infrared rays released from the earth's surface. Thus, the artificial satellite 6800 can be used, for example, as an earth observation satellite.

[0475] Note that in the present embodiment, an artificial satellite is shown as an example of a space device, but it is not limited thereto. For example, a semiconductor device according to one aspect of the present invention can be appropriately applied to space devices such as spacecraft, space capsules, and space probes.

[0476] As described above, compared with Si transistors, OS transistors have excellent effects such as enabling a wider memory bandwidth and high radiation resistance.

[0477] [Data Center] For example, a semiconductor device according to one embodiment of the present invention can be applied to a storage system adopted in a data center or the like. The data center is required to ensure data immutability and perform long-term management of data. When performing long-term management of data, it is necessary to enlarge the facility, such as setting up storage and servers for storing a huge amount of data, ensuring stable power supply to maintain data, or ensuring cooling equipment required during data retention.

[0478] By using a semiconductor device according to one embodiment of the present invention in a storage system adopted in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, reduce the scale of the cooling equipment, etc. As a result, space saving of the data center can be achieved.

[0479] In addition, the power consumption of a semiconductor device according to one embodiment of the present invention is small, so the circuit heat generation can be reduced. As a result, the negative impacts on the circuit itself, peripheral circuits, and modules caused by the heat generation can be reduced. In addition, by using a semiconductor device according to one embodiment of the present invention, a data center that can operate stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0480] Figure 38 A storage system applicable to a data center is shown. Figure 38 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001. In addition, a plurality of storage devices 7003md are included as storage 7003. A form in which the host 7001 and the storage 7003 are connected through a storage area network 7004 and a storage control circuit 7002 is shown.

[0481] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 can also be connected to each other through a network.

[0482] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for storing and outputting data is shortened, but this time is much longer than the time required for DRAM that can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is generally provided in the storage to shorten the time required for storing and outputting data.

[0483] The above cache memory is used in the storage control circuit 7002 and the storage 7003. The data exchanged between the host 7001 and the storage 7003 is output to the host 7001 or the storage 7003 after being stored in the cache memory in the storage control circuit 7002 and the storage 7003.

[0484] When an OS transistor is used as a transistor for storing data in the cache memory to maintain a potential corresponding to the data, the refresh frequency can be reduced to lower power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0485] Note that by using the semiconductor device according to one embodiment of the present invention for any one or more selected from electronic components, electronic devices, mainframe computers, space devices, and data centers, an effect of reducing power consumption can be expected. Therefore, currently, as the semiconductor device becomes more highly functional or highly integrated, the energy demand increases. By using the semiconductor device according to one embodiment of the present invention, it is also possible to reduce emissions of greenhouse gases represented by carbon dioxide (CO2). In addition, the semiconductor device according to one embodiment of the present invention has low power consumption, and thus is also effective as a measure against global warming.

[0486] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments and used. Example 1

[0487] In this example, the OS transistor included in the semiconductor device according to one embodiment of the present invention will be described. In addition, the memory cell array and its peripheral circuit that can be used for the semiconductor device according to one embodiment of the present invention will also be described. Note that in this example, for convenience, the memory cell array and the peripheral circuit are referred to as a memory device. In addition, the results of actually manufacturing the memory device and measuring the data retention characteristics of the memory device will also be described.

[0488] <OS transistor> As described in the above embodiment, by making the bandgap of the oxide semiconductor included in the OS transistor larger than the bandgap of silicon, the off-state current of the OS transistor can be reduced.

[0489] In addition, the OS transistor has higher voltage tolerance than the Si transistor. Figure 39A is a graph showing the source-drain breakdown voltage characteristics of the OS transistor. The horizontal axis represents the source-drain voltage (Vd [V]), and the vertical axis represents the amount of leakage current flowing between the source and drain (Id [A]). In addition, Figure 39B is a graph showing the gate breakdown voltage characteristics of the OS transistor. The horizontal axis represents the gate-source (drain) voltage (Vg [V]), and the vertical axis represents the amount of leakage current flowing between the gate-source (drain) (Ig [A]). Note that in Figure 39A and Figure 39B the size of the OS transistor used in each measurement is a channel length of 0.5 μm and a channel width of 0.5 μm. As in Figure 39A andFigure 39B As shown, the breakdown voltage between the source and drain of the OS transistor and the gate breakdown voltage are both 13.5 V or higher, and the leakage currents are both 1 pA (1×10 -12 A) or less.

[0490] Since the OS transistor can be formed using one or both of chemical vapor deposition and physical vapor deposition, for example, the OS transistor can be stacked on a CMOS circuit formed on a semiconductor substrate made of silicon. That is, a monolithic stacked semiconductor device having an OS transistor formed on a CMOS circuit can be manufactured.

[0491] <Circuit Structure of Storage Device> Figure 40 A memory cell MC that can be used for the memory cell array is shown. Figure 40 The memory cell MC shown has the same 3TrlC NOSRAM (registered trademark) structure as the Figure 1 memory cell MCa (memory cell MCb) shown, and includes transistors M11 to M13 and a capacitor C11.

[0492] In the memory cell MC, the first terminal of the transistor M11 is electrically connected to the gate of the transistor M12 and the first terminal of the capacitor C11, the second terminal of the transistor M11 is electrically connected to the wiring WBL, and the gate of the transistor M11 is electrically connected to the wiring WWL. The second terminal of the capacitor C1 is electrically connected to the wiring CL. The first terminal of the transistor M12 is electrically connected to the wiring RBL, and the second terminal of the transistor M12 is electrically connected to the first terminal of the transistor M13. The second terminal of the transistor M13 is electrically connected to the wiring WBL, and the gate of the transistor M13 is electrically connected to the wiring RWL.

[0493] According to the above description, the transistor M11 corresponds to the Figure 1 transistor M1 of the memory cell MCa (memory cell MCb), the transistor M12 corresponds to the Figure 1 transistor M2 of the memory cell MCa (memory cell MCb), the transistor M13 corresponds to the Figure 1 transistor M3 of the memory cell MCa (memory cell MCb), and the capacitor C11 corresponds to the Figure 1 capacitor C1 of the memory cell MCa (memory cell MCb). Note that the difference from the Figure 1 memory cell MCa (memory cell MCb) shown is that the second terminal of the transistor M11 is electrically connected to the wiring WBL, and the second terminal of the transistor M13 is electrically connected to the wiring WBL. In addition, similar to the Figure 1 transistor M1 of the memory cell MCa (memory cell MCb), the transistor M11 can also have a structure provided with a back gate.

[0494] The wiring WWL is used as a write word line, and the wiring RWL is used as a read word line. In addition, the wiring WBL is used as a write bit line, and the wiring RBL is used as a read bit line. Further, the wiring WBL is also used as a wiring for supplying a predetermined potential during reading. Similar to Figure 1 the description of the memory cell MCa (memory cell MCb), the wiring CL is used as a wiring for applying a predetermined potential to the second terminal of the capacitor C11. Note that during data writing and reading, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CL.

[0495] In particular, the transistor M11 uses an OS transistor with an In-Ga-Zn oxide (hereinafter referred to as CAAC-IGZO) having a CAAC-OS as the active layer. It is known that a transistor using CAAC-IGZO for the active layer has a very small off-state current characteristic. For example, the off-state current per channel width of 1 μm of this transistor can be 100 zA or less (z: zepto, 10 -21 ), 1 zA or less, or 10 yA or less (y: yocto, 10 -24 ). Therefore, by using this transistor for the transistor M11, it is possible to prevent the data held at the first terminal of the capacitor C11 from being lost due to current leakage. That is, the data written into the memory cell MC can be retained for a long time.

[0496] In addition, as the transistor M12, the transistor M13, and the transistors M21 to M23 described later, transistors having silicon in the active layer are used. Since a transistor having silicon as the active layer exhibits a high on-state current characteristic, it is suitable for transistors constituting a signal conversion circuit, an amplifier circuit, etc. As this silicon, amorphous silicon, microcrystalline silicon, polycrystalline silicon, etc. can be used.

[0497] The memory device of this embodiment has the following structure: the above-mentioned transistors are formed on a single-crystalline semiconductor substrate, and the transistors M11 to M13 and the capacitor C11 are formed above it with an insulating film or the like interposed therebetween.

[0498] Next, Figure 41 the structure of a memory cell array MA using the memory cell MC and its peripheral circuit is shown.

[0499] The memory cell array MA includes memory cells MC arranged in a matrix. Note that in Figure 41Among them, a memory cell MC configured at addresses of m rows and n columns, m rows and n + 1 columns, m + 1 rows and n columns, and m + 1 rows and n + 1 columns (where m and n are both integers of 1 or more) is shown. In addition, the symbol of the memory cell configured at the address of m rows and n columns is denoted as MC[m, n]. Similarly, the symbols of the memory cells configured at the addresses of m rows and n + 1 columns, m + 1 rows and n columns, and m + 1 rows and n + 1 columns are denoted as MC[m, n + 1], MC[m + 1, n], and MC[m + 1, n + 1], respectively. Note that in this embodiment, the addresses of one or more memory cells included in the memory cell array MA may sometimes be omitted and collectively referred to as the memory cell MC.

[0500] Note that in Figure 41 each of the shown memory cells MC, a node FN is shown as an electrical connection point of the first terminal of the transistor M11, the first terminal of the capacitor C11, and the gate of the transistor M12.

[0501] The wirings WWL[m] and WWL[m + 1] are wirings respectively electrically connected to the memory cells MC located in the m-th row and the (m + 1)-th row, and have Figure 40 the functions of the wiring WWL in Figure 40 The wirings RWL[m] and RWL[m + 1] are wirings respectively electrically connected to the memory cells MC located in the m-th row and the (m + 1)-th row, and have Figure 40 the functions of the wiring RWL in Figure 40 The wirings WBL[n] and WBL[n + 1] are wirings respectively electrically connected to the memory cells MC located in the n-th row and the (n + 1)-th row, and have

[0502] As an external circuit of the memory cell array MA, Figure 41 a circuit CD, a circuit RD, a circuit RS, and a readout circuit ROC are shown.

[0503] The circuit CD includes a column decoder and a column driver, and the circuit CD is electrically connected to the wiring WBL and the wiring RBL. The circuit CD has the following functions: a function of receiving 4-bit write data from the outside as the signal IN[3:0]; a function of selecting the wiring WBL of the column including the memory cell MC to which the data is to be written and applying a write voltage corresponding to the data; and a function of selecting the wiring WBL of the column including the memory cell MC from which the data is to be read and applying a prescribed potential.

[0504] The circuit RD includes a row decoder and a row driver, and the circuit RD is electrically connected to the wiring WWL and the wiring RWL. The circuit RD has the following functions: a function of selecting the wiring WWL of the row including the memory cell MC to which the data is to be written and applying a prescribed potential to the wiring WWL; and a function of selecting the wiring RWL of the row including the memory cell MC from which the data is to be read and applying a prescribed potential to the wiring RWL.

[0505] The circuit RS is electrically connected to the wiring RBL and the wiring SRL. The circuit RS has a function of selecting the wiring RBL of the column including the memory cell MC from which the data is to be read and being electrically connected to the wiring SRL.

[0506] The readout circuit ROC includes transistors M21 to M23 and an operational amplifier OP.

[0507] The first terminal of the transistor M21 is electrically connected to the wiring SRL and the gate of the transistor M23, the second terminal of the transistor M21 is electrically connected to the wiring VSS, and the gate of the transistor M21 is electrically connected to the wiring Vb1.

[0508] The wiring VSS is a wiring for supplying a low-level potential, and the wiring Vb1 is a wiring for supplying a voltage higher than the threshold voltage of the transistor M21.

[0509] Here, attention is paid to the transistor M12 and the transistor M21. In Figure 41 a source follower circuit SF1 is constituted by the connection structure of the transistor M12 and the transistor M21. Here, when reading data from the memory cell MC[m+1, n], by applying a high-level potential (for example, the potential supplied by the wiring VDD described later) to the wiring WBL[n] and applying a prescribed potential to the wiring RWL[m+1] to turn on the transistor M13, the source follower circuit SFl can supply a potential substantially equal to the potential input to the gate of the transistor M12 (the potential held in the capacitor C11) to the gate of the transistor M23.

[0510] The first terminal of transistor M22 is electrically connected to the first terminal of transistor M23 and the non-inverting input terminal of operational amplifier OP. The second terminal of transistor M22 is electrically connected to wiring VDD, and the gate of transistor M22 is electrically connected to wiring Vb2. The second terminal of transistor M23 is electrically connected to wiring VSS.

[0511] Wiring VDD is a wiring that supplies a high-level potential higher than the low-level potential supplied by wiring VSS, and wiring Vb2 is a wiring that supplies a voltage lower than the threshold voltage of transistor M22.

[0512] Transistors M22 and M23 form a source follower circuit SF2 through the above connections. Therefore, a potential approximately equal to the potential input to the gate of transistor M23 is input to the non-inverting input terminal of operational amplifier OP.

[0513] The inverting input terminal of operational amplifier OP is electrically connected to the output terminal of operational amplifier OP. In other words, operational amplifier OP has a connection structure of a voltage follower. In addition, the detailed specifications of the storage device of this embodiment will be described later, and the signal AOUT output from operational amplifier OP is an analog potential.

[0514] Note that by adjusting the potentials supplied by wiring Vb1 and wiring Vb2 respectively, the error between the read voltage and the write voltage can be reduced.

[0515] Figure 42 The timing diagram shows Figure 41 the operating example of the storage device shown. Figure 42 It shows the potential changes of wiring WWL, wiring WBL, wiring RWL, wiring RBL, node FN, and signal AOUT respectively.

[0516] As Figure 42 shown, when writing data, 4-bit write data DT is input to circuit CD as signal DIN[3:0]. In addition, circuit CD performs digital-to-analog conversion on data DT, generates a potential corresponding to data DT, and supplies a potential equivalent to data DT to wiring WBL. Then, circuit RD supplies a high-level potential to wiring WWL to turn on transistor M11. Thus, the potential of wiring WBL (the analog potential corresponding to data DT) can be written to the first terminal of capacitor C11. Then, a low-level potential is applied to wiring WWL to turn off transistor M11, thereby maintaining the potential of the first terminal of capacitor C11 and the potential of the gate of transistor M12 (node FN). Note that a low-level potential is applied to wiring RWL and wiring RBL. At this time, transistor M13 is in the off state.

[0517] Note that the 4-bit write data DT is converted into a 16-level analog potential by the digital-to-analog conversion circuit included in the circuit CD.

[0518] As Figure 42 shown, the data is read out by applying a prescribed potential to the wiring WBL and a high-level potential to the wiring RWL to turn on the transistor M13. At this time, the potential of the wiring RBL is determined according to the potential of the first terminal of the capacitor C11 and the potential of the gate (node FN) of the transistor M12. In addition, the potential of the wiring RBL is input to the circuit RS and the readout circuit ROC, and the readout circuit ROC outputs a signal AOUT corresponding to the potential of the wiring RBL, that is, the data written to the node FN. Thus, the information written to the memory cell can be read out.

[0519] <Manufacture of the storage device> The circuit structure of the above storage device is actually formed on a semiconductor substrate, and thus a memory die is prototyped. Figure 43 is an image of the top surface of the memory die.

[0520] In addition, the following table shows the specifications of the memory die. Note that in the design specification items shown in the following table, CMOS refers to the transistors M12, M13, and M21 to M23, and OSFET refers to the transistor M11. In addition, the density item indicates that the memory cell array MA includes a circuit configured in a matrix of 2 rows and 8 columns, and one such circuit includes 8 memory cells that can be accessed simultaneously in parallel.

[0521] [Table 1]

[0522] <Various measurements and results> In a memory die including the Figure 41 shown storage device, one memory cell MC is selected, and a 16-level voltage obtained by converting 4-bit digital data by a digital-to-analog conversion circuit (DAC) is written to the memory cell MC, and the readout voltage with respect to each write voltage is measured. And the same measurement is performed on the other 15 memory cells MC, and the average value and the standard deviation σ of the voltages of each level read from a total of 16 memory cells MC are obtained.

[0523] Figure 44A The results are shown. Figure 44A shows the relationship between the 16-level write voltage (DAC input 4-bit digital data [HEX]) and the average ±3σ of the readout voltage. Note that in Figure 44A it, the 16-level write voltages are described as 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. As Figure 44AAs shown, a good linearity between the write voltage and the read voltage can be confirmed. In addition, among adjacent write voltages, the voltage between the distributions of write voltage "E" and write voltage "F" is the narrowest within the range of "average value of read voltage ± 3σ" for each. Note that the voltage between the distributions at this time is 0.291V.

[0524] In addition, Figure 44B is a graph with the 16-level write voltage (4-bit digital data [HEX] input to the DAC) on the horizontal axis and 3σ on the vertical axis. From Figure 44B it can be seen that when the write voltage is "F", 3σ becomes the maximum value, that is, 3σ = 0.101V. In addition, the voltage range from -3σ to 3σ is 0.202V.

[0525] Based on the above results, the voltage range of -3σ to 3σ when 3σ is the maximum, which is 0.202V, is lower than the minimum value of the voltage between the distributions within the range of "average value of read voltage ± 3σ" for adjacent write voltages, which is 0.291V. Therefore, it is possible to increase the number of levels of the write voltage beyond 16.

[0526] For example, Figure 45A shows a schematic diagram of the threshold voltage distributions of write voltage "E" and write voltage "F". Based on the above results, the voltage between the distributions of write voltage "E" and write voltage "F" is 0.291V, and the voltage range from -3σ to 3σ for write voltage "F" when 3σ is the maximum is 0.202V. Therefore, the threshold voltage distribution for each of write voltage "E" and write voltage "F" is as Figure 45A shown. Therefore, as Figure 45B shown in the schematic diagram of the threshold voltage distribution, a write voltage of a new level can be set between write voltage "E" and write voltage "F". Note that in Figure 45B it is recorded as "F 32 " for the write voltage of the new level, represented by a dashed line. In addition, in Figure 45B the voltage range from -3σ to 3σ for write voltage "F 32 " is set to 0.202V.

[0527] Next, the data retention characteristics of the manufactured memory device are measured. Specifically, the 16-level write voltages used in the above measurements are written to the memory cells MC included in the memory cell array MA of the memory device, and the time variation of each read voltage at room temperature ( Figure 46A ) is measured. Figure 46A The graph shown in

[0528] shows the variation amount of the read voltage with respect to the retention time. From this graph, it can be seen that the 16-level voltages written to the memory cells MC continue to be retained without change for about 3 hours. In addition,Figure 46B The figure shows the variation amount of the read voltage after 3 hours with respect to the voltage written to the memory cell MC (4-bit digital data [HEX] input to the DAC). From Figure 46B the graph of, it can be confirmed that the range of the variation amount of the read voltage (voltage change [v] after 3 hours) is from 0 V to -0.05 V, and the data can be accurately retained even after 3 hours. In addition, the maximum variation amount at this time is 0.038 V for the write voltage "F".

[0529] Taking into account the above variation amount, the voltage range from -3σ to 3σ when 3σ is the maximum is 0.202 + 0.038 = 0.240 V, and the voltage between the distributions within the range of "average read voltage ±3σ with respect to adjacent write voltages" is 0.291 - 0.038 = 0.253 V. Even considering the above variation amount, the voltage range from -3σ to 3σ is lower than the voltage between the distributions within the range of "average read voltage ±3σ with respect to adjacent write voltages", so the number of levels of the write voltage that can be retained in the memory cell MC can be made greater than 16 levels. In addition, based on the voltage range from -3σ to 3σ and the voltage between the distributions within the range of "average read voltage ±3σ with respect to adjacent write voltages", it can be estimated that the memory cell MC can retain an analog potential of 32 levels (i.e., equivalent to 5-bit digital data) for 3 hours.

[0530] For example, Figure 47A shows a schematic diagram of the threshold voltage distributions of the write voltage "E" and the write voltage "F". According to the above results, the voltage range from -3σ to 3σ in the changed write voltage "F" is 0.240 V, and the voltage between the distributions within the range of "average read voltage ±3σ with respect to adjacent write voltages" is 0.291 - 0.038 = 0.251 V. Therefore, the threshold voltage distributions of the write voltage "E" and the write voltage "F" are as Figure 47A shown. Note that in Figure 47A , the changed voltage distribution is shown by a dotted line.

[0531] Therefore, even considering the above variation amount, as Figure 47B shown, a write voltage of a new level can be set between the write voltage "E" and the write voltage "F" in the same way as Figure 45B . Figure 47B is a schematic diagram of the threshold voltage distribution of the write voltage "F Figure 47A " with a new level set between the write voltage "E" and the write voltage "F" in 32 . Note that in Figure 45B , the write voltage "F 32 " before the change is shown by a dashed line, and the write voltage "F 32 " after the change is shown by a dotted line.”. In addition, in Figure 47B , the voltage range of -3σ to 3σ of the write voltage “F” 32 is set to 0.240V.

[0532] Based on the above results, in the circuit structure shown in Figure 41 , by using a transistor including CAAC-IGZO in the active layer as the write transistor, a storage device capable of processing 5-bit data per cell and retaining the data for 3 hours can be constructed. [Symbol Explanation]

[0533] DEV: Semiconductor device, DEVA: Semiconductor device, ALYa: Storage layer, ALYb: Storage layer, ALYc: Storage layer, MC: Memory cell, MCa: Memory cell, MCa[i,j]: Memory cell, MCa[i,j - 1]: Memory cell, MCa[i,j + 1]: Memory cell, MCa[i + 1,j + 1]: Memory cell, MCa[i + 1,j]: Memory cell, MCa[i + 1,j - 1]: Memory cell, MCb: Memory cell, MCb[i,j]: Memory cell, MCb[i,j + 1]: Memory cell, MCc: Memory cell, MCA[i,j]: Memory cell, MCA[i,j + 2]: Memory cell, MCB[i,j + 1]: Memory cell, MCC[i,j]: Memory cell, MCC[i,j + 2]: Memory cell, MCZ[i,j + 1]: Memory cell, WWLa[i]: Wiring, WWLa[i + 1]: Wiring, WWLb[i]: Wiring, WWLc[i]: Wiring, RWLa[i]: Wiring, RWLa[i + 1]: Wiring, RWLb[i]: Wiring, RWLc[i]: Wiring, CLa[i]: Wiring, CLa[i + 1]: Wiring, CLb[i]: Wiring, CLc[i]: Wiring, WRBLa[j]: Wiring, WRBLa[j + 1]: Wiring, WRBLa[j + 2]: Wiring, WRBLa[j + 3]: Wiring, WRBLb[j]: Wiring, WRBLb[j + 1]: Wiring, WRBLb[jjj + 2]: Wiring, WRBLc[j + 1]: Wiring, WRBLc[j + 3]: Wiring, SLa[j]: Wiring, SLa[j + 1]: Wiring, SLa[j + 2]: Wiring, SLb[j]: Wiring, SLb[j + 1]: Wiring, SLc[j]: Wiring, SLc[j + 2]: Wiring, WL[1]: Wiring, WL[i]: Wiring, WL[m]: Wiring, BL[1]: Wiring, BL[j]: Wiring, BL[n]: Wiring, WWL: Wiring, WWL[m]: Wiring, WWL[m + 1]: Wiring, WBL: Wiring, WBL[n]: Wiring, WBL[n + 1]: Wiring, RWL: Wiring, RWL[m]: Wiring, RWL[m + 1]: Wiring, RBL: Wiring, RBL[n]: Wiring, RBL[n + 1]: Wiring, CL: Wiring, Vb1: Wiring, Vb2: Wiring, CD: Circuit, RD: Circuit, RS: Circuit, ROC: Readout circuit, OP: Operational amplifier, M1: Transistor, M2: Transistor, M3: Transistor, M11: Transistor, M12: Transistor, M13: Transistor, M21: Transistor, M22: Transistor, M23: Transistor, C1: Capacitor, C11: Capacitor, FN: Node, PLa: Opening, PLb: Opening, PLc: Opening, PLd: Opening, PLe: Opening, 10: Memory cell10[1, 1]: Memory cell, 10[m, 1]: Memory cell, 10[1, n]: Memory cell, 10[m, n]: Memory cell, 10[i, j]: Memory cell, 22: PSW, 23: PSW, 31: Peripheral circuit, 32: Control circuit, 33: Voltage generation circuit, 41: Peripheral circuit, 42: Row decoder, 43: Row driver, 44: Column decoder, 45: Column driver, 46: Sense amplifier, 47: Input circuit, 48: Output circuit, 50: Driver circuit layer, 60_k: Storage layer, 60_1: Storage layer, 60_2: Storage layer, 60_3: Storage layer, 60_N: Storage layer, 100: Storage device, 122a: Insulator, 122b: Insulator, 122c: Insulator, 124: Insulator, 130: Oxide, 130a: Oxide, 130b: Oxide, 142a: Conductor, 142b: Conductor, 142c: Conductor, 142d: Conductor, 142e: Conductor, 142f: Conductor, 142g: Conductor, 153_0: Insulator, 153_1: Insulator, 153_2: Insulator, 153_3: Insulator, 153_4: Insulator, 154_0: Insulator, 154_1: Insulator, 154_2: Insulator, 154_3: Insulator, 154_4: Insulator, 157_3: Opening, 157_5: Opening, 158_2: Opening, 158_3: Opening, 158_4: Opening, 159: Opening, 160_0: Conductor, 160_1: Conductor, 160_2: Conductor, 160_3: Conductor, 160_4: Conductor, 160a_1: Conductor, 160a_2: Conductor, 160a_3: Conductor, 160a_4: Conductor, 160b_1: Conductor, 160b_2: Conductor, 160b_3: Conductor, 160b_4: Conductor, 170_0: Conductor, 170_1: Conductor, 170_2: Conductor, 170_3: Conductor, 170_4: Conductor, 170_5: Conductor, 170a_1: Conductor, 170a_2: Conductor, 170a_3: Conductor, 170a_4: Conductor, 170a_5: Conductor, 170b_1: Conductor, 170b_2: Conductor, 170b_3: Conductor, 170b_4: Conductor, 170b_5: Conductor, 171_1: Conductor, 171_3: Conductor, 175: Insulator, 180: Insulator, 180_0: Insulator, 301: Insulator, 311: Substrate, 313: Semiconductor region, 314a: Low-resistance region, 314b: Low-resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 356: Conductor, 357: Insulator400: Transistor, 700: Electronic component, 710: Semiconductor device, 711: Die, 712: Bond pad, 713: Electrode pad, 714: Lead, 715: Driver circuit layer, 716: Storage layer, 730: Electronic component, 731: Daughter board, 732: Package substrate, 735: Semiconductor device, 5600: Mainframe computer, 5610: Rack, 5620: Computer, 5621: Personal computer card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6600: Electronic device, 6611: Housing, 6612: Keyboard, 6613: Pointing device, 6614: External connection port, 6615: Display unit, 6616: Control device, 6800: Satellite, 6801: Main body, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7000: Storage system, 7001: Host, 7001sb: Server, 7002: Storage control circuit, 7003: Storage, 7003md: Storage device, 7004: Storage area network.

Claims

1. A semiconductor device, comprising: a first layer and a first insulator, wherein the first layer includes a first oxide semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a second insulator, a third insulator, a fourth insulator, and a fifth insulator, the first layer is located on the first insulator, the first oxide semiconductor is located above the first insulator, the first conductor is located on the top surface and side surfaces of the first oxide semiconductor and on the top surface of the first insulator, the second conductor is located on the top surface of the first oxide semiconductor, the second insulator is located between the first conductor and the second conductor when viewed in cross-section and on the top surface of the first oxide semiconductor, the third conductor is located on the top surface of the second insulator, the fourth conductor is located on the top surface of the first oxide semiconductor, the third insulator is located between the second conductor and the fourth conductor when viewed in cross-section and on the top surface of the first oxide semiconductor, the fifth conductor is located on the top surface of the third insulator, the sixth conductor is located on the top surface and side surfaces of the first oxide semiconductor and on the top surface of the first insulator, the fourth insulator is located between the fourth conductor and the sixth conductor when viewed in cross-section and on the top surface of the first oxide semiconductor, the seventh conductor is located on the top surface of the fourth insulator, the fifth insulator is located on the first conductor in a region that does not overlap with the first oxide semiconductor and overlaps with the first insulator, the eighth conductor is located on the fifth insulator, and the ninth conductor is located on the second conductor.

2. The semiconductor device according to claim 1, wherein the first layer includes a second oxide semiconductor, a tenth conductor, an eleventh conductor, a twelfth conductor, a thirteenth conductor, and a sixth insulator, the second oxide semiconductor is located above the first insulator, the tenth conductor is located on the top surface and side surfaces of the second oxide semiconductor and on the top surface of the first insulator, the eleventh conductor is located on the top surface of the second oxide semiconductor, the sixth insulator is located between the tenth conductor and the eleventh conductor when viewed in cross-section and on the top surface of the second oxide semiconductor, the twelfth conductor is located on the sixth insulator, and the thirteenth conductor is located on the first conductor and the twelfth conductor.

3. The semiconductor device according to claim 2, further comprising: a second layer and a seventh insulator, wherein the second layer includes a third oxide semiconductor, a fourteenth conductor, a seventh insulator, and an eighth insulator, the seventh insulator is located on the first layer, the second layer is located on the seventh insulator, the third oxide semiconductor has a region overlapping with the eighth conductor and the thirteenth conductor, the eighth insulator overlaps with the eighth conductor and is located on the top surface of the third oxide semiconductor, And the fourteenth conductor is located on the eighth insulator.

4. The semiconductor device according to claim 3, wherein each of the first oxide semiconductor, the second oxide semiconductor, and the third oxide semiconductor includes one or more selected from indium, zinc, and element M, and the element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.

5. A storage device, comprising: the semiconductor device according to any one of claims 1 to 4 and a drive circuit, wherein the first insulator is located above the drive circuit.

6. An electronic device including the storage device according to claim 5 and a housing.

7. A semiconductor device, comprising: a first layer, a second layer, a first insulator, a second insulator, and a first conductor, wherein each of the first layer and the second layer includes a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator, the first layer is located on the first insulator, the second insulator is located on the first layer, the second layer is located on the second insulator, in each of the above-mentioned first layer and the second layer, the second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, the third conductor is located on the top surface of the first oxide semiconductor, the fourth insulator is located between the second conductor and the third conductor when viewed in cross section and on the top surface of the first oxide semiconductor, the fourth conductor is located on the top surface of the fourth insulator, the fifth conductor is located on the top surface of the first oxide semiconductor, the fifth insulator is located between the third conductor and the fifth conductor when viewed in cross section and on the top surface of the first oxide semiconductor, the sixth conductor is located on the top surface of the fifth insulator, the seventh conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, the sixth insulator is located between the fifth conductor and the seventh conductor when viewed in cross section and on the top surface of the first oxide semiconductor, the eighth conductor is located on the top surface of the sixth insulator, the seventh insulator is located in a region of the top surface of the seventh conductor that does not overlap with the first oxide semiconductor, the ninth conductor is located on the top surface of the seventh insulator, the tenth conductor is located on the top surface of the fifth conductor, the second insulator has an opening, the first conductor is located in the opening, the first conductor is located on the top surface of the fourth conductor of the first layer, and a part of the seventh conductor of the second layer is located on the top surface of the first conductor.

8. A semiconductor device, comprising: The first layer, the second layer, the third layer, the first insulator, the second insulator, the third insulator, and the first conductor wherein the first layer, the second layer, and the third layer each include a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator The first layer is located on the first insulator The second insulator is located on the first layer The second layer is located on the second insulator The third insulator is located on the second layer The third layer is located on the third insulator In each of the first layer, the second layer, and the third layer the second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor the third conductor is located on the top surface of the first oxide semiconductor the fourth insulator is located between the second conductor and the third conductor when viewed in cross-section and on the top surface of the first oxide semiconductor the fourth conductor is located on the top surface of the fourth insulator the fifth conductor is located on the top surface of the first oxide semiconductor the fifth insulator is located between the third conductor and the fifth conductor when viewed in cross-section and on the top surface of the first oxide semiconductor the sixth conductor is located on the top surface of the fifth insulator the seventh conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor the sixth insulator is located between the fifth conductor and the seventh conductor when viewed in cross-section and on the top surface of the first oxide semiconductor the eighth conductor is located on the top surface of the sixth insulator the seventh insulator is located in a region of the top surface of the seventh conductor that does not overlap with the first oxide semiconductor the ninth conductor is located on the top surface of the seventh insulator the tenth conductor is located on the top surface of the fifth conductor The second insulator has an opening The first conductor is located in the opening The first conductor is located on the top surface of the fourth conductor of the first layer A part of the seventh conductor of the second layer is located on the top surface of the first conductor and, the ninth conductor of the second layer is located in a region overlapping with the eighth conductor of the third layer 9. A semiconductor device, comprising: a first layer, a second layer, a first insulator, a second insulator, and a first conductor wherein the first layer and the second layer each include a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator The first layer is located on the first insulator The second insulator is located on the first layer The second layer is located on the second insulator In each of the first layer and the second layer, the second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, the third conductor is located on the top surface of the first oxide semiconductor, the fourth insulator is located between the second conductor and the third conductor when viewed in cross section and on the top surface of the first oxide semiconductor, the fourth conductor is located on the top surface of the fourth insulator, the fifth conductor is located on the top surface of the first oxide semiconductor, the fifth insulator is located between the third conductor and the fifth conductor when viewed in cross section and on the top surface of the first oxide semiconductor, the sixth conductor is located on the top surface of the fifth insulator, the seventh conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, the sixth insulator is located between the fifth conductor and the seventh conductor when viewed in cross section and on the top surface of the first oxide semiconductor, the eighth conductor is located on the top surface of the sixth insulator, the seventh insulator is located in a region of the top surface of the seventh conductor that does not overlap with the first oxide semiconductor, the ninth conductor is located on the top surface of the seventh insulator, the tenth conductor is located on the top surface of the fifth conductor, the second insulator has an opening, the first conductor is located in the opening, the first conductor is located on the top surface of the sixth conductor of the first layer, and a part of the seventh conductor of the second layer is located on the top surface of the first conductor.

10. A semiconductor device, comprising: a first layer, a second layer, a third layer, a first insulator, a second insulator, a third insulator, and a first conductor, wherein each of the first layer, the second layer, and the third layer includes a first oxide semiconductor, a second conductor, a third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a seventh conductor, an eighth conductor, a ninth conductor, a tenth conductor, a fourth insulator, a fifth insulator, a sixth insulator, and a seventh insulator, the first layer is located on the first insulator, the second insulator is located on the first layer, the second layer is located on the second insulator, the third insulator is located on the second layer, the third layer is located on the third insulator, in each of the first layer, the second layer, and the third layer, the second conductor is located on the top surface and side surfaces of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor, the third conductor is located on the top surface of the first oxide semiconductor, the fourth insulator is located between the second conductor and the third conductor when viewed in cross section and on the top surface of the first oxide semiconductor, the fourth conductor is located on the top surface of the fourth insulator, the fifth conductor is located on the top surface of the first oxide semiconductor, The fifth insulator is located between the third conductor and the fifth conductor when viewed in cross section and on the top surface of the first oxide semiconductor. The sixth conductor is located on the top surface of the fifth insulator. The seventh conductor is located on the top surface and side surface of the first oxide semiconductor and in a region not overlapping with the first oxide semiconductor. The sixth insulator is located between the fifth conductor and the seventh conductor when viewed in cross section and on the top surface of the first oxide semiconductor. The eighth conductor is located on the top surface of the sixth insulator. The seventh insulator is located in a region of the top surface of the seventh conductor that does not overlap with the first oxide semiconductor. The ninth conductor is located on the top surface of the seventh insulator. The tenth conductor is located on the top surface of the fifth conductor. The second insulator has an opening. The first conductor is located in the opening. The first conductor is located on the top surface of the sixth conductor of the first layer. A part of the seventh conductor of the second layer is located on the top surface of the first conductor. And, the ninth conductor of the second layer is located in a region overlapping with the eighth conductor of the third layer.

11. The semiconductor device according to any one of claims 7 to 10, wherein the first oxide semiconductor contains one or more selected from indium, zinc, and element M, and the element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.

12. A storage device, comprising: the semiconductor device according to claim 11 and a drive circuit, wherein the first insulator is located above the drive circuit.

13. An electronic device including the storage device according to claim 12 and a housing.

Images