Method and system for testing power consumption of processor chip

Abstract

The invention discloses a processor chip power consumption test method and test system, and belongs to the technical field of processor chips, and the method comprises the steps: collecting and processing the real-time test data of a processor chip, and determining the feature test data of the processor chip; training a processor chip power consumption test prediction model, analyzing the processor chip feature test data, predicting processor chip power consumption, and determining a processor chip power consumption prediction result; and displaying the power consumption test condition of the processor chip in a visual form, managing and controlling the processor chip, and adjusting the set dynamic power consumption threshold value by using the dynamic adjustment coefficient. The problem that the power consumption test effect of the processor chip is poor due to the fact that the power consumption characteristic of the processor chip cannot be comprehensively evaluated and the processor chip cannot be effectively controlled in the prior art is solved. The power consumption characteristic of the processor chip can be comprehensively evaluated, the processor chip can be effectively controlled, and the power consumption test effect of the processor chip can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of processor chips, and specifically to a method and a test system for testing the power consumption of processor chips. Background Art

[0002] While a processor chip realizes powerful processing functions, its power consumption is also one of the key factors for measuring the performance of the processor chip. Therefore, it is necessary to test the power consumption of the processor chip.

[0003] Chinese Patent No. CN118070740A discloses a method for manufacturing a processor chip, a processor chip, an electronic device, and a medium, including: obtaining a first IP core according to a first chip layout, where the first IP core is used to provide the core function of the processor chip; obtaining a second IP core according to a second chip layout, where the second IP core is used to provide the auxiliary function of the processor chip; the layout difference between the first chip layouts corresponding to different first IP cores is greater than the layout difference between the second chip layouts corresponding to different second IP cores. Layout the corresponding chip layouts according to the performance characteristics and functional requirements of different IP cores, so that the layout difference between the first chip layouts corresponding to different first IP cores is greater than the layout difference between the second chip layouts corresponding to different second IP cores, which can avoid changing the full-level chip layout, thereby achieving the reduction of the manufacturing cost of the chip layout while ensuring the chip performance, so as to obtain a processor chip product that meets the application requirements; however, the patent has the following defects:

[0004] The existing technology cannot comprehensively evaluate the power consumption characteristics of the processor chip and cannot effectively control the processor chip, resulting in poor power consumption test results of the processor chip. Summary of the Invention

[0005] The purpose of the present invention is to provide a method and a test system for testing the power consumption of processor chips, which can comprehensively evaluate the power consumption characteristics of the processor chip, can effectively control the processor chip, and can improve the power consumption test effect of the processor chip, and solve the problems raised in the above background art.

[0006] To achieve the above purpose, the present invention provides the following technical solutions:

[0007] A method for testing the power consumption of a processor chip, including:

[0008] Collecting real-time test data of the processor chip and processing it to determine the characteristic test data of the processor chip;

[0009] Training a power consumption test prediction model for the processor chip, analyzing the characteristic test data of the processor chip, predicting the power consumption of the processor chip, and determining the power consumption prediction result of the processor chip;

[0010] Display the power consumption test situation of the processor chip in a visual form and control the processor chip;

[0011] Among them, the set dynamic power threshold is adjusted by using a dynamic adjustment coefficient.

[0012] Preferably, real-time test data of the processor chip is collected, including:

[0013] The current and voltage of the processor chip in the idle state are monitored and collected in real time to obtain the static test data of the processor chip;

[0014] The current and voltage of the processor chip under different loads are monitored and collected in real time to obtain the dynamic test data of the processor chip;

[0015] Among them, the real-time test data of the processor chip is determined according to the static test data and dynamic test data of the processor chip.

[0016] Preferably, the real-time test data of the processor chip is processed, including:

[0017] The real-time test data of the processor chip is cleaned, the integrity of the real-time test data of the processor chip is checked, and duplicate values, missing values and outliers in the real-time test data of the processor chip are identified;

[0018] For the duplicate values in the real-time test data of the processor chip, the duplicate values are removed and only unique data records are retained;

[0019] For the missing values in the real-time test data of the processor chip that are tested to be useless for the power consumption test of the processor chip, the missing values are removed; for the missing values in the real-time test data of the processor chip that are tested to be useful for the power consumption test of the processor chip, the missing values are filled;

[0020] For the outliers in the real-time test data of the processor chip that are tested to be useless for the power consumption test of the processor chip, the outliers are removed; for the outliers in the real-time test data of the processor chip that are tested to be useful for the power consumption test of the processor chip, the outliers are replaced or corrected;

[0021] Based on a filtering algorithm, the cleaned real-time test data of the processor chip is filtered to remove the noise in the real-time test data of the processor chip to reduce noise interference.

[0022] Preferably, the processing of the real-time test data of the processor chip further includes:

[0023] The real-time test data of the processor chip is normalized to reduce the dimensional difference of the real-time test data of the processor chip and determine the standardized real-time test data of the processor chip;

[0024] Extract features from the real-time test data of the processor chip, extract the features related to the power consumption test of the processor chip from the real-time test data of the processor chip, and determine the feature test data of the processor chip.

[0025] Preferably, training the power consumption test prediction model of the processor chip includes:

[0026] Collect historical test data of the processor chip, including historical current, voltage, and power consumption;

[0027] Divide the collected historical test data of the processor chip to determine the training set and the test set;

[0028] Based on deep learning technology, use the training set to train the deep learning model, enable the deep learning model to autonomously learn the power consumption test prediction behavior of the processor chip, and predict the power consumption of the processor chip to determine the power consumption test prediction model of the processor chip based on deep learning;

[0029] Based on the test set, conduct performance testing on the power consumption test prediction model of the processor chip based on deep learning, and evaluate whether the power consumption test prediction model of the processor chip based on deep learning can achieve the expected effect;

[0030] When the power consumption test prediction model of the processor chip based on deep learning cannot achieve the expected effect, adjust the parameters of the power consumption test prediction model of the processor chip based on deep learning, and continuously optimize the power consumption test prediction model of the processor chip based on deep learning until a power consumption test prediction model of the processor chip that can achieve the expected effect is determined.

[0031] Preferably, analyzing the feature test data of the processor chip includes:

[0032] Obtain the power consumption test prediction model of the processor chip, and deploy the power consumption test prediction model of the processor chip in the actual power consumption test prediction environment of the processor chip;

[0033] Input the feature test data of the processor chip into the power consumption test prediction model of the processor chip, analyze the feature test data of the processor chip according to the power consumption test prediction model of the processor chip, and predict the power consumption of the processor chip to determine the power consumption prediction result of the processor chip.

[0034] Preferably, display the power consumption test situation of the processor chip in a visual form, and conduct control over the processor chip, including:

[0035] According to the power consumption prediction result of the processor chip and combined with the feature test data of the processor chip, form a power consumption test report of the processor chip, and display the power consumption test report of the processor chip to the management personnel in a visual form;

[0036] The management personnel evaluate the power consumption performance of the processor chip according to the power consumption test report of the processor chip, obtain the power consumption performance coefficient by combining the set dynamic power consumption threshold, and output the power consumption performance coefficient as the power consumption performance evaluation result;

[0037] Intelligently control the processor chip according to the power consumption performance evaluation result. Among them, dynamically adjust the voltage and frequency of the processor chip to reduce power consumption, and set a power consumption upper limit to make the processor chip operate within the budget. In a multi-core processor, allocate tasks to the core with the highest energy efficiency to achieve load balancing.

[0038] Preferably, it further includes:

[0039] Regularly obtain the historical working temperature data, historical working condition data, and historical load data of the processor chip within a preset time period;

[0040] According to the historical working temperature data, determine the historical working temperature extreme value and historical working temperature average value of the processor chip, and calculate the temperature reference value;

[0041] Perform difference analysis on the first temperature reference value of the processor chip in the current preset time period and the second temperature reference value of the previous preset time period to obtain the temperature change reference coefficient;

[0042] Use the historical working condition data and historical load data to establish the working condition change curve and load change curve of the processor chip within the current preset time period respectively according to the time sequence;

[0043] After dividing the working condition change curve and load change curve of the processor chip in the current preset time period proportionally, obtain the first working condition sub-curve and the first load sub-curve respectively, and mark the curve acquisition order for the first working condition sub-curve and the first load sub-curve;

[0044] The sub-curves obtained by dividing the working condition change curve and load change curve of the processor chip in the previous preset time period proportionally are respectively marked as the second working condition sub-curve and the second load sub-curve, and the curve acquisition order is marked for the second working condition sub-curve and the second load sub-curve;

[0045] Use the set similarity algorithm to perform similarity analysis on the first working condition sub-curve and the second working condition sub-curve with the same curve acquisition order, and mark the target first working condition sub-curve and the target second working condition sub-curve with a similarity representation coefficient greater than the set similarity threshold as the first analysis condition sub-curve and the second analysis condition sub-curve respectively;

[0046] Respectively obtain the condition reference values of the first analysis condition sub-curve and the second analysis condition sub-curve with the same curve acquisition order, and obtain the condition difference value through difference comparison;

[0047] Perform similarity analysis on the first load sub-curve and the second load sub-curve obtained in the same curve acquisition order, and mark the first load sub-curve and the second load sub-curve with a similarity representation coefficient greater than the set similarity threshold as the first analysis load sub-curve and the second analysis load sub-curve respectively;

[0048] Obtain the load reference values of the target first analysis load sub-curve and the target second analysis load sub-curve obtained in the same curve acquisition order respectively, and obtain the load difference value through difference comparison;

[0049] Combine the condition difference value and similarity representation coefficient of the first analysis condition sub-curve and the second analysis condition sub-curve obtained in the same curve acquisition order, and the load difference value and similarity representation coefficient of the first analysis load sub-curve and the second analysis load sub-curve with the temperature change reference coefficient to calculate the dynamic adjustment coefficient;

[0050] Use the dynamic adjustment coefficient to adjust the set dynamic power consumption threshold.

[0051] According to another aspect of the present invention, there is provided a processor chip power consumption test system for implementing the processor chip power consumption test method as described above, including:

[0052] A data acquisition module configured to acquire real-time test data of the processor chip;

[0053] A data processing module configured to process the real-time test data of the acquired processor chip to determine the characteristic test data of the processor chip;

[0054] A model construction module configured to construct a processor chip power consumption test prediction model according to the processor chip power consumption test requirements;

[0055] A power consumption prediction module configured to analyze the characteristic test data of the processor chip according to the processor chip power consumption test prediction model and predict the power consumption of the processor chip;

[0056] A display and control module configured to visually display the processor chip power consumption test situation and control the processor chip according to the displayed processor chip power consumption test situation.

[0057] Compared with the prior art, the beneficial effects of the present invention are:

[0058] The present invention determines the real-time test data of a processor chip by collecting the static test data and dynamic test data of the processor chip, determines the characteristic test data of the processor chip by processing the real-time test data of the processor chip, constructs a power consumption test prediction model for the processor chip according to the power consumption test requirements of the processor chip, analyzes the characteristic test data of the processor chip based on the power consumption test prediction model of the processor chip, predicts the power consumption of the processor chip, determines the power consumption prediction result of the processor chip, and displays the power consumption test situation of the processor chip in a visual form, and effectively manages the processor chip, so as to comprehensively evaluate the power consumption characteristics of the processor chip, and can effectively manage the processor chip, and improve the power consumption test effect of the processor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 is a flowchart of the method for testing the power consumption of a processor chip according to the present invention;

[0060] Figure 2 is a block diagram of the system for testing the power consumption of a processor chip according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0061] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0062] In order to solve the problem that the existing technology cannot comprehensively evaluate the power consumption characteristics of a processor chip and cannot effectively manage the processor chip, resulting in poor power consumption test effect of the processor chip, please refer to Figure 1 - Figure 2 , the following technical solutions are provided in this embodiment:

[0063] A system for testing the power consumption of a processor chip includes: a data acquisition module, a data processing module, a model construction module, a power consumption prediction module, and a display and management module.

[0064] Specifically, the real-time test data of the processor chip is collected through the data acquisition module;

[0065] Specifically, the real-time test data of the collected processor chip is processed through the data processing module to determine the characteristic test data of the processor chip;

[0066] Specifically, a power consumption test prediction model for the processor chip is constructed through the model construction module;

[0067] Specifically, the characteristic test data of the processor chip is analyzed through the power consumption prediction module, and the power consumption of the processor chip is predicted;

[0068] Specifically, the display control module visually displays the power consumption test situation of the processor chip, and controls the processor chip according to the displayed power consumption test situation of the processor chip.

[0069] It should be noted that through the interactive communication between the data acquisition module, the data processing module, the model construction module, the power consumption prediction module and the display control module, the power consumption characteristics of the processor chip can be comprehensively evaluated, and the processor chip can be effectively controlled, which can improve the power consumption test effect of the processor chip. Among them, by measuring the power consumption of the processor chip under different workloads, the energy consumption level of the processor chip in the normal operation state can be understood.

[0070] To better present the power consumption test process of the processor chip, this embodiment now provides a power consumption test method for the processor chip, which is implemented based on the above-mentioned power consumption test system of the processor chip, and includes:

[0071] Collect real-time test data of the processor chip;

[0072] In this embodiment, collecting real-time test data of the processor chip includes:

[0073] Real-time monitor and collect the current and voltage of the processor chip in the idle state to obtain the static test data of the processor chip;

[0074] Real-time monitor and collect the current and voltage of the processor chip under different loads to obtain the dynamic test data of the processor chip;

[0075] Among them, according to the static test data and dynamic test data of the processor chip, the real-time test data of the processor chip is determined.

[0076] It should be noted that by real-time monitoring and collecting the current and voltage of the processor chip in the idle state to obtain the static test data of the processor chip, by real-time monitoring and collecting the current and voltage of the processor chip under different loads to obtain the dynamic test data of the processor chip, and by collecting the static test data and dynamic test data of the processor chip to determine the real-time test data of the processor chip, it is convenient to comprehensively evaluate the power consumption characteristics of the processor chip subsequently.

[0077] Process the real-time test data of the processor chip to determine the characteristic test data of the processor chip;

[0078] In this embodiment, processing the real-time test data of the processor chip includes:

[0079] Clean the real-time test data of the processor chip, check the integrity of the real-time test data of the processor chip, and identify duplicate values, missing values and outliers in the real-time test data of the processor chip;

[0080] For duplicate values in the real-time test data of the processor chip, the duplicate values are removed and only unique data records are retained;

[0081] For missing values in the real-time test data of the processor chip that are found to be useless for the power consumption test of the processor chip, the missing values are removed; for missing values in the real-time test data of the processor chip that are found to be useful for the power consumption test of the processor chip, the missing values are filled;

[0082] For outliers in the real-time test data of the processor chip that are found to be useless for the power consumption test of the processor chip, the outliers are removed; for outliers in the real-time test data of the processor chip that are found to be useful for the power consumption test of the processor chip, the outliers are replaced or corrected;

[0083] Based on the filtering algorithm, the cleaned real-time test data of the processor chip is filtered to remove the noise in the real-time test data of the processor chip, so as to reduce the noise interference.

[0084] It should be noted that by cleaning and filtering the real-time test data of the processor chip, the noise, duplicate values, missing values, and outliers that are useless for the power consumption test of the processor chip can be removed from the real-time test data of the processor chip, which can improve the processing speed and accuracy of the subsequent real-time test data of the processor chip and improve the data quality.

[0085] In this embodiment, the processing of the real-time test data of the processor chip further includes:

[0086] Normalize the real-time test data of the processor chip to reduce the dimensional difference of the real-time test data of the processor chip and determine the standardized real-time test data of the processor chip;

[0087] Extract features from the real-time test data of the processor chip, extract features related to the power consumption test of the processor chip from the real-time test data of the processor chip, and determine the feature test data of the processor chip.

[0088] It should be noted that by normalizing and extracting features from the real-time test data of the processor chip, the feature test data of the processor chip can be determined, which is convenient for subsequent analysis of the feature test data of the processor chip and predicting the power consumption of the processor chip.

[0089] Train the power consumption test prediction model of the processor chip;

[0090] In this embodiment, training the power consumption test prediction model of the processor chip includes:

[0091] Collect the historical test data of the processor chip, including historical current, voltage, and power consumption;

[0092] Divide the historical test data of the processor chip collected to determine the training set and the test set;

[0093] Based on deep learning technology, use the training set to train the deep learning model, enabling the deep learning model to autonomously learn the power consumption test prediction behavior of the processor chip and predict the power consumption of the processor chip, so as to determine the power consumption test prediction model of the processor chip based on deep learning;

[0094] Based on the test set, conduct performance testing on the power consumption test prediction model of the processor chip based on deep learning to evaluate whether the power consumption test prediction model of the processor chip based on deep learning can achieve the expected effect;

[0095] When the power consumption test prediction model of the processor chip based on deep learning cannot achieve the expected effect, then adjust the parameters of the power consumption test prediction model of the processor chip based on deep learning and continuously optimize the power consumption test prediction model of the processor chip based on deep learning until a power consumption test prediction model of the processor chip that can achieve the expected effect is determined.

[0096] Analyze the feature test data of the processor chip, predict the power consumption of the processor chip, and determine the power consumption prediction result of the processor chip;

[0097] In this embodiment, analyzing the feature test data of the processor chip includes:

[0098] Obtain the power consumption test prediction model of the processor chip and deploy the power consumption test prediction model of the processor chip in the actual power consumption test prediction environment of the processor chip;

[0099] Input the feature test data of the processor chip into the power consumption test prediction model of the processor chip, analyze the feature test data of the processor chip according to the power consumption test prediction model of the processor chip, and predict the power consumption of the processor chip to determine the power consumption prediction result of the processor chip.

[0100] It should be noted that by analyzing the feature test data of the processor chip through the power consumption test prediction model of the processor chip and predicting the power consumption of the processor chip, the power consumption prediction result of the processor chip can be determined, which is convenient for comprehensively evaluating the power consumption characteristics of the processor chip.

[0101] Display the power consumption test situation of the processor chip in a visual form and conduct control over the processor chip.

[0102] In this embodiment, displaying the power consumption test situation of the processor chip in a visual form and conducting control over the processor chip includes:

[0103] Based on the power consumption prediction results of the processor chip and combined with the characteristic test data of the processor chip, a power consumption test report of the processor chip is formed, and the power consumption test report of the processor chip is presented to the management personnel in a visual form;

[0104] The management personnel evaluate the power consumption performance of the processor chip according to the power consumption test report of the processor chip, and obtain a power consumption performance coefficient by combining the set dynamic power consumption threshold, and output the power consumption performance coefficient as the power consumption performance evaluation result;

[0105] The processor chip is intelligently controlled according to the power consumption performance evaluation result. Among them, the voltage and frequency of the processor chip are dynamically adjusted to reduce power consumption, and a power consumption upper limit is set to make the processor chip operate within the budget. In a multi-core processor, tasks are assigned to the core with the highest energy efficiency to achieve load balancing.

[0106] In this embodiment, the calculation formula of the power consumption performance coefficient is as follows:

[0107]

[0108] In the formula, P represents the power consumption performance coefficient; x1 represents the power consumption prediction result of the processor chip; x0 represents the set dynamic power consumption threshold; ω1 represents the influence weight of the power consumption prediction result reaching the standard on analyzing the power consumption performance of the processor chip, and the value range is (0, 1); X i represents the actual power consumption of the processor chip at the i-th moment, where i = 1, 2, 3; Δt i represents the time interval between the i-th moment and the corresponding prediction moment of the power consumption prediction result of the processor chip; ω2 represents the influence weight of the difference between the past actual power consumption situation of the processor chip and the predicted power consumption on analyzing the power consumption performance of the processor chip, and the value range is (0, 1); ω1 + ω2 = 1; e represents a constant, and the value is 2.7.

[0109] In this embodiment, the weights ω1 and ω2 assigned to the power consumption prediction result reaching the standard and the difference between the past actual power consumption situation and the predicted power consumption are obtained by solving the matrix constructed after pairwise comparison and scoring using the analytic hierarchy process.

[0110] In this embodiment, for example, there is a corresponding prediction moment 1 of the power consumption prediction result 1 of the processor chip, and the time interval from the current moment is 20s;

[0111] At this time, the 1st moment is the current moment, the 2nd moment is the past moment with a time interval of 20s from the current moment, and the 3rd moment is the past moment with a time interval of 20s from the 2nd moment.

[0112] In this embodiment, setting the dynamic power consumption threshold refers to the standard for measuring whether the power consumption prediction result of the processor chip meets the standard.

[0113] The beneficial effects of the above technical solution are as follows: By quantifying the power consumption performance of the processor chip and calculating the power consumption performance coefficient, an intuitive and comparable evaluation index is provided for the management personnel. It can help the management personnel quickly understand the current power consumption status of the chip, and at the same time, it can provide a scientific data basis for subsequent intelligent control, realizing the effective management of the power consumption of the processor chip.

[0114] In this embodiment, it further includes:

[0115] Regularly obtain the historical working temperature data, historical working condition data, and historical load data of the processor chip within a preset time period;

[0116] According to the historical working temperature data, determine the historical working temperature extreme value and the historical working temperature average value of the processor chip, and calculate the temperature reference value;

[0117] Perform a difference analysis on the first temperature reference value of the processor chip in the current preset time period and the second temperature reference value of the previous preset time period to obtain a temperature change reference coefficient;

[0118] Use the historical working condition data and historical load data to respectively establish the working condition change curve and load change curve of the processor chip within the current preset time period in chronological order;

[0119] After dividing the working condition change curve and load change curve of the processor chip in the current preset time period by the same proportion respectively, the first working condition sub-curve and the first load sub-curve are obtained correspondingly, and the curve acquisition order is marked for the first working condition sub-curve and the first load sub-curve;

[0120] The sub-curves obtained by dividing the working condition change curve and load change curve of the processor chip in the previous preset time period by the same proportion respectively are marked as the second working condition sub-curve and the second load sub-curve respectively, and the curve acquisition order is marked for the second working condition sub-curve and the second load sub-curve;

[0121] Use the set similarity algorithm to perform a similarity analysis on the first working condition sub-curve and the second working condition sub-curve with the same curve acquisition order, and mark the target first working condition sub-curve and the target second working condition sub-curve with a similarity representation coefficient greater than the set similarity threshold as the first analysis condition sub-curve and the second analysis condition sub-curve respectively;

[0122] Respectively obtain the condition reference values of the first analysis condition sub-curve and the second analysis condition sub-curve with the same curve acquisition order, and obtain a condition difference value through difference comparison;

[0123] Perform similarity analysis on the first load sub-curve and the second load sub-curve obtained in the same curve acquisition order, and mark the first load sub-curve and the second load sub-curve with a similarity representation coefficient greater than the set similarity threshold as the first analysis load sub-curve and the second analysis load sub-curve respectively;

[0124] Obtain the load reference values of the target first analysis load sub-curve and the target second analysis load sub-curve in the same curve acquisition order respectively, and obtain the load difference value through difference comparison;

[0125] Combine the condition difference value and similarity representation coefficient of the first analysis condition sub-curve and the second analysis condition sub-curve, and the load difference value and similarity representation coefficient of the first analysis load sub-curve and the second analysis load sub-curve in the same curve acquisition order with the temperature change reference coefficient to calculate the dynamic adjustment coefficient;

[0126] Use the dynamic adjustment coefficient to adjust the set dynamic power consumption threshold.

[0127] In this embodiment, the preset time period refers to the preset time range for collecting historical working temperature, historical working conditions, and historical load; historical working condition data refers to historical voltage data, historical current data, and historical frequency data; historical working temperature data refers to the temperature records of the processor chip in the past preset time period; historical load data refers to the load records of the processor chip in the past preset time period, such as the number of tasks.

[0128] In this embodiment, the historical working temperature extreme value refers to the maximum working temperature and the minimum working temperature in the historical working temperature data; the temperature reference value refers to the value used to represent the average temperature level of the processor chip in a certain time period, and the calculation formula is expressed as: In the formula, b1 represents the temperature reference value of the current preset time period; y avg represents the average working temperature within the current preset time period; y max represents the maximum working temperature within the current preset time period; y min represents the minimum working temperature within the current preset time period.

[0129] In this embodiment, the first temperature reference value refers to the temperature reference value of the current preset time period; the second temperature reference value refers to the temperature reference value of the previous preset time period.

[0130] In this embodiment, the temperature change reference coefficient is obtained by dividing the difference between the first temperature reference value and the second temperature reference value by the first temperature reference value.

[0131] In this embodiment, the operating conditions refer to voltage, current, and frequency; the operating condition change curve is established according to historical operating condition data in chronological order and is used to represent the curve of the processor chip's operating conditions changing over time. Specifically, it refers to the voltage change curve, the current change curve, or the frequency change curve; the load change curve is established according to historical load data in chronological order and is used to represent the curve of the processor chip's load changing over time.

[0132] In this embodiment, the first operating condition sub-curve is a smaller curve segment obtained by equally dividing the corresponding operating condition change curve of the current preset time period; the first load sub-curve is a smaller curve segment obtained by equally dividing the corresponding load change curve of the current preset time period.

[0133] In this embodiment, the second operating condition sub-curve is a smaller curve segment obtained by equally dividing the corresponding operating condition change curve of the previous preset time period; the second load sub-curve is a smaller curve segment obtained by equally dividing the corresponding load change curve of the previous preset time period.

[0134] In this embodiment, the curve acquisition order refers to the arrangement order of the sub-curves obtained after equally dividing the operating condition change curve or the load change curve of the processor chip on the time axis.

[0135] In this embodiment, a similarity algorithm is set to quantify the similarity degree between curves, generally referring to the dynamic time warping algorithm; the similarity representation coefficient is a value obtained by normalizing the value obtained using the set similarity algorithm and is used to represent the similarity degree between curves. The value range is between 0 and 1. The smaller the similarity representation coefficient, the higher the similarity between the curves; the set similarity threshold is preset, generally 0.25.

[0136] In this embodiment, for example, there is a similarity representation coefficient of 0.35 between the first operating condition sub-curve L1 and the second operating condition sub-curve L2 in the same curve acquisition order, which is greater than the set similarity threshold of 0.25;

[0137] At this time, the first operating condition sub-curve L1 is labeled as the first analysis condition sub-curve, and the second operating condition sub-curve L2 is labeled as the second analysis condition sub-curve.

[0138] In this embodiment, for example, there is a similarity representation coefficient of 0.15 between the first load sub-curve L3 and the second load sub-curve L4 in the same curve acquisition order, which is less than the set similarity threshold of 0.25;

[0139] At this time, the first load sub-curve L3 is not labeled as the first analysis load sub-curve, and the second load sub-curve L4 is not labeled as the second analysis load sub-curve.

[0140] In this embodiment, the condition reference value is expressed as In the formula, c1 represents the condition reference value of the current analysis condition sub-curve; h avg represents the average working condition of the current analysis condition sub-curve; h max represents the maximum working condition of the current analysis condition sub-curve; h min represents the minimum working condition of the current analysis condition sub-curve; the condition difference value is obtained by subtracting the condition reference value of the corresponding second analysis condition sub-curve in the same curve acquisition order from the condition reference value of the first analysis condition sub-curve.

[0141] In this embodiment, the load reference value is expressed as In the formula, d1 represents the condition reference value of the current analysis load sub-curve; k avg represents the average working condition of the current analysis load sub-curve; k max represents the maximum working condition of the current analysis load sub-curve; k min represents the minimum working condition of the current analysis load sub-curve; the load difference value is obtained by subtracting the condition reference value of the corresponding second analysis load sub-curve in the same curve acquisition order from the condition reference value of the first analysis load sub-curve.

[0142] In this embodiment, the formula for the dynamic adjustment coefficient is as follows:

[0143]

[0144] In the formula, s represents the dynamic adjustment coefficient; f1 represents the temperature change reference coefficient; γ1 represents the influence weight of the temperature change situation on the calculation of the dynamic adjustment coefficient, and its value range is (0, 1); γ2 represents the influence weight of the working condition change situation on the calculation of the dynamic adjustment coefficient, and its value range is (0, 1); g j represents the jth condition difference value of the current working condition, where j = 1, 2,..., m; m represents the total number of acquired condition difference values of the current working condition; v j represents the similarity representation coefficient of the corresponding first analysis condition sub-curve and second analysis condition sub-curve of the jth condition difference value of the current working condition; v max represents the maximum value among the similarity representation coefficients of the corresponding first analysis condition sub-curve and second analysis condition sub-curve of all condition difference values of the current working condition in the same curve acquisition order; Δz jThe time interval from the curve start point of the corresponding first analysis condition sub - curve or second analysis condition sub - curve, representing the j - th condition difference value for the current working conditions, to the current moment; γ3 represents the influence weight of the load change situation on calculating the dynamic adjustment coefficient, and its value range is (0, 1); γ1 + γ2 + γ3 = 1; wr represents the r - th load difference value, where r = 1, 2, …, q; q represents the total number of obtained load difference values; a r Represents the similarity representation coefficient of the corresponding first analysis load sub - curve and second analysis load sub - curve for the r - th condition difference value; a max Represents the maximum value among the similarity representation coefficients of the first analysis load sub - curve and second analysis load sub - curve for the same curve acquisition order corresponding to all load difference values; Δo r The time interval from the curve start point of the corresponding first analysis load sub - curve or second analysis load sub - curve for the r - th load difference value to the current moment; e represents a constant with a value of 2.7.

[0145] In this embodiment, the weights assigned to the temperature change situation, working condition change situation, and load change situation, namely γ1, γ2, and γ3, are obtained by solving the matrix constructed through pairwise comparison and relative importance scoring using the analytic hierarchy process.

[0146] In this embodiment, for example, there is a set dynamic power consumption threshold u0, and the set dynamic power consumption threshold u0 is adjusted using the dynamic adjustment coefficient s1 to obtain In the formula, u1 represents the adjusted set dynamic power consumption threshold u0; e represents a constant with a value of 2.7.

[0147] The beneficial effects of the above - mentioned technical solution are as follows: By deeply analyzing the historical working temperature, working conditions, and load data of the processor chip obtained regularly, the temperature change reference coefficient, condition difference value, and load difference value are obtained; then, based on the obtained temperature change reference coefficient, condition difference value, and load difference value, the intelligent adjustment of the set dynamic power consumption threshold is realized, which can provide an effective basis for accurately obtaining the power consumption performance coefficient, improve the accuracy of power consumption performance evaluation, and further provide strong support for subsequent intelligent management and control to ensure the stable operation of the processor chip in a complex and changeable working environment.

[0148] The working principle of the above technical solution is as follows: First, collect the historical data of the processor chip, including temperature, working conditions, and load. Then, analyze the collected historical working temperature data to obtain the temperature reference value and the temperature change reference coefficient, which are used to characterize the temperature change. Next, equally divide the working condition and load change curves established using the historical working condition data and historical load data, and compare and analyze the similarity representation coefficients of the sub-curves. Determine the condition difference value and the load difference value through the result of the difference analysis. Finally, combine the condition difference value and the load difference value with the temperature change reference coefficient to calculate the dynamic adjustment coefficient, and adjust the set dynamic power consumption threshold.

[0149] In summary, by collecting the static test data and dynamic test data of the processor chip, determining the real-time test data of the processor chip, processing the real-time test data of the processor chip to determine the characteristic test data of the processor chip, constructing a power consumption test prediction model for the processor chip according to the power consumption test requirements of the processor chip, analyzing the characteristic test data of the processor chip based on the power consumption test prediction model of the processor chip, predicting the power consumption of the processor chip, determining the power consumption prediction result of the processor chip, and displaying the power consumption test situation of the processor chip in a visual form, and effectively controlling the processor chip, the power consumption characteristics of the processor chip can be comprehensively evaluated, and the processor chip can be effectively controlled, which can improve the power consumption test effect of the processor chip.

[0150] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device.

[0151] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for testing the power consumption of a processor chip, characterized in that, Including: Collecting real-time test data of the processor chip and processing it to determine the characteristic test data of the processor chip; Training the power consumption test prediction model of the processor chip, analyzing the characteristic test data of the processor chip, predicting the power consumption of the processor chip, and determining the power consumption prediction result of the processor chip; Displaying the power consumption test situation of the processor chip in a visual form and controlling the processor chip; Among them, a dynamic adjustment coefficient is used to adjust the set dynamic power threshold.

2. The processor chip power consumption testing method according to claim 1, characterized in that Collecting real-time test data of the processor chip, including: Real-time monitoring and collecting the current and voltage of the processor chip in the idle state to obtain the static test data of the processor chip; Real-time monitoring and collecting the current and voltage of the processor chip under different loads to obtain the dynamic test data of the processor chip; Among them, according to the static test data and dynamic test data of the processor chip, the real-time test data of the processor chip is determined.

3. The processor chip power consumption testing method according to claim 1, wherein Processing the real-time test data of the processor chip, including: Cleaning the real-time test data of the processor chip, checking the integrity of the real-time test data of the processor chip, and identifying duplicate values, missing values, and abnormal values in the real-time test data of the processor chip; For duplicate values in the real-time test data of the processor chip, the duplicate values are removed and only unique data records are retained; For missing values in the real-time test data of the processor chip that are tested to be useless for the power consumption test of the processor chip, the missing values are removed; for missing values in the real-time test data of the processor chip that are tested to be useful for the power consumption test of the processor chip, the missing values are filled; For abnormal values in the real-time test data of the processor chip that are tested to be useless for the power consumption test of the processor chip, the abnormal values are removed; for abnormal values in the real-time test data of the processor chip that are tested to be useful for the power consumption test of the processor chip, the abnormal values are replaced or corrected; Based on a filtering algorithm, filtering the cleaned real-time test data of the processor chip to remove noise in the real-time test data of the processor chip.

4. The processor chip power consumption testing method according to claim 3, wherein Processing the real-time test data of the processor chip also includes: Normalizing the real-time test data of the processor chip to reduce the dimensional difference of the real-time test data of the processor chip and determining the standardized real-time test data of the processor chip; Extracting features from the real-time test data of the processor chip, extracting features related to the power consumption test of the processor chip from the real-time test data of the processor chip, and determining the characteristic test data of the processor chip.

5. The processor chip power consumption testing method according to claim 1, wherein Training the power consumption test prediction model of the processor chip, including: Collecting historical test data of the processor chip, including historical current, voltage, and power consumption; Dividing the collected historical test data of the processor chip to determine the training set and the test set; Based on deep learning technology, using the training set to train the deep learning model, enabling the deep learning model to autonomously learn the power consumption test prediction behavior of the processor chip and predicting the power consumption of the processor chip to determine the power consumption test prediction model of the processor chip based on deep learning; Perform performance testing on the power consumption test prediction model of the deep learning-based processor chip based on the test set, and evaluate whether the power consumption test prediction model of the deep learning-based processor chip can achieve the expected effect; When the power consumption test prediction model of the deep learning-based processor chip cannot achieve the expected effect, adjust the parameters of the power consumption test prediction model of the deep learning-based processor chip, and continuously optimize the power consumption test prediction model of the deep learning-based processor chip until a power consumption test prediction model that can achieve the expected effect is determined.

6. The processor chip power consumption testing method according to claim 5, wherein Analyze the processor chip feature test data, including: Obtain the power consumption test prediction model of the processor chip, and deploy the power consumption test prediction model of the processor chip in the actual power consumption test prediction environment of the processor chip; Input the processor chip feature test data into the power consumption test prediction model of the processor chip, analyze the processor chip feature test data according to the power consumption test prediction model of the processor chip, and predict the power consumption of the processor chip to determine the power consumption prediction result of the processor chip.

7. The processor chip power consumption testing method according to claim 1, wherein Display the processor chip power consumption test situation in a visual form, and control the processor chip, including: Based on the processor chip power consumption prediction result and combined with the processor chip feature test data, form a processor chip power consumption test report, and display the processor chip power consumption test report to the management personnel in a visual form; The management personnel evaluate the power consumption performance of the processor chip according to the processor chip power consumption test report, and obtain the power consumption performance coefficient by combining the set dynamic power consumption threshold, and output the power consumption performance coefficient as the power consumption performance evaluation result; Perform intelligent control on the processor chip according to the power consumption performance evaluation result. Among them, dynamically adjust the voltage and frequency of the processor chip to reduce power consumption, and set a power consumption upper limit to make the processor chip operate within the budget. In a multi-core processor, allocate tasks to the core with the highest energy efficiency to achieve load balancing.

8. The processor chip power consumption testing method according to claim 7, wherein, It also includes: Regularly obtain the historical working temperature data, historical working condition data, and historical load data of the processor chip within a preset time period; Based on the historical working temperature data, determine the historical working temperature extreme value and historical working temperature average value of the processor chip, and calculate the temperature reference value; Perform difference analysis on the first temperature reference value of the processor chip in the current preset time period and the second temperature reference value of the previous preset time period to obtain the temperature change reference coefficient; Use the historical working condition data and historical load data to establish the working condition change curve and load change curve of the processor chip within the current preset time period respectively in chronological order; After dividing the working condition change curve and load change curve of the processor chip within the current preset time period in equal proportion, obtain the first working condition sub-curve and the first load sub-curve respectively, and mark the curve acquisition order for the first working condition sub-curve and the first load sub-curve; The sub-curves obtained by equally dividing the working condition change curve and the load change curve of the processor chip in the previous preset time period are respectively labeled as the second working condition sub-curve and the second load sub-curve, and the curve acquisition order is marked for the second working condition sub-curve and the second load sub-curve; Using the set similarity algorithm, perform similarity analysis on the first working condition sub-curve and the second working condition sub-curve with the same curve acquisition order, and mark the target first working condition sub-curve and the target second working condition sub-curve with a similarity representation coefficient greater than the set similarity threshold as the first analysis condition sub-curve and the second analysis condition sub-curve respectively; Respectively obtain the condition reference values of the first analysis condition sub-curve and the second analysis condition sub-curve with the same curve acquisition order, and obtain the condition difference value through difference comparison; Perform similarity analysis on the first load sub-curve and the second load sub-curve with the same curve acquisition order, and mark the first load sub-curve and the second load sub-curve with a similarity representation coefficient greater than the set similarity threshold as the first analysis load sub-curve and the second analysis load sub-curve respectively; Respectively obtain the load reference values of the target first analysis load sub-curve and the target second analysis load sub-curve with the same curve acquisition order, and obtain the load difference value through difference comparison; Combine the condition difference value and the similarity representation coefficient of the first analysis condition sub-curve and the second analysis condition sub-curve with the same curve acquisition order, and the load difference value and the similarity representation coefficient of the first analysis load sub-curve and the second analysis load sub-curve with the temperature change reference coefficient to calculate the dynamic adjustment coefficient; Use the dynamic adjustment coefficient to adjust the set dynamic power consumption threshold.

9. A processor chip power consumption testing system for implementing the processor chip power consumption testing method according to any one of claims 1-8, characterized in that, Includes: A data acquisition module configured to acquire real-time test data of the processor chip; A data processing module configured to process the real-time test data of the acquired processor chip to determine the characteristic test data of the processor chip; A model construction module configured to construct a processor chip power consumption test prediction model according to the processor chip power consumption test requirements; A power consumption prediction module configured to analyze the characteristic test data of the processor chip according to the processor chip power consumption test prediction model and predict the power consumption of the processor chip; A display control module configured to visually display the processor chip power consumption test situation and control the processor chip according to the displayed processor chip power consumption test situation.

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