An integrated circuit chip testing system based on AI algorithm

Abstract

The present invention discloses an integrated circuit chip testing system based on an AI algorithm, which relates to the field of integrated circuit chip testing technology and includes a chip testing platform. The chip testing platform is communicatively connected to the following modules, including: a data acquisition module for collecting historical test data from existing integrated circuit chip testing equipment, preprocessing the data, and integrating the data to obtain a chip test data set; a model training and optimization module for analyzing the chip test data set, learning the relationship between chip performance and test vectors, and training a test vector AI optimization model. The present invention automatically generates optimized test vectors by analyzing historical test data, avoiding the redundant item-by-item test process in traditional testing, accurately locating key test nodes through the test vector AI optimization model, reducing unnecessary test steps, thereby significantly shortening test time and improving test efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit chip testing, and in particular to an integrated circuit chip testing system based on an AI algorithm. Background Art

[0002] As semiconductor manufacturing processes continue to develop towards smaller line widths and higher integration, the number of transistors inside chips is growing exponentially, and the structure is becoming increasingly complex. This places higher demands on chip testing. In addition, the chip market is highly competitive, and products are rapidly updated. In order to gain an advantage in the market, it is necessary to quickly launch high-quality, high-performance chip products. The test system is an important link in the chip production process. Its test efficiency and accuracy directly affect the chip's time to market and product quality. An efficient test system can shorten the chip production cycle, reduce production costs, and improve the company's market competitiveness.

[0003] In the prior art, integrated circuit chip testing usually uses fixed test vectors and test processes to test all chips one by one. For chips produced on a large scale, the test time is long, which will lead to extended production cycles and increased costs. Therefore, how to use machine learning algorithms to analyze historical test data, automatically generate optimized test vectors, reduce redundant tests, and improve test efficiency is the problem to be solved by the present invention. To this end, an integrated circuit chip testing system based on AI algorithm is proposed. Summary of the Invention

[0004] The present invention aims to provide an integrated circuit chip testing system based on AI algorithm to solve the problems raised in the above background technology.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] An integrated circuit chip testing system based on an AI algorithm includes a chip testing platform, wherein the chip testing platform is communicatively connected to the following modules:

[0007] The data acquisition module is used to collect historical test data from existing integrated circuit chip testing equipment, pre-process it, and integrate it to obtain a chip test data set;

[0008] Model training and optimization module, used to analyze chip test data sets, learn the relationship between chip performance and test vectors, and train the test vector AI optimization model;

[0009] The test vector generation module is used to automatically generate initial test vectors based on the trained test vector AI optimization model and the current chip test requirements. The test vectors are customized according to the chip's test characteristics to avoid repeated testing and ensure comprehensive testing.

[0010] The test vector evaluation module is used to evaluate the generated test vectors, analyze their effects in chip testing, and optimize the initial test vectors;

[0011] The test execution feedback module is used to apply the optimized test vectors to test the integrated circuit chip, and further optimize the test vector AI optimization model and test vectors based on the test execution results.

[0012] A further improvement of the technical solution of the present invention is that the data acquisition module specifically includes:

[0013] Establish a connection with existing integrated circuit chip test equipment through a standard communication interface (TCP / IP, GPIB, USB, etc.), automatically scan the historical test data files stored in the equipment, and encapsulate the collected raw data of the historical test data files in a unified format and temporarily store them in a temporary buffer;

[0014] Preprocess the raw data in the buffer to identify and remove missing values, outliers, and duplicate records. Then, convert the preprocessed data into a unified JSON format to generate an intermediate data set to ensure data standardization and consistency.

[0015] The intermediate data sets are classified and integrated according to the dimensions of integrated circuit chip models and test batches, and a data association index is established. A distributed storage architecture is used to partition and store the integrated data according to feature dimensions, and the data source, processing process and version information are recorded to form a chip test data set containing a complete test context.

[0016] A further improvement of the technical solution of the present invention is that: the model training optimization module includes a feature analysis unit and a model training optimization unit;

[0017] The feature analysis unit is used to analyze historical test data in the chip test data set, extract test features related to test vector optimization, and obtain a test feature sequence table;

[0018] The model training optimization unit is used to combine the test feature sequence table and historical test data, use the support vector machine model as the basic architecture, learn the relationship between chip performance and test vectors, and train the test vector AI optimization model.

[0019] A further improvement of the technical solution of the present invention is that the feature analysis unit specifically includes:

[0020] Perform structured parsing of chip test datasets to identify potential feature domains contained in the data. By analyzing the semantic labels, data types, and associations of data fields, we can classify core feature categories directly related to test vector optimization, including electrical performance parameters, functional test results, process parameters, and test environment variables. Combined with the domain knowledge base of integrated circuit chip testing, we establish a mapping relationship between features and test vector optimization goals, clarify the potential role of each feature in test efficiency, coverage, and cost optimization, and form a list of features to be extracted.

[0021] Based on the list of features to be extracted, specific test feature categories are extracted from historical test data, including test vector coverage, fault detection rate, test time, test vector length, fault coverage improvement efficiency and test redundancy. Multi-dimensional correlation analysis is performed to quantify the correlation strength between test features and test vector effectiveness, and generate a structured test feature sequence list containing feature names and definitions.

[0022] A further improvement of the technical solution of the present invention is that the model training optimization unit specifically includes:

[0023] Integrate the test feature sequence list with historical test data to ensure data consistency and integrity. Use the feature name and the unique identifier of the data record (chip batch number) to match the extracted test features with the corresponding records in the historical data to form a unified training data set. The training data set is divided into training set, validation set, and test set.

[0024] Using support vector machines (SVMs) as the core architecture, we built an AI optimization model for test vectors. We used radial basis functions (RBFs) to process nonlinear feature relationships, set the search range for the regularization parameter C and the candidate value for the kernel function parameter γ, fed the training set into the SVM model, and used 5-fold cross-validation to evaluate the model's generalization ability. We calculated the average accuracy and standard deviation, then iteratively adjusted C and γ on the validation set using a grid search. We selected the parameter combination that minimized the cross-validation error, outputted the trained SVM model, and recorded the optimal hyperparameters and performance metrics during the training process.

[0025] Execute model prediction on the test set, calculate the deviation between the prediction results of the support vector machine model and the actual label, generate an evaluation report, analyze the contribution of each test feature to the model output based on the SHAP value, identify key features and redundant features, adjust the model architecture according to the evaluation results, retrain the model until the performance converges (the accuracy of the test set is improved to 94.1%), and finally generate a test vector AI optimization model with high generalization ability, and simultaneously output the model version number, training log and deployment interface documentation.

[0026] A further improvement of the technical solution of the present invention is that the test vector generation module specifically includes:

[0027] Receive the test requirement document of the current chip, including the chip model, functional characteristics, performance indicators, and specific test objectives, parse the test requirement document of the current chip, extract key test objectives and constraints, and extract the test characteristics of the current chip from the chip design document, process parameter library, and historical test data based on the test feature sequence table. Map the test requirements and the test characteristics of the chip into a structured input vector to ensure that the input data is compatible with the trained test vector AI optimization model;

[0028] The constructed input vector is input into the trained test vector AI optimization model to generate an initial test vector set. Based on the feature importance ranking of the model output (SHAP value analysis results), the initial vector is customized and optimized, including coverage enhancement, redundancy elimination and resource balancing. Then, a customized test vector set is output, which includes vector sequence, target coverage nodes and expected resource consumption, to form a preliminary test plan.

[0029] A further improvement of the technical solution of the present invention is that the test vector evaluation module specifically includes:

[0030] Deploy the test vector set to the simulation platform (Synopsys VCS), execute the full-process test, and collect indicator data, including logic coverage, fault detection rate, total test time, and resource usage. Compare the vector similarity calculation (cosine similarity) with the execution path to identify redundant test patterns with repeated stimulation or redundant timing constraints, quantify the redundancy ratio, and then compare the collected indicators with the constraints in the test requirements document. Generate a compliance report, mark non-compliant items, and output an evaluation results list to clarify the performance shortcomings of the current test vectors and deviations from requirements.

[0031] Based on the evaluation results, we identify key problem modules and the root causes of redundancy, analyze the performance of test vectors in reducing test time, improving test coverage, and lowering test costs, and develop optimization strategies for deficiencies, including coverage improvement, time compression, resource optimization, and dynamic vector adjustment. Based on the optimization strategies, we generate optimized test vector sets, update vector sequences, delete redundant items, and reallocate resources. We then generate iterative version vector files, output optimization strategy documents and the adjusted test vector set, and clearly define the optimization direction and expected improvement goals.

[0032] The adjusted test vector set is put into the simulation environment again, and the indicator data of logic coverage, fault detection rate, total test time and resource occupancy are re-collected. The performance changes before and after optimization are compared, and it is checked whether the optimization introduces new problems. If so, the optimization strategy is adjusted retroactively. The convergence condition is set as a performance improvement of <1% for two consecutive iterations and no new problems. If it is met, the optimization is terminated, otherwise the iteration is continued until the test vector achieves the optimal balance in time, coverage and cost. The final optimized test vector set, evaluation report and deployment guide are then output to ensure that the test vector is efficient, accurate and meets the constraints in actual applications.

[0033] A further improvement of the technical solution of the present invention is that: the test execution feedback module includes a test execution unit and a feedback update unit;

[0034] The test execution unit is used to apply the optimized test vectors to the actual integrated circuit chip test process, execute the test tasks, and record the test results. The optimized test vectors can improve the test efficiency, shorten the test time, and reduce the test cost.

[0035] The feedback update unit is used to collect feedback information based on the results of the test execution, and further optimize the test vector AI optimization model and test vectors to adapt to changes in chip production processes and new testing requirements.

[0036] A further improvement of the technical solution of the present invention is that the test execution unit specifically includes:

[0037] Configure the parameters of the automated test equipment, including clock frequency, power supply voltage, and signal level, according to the chip test requirements document and deployment guide, ensuring consistency with the test vector generation environment. Load the optimized test vector set (iterative version vector file) into the test equipment, parse the vector sequence, target coverage nodes, and resource allocation parameters, generate an executable test instruction stream, and verify the integrity of the vector loading through the equipment self-test function. Check the status of test resources to ensure there are no hardware failures.

[0038] The test task is launched according to the optimized vector execution sequence. The test progress is monitored in real time, the execution time and resource usage of each vector are recorded, the chip output response signal is captured, and a bit-by-bit comparison is performed with the expected result (the target value generated based on the test vector). The pass / fail test results and fault location information are recorded. If a test interruption is detected, a rollback mechanism is triggered, the current test status is saved, and the failed vector is restarted to ensure test continuity. The timestamp and error code of the abnormal event are also recorded simultaneously.

[0039] Compare the test data before and after optimization, calculate the test time compression rate and resource utilization improvement, verify whether the optimization effect meets the expected goals, integrate the test results containing the pass rate and fault distribution diagram with the log file containing the execution time and resource consumption into a standardized report, and store it in the database according to the chip batch and test type. Then generate a test efficiency analysis report, mark the test items that do not meet the standards, and feed back to the test vector generation module to drive the next round of optimization iterations, forming a continuous improvement closed loop.

[0040] A further improvement of the technical solution of the present invention is that the feedback update unit specifically includes:

[0041] Collect all types of feedback generated during the test execution process, including test results, fault location information, test time, resource usage, and abnormal event records, and organize and categorize them. At the same time, record new chip features and potential defects discovered during the test, as well as changes in the test environment. Store the feedback information in the database by category and establish field indexes.

[0042] Based on the collected feedback, the test vector AI optimization model is analyzed to determine its adaptability and accuracy in the current test environment. Combined with the test results, the model's shortcomings in predicting the effectiveness of test vectors are identified. Furthermore, the performance of the test vectors in actual tests is analyzed to identify areas for optimization.

[0043] Based on the results of the optimization analysis, the test vector AI optimization model is updated, model parameters are adjusted, or the model architecture is improved to adapt to changes in the chip production process and new testing requirements. At the same time, the test vectors are adjusted according to the optimization strategy to generate a new test vector set. The updated model and vectors are applied to new test tasks, and feedback information is continuously collected. Performance indicators before and after iteration are compared to verify the optimization effect. If the standard is not met, backtracking adjustments are made to form a closed-loop mechanism of "collection-analysis-optimization-verification".

[0044] Due to the adoption of the above technical solution, the present invention has the following technical advancements compared to the prior art:

[0045] The present invention provides an integrated circuit chip testing system based on an AI algorithm. By analyzing historical test data, it automatically generates optimized test vectors, avoiding the redundant item-by-item testing process in traditional testing. The test vector AI optimization model is used to accurately locate key test nodes, reducing unnecessary test steps, thereby significantly shortening test time and improving test efficiency.

[0046] The present invention provides an integrated circuit chip testing system based on an AI algorithm. By optimizing test vectors, the system reduces resource consumption during the testing process, including test time, labor costs, and loss of test equipment. At the same time, by reducing redundant tests, unnecessary consumption of test materials is avoided, thereby further reducing testing costs. Moreover, by being able to learn the relationship between chip performance and test vectors, the system continuously optimizes test vectors, improves the comprehensiveness and accuracy of the test, and can identify and cover potential defects in the chip, reducing the risk of missed tests and false tests, thereby helping to ensure chip quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments described in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0048] Figure 1 It is a schematic diagram of the workflow of the present invention;

[0049] Figure 2 Schematic diagram of the system functional modules of the present invention. DETAILED DESCRIPTION

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0051] Example 1, as Figure 1 、 Figure 2 As shown, the present invention provides an integrated circuit chip testing system based on AI algorithm, including a chip testing platform, which is communicatively connected to the following modules, wherein:

[0052] The data acquisition module is used to collect historical test data from existing integrated circuit chip test equipment, pre-process it, integrate it to obtain a chip test data set, establish a connection with the existing integrated circuit chip test equipment through a standard communication interface (TCP / IP, GPIB, USB, etc.), and automatically scan the historical test data files stored in the equipment, covering the electrical parameters, functional test results, test vector execution status of the integrated circuit chip, as well as the batch and process parameters of the chip. The original data of the collected historical test data files are packaged in a unified format and temporarily stored in a temporary buffer. The original data in the buffer is pre-processed to identify and eliminate missing values, outliers and duplicate records. Through data standardization, the parameter units and precision of different device outputs are unified to eliminate dimensional differences. For unstructured data, natural language processing technology is used to extract key features and convert them into structured fields. Logically contradictory data is corrected or marked. The pre-processed data is then converted into a unified JSON format to generate an intermediate data set to ensure data standardization and consistency. The intermediate data set is classified and integrated according to the dimensions of integrated circuit chip model and test batch, and a data association index is established. A distributed storage architecture is used to partition and store the integrated data according to feature dimensions, recording data sources, processing processes, and version information to form a chip test data set that contains complete test context.

[0053] The model training and optimization module is used to analyze chip test data sets, learn the relationship between chip performance and test vectors, and train the test vector AI optimization model. The model training and optimization module includes a feature analysis unit and a model training and optimization unit.

[0054] Among them, the feature analysis unit is used to analyze the historical test data in the chip test data set, extract the test features related to the test vector optimization, obtain the test feature sequence list, perform structured analysis on the chip test data set, identify the potential feature domains contained in the data, and divide the core feature categories directly related to the test vector optimization by parsing the semantic labels, data types and associations of the data fields, including electrical performance parameters, functional test results, process parameters and test environment variables. Combined with the domain knowledge base of integrated circuit chip testing, a mapping relationship between features and test vector optimization goals is established, and the potential role of each feature in test efficiency, coverage and cost optimization is clarified. A list of features to be extracted is formed. Based on the list of features to be extracted, specific test feature categories are extracted from the historical test data, including test vector coverage, fault detection rate, test time, test vector length, fault coverage improvement efficiency and test redundancy, and multi-dimensional correlation analysis is performed to quantify the test The strength of the correlation between the feature and the effectiveness of the test vector is used to generate a structured test feature sequence list containing the feature name and definition. Among them, the test vector coverage is the ratio of the number of chip logic nodes actually covered by the test vector to the total number of logic nodes. A high coverage rate indicates that the test vector can more comprehensively detect potential defects in the chip. The fault detection rate is the ratio of the number of faults detected by the test vector to the total number of faults actually existing in the chip, which directly reflects the sensitivity of the test vector to defects. The test time is the time required for a single test vector to execute on the chip. Shortening the test time can reduce the test cost. The test vector length is the number of binary bits contained in the test vector. The vector length directly affects the test data storage and transmission cost. The fault coverage improvement efficiency is the percentage of fault coverage improved by each increase in the test vector length by 1 unit, which quantifies the relationship between the test vector length and fault coverage. The test redundancy is the proportion of repeated detection of the same fault in the test vector. High redundancy indicates that the test vector is inefficient.

[0055] The model training optimization unit is used to combine the test feature sequence table and historical test data, use the support vector machine model as the basic architecture, learn the relationship between chip performance and test vectors, train the test vector AI optimization model, integrate the test feature sequence table with the historical test data to ensure data consistency and integrity, and match the extracted test features with the corresponding records in the historical data through the feature name and the unique identifier of the data record (chip batch number) to form a unified training data set, divide the training data set into training set, verification set and test set, build the test vector AI optimization model with support vector machine (SVM) as the core architecture, select radial basis function (RBF) to process nonlinear feature relationships, set the search range of regularization parameter C and the candidate value of kernel function parameter γ, and input the training set into the training set. For the support vector machine model, we use 5-fold cross-validation to evaluate the generalization ability of the model, calculate the average accuracy and standard deviation, iteratively adjust C and γ on the validation set based on grid search, select the parameter combination that minimizes the cross-validation error, output the trained support vector machine model, record the optimal hyperparameters and performance indicators during training, perform model prediction on the test set, calculate the deviation between the support vector machine model's prediction results and the actual labels, generate an evaluation report, analyze the contribution of each test feature to the model output based on the SHAP value, identify key features and redundant features, adjust the model architecture based on the evaluation results, and retrain the model until performance converges (test set accuracy increases to 94.1%). Finally, we generate a highly generalizable test vector AI optimization model and simultaneously output the model version number, training log, and deployment interface documentation.

[0056] The test vector generation module is used to automatically generate initial test vectors based on the trained test vector AI optimization model and the current chip test requirements. The test vectors are customized according to the chip's test characteristics to avoid repeated testing and ensure comprehensive testing.

[0057] The test vector evaluation module is used to evaluate the generated test vectors, analyze their effects in chip testing, and optimize the initial test vectors. The optimization goals are to reduce test time, improve test coverage, and reduce test costs. Through continuous iteration and adjustment, the test vectors are optimized while meeting the test requirements.

[0058] The test execution feedback module is used to apply the optimized test vectors to test the integrated circuit chip, and further optimize the test vector AI optimization model and test vectors based on the test execution results.

[0059] Example 2, as Figure 1 、 Figure 2 As shown, based on Example 1, the present invention provides a technical solution: preferably, the test vector generation module specifically includes:

[0060] Receive the test requirement document of the current chip, including chip model, functional characteristics, performance indicators and specific test targets, parse the test requirement document of the current chip, extract key test targets (functional coverage threshold, defect detection priority) and constraints (test time limit, resource occupancy limit), extract the test features of the current chip from the chip design documents, process parameter library and historical test data based on the test feature sequence table, map the test requirements and the test features of the chip into a structured input vector, ensure that the input data is compatible with the trained test vector AI optimization model, input the constructed input vector into the trained test vector AI optimization model, and generate the initial The test vector set is customized and optimized for the initial vectors based on the feature importance ranking output by the model (SHAP value analysis results), including coverage enhancement, redundancy elimination, and resource balancing. Coverage enhancement prioritizes the allocation of test resources to high-fault-sensitivity modules to improve critical path coverage. Redundancy elimination uses a feature matching algorithm to identify and eliminate test patterns that are repeated with historical test vectors to avoid redundant detection. Resource balancing dynamically adjusts the vector length and complexity based on resource constraint parameters to ensure a balance between test efficiency and cost. The result is a customized test vector set, including the vector sequence, target coverage nodes, and expected resource consumption, to form a preliminary test plan.

[0061] The test vector evaluation module specifically includes:

[0062] Deploy the test vector set to the simulation platform (Synopsys VCS), perform full-process testing and collect indicator data, including logic coverage, fault detection rate, total test time and resource usage, and compare with the execution path through vector similarity calculation (cosine similarity) to identify redundant test modes with repeated stimulation or redundant timing constraints, quantify the redundancy ratio, and then compare the collected indicators with the constraints in the test requirement document, generate a compliance report, mark non-compliant items, output a list of evaluation results, clarify the performance shortcomings and requirement deviations of the current test vectors, locate key problem modules and redundancy roots based on the evaluation results, analyze the performance of test vectors in reducing test time, improving test coverage and reducing test costs, and formulate optimization strategies for deficiencies, including coverage improvement, time compression, resource optimization and dynamic vector adjustment. Among them, for uncovered nodes, add high-priority test items or adjust the vector stimulation intensity, shorten the length of redundant vectors, merge low-priority test sequences or optimize the vector execution sequence Sequence, adjust resource allocation parameters or switch to low resource consumption test mode, generate optimized test vector set according to optimization strategy, update vector sequence, delete redundant items and reallocate resources, generate iterative version vector file, and then output optimization strategy document and adjusted test vector set, clarify optimization direction and expected improvement goals, put the adjusted test vector set into simulation environment again, re-collect indicator data of logic coverage, fault detection rate, total test time and resource occupancy, compare performance changes before and after optimization, check whether optimization introduces new problems, if so, backtrack and adjust optimization strategy, set performance improvement of two consecutive iterations <1% and no new problems as convergence conditions, terminate optimization if met, otherwise continue iteration until test vectors achieve optimal balance in time, coverage and cost, and then output final optimized test vector set, evaluation report and deployment guide to ensure that test vectors are efficient, accurate and meet constraints in actual applications;

[0063] The test execution feedback module includes a test execution unit and a feedback update unit;

[0064] Among them, the test execution unit is used to apply the optimized test vectors to the actual integrated circuit chip testing process, execute the test tasks, and record the test results. Through the optimized test vectors, the test efficiency is improved, the test time is shortened, and the test cost is reduced. According to the chip test requirement document and deployment guide, the parameters of the automated test equipment are configured, including clock frequency, power supply voltage and signal level, to ensure consistency with the test vector generation environment, and the optimized test vector set (iterative version vector file) is loaded into the test equipment. The vector sequence, target coverage nodes and resource allocation parameters are parsed to generate an executable test instruction stream, and the vector loading integrity is verified through the device self-test function. The test resource status is checked to ensure that there is no hardware failure. The test task is started in the optimized vector execution order, the test progress is monitored in real time, and the execution time and Resource usage: Capture chip output response signals and compare them bit by bit with expected results (target values ​​generated based on test vectors). Record pass / fail test results and fault location information. If a test interruption is detected, trigger a rollback mechanism, save the current test state, and restart the failed vector to ensure test continuity. Synchronously record the timestamps and error codes of abnormal events, compare test data before and after optimization, calculate the test time compression rate and resource utilization improvement, and verify whether the optimization effect meets the expected goals. Combine test results containing pass rates and fault distribution maps with log files containing execution time and resource consumption into a standardized report, categorize and store them in a database by chip batch and test type, and then generate a test efficiency analysis report, mark test items that do not meet the standards, and feedback to the test vector generation module to drive the next round of optimization iterations, forming a continuous improvement closed loop.

[0065] The feedback update unit is used to collect feedback information based on the results of the test execution, further optimize the test vector AI optimization model and test vectors to adapt to changes in chip production processes and new test requirements, collect various types of feedback information generated during the test execution, including test results, fault location information, test time, resource usage, and abnormal event records, and organize and classify them. At the same time, it records new chip features and potential defects found during the test process, as well as changes in the test environment, stores the feedback information in the database by category, establishes a field index, and analyzes the test vector AI optimization model based on the collected feedback information. The adaptability and accuracy of the analysis model in the current test environment are analyzed, and combined with the test results, identification is carried out. The model's shortcomings in predicting the effectiveness of test vectors. At the same time, analyze the performance of test vectors in actual tests, find out the direction that needs to be optimized, and update the test vector AI optimization model based on the results of the optimization analysis, adjust the model parameters or improve the model architecture to adapt to changes in chip production processes and new testing requirements. At the same time, adjust the test vectors according to the optimization strategy, generate a new set of test vectors, apply the updated model and vectors to new test tasks, continuously collect feedback information, compare performance indicators before and after iteration, verify the optimization effect, and retroactively adjust if it does not meet the standards, forming a closed-loop mechanism of "collection-analysis-optimization-verification" to ensure that test vectors and models continue to adapt to changes in chip production processes and upgraded testing requirements.

[0066] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. An integrated circuit chip testing system based on AI algorithms, including a chip testing platform, characterized by: The chip testing platform is communicatively connected to the following modules: The data acquisition module is used to collect historical test data from existing integrated circuit chip testing equipment, pre-process it, and integrate it to obtain a chip test data set; Model training and optimization module, used to analyze chip test data sets, learn the relationship between chip performance and test vectors, and train the test vector AI optimization model; The test vector generation module is used to automatically generate initial test vectors based on the trained test vector AI optimization model and the current chip test requirements; The test vector evaluation module is used to evaluate the generated test vectors, analyze their effects in chip testing, and optimize the initial test vectors; A test execution feedback module is used to apply the optimized test vectors to test the integrated circuit chip and further optimize the test vector AI optimization model and test vectors based on the test execution results; The model training optimization module includes a feature analysis unit and a model training optimization unit; The model training optimization unit is used to combine the test feature sequence table and historical test data, use the support vector machine model as the basic architecture, learn the relationship between chip performance and test vectors, and train the test vector AI optimization model; The feature analysis unit specifically includes: Perform structured parsing of chip test datasets to identify potential feature domains contained in the data. By analyzing the semantic labels, data types, and associations of data fields, we can classify core feature categories directly related to test vector optimization, including electrical performance parameters, functional test results, process parameters, and test environment variables. Combined with the domain knowledge base of integrated circuit chip testing, we establish a mapping relationship between features and test vector optimization goals, clarify the potential role of each feature in test efficiency, coverage, and cost optimization, and form a list of features to be extracted. Based on the list of features to be extracted, specific test feature categories are extracted from historical test data, including test vector coverage, fault detection rate, test time, test vector length, fault coverage improvement efficiency and test redundancy. Multi-dimensional correlation analysis is performed to quantify the correlation strength between test features and test vector effectiveness, and generate a structured test feature sequence list containing feature names and definitions.

2. The integrated circuit chip testing system based on AI algorithm according to claim 1, characterized in that: The data acquisition module specifically includes: Establish a connection with the existing integrated circuit chip test equipment through a standard communication interface, automatically scan the historical test data files stored in the equipment, and encapsulate the collected original data of the historical test data files in a unified format and temporarily store them in a temporary buffer; Preprocess the raw data in the buffer, identify and remove missing values, outliers, and duplicate records, and then convert the preprocessed data into a unified JSON format to generate an intermediate data set; The intermediate data sets are classified and integrated according to the dimensions of integrated circuit chip models and test batches, and a data association index is established. A distributed storage architecture is used to partition and store the integrated data according to feature dimensions, and the data source, processing process and version information are recorded to form a chip test data set containing a complete test context.

3. The integrated circuit chip testing system based on AI algorithm according to claim 1, characterized in that: The model training optimization unit specifically includes: Integrate the test feature sequence list with the historical test data, and match the extracted test features with the corresponding records in the historical data using the feature name and the unique identifier of the data record to form a unified training data set. The training data set is divided into a training set, a validation set, and a test set. With the support vector machine as the core architecture, a test vector AI optimization model was constructed. The radial basis function was used to process nonlinear feature relationships. The search range of the regularization parameter C and the candidate value of the kernel function parameter γ were set. The training set was input into the support vector machine model. 5-fold cross-validation was used to evaluate the model's generalization ability. C and γ were iteratively adjusted on the validation set based on a grid search. The parameter combination that minimized the cross-validation error was selected. The trained support vector machine model was output, and the optimal hyperparameters and performance indicators during the training process were recorded. Execute model prediction on the test set, calculate the deviation between the prediction results of the support vector machine model and the actual label, generate an evaluation report, analyze the contribution of each test feature to the model output based on the SHAP value, identify key features and redundant features, adjust the model architecture according to the evaluation results, retrain the model until the performance converges, and finally generate a test vector AI optimization model with high generalization ability, and synchronously output the model version number, training log and deployment interface document.

4. The integrated circuit chip testing system based on AI algorithm according to claim 1, characterized in that: The test vector generation module specifically includes: Receive the test requirement document of the current chip, including the chip model, functional characteristics, performance indicators and specific test objectives, parse the test requirement document of the current chip, extract key test objectives and constraints, extract the test characteristics of the current chip from the chip design document, process parameter library and historical test data based on the test feature sequence table, and map the test requirements and chip test characteristics into a structured input vector; The constructed input vector is input into the trained test vector AI optimization model to generate an initial test vector set. Based on the feature importance ranking of the model output, the initial vector is customized and optimized, including coverage enhancement, redundancy elimination and resource balancing. Then, a customized test vector set is output, which includes vector sequence, target coverage nodes and expected resource consumption, to form a preliminary test plan.

5. The integrated circuit chip testing system based on AI algorithm according to claim 4, characterized in that: The test vector evaluation module specifically includes: Deploy the test vector set to the simulation platform, execute the full-process test, and collect indicator data, including logic coverage, fault detection rate, total test time, and resource usage. By calculating vector similarity and comparing execution paths, identify redundant test patterns with repeated stimulation or redundant timing constraints, quantify the redundancy ratio, and then compare the collected indicators with the constraints in the test requirements document. Generate a compliance report, mark non-compliant items, and output an evaluation results list to clarify the performance shortcomings of the current test vectors and deviations from requirements. Based on the evaluation results, we identify key problem modules and the root causes of redundancy, analyze the performance of test vectors in reducing test time, improving test coverage, and lowering test costs, and develop optimization strategies for deficiencies, including coverage improvement, time compression, resource optimization, and dynamic vector adjustment. Based on the optimization strategies, we generate optimized test vector sets, update vector sequences, delete redundant items, and reallocate resources. We then generate iterative version vector files, output optimization strategy documents and the adjusted test vector set, and clearly define the optimization direction and expected improvement goals. The adjusted test vector set is put back into the simulation environment, and the indicator data of logic coverage, fault detection rate, total test time and resource usage are re-collected. The performance changes before and after optimization are compared, and it is checked whether the optimization introduces new problems. If so, the optimization strategy is adjusted retroactively. The convergence condition is set as a performance improvement of <1% for two consecutive iterations and no new problems. If it is met, the optimization is terminated, otherwise the iteration is continued until the test vector achieves the optimal balance in terms of time, coverage and cost, and then the final optimized test vector set, evaluation report and deployment guide are output.

6. The integrated circuit chip testing system based on AI algorithm according to claim 5, characterized in that: The test execution feedback module includes a test execution unit and a feedback update unit; The test execution unit is used to apply the optimized test vectors to the actual integrated circuit chip test process, execute the test task, and record the test results; The feedback update unit is used to collect feedback information based on the results of the test execution, and further optimize the test vector AI optimization model and test vectors to adapt to changes in chip production processes and new testing requirements.

7. The integrated circuit chip testing system based on AI algorithm according to claim 6, characterized in that: The test execution unit specifically includes: Configure the parameters of the automated test equipment, including clock frequency, power supply voltage, and signal levels, according to the chip test requirements document and deployment guide. Load the optimized test vector set into the test equipment. Parse the vector sequence, target coverage nodes, and resource allocation parameters to generate an executable test instruction stream. Verify the integrity of the vector loading and check the status of test resources through the equipment self-test function. The test task is launched according to the optimized vector execution sequence, and the test progress is monitored in real time. The execution time and resource usage of each vector are recorded. The chip output response signal is captured and compared bit by bit with the expected result. The pass / fail test results and fault location information are recorded. If a test interruption is detected, the rollback mechanism is triggered, the current test status is saved, and the failed vector is restarted. The timestamp and error code of the abnormal event are also recorded simultaneously. Compare the test data before and after optimization, calculate the test time compression rate and resource utilization improvement, verify whether the optimization effect meets the expected goals, integrate the test results containing the pass rate and fault distribution diagram with the log file containing the execution time and resource consumption into a standardized report, and store it in the database according to the chip batch and test type. Then generate a test efficiency analysis report, mark the test items that do not meet the standards, and feed back to the test vector generation module to drive the next round of optimization iterations, forming a continuous improvement closed loop.

8. The integrated circuit chip testing system based on AI algorithm according to claim 7, characterized in that: The feedback updating unit specifically includes: Collect all types of feedback generated during the test execution process, including test results, fault location information, test time, resource usage, and abnormal event records, and organize and categorize them. At the same time, record new chip features and potential defects discovered during the test, as well as changes in the test environment. Store the feedback information in the database by category and establish field indexes. Based on the collected feedback, the test vector AI optimization model is analyzed to determine its adaptability and accuracy in the current test environment. Combined with the test results, the model's shortcomings in predicting the effectiveness of test vectors are identified. Furthermore, the performance of the test vectors in actual tests is analyzed to identify areas for optimization. Based on the results of the optimization analysis, the test vector AI optimization model is updated. At the same time, the test vector is adjusted according to the optimization strategy to generate a new test vector set. The updated model and vector are applied to new test tasks. Feedback information is continuously collected, and performance indicators before and after iteration are compared to verify the optimization effect. If the standard is not met, retroactive adjustments are made to form a closed-loop mechanism of "collection-analysis-optimization-verification".

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