Rising edge and falling edge conversion rate enhancement circuit and current detection amplifier

Abstract

The invention provides a rising edge and falling edge conversion rate enhancement circuit and a current detection amplifier. The circuit comprises a first detection module, a first driving module and a first current module which are connected in sequence, the first input end and the second input end of the first detection module are respectively connected with the first input end and the second input end of the operational amplifier, and the first driving module comprises a first current mirror and a second current mirror which are connected in sequence; the first current mirror is used for conducting under the condition that the first voltage difference value reaches a first preset threshold value, increasing the current flowing through the second current mirror and controlling the first potential at the joint of the second current mirror and the first current module to drop; the first current module is started and generates the first current under the condition that the first potential drops, the first current module is driven to form the first current to accelerate the rising edge conversion rate, and the problem that the rising edge conversion rate of the operational amplifier is too low under the action of a large signal is effectively solved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and particularly to a rising-edge and falling-edge conversion rate enhancement circuit and a current detection amplifier. Background Art

[0002] A current detection amplifier is an operational amplifier that can convert a current signal into a voltage signal and amplify it. It can sense the voltage drop across a shunt resistor at a common-mode voltage independent of the power supply voltage, and is commonly used in overcurrent protection, precision current measurement for system optimization, or closed-loop feedback circuits. The current detection amplifier has an extremely low offset voltage, so when performing current sensing, it can keep the voltage drop across the shunt resistor above the maximum offset voltage of the current detection amplifier.

[0003] For a current detection amplifier, when the difference between the input signals reaches a certain threshold, the internal amplifier will transmit the input signals to the output terminal of the operational amplifier at a certain conversion rate. This conversion rate is closely related to the magnitude of the bias current and the compensation capacitance of the internal amplifier. When the bias current value and capacitance value are fixed, the conversion rate of the operational amplifier is determined. However, in many usage scenarios, the conversion rate of existing operational amplifiers is difficult to meet the requirements of fast signal transmission. Summary of the Invention

[0004] The technical problem to be solved by the present disclosure is to overcome the defect that the conversion rate of the operational amplifier in the prior art is difficult to meet the requirements of fast signal transmission, and to provide a rising-edge and falling-edge conversion rate enhancement circuit and a current detection amplifier.

[0005] The present disclosure solves the above technical problem through the following technical solutions:

[0006] In a first aspect, the present disclosure provides a rising-edge conversion rate enhancement circuit, which includes a first detection module, a first driving module, and a first current module connected in sequence;

[0007] The first input terminal and the second input terminal of the first detection module are respectively connected to the first input terminal and the second input terminal of the operational amplifier. The first detection module is used to detect the first voltage difference between the first input terminal and the second input terminal of the operational amplifier;

[0008] The first driving module includes a first current mirror and a second current mirror connected in sequence; the first current mirror is used to conduct when the first voltage difference reaches a first preset threshold and increase the current flowing through the second current mirror; the second current mirror is used to control the first potential at the connection between the second current mirror and the first current module to decrease when the flowing current increases;

[0009] The first current module is connected to the first capacitor of the operational amplifier. The first current module is turned on and generates a first current when the first potential drops. The first current is used to increase the conversion rate of the rising edge.

[0010] Optionally, the first detection module includes a first NMOS transistor, a second NMOS transistor, and a first current source;

[0011] The gate of the first NMOS transistor is connected to the first input terminal, the source of the first NMOS transistor is connected to the first current source, and the drain of the first NMOS transistor is connected to the third input terminal of the first current mirror;

[0012] The gate of the second NMOS transistor is electrically connected to the second input terminal, the source of the second NMOS transistor is connected to the first current source, and the drain of the second NMOS transistor is connected to the fourth input terminal of the first current mirror.

[0013] Optionally, the first current mirror includes a first PMOS transistor and a second PMOS transistor;

[0014] The source of the first PMOS transistor is connected to the working voltage power supply, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor;

[0015] The source of the second PMOS transistor is connected to the working voltage power supply, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor.

[0016] Optionally, the ratio between the width-to-length ratio of the conductive channel of the first PMOS transistor and the width-to-length ratio of the conductive channel of the second PMOS transistor is a preset threshold.

[0017] Optionally, the second current mirror includes a third NMOS transistor and a fourth NMOS transistor;

[0018] The drain and gate of the third NMOS transistor are connected to the drain of the first PMOS transistor, and the source of the third NMOS transistor is connected to the ground terminal;

[0019] The gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the second PMOS transistor, and the source of the fourth NMOS transistor is connected to the ground terminal.

[0020] Optionally, the first driving module further includes a first common-gate current mirror;

[0021] The common-gate current mirror is connected between the first current mirror and the second current mirror.

[0022] Optionally, the first current module includes a third PMOS transistor, a first clamping transistor, and a first resistor;

[0023] The gate of the third PMOS transistor is connected to the second current mirror, and a first clamping transistor is connected between the gate of the third PMOS transistor and the operating voltage power supply. A first resistor is connected between the source of the third PMOS transistor and the operating voltage power supply, and the drain of the third PMOS transistor outputs a first current.

[0024] Optionally, the first resistor is a resistor with adjustable resistance value.

[0025] In a second aspect, the present disclosure provides a falling-edge conversion rate enhancement circuit, which includes a second detection module, a second driving module, and a second current module connected in sequence;

[0026] The first input terminal and the second input terminal of the second detection module are respectively connected to the second input terminal and the first input terminal of the operational amplifier. The second detection module is used to detect the second voltage difference between the first input terminal and the second input terminal of the operational amplifier;

[0027] The second driving module includes a third current mirror and a fourth current mirror connected in sequence; the third current mirror is used to conduct when the second voltage difference reaches a second preset threshold and increase the current flowing through the third current mirror; the fourth current mirror is used to control the second potential at the connection between the fourth current mirror and the second current module to decrease when the flowing current increases;

[0028] The second current module is connected to the second capacitor of the operational amplifier. The second current module is turned on and generates a second current when the second potential decreases, and the second current is used to increase the conversion rate of the falling edge.

[0029] In a third aspect, the present disclosure provides a current detection amplifier. The first input terminal of the current detection amplifier is respectively connected to the first input terminal of the rising-edge conversion rate enhancement circuit according to any item of the first aspect and the second input terminal of the falling-edge conversion rate enhancement circuit according to the second aspect;

[0030] The second input terminal of the current detection amplifier is respectively connected to the second input terminal of the rising-edge conversion rate enhancement circuit and the first input terminal of the falling-edge conversion rate enhancement circuit;

[0031] The output terminal of the rising-edge conversion rate enhancement circuit is connected to the first capacitor of the current detection amplifier;

[0032] The output terminal of the falling-edge conversion rate enhancement circuit is connected to the second capacitor of the current detection amplifier.

[0033] The positive and progressive effects of the present disclosure are as follows:

[0034] The present disclosure sets a first preset threshold through a first current mirror. The first detection module samples the first voltage difference of the input signal of the operational amplifier at the moment of the rising edge conversion, and drives the first current module to form a first current to accelerate the rising edge conversion rate, effectively solving the problem that the rising edge conversion rate of the operational amplifier is too slow under the action of a large signal, and improving to meet the fast transmission requirements of signals.

[0035] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of modules of a rising edge conversion efficiency enhancement circuit provided by an exemplary embodiment of the present disclosure;

[0037] Figure 2 It is a first connection schematic diagram of a rising edge conversion efficiency enhancement circuit provided by an exemplary embodiment of the present disclosure;

[0038] Figure 3 It is a second connection schematic diagram of a rising edge conversion efficiency enhancement circuit provided by an exemplary embodiment of the present disclosure;

[0039] Figure 4 It is a schematic diagram of modules of a falling edge conversion efficiency enhancement circuit provided by an exemplary embodiment of the present disclosure;

[0040] Figure 5 It is a first connection schematic diagram of a falling edge conversion efficiency enhancement circuit provided by an exemplary embodiment of the present disclosure;

[0041] Figure 6 It is a second connection schematic diagram of a current detection amplifier provided by an exemplary embodiment of the present disclosure;

[0042] Figure 7 It is a first partial connection schematic diagram of a falling edge conversion efficiency enhancement circuit provided by an exemplary embodiment of the present disclosure;

[0043] Figure 8 It is a second partial connection schematic diagram of a falling edge conversion efficiency enhancement circuit provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0045] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of the present disclosure are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or server comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0046] The following introduces a rising-edge conversion rate enhancement circuit provided by an embodiment of the present disclosure. Refer to Figure 1 , the circuit 10 includes a first detection module 11, a first driving module 12, and a first current module 13 connected in sequence. The first input terminal 111 and the second input terminal 112 of the first detection module 11 are respectively connected to the first input terminal 21 and the second input terminal 22 of the operational amplifier 20, and the first current module 13 is connected to the first capacitor of the operational amplifier 20.

[0047] Among them, the first detection module 11 is used to detect the first voltage difference between the first input terminal 21 and the second input terminal 22 of the operational amplifier 20. The first driving module 12 includes a first current mirror 121 and a second current mirror 122 connected in sequence. The first current mirror 121 is used to conduct when the first voltage difference reaches a first preset threshold and increase the current flowing through the second current mirror 122. The second current mirror 122 is used to control the first potential at the connection between the second current mirror 122 and the first current module 13 to decrease when the flowing current increases. The first current module is turned on and generates a first current when the first potential drops, and the first current is used to increase the conversion rate of the rising edge.

[0048] The function of the rising-edge flip rate enhancement circuit provided in this embodiment is to increase the output voltage change rate (SR) of the operational amplifier when a large signal is input, making the rising edge steeper. While dynamically adjusting the internal current of the operational amplifier to increase the amplification rate of the operational amplifier, the operational amplifier does not have to be in a high-power consumption state all the time.

[0049] In this embodiment, a first preset threshold is set through the first current mirror. The first detection module samples the first voltage difference of the input signal of the operational amplifier at the moment of rising-edge conversion, and drives the first current module to form a first current to accelerate the rising-edge conversion rate, effectively solving the problem that the rising-edge conversion rate of the operational amplifier is too slow under the action of a large signal.

[0050] The following is a detailed description of the rising edge conversion rate enhancement circuit provided in this embodiment in conjunction with Figure 2 :

[0051] The first detection module includes a first NMOS transistor M1, a second NMOS transistor M2, and a first current source I3. The first current mirror includes a first PMOS transistor M3 and a second PMOS transistor M4. The second current mirror includes a third NMOS transistor M7 and a fourth NMOS transistor M8. The first current module includes a third PMOS transistor M9, a first clamping transistor, and a first resistor R1.

[0052] Specifically, the gate of the first NMOS transistor M1 is connected to the first input terminal INN. The source of the first NMOS transistor M1 is connected to the first current source I3. The drain of the first NMOS transistor M1 is connected to the third input terminal of the first current mirror (i.e., the drain of the first PMOS transistor M3). The gate of the second NMOS transistor M2 is electrically connected to the second input terminal INP. The source of the second NMOS transistor M2 is connected to the first current source. The drain of the second NMOS transistor M2 is connected to the fourth input terminal of the first current mirror (i.e., the drain of the second PMOS transistor M4). The source of the first PMOS transistor M3 is connected to the operating voltage power supply VDDA. The drain of the first PMOS transistor M3 is connected to the drain of the first NMOS transistor M1. The gate of the first PMOS transistor M3 is connected to the gate of the second PMOS transistor M4. The source of the second PMOS transistor M4 is connected to the operating voltage power supply VDDA. The drain of the second PMOS transistor M4 is connected to the drain of the second NMOS transistor M2. The drain and gate of the third NMOS transistor M7 are connected to the drain of the first PMOS transistor M3. The source of the third NMOS transistor M7 is connected to the ground terminal VSS. The gate of the fourth NMOS transistor M8 is connected to the gate of the third NMOS transistor M7. The drain of the fourth NMOS transistor M8 is connected to the drain of the second PMOS transistor M4. The source of the fourth NMOS transistor M8 is connected to the ground terminal Vss. The gate of the third PMOS transistor M9 is connected to the second current mirror (i.e., the source of the fourth NMOS transistor), and a first clamping transistor is connected between the gate of the third PMOS transistor M9 and the operating voltage power supply VDDA. A first resistor is connected between the source of the third PMOS transistor M9 and the operating voltage power supply VDDA. The drain of the third PMOS transistor M9 outputs a first current Islewp.

[0053] Among them, when the voltage of the second input terminal INP is greater than the voltage of the first input terminal INN, M1 and M2 sample the first voltage difference of the input signal of the operational amplifier at the moment of the rising edge conversion. When a relatively large first voltage difference appears at the rising edge of the input signal, the conduction states of M1 and M2 are unbalanced, generating a differential-mode current. At this time, the current flowing through M1 is less than the current flowing through M2. With the current of I3 remaining unchanged, the current flowing through M1 becomes smaller, and the current flowing through M2 becomes larger. Since the current flowing through M1 becomes smaller, if the current flowing through M3 remains unchanged, the current flowing through M7 increases. At the same time, since the ratio of the current mirror formed by M7 and M8 is 1:1, when the current flowing through M7 increases, the current of M8 increases. Therefore, since the drain potential of M8 (i.e., the first potential) drops, M9 is turned on and a first current Islewp is generated. The first current Islewp is used to increase the conversion rate of the rising edge.

[0054] In a specific embodiment, the ratio of the width-to-length of the conductive channel of the first PMOS transistor M3 to the width-to-length of the conductive channel of the second PMOS transistor M4 is a first preset threshold. By setting the ratio of the width-to-length of the conductive channel, the first preset threshold can be determined. The larger the first preset threshold, the higher the first voltage difference required to trigger the first current. In this embodiment, the first preset threshold is preferably 20 mV, and the specific setting can be selected according to actual needs and is not particularly limited here.

[0055] In a specific embodiment, referring to Figure 3 , the first driving module may further include a first cascode current mirror, which is connected between the first current mirror and the second current mirror. The first cascode current mirror acts as a current buffer to increase the output impedance and isolate the input stage, and specifically includes a fourth PMOS transistor M5 and a fifth PMOS transistor M6.

[0056] The source of the fourth PMOS transistor M5 is connected to the drain of the first PMOS transistor M3, and the gate of the fourth PMOS transistor M5 is connected to the gate of the fifth PMOS transistor M6. The drain of the fourth PMOS transistor M5 is connected to the drain of the third NMOS transistor M7. The source of the fifth PMOS transistor M6 is connected to the drain of the second PMOS transistor M4, and the drain of the fifth PMOS transistor M6 is connected to the drain of the fourth NMOS transistor M8.

[0057] In a specific embodiment, the first clamping transistor includes a sixth PMOS transistor Mc1 and a seventh PMOS transistor Mc2.

[0058] The source of the sixth PMOS transistor Mc1 is connected to the operating voltage power supply VDDA, and the gate and drain of the sixth PMOS transistor Mc1 are connected to the source of the seventh PMOS transistor. The drain and source of the seventh PMOS transistor Mc2 are connected to the gate of the third PMOS transistor M9.

[0059] The sizes of the sixth PMOS transistor Mc1 and the seventh PMOS transistor Mc2 can ensure that the gate voltage of the third PMOS transistor M9 is limited within the maximum safe range of the third PMOS transistor, such as 5V, but not limited thereto, and can be set according to the actual product parameters of the third PMOS transistor.

[0060] In a specific embodiment, the first resistor R1 is a resistor with adjustable resistance. The first resistor R1 is used for current limiting. By reasonably setting the resistance value of the first resistor R1, the magnitude of the first current Islewp can be controlled, and thus the conversion rate of the signal rising edge can be determined.

[0061] An exemplary embodiment of the present disclosure further provides a falling-edge conversion rate enhancement circuit. Refer to Figure 4 , the circuit 30 includes a second detection module 31, a second driving module 32, and a second current module 33 connected in sequence. The first input terminal 311 and the second input terminal 312 of the second detection module 31 are respectively connected to the second input terminal 22 and the first input terminal 21 of the operational amplifier, and the second current module 33 is connected to the second capacitor of the operational amplifier.

[0062] Among them, the second detection module 31 is used to detect the second voltage difference between the first input terminal 21 and the second input terminal 22. The second driving module 32 includes a third current mirror 321 and a fourth current mirror 322 connected in sequence. The third current mirror 321 is used to conduct when the second voltage difference reaches a second preset threshold and increase the current flowing through the fourth current mirror 322. The fourth current mirror 322 is used to control the second potential at the connection between the fourth current mirror 322 and the second current module 33 to decrease when the flowing current increases. The second current module 33 is turned on and generates a second current when the second potential decreases, and the second current is used to increase the conversion rate of the falling edge.

[0063] The function of the falling-edge flip rate enhancement circuit provided in this embodiment is to increase the output voltage change rate (SR) of the operational amplifier when a large signal is input, making the falling edge steeper. While dynamically adjusting the internal current of the operational amplifier to increase the amplification rate of the operational amplifier, the operational amplifier does not have to be in a high-power consumption state all the time.

[0064] In this embodiment, a second preset threshold is set through the third current mirror. The second detection module samples the second voltage difference of the input signal of the operational amplifier at the moment of falling-edge conversion and drives the second current module to form a second current to accelerate the falling-edge conversion rate, effectively solving the problem that the falling-edge conversion rate of the operational amplifier is too slow under the action of a large signal.

[0065] The following will combine Figure 5 to elaborate on the falling-edge conversion rate enhancement circuit provided in this embodiment:

[0066] The second detection module includes a fifth NMOS transistor M10, a sixth NMOS transistor M11, and a second current source I4. The third current mirror includes an eighth PMOS transistor M12 and a ninth PMOS transistor M13. The second current source includes a seventh NMOS transistor M16 and an eighth NMOS transistor M17. The second current module includes a tenth PMOS transistor M18, a second clamping transistor, and a second resistor R2.

[0067] Specifically, the gate of the fifth NMOS transistor M10 is connected to the second input terminal INP. The source of the fifth NMOS transistor M10 is connected to the second current source I4. The drain of the fifth NMOS transistor M10 is connected to the third input terminal of the third current mirror (i.e., the drain of the eighth PMOS transistor M12). The gate of the sixth NMOS transistor M11 is electrically connected to the first input terminal INN. The source of the sixth NMOS transistor M11 is connected to the second current source. The drain of the sixth NMOS transistor M11 is connected to the fourth input terminal of the third current mirror (i.e., the drain of the ninth PMOS transistor M13). The source of the eighth PMOS transistor M12 is connected to the operating voltage power supply VDDA. The drain of the eighth PMOS transistor M12 is connected to the drain of the fifth NMOS transistor M10. The gate of the eighth PMOS transistor M12 is connected to the gate of the ninth PMOS transistor M13. The source of the ninth PMOS transistor M13 is connected to the operating voltage power supply VDDA. The drain of the ninth PMOS transistor M13 is connected to the drain of the sixth NMOS transistor M11. The drain and gate of the seventh NMOS transistor M16 are connected to the drain of the eighth PMOS transistor M12. The source of the seventh NMOS transistor M16 is connected to the ground terminal VSS. The gate of the eighth NMOS transistor M17 is connected to the gate of the seventh NMOS transistor M16. The drain of the eighth NMOS transistor M17 is connected to the drain of the ninth PMOS transistor M13. The source of the eighth NMOS transistor M17 is connected to the ground terminal Vss. The gate of the tenth PMOS transistor M18 is connected to the fourth current mirror (i.e., the source of the fourth NMOS transistor), and a second clamping transistor is connected between the gate of the tenth PMOS transistor M18 and the operating voltage power supply VDDA. A second resistor is connected between the source of the tenth PMOS transistor M18 and the operating voltage power supply VDDA. The drain of the tenth PMOS transistor M18 outputs a second current Islewn.

[0068] Among them, when the voltage of the first input terminal INN is greater than the voltage of the second input terminal INP, M10 and M11 sample the second voltage difference of the input signal of the operational amplifier at the moment of the falling edge conversion. When a relatively large second voltage difference appears at the falling edge of the input signal, the conduction states of M10 and M11 are unbalanced, generating a differential-mode current. At this time, the current flowing through M10 is less than the current flowing through M11. With the current of I4 remaining unchanged, the current flowing through M10 becomes smaller, and the current flowing through M11 becomes larger. Since the current flowing through M10 becomes smaller, if the current flowing through M12 remains unchanged, the current flowing through M16 increases. At the same time, since the ratio of the current mirror formed by M16 and M17 is 1:1, when the current flowing through M16 increases, the current of M17 increases. Therefore, due to the decrease in the drain potential of M17, M18 is turned on and a second current Islewn is generated. The second current Islewn is used to increase the conversion rate of the falling edge.

[0069] In a specific embodiment, the ratio of the width-to-length of the conductive channel of the eighth PMOS transistor M12 to the width-to-length of the conductive channel of the ninth PMOS transistor M13 is a second preset threshold. By setting the ratio of the width-to-length of the conductive channel, the second preset threshold can be determined. The larger the second preset threshold, the higher the second voltage difference is required to trigger the second current. In this embodiment, the second preset threshold is preferably 20 mV, and the specific setting can be selected according to actual needs and is not particularly limited here.

[0070] In a specific embodiment, referring to Figure 6 , the second driving module may further include a second cascode current mirror, which is connected between the third current mirror and the fourth current mirror. The second cascode current mirror acts as a current buffer to increase the output impedance and isolate the input stage, and specifically includes an eleventh PMOS transistor M14 and a twelfth PMOS transistor M15.

[0071] The source of the eleventh PMOS transistor M14 is connected to the drain of the eighth PMOS transistor M12, the gate of the eleventh PMOS transistor M14 is connected to the gate of the twelfth PMOS transistor M15, and the drain of the eleventh PMOS transistor M14 is connected to the drain of the seventh NMOS transistor M16. The source of the twelfth PMOS transistor M15 is connected to the drain of the ninth PMOS transistor M13, and the drain of the twelfth PMOS transistor M15 is connected to the drain of the eighth NMOS transistor M17.

[0072] In a specific embodiment, the second clamping transistor includes a thirteenth PMOS transistor Mc3 and a fourteenth PMOS transistor Mc4.

[0073] The source of the thirteenth PMOS transistor Mc3 is connected to the operating voltage power supply VDDA, and the gate and drain of the thirteenth PMOS transistor Mc3 are connected to the source of the eighth PMOS transistor. The drain and source of the fourteenth PMOS transistor Mc4 are connected to the gate of the tenth PMOS transistor M18.

[0074] The sizes of the thirteenth PMOS transistor Mc3 and the fourteenth PMOS transistor Mc4 can ensure that the gate voltage of the tenth PMOS transistor M18 is limited within the maximum safe range of the tenth PMOS transistor, such as 5V, but not limited thereto, and can be set according to the actual product parameters of the tenth PMOS transistor.

[0075] In a specific embodiment, the second resistor R2 is a resistor with adjustable resistance. The second resistor R2 is used for current limiting. By reasonably setting the resistance value of the second resistor R2, the magnitude of the second current Islewp can be controlled, thereby determining the conversion rate of the signal falling edge.

[0076] An exemplary embodiment of the present disclosure further provides a current detection amplifier. The current detection amplifier is a type of operational amplifier. In this embodiment, the current detection amplifier is used for illustration, but not limited thereto. Compared with the operational amplifier, the current detection amplifier provided in this embodiment also has the function of detecting the magnitude of the current.

[0077] See Figure 7 and Figure 8 , the first input terminal INN of the current detection amplifier is respectively connected to the first input terminal of the rising edge conversion rate enhancement circuit (Positive Slew Boost in the figure) in the above embodiment and the second input terminal of the falling edge conversion rate enhancement circuit (Negative Slew Boost in the figure) in the above embodiment.

[0078] The second input terminal INP of the current detection amplifier is respectively connected to the second input terminal of the rising edge conversion rate enhancement circuit and the first input terminal of the falling edge conversion rate enhancement circuit.

[0079] The output terminal of the rising edge conversion rate enhancement circuit is connected to the first capacitor c1 of the current detection amplifier. The output terminal of the falling edge conversion rate enhancement circuit is connected to the second capacitor c2 of the current detection amplifier.

[0080] Specifically, the current detection amplifier further includes a fifteenth PMOS transistor PM1 and a sixteenth PMOS transistor PM2, a ninth NMOS transistor NM1 and a tenth NMOS transistor NM2, which are respectively the input pair transistors of the current detection amplifier, so that the input signal satisfies the rail-to-rail input range.

[0081] The current detection amplifier further includes a cascode current mirror of the operational amplifier formed by the seventeenth PMOS transistor PM3 to the twentieth PMOS transistor PM6. The twenty-first PMOS transistor PM7 to the twenty-fifth PMOS transistor PM11 and the eleventh NMOS transistor NM3 to the fifteenth NMOS transistor NM7 together constitute a Class AB (Class AB amplification) output of the overall operational amplifier, so that the output signal range meets the rail-to-rail range.

[0082] The current detection amplifier further includes a chopper operational amplifier (Aux chop amp), which is connected to the first input terminal INN and the second input terminal INP of the current detection amplifier, and is used to improve the signal-to-noise ratio and DC accuracy of the current detection amplifier.

[0083] Specifically, the first current Islewp flows through the thirteenth NMOS transistor NM5, causing the current of the thirteenth NMOS transistor NM5 to increase. Since the thirteenth NMOS transistor NM5 and the fourteenth NMOS transistor NM6 form a current mirror, the current of the fourteenth NMOS transistor NM6 increases proportionally, that is, the current flowing through the twelfth NMOS transistor NM4 increases, and the drain potential of the twelfth NMOS transistor NM4 is pulled down. Since the current of the twenty-fourth PMOS transistor PM10 remains unchanged, additional current will be drawn from the first capacitor C1 to discharge the second capacitor C2, so the conversion rate of the signal rising edge is enhanced.

[0084] The second current Islewn flows through Figure 1 the fourteenth NMOS transistor NM6 in, causing the current of the fourteenth NMOS transistor NM6 to increase, then the current flowing through the twelfth NMOS transistor NM4 decreases. Since the current of the twelfth NMOS transistor NM4 is fixed, the excess current will be injected into the second capacitor C2 to charge the second capacitor C2, enhancing the conversion rate of the signal falling edge.

[0085] Although the specific embodiments of the present disclosure have been described above, those skilled in the art should understand that this is only an example. The protection scope of the present disclosure is defined by the appended claims. Without departing from the principles and essence of the present disclosure, those skilled in the art can make various changes or modifications to these embodiments, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. An ascending edge conversion rate enhancement circuit, characterized in that, The circuit includes a first detection module, a first drive module, and a first current module connected in sequence; A first input terminal and a second input terminal of the first detection module are respectively connected to a first input terminal and a second input terminal of an operational amplifier. The first detection module is configured to detect a first voltage difference between the first input terminal and the second input terminal of the operational amplifier; The first drive module includes a first current mirror and a second current mirror connected in sequence. The first current mirror is configured to conduct when the first voltage difference reaches a first preset threshold and increase the current flowing through the second current mirror. The second current mirror is configured to control a first potential at a connection between the second current mirror and the first current module to decrease when the flowing current increases; The first current module is connected to a first capacitor of the operational amplifier. The first current module is turned on and generates a first current when the first potential decreases. The first current is used to increase the conversion rate of the rising edge.

2. The rising edge conversion rate enhancement circuit according to claim 1, characterized in that The first detection module includes a first NMOS transistor, a second NMOS transistor, and a first current source; A gate of the first NMOS transistor is connected to the first input terminal of the operational amplifier. A source of the first NMOS transistor is connected to the first current source. A drain of the first NMOS transistor is connected to a third input terminal of the first current mirror; A gate of the second NMOS transistor is electrically connected to the second input terminal of the operational amplifier. A source of the second NMOS transistor is connected to the first current source. A drain of the second NMOS transistor is connected to a fourth input terminal of the first current mirror.

3. The rising edge conversion rate enhancement circuit according to claim 2, wherein The first current mirror includes a first PMOS transistor and a second PMOS transistor; A source of the first PMOS transistor is connected to a working voltage power supply. A drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. A gate of the first PMOS transistor is connected to a gate of the second PMOS transistor; A source of the second PMOS transistor is connected to the working voltage power supply. A drain of the second PMOS transistor is connected to the drain of the second NMOS transistor.

4. The rising edge conversion rate enhancement circuit according to claim 3, wherein A ratio between a width-to-length of a conductive channel of the first PMOS transistor and a width-to-length of a conductive channel of the second PMOS transistor is the preset threshold; 5. The rising edge conversion rate enhancement circuit according to claim 3, wherein The second current mirror includes a third NMOS transistor and a fourth NMOS transistor; A drain and a gate of the third NMOS transistor are connected to the drain of the first PMOS transistor. A source of the third NMOS transistor is connected to a ground terminal; A gate of the fourth NMOS transistor is connected to the gate of the third NMOS transistor. A drain of the fourth NMOS transistor is connected to the drain of the second PMOS transistor. A source of the fourth NMOS transistor is connected to the ground terminal.

6. The rising edge conversion rate enhancement circuit according to claim 1, characterized in that The first drive module further includes a first common-gate current mirror; The first common-gate current mirror is connected between the first current mirror and the second current mirror.

7. The rising edge conversion rate enhancement circuit according to claim 1, characterized in that The first current module includes a third PMOS transistor, a first clamping transistor, and a first resistor; The gate of the third PMOS transistor is connected to the second current mirror, and a first clamping transistor is connected between the gate of the third PMOS transistor and the operating voltage power supply. A first resistor is connected between the source of the third PMOS transistor and the operating voltage power supply, and a first current is output from the drain of the third PMOS transistor.

8. The rising edge conversion rate enhancement circuit according to claim 1, characterized in that, The first resistor is a resistor with adjustable resistance value.

9. A falling-edge conversion rate enhancement circuit, characterized in that The circuit includes a second detection module, a second drive module, and a second current module connected in sequence; A first input terminal and a second input terminal of the second detection module are respectively connected to a second input terminal and a first input terminal of the operational amplifier. The second detection module is configured to detect a second voltage difference between the first input terminal and the second input terminal of the operational amplifier. The second drive module includes a third current mirror and a fourth current mirror connected in sequence. The third current mirror is configured to conduct when the second voltage difference reaches a second preset threshold and increase the current flowing through the third current mirror. The fourth current mirror is configured to control the second potential at the connection between the fourth current mirror and the second current module to decrease when the flowing current increases. The second current module is connected to a second capacitor of the operational amplifier. The second current module is turned on and generates a second current when the second potential decreases, and the second current is used to increase the conversion rate of the falling edge.

10. A current detection amplifier, characterized in that, A first input terminal of the current detection amplifier is respectively connected to a first input terminal of the rising edge conversion rate enhancement circuit according to any one of claims 1-8 and a second input terminal of the falling edge conversion rate enhancement circuit according to claim 9; A second input terminal of the current detection amplifier is respectively connected to a second input terminal of the rising edge conversion rate enhancement circuit and a first input terminal of the falling edge conversion rate enhancement circuit; An output terminal of the rising edge conversion rate enhancement circuit is connected to a first capacitor of the current detection amplifier; An output terminal of the falling edge conversion rate enhancement circuit is connected to a second capacitor of the current detection amplifier.

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