Flash memory block management method and storage system

Abstract

The invention provides a management method of a flash memory block and a storage system, and belongs to the technical field of storage. The management method comprises the following steps: when the quantity of error data of a flash page in a flash block exceeds a set threshold value, adjusting the working mode of the flash block from a normal working mode to a pseudo single-layer unit mode to form a low-performance flash block; and when a verification trigger signal of the low-performance flash memory block is received, reducing the power supply voltage of the vacant low-performance flash memory block from a standard voltage to a weak current voltage, switching the vacant low-performance flash memory block from a pseudo single-layer unit mode to a normal working mode, and writing data into the vacant low-performance flash memory block, verifying whether the low-performance flash memory block reaches a verification standard or not; and repeatedly verifying whether the low-performance flash memory block reaches the verification standard or not, and when the number of times that the low-performance flash memory block reaches the verification standard reaches the preset number of times, using the low-performance flash memory block as a conventional flash memory block. Through the management method of the flash memory block provided by the invention, the service life of the memory chip can be prolonged.

Description

Technical Field

[0001] The present invention belongs to the technical field of storage, and particularly relates to a management method for flash memory blocks and a storage system. Background Art

[0002] NAND flash memory devices include storage chips such as Solid State Disks (SSDs), Embedded Multi Media Cards (EMMCs), and Universal Flash Storages (UFSs). However, the lifespan of these storage chips is limited by the physical characteristics of the NAND flash memory itself.

[0003] When the error correction ability of a flash memory block in a storage chip exceeds a threshold, the flash memory block is identified as a bad block and is no longer enabled. When all the flash memory blocks in a NAND flash memory device reach the end of their lifespan, the storage chip is directly scrapped, but this processing method greatly reduces the lifespan of the storage chip. Summary of the Invention

[0004] The purpose of the present invention is to provide a management method for flash memory blocks and a storage system, which can improve the lifespan of storage chips.

[0005] To achieve the above purpose, the present invention provides a management method for flash memory blocks and a storage system, and the management method for the flash memory blocks at least includes the following steps: When the number of error data in a flash memory page in a flash memory block exceeds a set threshold, adjust the working mode of the flash memory block from the normal working mode to the pseudo single-level cell mode to form a low-performance flash memory block; When receiving a verification trigger signal for a low-performance flash memory block, reduce the power supply voltage of the vacant low-performance flash memory block from the standard voltage to a weak voltage, and switch the vacant low-performance flash memory block from the pseudo single-level cell mode to the normal working mode, and write data into the vacant low-performance flash memory block to verify whether the low-performance flash memory block meets the verification standard; and Repeatedly verify whether the low-performance flash memory block meets the verification standard. When the number of times the low-performance flash memory block meets the verification standard reaches a preset number of times, use the low-performance flash memory block as a regular flash memory block.

[0006] In an embodiment of the present invention, when the low-performance flash memory block does not meet the verification standard, switch the low-performance flash memory block from the normal working mode to the pseudo single-level cell mode and keep the low-performance flash memory block in the pseudo single-level cell mode.

[0007] In an embodiment of the present invention, forming the low-performance flash memory block includes the following steps: Detect the remaining capacity of the storage chip; If the capacity of the storage chip is greater than or equal to the first threshold, move the data in the flash block to the idle flash block, and switch the storage unit of the flash block from the normal working mode to the pseudo single-level cell mode to form the low-performance flash block; If the capacity of the storage chip is less than the first threshold, set the garbage collection flag and perform garbage collection until the capacity of the storage chip is greater than the second threshold, then move the data in the flash block to the idle flash block, and switch the storage unit of the flash block from the normal working mode to the pseudo single-level cell mode to form the low-performance flash block; Wherein, the second threshold is greater than the first threshold.

[0008] In an embodiment of the present invention, the verification trigger signal is a power signal or a time signal; When the verification trigger signal is a power signal, when the power-on times of the storage chip reach the set times, the host sends the verification trigger signal to the storage chip; When the verification trigger signal is a time signal, when the system time reaches the set time, the host sends the verification trigger signal to the storage chip.

[0009] In an embodiment of the present invention, the flash block is provided with a first power supply circuit and a second power supply circuit, the first power supply circuit outputs the standard voltage, and the second power supply circuit outputs the weak voltage.

[0010] In an embodiment of the present invention, the first power supply circuit includes: A power supply; and A control tube, one end of the control tube is electrically connected to the power supply, the other end of the control tube is electrically connected to the power supply terminal of the flash block, and the control end of the control tube is electrically connected to the controller of the storage chip; When the storage chip is in the normal working mode, the controller outputs a high level, the control tube is turned on, and the first power supply circuit provides the standard voltage for the flash block.

[0011] In an embodiment of the present invention, the second power supply circuit includes: The power supply; and A diode, the positive electrode of the diode is electrically connected to the power supply, and the negative electrode of the diode is electrically connected to the power supply terminal of the flash block; When the storage chip receives the verification trigger signal of the low-performance flash memory block, the controller provides a low level to the control end of the control transistor in the first power supply circuit of the vacant low-performance flash memory block, the control transistor is turned off, the first power supply circuit is turned off, the second power supply circuit is turned on, and the second power supply circuit provides a weak power voltage to the vacant low-performance flash memory block.

[0012] In an embodiment of the present invention, writing data into the vacant low-performance flash memory block to verify whether the low-performance flash memory block meets the verification standard includes the following steps: Writing repeated fixed data into the vacant low-performance flash memory block, and determining whether the number of error data bits in the low-performance flash memory block exceeds a preset ratio. If the number of error data bits in the low-performance flash memory block exceeds the preset ratio, the low-performance flash memory block does not meet the verification standard. If the number of error data bits in the low-performance flash memory block does not exceed the preset ratio, the low-performance flash memory block meets the verification standard.

[0013] In an embodiment of the present invention, after writing data into the vacant low-performance flash memory block, monitoring whether the remaining capacity of the storage chip is less than a third threshold. When the capacity of the storage chip is less than the third threshold, then determining whether the number of error data bits in the low-performance flash memory block exceeds a preset ratio.

[0014] The present invention also provides a storage system, characterized in that the storage system includes an electronic device, and the electronic device includes: A memory storing program instructions; and A processor that runs the program instructions to implement the management method of the flash memory block as described in any one of the above.

[0015] In an embodiment of the present invention, the storage system includes a storage chip, and the storage chip includes: Flash memory blocks; A first power supply circuit, and the first power supply circuit includes a power supply and a control transistor. One end of the control transistor is electrically connected to the power supply, the other end of the control transistor is electrically connected to the power supply terminal of the flash memory block, and the control end of the control transistor is electrically connected to the controller of the storage chip; and A second power supply circuit, and the second power supply circuit includes the power supply and a diode. The positive electrode of the diode is electrically connected to the power supply, and the negative electrode of the diode is electrically connected to the power supply terminal of the flash memory block.

[0016] In summary, the management method for a flash memory block and the storage system provided by the present invention determine the status of the flash memory block based on the number of error data in the flash memory pages of the flash memory block. When the number of error data in the flash memory pages approaches the number of error data set in the error correction capability, the flash memory block is switched to the pseudo single-level cell mode and used as a low-performance flash memory block, thereby increasing the lifespan of the flash memory block. At the same time, to avoid misjudgment of the number of error data caused by various factors such as hardware-related factors, limitations of error correction algorithms, and system and environmental factors, after the flash memory block is switched from the normal working mode to the pseudo single-level cell mode, the vacant low-performance flash memory blocks are verified, and then the misjudged flash memory blocks are switched back to the normal working mode and used as regular flash memory blocks. And when verifying the low-performance flash memory blocks, when writing data, the power supply voltage of the vacant low-performance flash memory blocks is pulled down to deteriorate the environment for data storage in the low-performance flash memory blocks, making it easier to test the quality of the low-performance flash memory blocks during data writing, and avoiding low-performance flash memory blocks with quality deviations from being switched back to the normal working mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0018] Figure 1 It is a schematic structural diagram of a storage system in an embodiment of the present application.

[0019] Figure 2 It is a power supply circuit diagram of a flash memory block in an embodiment of the present application.

[0020] Figure 3 It is a flowchart of a management method for a flash memory block in an embodiment of the present application.

[0021] Figure 4 It is a flowchart of a method for forming a low-performance flash memory block in an embodiment of the present application.

[0022] Figure 5 It is a schematic structural diagram of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0025] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "center", "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention. The degrees indicated by "high", "low", etc. are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a high or low level, and thus should not be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0026] Please refer to Figure 1 As shown, compared with traditional disks, the storage chip 100 with Nand flash as the storage medium has characteristics such as non-volatility, fast read and write speed, earthquake resistance, low power consumption, and small volume, and is currently widely used in fields such as embedded systems, consumer electronics, and aerospace. According to the different protocols for the storage chip 100 to communicate with the host 200, it can be divided into Embedded Multi Media Card (eMMC), Universal Flash Storage (UFS), Serial ATA (SATA), and peripheral component interconnect express (PCIe), etc.

[0027] Please refer to Figure 1 As shown, in an embodiment of the present invention, a controller 101, a buffer 102, and a non-volatile memory 103 are provided in the storage chip 100. Among them, the controller 101 can execute multiple logic gates or control instructions implemented in hardware form or firmware form, and perform operations such as data writing, reading, and erasing in the non-volatile memory 103 according to the instructions of the host 200.

[0028] Please refer to Figure 1As shown, in an embodiment of the present invention, the buffer 102 is a high-speed storage device with an access speed faster than that of the non-volatile memory 103. When the host 200 wants to read a piece of data, it first looks up in the buffer 102. If found, it is immediately read and sent to the controller 101 for processing. If not found in the buffer 102, it is read from the relatively slower non-volatile memory 103 and sent to the controller 101 for processing. At the same time, the data block where this data is located is transferred into the buffer 102, so that subsequent reads of the entire data block can be performed from the buffer 102 without having to call the memory again. This greatly saves the time for data reading and also makes the controller 101 basically not have to wait when reading data. Among them, the buffer 102 is usually a Dynamic Random Access Memory (DRAM). Among them, the lifetimes of the controller 101 and the buffer 102 have no clear expected damage and can theoretically be used all the time. Therefore, the lifetime of the storage chip 100 mainly depends on the lifetime of the non-volatile memory 103.

[0029] Please refer to Figure 1 As shown, the non-volatile memory 103 stores the data written by the host 200 and other necessary data such as the mapping table. Among them, the non-volatile memory 103 is a NAND flash memory or a vertical NAND (VNAND). And the non-volatile memory 103 includes a plurality of flash blocks 1031, and the flash blocks 1031 can belong to the same memory die or different memory dies. Each flash block 1031 has a plurality of flash pages respectively, and each flash page has at least one physical sector. Among them, the flash pages belonging to the same flash block 1031 can be independently written and simultaneously erased. For example, each flash block 1031 is composed of 128 flash pages, and each flash page has 8 physical sectors. That is to say, in the example where each physical sector is 512 bytes (byte), the capacity of each flash page is 4 Kilobytes (K). However, in an embodiment, each flash block 1031 can be composed of 64 flash pages, 256 flash pages or any other number of flash pages. Among them, the flash block 1031 is the smallest unit for erasure. That is, each flash block 1031 contains the smallest number of storage units that are erased together. The flash page is the smallest programmable unit. That is, the flash page is the smallest unit for writing data. However, in some embodiments, the smallest unit for writing data can also be a physical sector or other sizes. Each flash page usually includes a data bit area and a redundant bit area. The data bit area is used to store the user's data, and the redundant bit area is used to store the system's data (for example, error checking and correction codes).

[0030] Please refer to Figure 1As shown, in an embodiment of the present invention, the flash memory block 1031 may include single-level cells (SLCs), multi-level cells (MLCs), triple-level cells, quad-level cells (QLCs), or a combination of two or more of these cell types. Among them, a single-level cell can store, for example, 1 bit of data, a multi-level cell can store, for example, 2 bits of data, a triple-level cell can store, for example, 3 bits of data, and a quad-level cell can store, for example, 4 bits of data. Compared with single-level cells and multi-level cells, triple-level cells and quad-level cells can store a larger amount of data, but have a shorter erase / write lifespan and relatively poor read / write performance. The approximate number of erase cycles for single-level cells, multi-level cells, triple-level cells, and quad-level cells is 80,000 times, 3,000 times, 3,000 times, and 1,000 times, respectively. For the flash memory blocks 1031 of multi-level cells, triple-level cells, and quad-level cells, the memory cells in the flash memory block 1031 can be configured to operate in a normal operating mode or a pseudo-single-level cell (pSLC) mode. When the memory cells in the flash memory block 1031 are configured to operate in the normal operating mode, the number of bits of data that can be stored in each memory cell is equal to the set number of bits, that is, a multi-level cell stores 2 bits of data, a triple-level cell stores 3 bits of data, and a quad-level cell stores 4 bits of data. When the cells in the flash memory block 1031 are configured to operate in the pseudo-single-level cell mode, only 1 bit of data can be stored in each memory cell. The lifespan of the memory cells in the pseudo-single-level cell mode is much higher than that in the normal operating mode.

[0031] Please refer to Figure 1 and Figure 3 As shown, the present invention provides a method for managing a flash memory block and a storage system, which can adjust the operating mode of the memory cells in the flash memory block 1031 between the normal operating mode and the single-level cell mode according to the state of the flash memory block 1031, thereby maximizing the lifespan of the flash memory block 1031 and improving the storage capacity of the flash memory block 1031. Specifically, the method for managing the flash memory block provided by the present invention includes steps S110 to S190.

[0032] Step S110: Monitor the number of error data in each flash memory block. When the number of error data in the flash memory pages in the flash memory block exceeds the set threshold, execute step S120.

[0033] Step S120: Move the data in the flash memory block and switch the memory cells in the flash memory block from the normal operating mode to the pseudo-single-level cell mode to form a low-performance flash memory block.

[0034] Step S130: Monitor the verification trigger signal of the low-performance flash block. When the verification trigger signal of the low-performance flash block is received, execute Step S140.

[0035] Step S140: Reduce the power supply voltage of the vacant low-performance flash block from the standard voltage to a weak voltage, and switch the vacant low-performance flash block from the pseudo single-level cell mode to the normal operating mode, and write data into the low-performance flash block.

[0036] Step S150: Verify whether the low-performance flash block meets the verification standard according to the data written into the low-performance flash block. If the low-performance flash block meets the verification standard, execute Step S160. If the low-performance flash block does not meet the verification standard, execute Step S190.

[0037] Step S160: Increment the number of times the low-performance flash block meets the verification standard by one.

[0038] Step S170: Determine whether the number of times the low-performance flash block meets the verification standard reaches the preset number of times. If the number of times the low-performance flash block meets the verification standard reaches the preset number of times, execute Step S180. If the number of times the low-performance flash block does not meet the verification standard reaches the preset number of times, return to Step S130.

[0039] Step S180: Use the low-performance flash block as a regular flash block.

[0040] Step S190: Switch the storage cells in the low-performance flash block from the normal operating mode to the pseudo single-level cell mode, and keep the low-performance flash block in the pseudo single-level cell mode.

[0041] Please refer to Figure 3As shown, in an embodiment of the present invention, the hardware error correction ability is calculated according to the flash memory pages. Therefore, the number of error data in each flash memory page within the flash memory block is used as the basis for determining whether the flash memory block needs to perform a mode switch. Thus, when determining whether the flash memory block needs to perform a working mode conversion, the number of error data in each flash memory page within the flash memory block is compared with the number of error data set in the hardware error correction ability. In this application, the set threshold in step S110 is less than the number of error data set in the hardware error correction ability and is close to the number of error data set in the hardware error correction ability. When the number of error data in a flash memory page within the flash memory block exceeds the set threshold, it indicates that the lifespan of the flash memory block is approaching its limit. At this time, to avoid errors in stored data and extend the lifespan of the flash memory block, the storage unit of the flash memory block is switched from the normal working mode to the pseudo single-level cell mode for use. In a specific embodiment, for example, the hardware error correction ability is 105bit / 4k, and the range of the set threshold is, for example, 85bit to 95bit, specifically, for example, 90bit. That is, when the number of error data in a flash memory page within the flash memory block is greater than 90bit, step S120 is executed. When the number of error data in two or more flash memory pages within the flash memory block is greater than 90bit simultaneously, step S120 is also executed.

[0042] Please refer to Figures 3 to 4 As shown, in an embodiment of the present invention, in step S120, when the number of error data in a flash memory page within the flash memory block exceeds the set threshold, the data in the flash memory block is moved, and the storage unit of the flash memory block is switched from the normal working mode to the pseudo single-level cell mode, forming a low-performance flash memory block. And step S120 specifically includes steps S121 to S125.

[0043] Step S121: Detect the remaining capacity of the storage chip.

[0044] Please refer to Figures 3 to 4 As shown, in an embodiment of the present invention, before switching the storage unit of the flash memory block from the normal working mode to the pseudo single-level cell mode, the data in the flash memory block needs to be moved to an idle flash memory block. And before moving the data of the flash memory block, it is necessary to detect the remaining capacity of the storage chip to avoid the remaining capacity of the storage chip being too small to perform data movement or the data movement process being aborted due to the absence of an idle flash memory block during the data movement process.

[0045] Step S122: Determine whether the remaining capacity of the storage chip is less than the first threshold. If the remaining capacity of the storage chip is less than the first threshold, then execute step S123. If the remaining capacity of the storage chip is greater than or equal to the first threshold, then execute step S125.

[0046] Please refer to Figures 3 to 4As shown, in an embodiment of the present invention, the remaining capacity of the storage chip is the total capacity of the idle flash memory blocks in the storage chip. Among them, the first threshold is, for example, 100 Mb.

[0047] Step S123: Set the garbage collection flag and perform garbage collection.

[0048] Please refer to Figures 3 to 4 As shown, in an embodiment of the present invention, when the remaining capacity of the storage chip is less than the first threshold, the remaining capacity in the storage chip is extremely small and is not sufficient to transfer data in a continuous plurality of flash memory blocks. At this time, the data in the flash memory block will not be directly moved, but the garbage collection flag will be set, waiting for the storage chip to perform garbage collection to release more idle flash memory blocks. Among them, the set garbage collection flag is a self-defined variable Warning_Free. In the normal working mode, the variable Warning_Free is set to 0. When the remaining capacity of the storage chip is less than the first threshold, the variable Warning_Free is set to 1. The host periodically queries the status of the variable Warning_Free. When it is detected that the variable Warning_Free is set to 1, that is, the garbage collection flag is detected, the garbage collection function is started to perform garbage collection.

[0049] Step S124: Determine whether the remaining capacity of the storage chip is greater than the second threshold. If the remaining capacity of the storage chip is greater than the second threshold, execute step S125. If the remaining capacity of the storage chip is less than or equal to the second threshold, execute step S123.

[0050] Please refer to Figures 3 to 4 As shown, in an embodiment of the present invention, after the storage chip performs garbage collection, the capacity of the storage chip will be detected again to determine whether the remaining capacity of the storage chip is greater than the second threshold. The second threshold is greater than the first threshold and is, for example, 300 Mb. When the remaining capacity of the storage chip is greater than the second threshold, the number of idle flash memory blocks in the storage chip is sufficient for data transfer, so step S125 is executed to perform data transfer. When the remaining capacity of the storage chip is less than or equal to the second threshold, the number of idle flash memory blocks released by garbage collection is not sufficient, so step S123 is returned again to set the garbage collection flag and perform garbage collection to release more idle flash memory blocks until the remaining capacity of the storage chip is greater than the second threshold. At this time, the remaining capacity of the storage chip can support continuous data transfer in multiple flash memory blocks. By releasing multiple idle flash memory blocks through multiple garbage collections, it is possible to avoid the process of immediately needing to perform garbage collection again after this data transfer, and avoid frequently setting the garbage collection flag to notify the host to start garbage collection.

[0051] Step S125: Move the data in the flash memory block to the idle flash memory block, and switch the storage units of the flash memory block from the normal working mode to the pseudo single-level cell mode to form a low-performance flash memory block.

[0052] Please refer to Figures 3 to 4 As shown, in an embodiment of the present invention, when the remaining capacity of the storage chip is sufficient, move the data in the flash memory block to the idle flash memory block, switch the storage units of the flash memory block from the normal working mode to the pseudo single-level cell mode to form a low-performance flash memory block. And set the position of the low-performance flash memory block with a pseudo single-level cell mode flag in the physical address management table of the firmware.

[0053] Please refer to Figure 3 As shown, in the present application, after switching the storage units of the flash memory block from the normal working mode to the pseudo single-level cell mode, the flash memory block is defined as a low-performance flash memory block. At this time, each storage unit in the low-performance flash memory block stores only 1 bit of data. However, the number of error data in the low-performance flash memory block exceeding the set threshold may be due to multiple factors such as hardware-related factors such as charge leakage, programming interference, or read interference, limitations of error correction algorithms such as insufficient error correction ability or soft decision error, and system and environmental factors such as radiation or electromagnetic interference, in addition to the life of the flash memory block approaching the limit. Therefore, in the present application, after switching the storage units of the flash memory block from the normal working mode to the pseudo single-level cell mode, the low-performance flash memory block will be verified regularly.

[0054] Please refer to Figure 3 As shown, in an embodiment of the present invention, in step S130, the verification trigger signal of the low-performance flash memory block can be a power signal, a time signal, or any other signal that can achieve the trigger function. When the verification trigger signal of the low-performance flash memory block is a power signal, when the number of power-on times of the storage chip reaches the set number of times, for example, the number of power-on times of the storage chip reaches 100 times, the host sends a verification trigger signal to the storage chip, and the storage chip can receive the verification trigger signal of the low-performance flash memory block. When the verification trigger signal of the low-performance flash memory block is a time signal, when the system time reaches the set time signal, for example, the system time reaches 24 hours and the storage chip is in the working state, the host sends a verification trigger signal to the storage chip, and the storage chip can receive the verification trigger signal of the low-performance flash memory block. In this embodiment, the verification trigger signal of the low-performance flash memory block is set as a power signal, that is, when the number of power-on times of the storage chip reaches the set number of times, the low-performance flash memory block is verified.

[0055] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, each flash memory block 1031 is provided with two power supply circuits, namely the first power supply circuit and the second power supply circuit. Among them, the first power supply circuit includes a power supply V CCand a control transistor Q1. One end of the control transistor Q1 is electrically connected to a power supply V CC , and the other end is electrically connected to the flash memory block 1031. The control end of the control transistor Q1 is electrically connected to the controller 101 of the memory chip 100. The second power supply circuit includes a power supply V CC and a diode D1. The positive electrode of the diode D1 is electrically connected to the power supply V CC , and the negative electrode is electrically connected to the flash memory block 1031. When the controller 101 outputs a high level, the control transistor Q1 is turned on, and the voltage provided by the first power supply circuit to the flash memory block 1031 is equal to the power supply voltage. The second power supply circuit remains in a conducting state. Since a voltage drop will occur across the diode D1 in the second power supply circuit, the voltage provided by the second power supply circuit to the flash memory block 1031 is equal to the power supply voltage minus the voltage across the two ends of the diode D1. At this time, the power supply voltage of the flash memory block 1031 is equal to the power supply voltage provided by the first power supply circuit to the flash memory block 1031, that is, the power supply voltage. When the controller 101 outputs a low level, the control transistor Q1 is turned off, the first power supply circuit is turned off, and the second power supply circuit remains in a conducting state. At this time, the power supply voltage of the flash memory block 1031 is equal to the power supply voltage provided by the second power supply circuit to the flash memory block 1031, that is, the power supply voltage minus the voltage across the two ends of the diode D1.

[0056] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, if the power supply voltage is, for example, 3.3V, then the power supply voltage of the first power supply circuit is 3.3V, and the power supply voltage of the second power supply circuit is 2.7V. In this application, the power supply voltage of the first power supply circuit is defined as the standard voltage, and the power supply voltage of the second power supply circuit is defined as the weak voltage.

[0057] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, when the memory chip 100 is operating normally, when the controller 101 outputs a high level, the control transistor Q1 is turned on, the first power supply circuit and the second power supply circuit are turned on, and the power supply voltage of the flash memory block 1031 is equal to the standard voltage. When the memory chip 100 receives a verification trigger signal for a low-performance flash memory block 1031, the controller 101 provides a low level to the control end of the control transistor Q1 in the first power supply circuit for the vacant low-performance flash memory block 1031. The control transistor Q1 is turned off, the first power supply circuit is turned off, and the second power supply circuit is turned on. The power supply voltage of the vacant low-performance flash memory block 1031 is equal to the weak voltage. That is, the power supply voltage of the vacant low-performance flash memory block 1031 is reduced from the standard voltage to the weak voltage.

[0058] It should be noted that when verifying a low-performance flash memory block, not all low-performance flash memory blocks are verified, but only the vacant low-performance flash memory blocks are verified to avoid damaging the data in the low-performance flash memory blocks that already store data.

[0059] Please refer to Figure 2 and Figure 3 As shown, in this application, when verifying an empty low-performance flash memory block, reducing the power supply voltage of the empty low-performance flash memory block from the standard voltage to a weak voltage can deteriorate the environment for data storage in the low-performance flash memory block, making it easier to test the quality of the low-performance flash memory block during data writing, and preventing low-performance flash memory blocks with quality deviations from switching back to the normal operating mode.

[0060] Please refer to Figure 3 As shown, in an embodiment of the present invention, the process from step S140 to step S190 is a process of verifying an empty low-performance flash memory block multiple times, and the process from step S140 to step S150 is a process of verifying an empty low-performance flash memory block once.

[0061] Please refer to Figure 3 As shown, in an embodiment of the present invention, in step S140, during the process of verifying an empty low-performance flash memory block, after switching the empty low-performance flash memory block from the pseudo single-level cell mode to the normal operating mode, the data written into the empty low-performance flash memory block is repeated fixed data, which is convenient for detecting whether the repeated fixed data written into the low-performance flash memory block is correct. Specifically, the repeated fixed data written is, for example, 5a5a5a5a.

[0062] Please refer to Figure 2 and Figure 3 As shown, in an embodiment of the present invention, after writing data into the low-performance flash memory block 1031 in step S140, the controller 101 is used to trigger the control transistor Q1 to conduct, so that the power supply voltage of the low-performance flash memory block 1031 is restored to the standard voltage. The weak voltage is only used when writing the repeated fixed data into the low-performance flash memory block 1031.

[0063] Please refer to Figure 3 As shown, in an embodiment of the present invention, in step S150, the specific method for verifying whether the flash memory block meets the verification standard based on the data written into the low-performance flash memory block is: determining whether the number of error data bits in the low-performance flash memory block exceeds a preset ratio. If the number of error data bits in the low-performance flash memory block exceeds the preset ratio, the low-performance flash memory block does not meet the verification standard; if the number of error data bits in the low-performance flash memory block does not exceed the preset ratio, the low-performance flash memory block meets the verification standard. Among them, the range of the preset ratio is, for example, 20% - 40%, and specifically, for example, 30%, 35% or 40%.

[0064] Please refer to Figure 3As shown, in an embodiment of the present invention, when a low-performance flash memory block meets the verification standard, the number of times the low-performance flash memory block meets the verification standard is recorded. After the number of times the low-performance flash memory block meets the verification standard reaches a preset number, the low-performance flash memory block is switched to the normal working mode and used as a regular flash memory block. Among them, the preset number is, for example, 3 to 5, specifically, for example, 3 times, 4 times, or 5 times.

[0065] Please refer to Figure 3 As shown, in an embodiment of the present invention, if after each empty low-performance flash memory block is switched from the pseudo single-level cell mode to the normal working mode and data is written into the low-performance flash memory block, the low-performance flash memory block is immediately verified whether it meets the verification standard, the verification is frequent. And regardless of whether the low-performance flash memory block meets the verification standard, the repeated fixed data written in the low-performance flash memory block needs to be erased. Therefore, in the present invention, after the empty low-performance flash memory block is switched from the pseudo single-level cell mode to the normal working mode and data is written into the low-performance flash memory block, it is monitored whether the remaining capacity of the storage chip is less than a third threshold. When the remaining capacity of the storage chip is less than the third threshold, the low-performance flash memory block is verified whether it meets the verification standard. Among them, the third threshold is, for example, 50 Mb. At this time, multiple low-performance flash memory blocks can be verified simultaneously.

[0066] Please refer to Figure 3 As shown, in an embodiment of the present invention, after each verification is completed, whether step S180 is executed, that is, the low-performance flash memory block is used as a regular flash memory block, or step S190 is executed, that is, the storage units in the low-performance flash memory block are switched from the normal working mode to the pseudo single-level cell mode and the low-performance flash memory block is maintained in the pseudo single-level cell mode, or step S130 is returned, that is, the verification trigger signal of the low-performance flash memory block is monitored, the repeated fixed data written in the low-performance flash memory block needs to be erased.

[0067] Please refer to Figure 3 As shown, in an embodiment of the present invention, in step S180, since the low-performance flash memory block has been switched from the pseudo single-level cell mode to the normal working mode during the verification process, only the mark of the pseudo single-level cell mode of the low-performance flash memory block needs to be deleted in the physical address management table of the firmware, and then the low-performance flash memory block can be used as the regular flash memory block 1031.

[0068] Please refer to Figure 3 As shown, in an embodiment of the present invention, in step S190, after the storage units in the low-performance flash memory block are switched from the normal working mode to the pseudo single-level cell mode, the mark of the pseudo single-level cell mode of the low-performance flash memory block can be set as a fixed mark in the physical address management table of the firmware. During the cyclic verification process of the low-performance flash memory block, the verification of the low-performance flash memory block is skipped and the low-performance flash memory block is maintained in the pseudo single-level cell mode.

[0069] Please refer to Figure 1 and Figure 5 As shown, an example of a storage system provided by an embodiment of the present application includes a storage chip 100 and an electronic device. Among them, the electronic device includes a processor 301 and a program stored in a memory 302 and executable on the processor. The processor executes to implement the above-mentioned management method for flash memory blocks. Among them, the electronic device is, for example, integrated in a host 200 or is the host 200 itself.

[0070] Please refer to Figure 5 As shown, the memory 302 includes at least one type of readable storage medium. The readable storage medium includes flash memory, a mobile hard disk, a multimedia card, a card-type memory (such as an SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, etc. The memory can be an internal storage unit of the electronic device in some embodiments. For example, the mobile hard disk of the electronic device. The memory can also be an external storage device of the electronic device in other embodiments. For example, a plug-in mobile hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the electronic device. Further, the memory can also include both an internal storage unit and an external storage device of the electronic device. The memory can be used not only to store application software installed in the electronic device and various types of data, but also to temporarily store data that has been output or will be output.

[0071] Please refer to Figure 5 As shown, the processor 301 can be composed of integrated circuits in some embodiments. For example, it can be composed of a single packaged integrated circuit, or can be composed of multiple integrated circuits with the same or different functions packaged together, including a combination of one or more Central Processing Units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips, etc. The processor is the control core (Control Unit) of the vehicle-mounted device, connecting various components of the entire vehicle-mounted device through various interfaces and circuits, and executing various functions of the vehicle-mounted device and processing data by running or executing programs or modules stored in the memory and calling data stored in the memory.

[0072] The processor executes the operating system of the vehicle-mounted device and various installed application programs. The processor executes the application program to implement the steps in the above method embodiments.

[0073] Exemplarily, the program can be divided into one or more modules, which are stored in the memory and executed by the processor to implement the present invention. The one or more modules can be a series of program instruction segments capable of performing specific functions, and these instruction segments are used to describe the execution process of the program in the vehicle-mounted device.

[0074] The integrated unit implemented in the form of a software functional module can be stored in a computer-readable storage medium. The above-mentioned software functional module stored in a storage medium includes several instructions for causing a computer device (which can be a personal computer, a computer device, or a network device, etc.) or a processor to execute some functions of the lithium battery virtual soldering detection method in various embodiments of the present invention.

[0075] In summary, a method for managing flash memory blocks and a storage system, the method for managing flash memory blocks includes: when the number of error data of flash memory pages in a flash memory block exceeds a set threshold, adjusting the working mode of the flash memory block from the normal working mode to the pseudo single-level cell mode to form a low-performance flash memory block; when receiving a verification trigger signal for the low-performance flash memory block, reducing the power supply voltage of the vacant low-performance flash memory block from the standard voltage to a weak voltage, and switching the vacant low-performance flash memory block from the pseudo single-level cell mode to the normal working mode, writing data into the vacant low-performance flash memory block to verify whether the low-performance flash memory block meets the verification standard; and repeatedly verifying whether the low-performance flash memory block meets the verification standard, and when the number of times the low-performance flash memory block meets the verification standard reaches a preset number of times, using the low-performance flash memory block as a conventional flash memory block. Through the method for managing flash memory blocks and the storage system provided by the present application, the service life of the storage chip can be extended.

[0076] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art in the relevant technical field can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A method for managing a flash memory block, characterized in that At least include the following steps: When the number of error data of flash pages in a flash block exceeds a set threshold, adjust the working mode of the flash block from the normal working mode to the pseudo single-level cell mode to form a low-performance flash block; When receiving a verification trigger signal for the low-performance flash block, reduce the power supply voltage of the vacant low-performance flash block from the standard voltage to a weak voltage, and switch the vacant low-performance flash block from the pseudo single-level cell mode to the normal working mode, and write data into the vacant low-performance flash block to verify whether the low-performance flash block meets the verification standard; And Repeatedly verify whether the low-performance flash block meets the verification standard. When the number of times the low-performance flash block meets the verification standard reaches a preset number of times, use the low-performance flash block as a regular flash block.

2. The management method of a flash memory block according to claim 1, characterized in that, When the low-performance flash block does not meet the verification standard, switch the low-performance flash block from the normal working mode to the pseudo single-level cell mode, and keep the low-performance flash block in the pseudo single-level cell mode.

3. A method for managing a flash memory block according to claim 1, characterized in that, Forming the low-performance flash block includes the following steps: Detect the remaining capacity of the storage chip; If the capacity of the storage chip is greater than or equal to a first threshold, move the data in the flash block to an idle flash block, and switch the storage unit of the flash block from the normal working mode to the pseudo single-level cell mode to form the low-performance flash block; If the capacity of the storage chip is less than the first threshold, set a garbage collection flag and perform garbage collection until the capacity of the storage chip is greater than a second threshold, then move the data in the flash block to an idle flash block, and switch the storage unit of the flash block from the normal working mode to the pseudo single-level cell mode to form the low-performance flash block; Wherein, the second threshold is greater than the first threshold.

4. A method for managing a flash memory block according to claim 1, characterized in that, The verification trigger signal is a power signal or a time signal; When the verification trigger signal is a power signal, when the number of power-on times of the storage chip reaches a set number of times, the host sends the verification trigger signal to the storage chip; When the verification trigger signal is a time signal, when the system time reaches a set time, the host sends the verification trigger signal to the storage chip.

5. The management method of a flash memory block according to claim 1, characterized in that, The flash block is provided with a first power supply circuit and a second power supply circuit. The first power supply circuit outputs the standard voltage, and the second power supply circuit outputs the weak voltage.

6. A method for managing a flash memory block according to claim 5, characterized in that, The first power supply circuit includes: A power supply; and A control tube, one end of the control tube is electrically connected to the power supply, the other end of the control tube is electrically connected to the power supply terminal of the flash block, and the control terminal of the control tube is electrically connected to the controller of the storage chip; When the storage chip is in the normal working mode, the controller outputs a high level, the control tube is turned on, and the first power supply circuit provides the standard voltage for the flash block.

7. The management method of a flash memory block according to claim 6, characterized in that, The second power supply circuit includes: The power supply; and A diode, the positive electrode of the diode is electrically connected to the power supply, and the negative electrode of the diode is electrically connected to the power supply terminal of the flash block; When the storage chip receives the verification trigger signal of the low-performance flash memory block, the controller provides a low level to the control terminal of the control transistor in the first power supply circuit of the vacant low-performance flash memory block. The control transistor is turned off, the first power supply circuit is turned off, the second power supply circuit is turned on, and the second power supply circuit provides a weak voltage to the vacant low-performance flash memory block.

8. A method for managing a flash memory block according to claim 1, wherein, Writing data into the vacant low-performance flash memory block to verify whether the low-performance flash memory block meets the verification standard includes the following steps: Writing repeated fixed data into the vacant low-performance flash memory block, and determining whether the number of error data bits in the low-performance flash memory block exceeds a preset ratio. If the number of error data bits in the low-performance flash memory block exceeds the preset ratio, the low-performance flash memory block does not meet the verification standard. If the number of error data bits in the low-performance flash memory block does not exceed the preset ratio, the low-performance flash memory block meets the verification standard.

9. A method for managing a flash memory block according to claim 8, wherein After writing data into the vacant low-performance flash memory block, monitor whether the remaining capacity of the storage chip is less than a third threshold. When the capacity of the storage chip is less than the third threshold, then determine whether the number of error data bits in the low-performance flash memory block exceeds a preset ratio.

10. A storage system, characterized in that, The storage system includes an electronic device, and the electronic device includes: A memory storing program instructions; and A processor that runs the program instructions to implement the flash memory block management method according to any one of claims 1 to 9.

11. The storage system according to claim 10, wherein The storage system includes a storage chip, and the storage chip includes: A flash memory block; A first power supply circuit, and the first power supply circuit includes a power supply and a control transistor. One end of the control transistor is electrically connected to the power supply, the other end of the control transistor is electrically connected to the power supply terminal of the flash memory block, and the control terminal of the control transistor is electrically connected to the controller of the storage chip; and A second power supply circuit, and the second power supply circuit includes the power supply and a diode. The positive electrode of the diode is electrically connected to the power supply, and the negative electrode of the diode is electrically connected to the power supply terminal of the flash memory block.

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