Flash memory block management method and storage system

Abstract

The present invention provides a flash memory block management method and storage system, belonging to the field of storage technology. The management method includes: when the number of erroneous data in the flash memory page in the flash memory block exceeds a set threshold, adjusting the operating mode of the flash memory block from the normal operating mode to the pseudo single-layer unit mode to form a low-performance flash memory block; upon receiving a verification trigger signal for the low-performance flash memory block, reducing the power supply voltage of the vacant low-performance flash memory block from the standard voltage to the weak voltage, switching the vacant low-performance flash memory block from the pseudo single-layer unit mode to the normal operating mode, and writing data to the vacant low-performance flash memory block to verify whether the low-performance flash memory block meets the verification standard; and repeatedly verifying whether the low-performance flash memory block meets the verification standard. When the low-performance flash memory block meets the verification standard a preset number of times, the low-performance flash memory block is used as a regular flash memory block. The flash memory block management method provided by the present invention can extend the life of the storage chip.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology, and in particular relates to a flash memory block management method and a storage system. Background Art

[0002] NAND flash devices include storage chips such as solid-state drives (SSDs), embedded multi-media cards (EMMCs), and universal flash storage (UFS). However, the lifespan of these storage chips is limited by the physical properties of NAND flash memory itself.

[0003] When the error correction capability of a flash memory block in a memory chip exceeds a threshold, the flash memory block is identified as a bad block and is no longer used. When all flash memory blocks in a NAND flash memory expire, the memory chip is directly scrapped, but this treatment significantly reduces the lifespan of the memory chip. Summary of the Invention

[0004] The object of the present invention is to provide a flash memory block management method and a storage system, which can improve the life of the storage chip.

[0005] To achieve the above object, the present invention provides a flash memory block management method and a storage system, and the flash memory block management method includes at least the following steps:

[0006] When the number of erroneous data in the flash memory page in the flash memory block exceeds a set threshold, the operating mode of the flash memory block is adjusted from the normal operating mode to the pseudo single-layer cell mode to form a low-performance flash memory block;

[0007] Upon receiving a verification trigger signal of a low-performance flash memory block, reducing the power supply voltage of the vacant low-performance flash memory block from a standard voltage to a weak voltage, switching the vacant low-performance flash memory block from a pseudo single-layer cell mode to a normal operating mode, and writing data into the vacant low-performance flash memory block to verify whether the low-performance flash memory block meets the verification standard; and

[0008] Repeatedly verifying whether the low-performance flash memory block meets the verification standard, and when the number of times the low-performance flash memory block meets the verification standard reaches a preset number, using the low-performance flash memory block as a normal flash memory block.

[0009] In one embodiment of the present invention, when the low-performance flash memory block fails to meet the verification standard, the low-performance flash memory block is switched from the normal operating mode to the pseudo single-layer cell mode and maintained in the pseudo single-layer cell mode.

[0010] In one embodiment of the present invention, forming the low-performance flash memory block includes the following steps:

[0011] Detect the remaining capacity of the memory chip;

[0012] If the capacity of the memory chip is greater than or equal to a first threshold, the data in the flash memory block is moved to an idle flash memory block, and the storage unit of the flash memory block is switched from a normal working mode to a pseudo single-layer unit mode to form the low-performance flash memory block;

[0013] If the capacity of the memory chip is less than a first threshold, a garbage collection flag is set to perform garbage collection until the capacity of the memory chip is greater than a second threshold, and then the data in the flash memory block is moved to an idle flash memory block, and the storage unit of the flash memory block is switched from a normal working mode to a pseudo single-layer unit mode to form the low-performance flash memory block;

[0014] The second threshold is greater than the first threshold.

[0015] In one embodiment of the present invention, the verification trigger signal is a power signal or a time signal;

[0016] When the verification trigger signal is a power signal, when the number of times the memory chip is powered on reaches a set number, the host sends the verification trigger signal to the memory chip;

[0017] When the verification trigger signal is a time signal, when the system time reaches a set time, the host sends the verification trigger signal to the storage chip.

[0018] In one embodiment of the present invention, the flash memory block is provided with a first power supply circuit and a second power supply circuit, the first power supply circuit outputs the standard voltage, and the second power supply circuit outputs the weak voltage.

[0019] In one embodiment of the present invention, the first power supply circuit includes:

[0020] Power supply; and

[0021] a control tube, one end of which is electrically connected to the power supply, the other end of which is electrically connected to the power supply end of the flash memory block, and the control end of which is electrically connected to the controller of the memory chip;

[0022] When the memory chip is in a normal working mode, the controller outputs a high level, the control tube is turned on, and the first power supply circuit provides a standard voltage for the flash memory block.

[0023] In one embodiment of the present invention, the second power supply circuit includes:

[0024] the power supply; and

[0025] a diode, wherein the anode of the diode is electrically connected to the power supply, and the cathode of the diode is electrically connected to the power supply end of the flash memory block;

[0026] When the storage chip receives the verification trigger signal of the low-performance flash memory block, the controller provides a low level to the control end of the control tube in the first power supply circuit of the vacant low-performance flash memory block, the control tube is cut off, the first power supply circuit is cut off, and the second power supply circuit is turned on, and the second power supply circuit provides a weak voltage for the vacant low-performance flash memory block.

[0027] In one embodiment of the present invention, writing data into the vacant low-performance flash memory block to verify whether the low-performance flash memory block meets the verification standard includes the following steps:

[0028] Repeated fixed data is written into the vacant low-performance flash memory block, and it is determined whether the number of erroneous data bits in the low-performance flash memory block exceeds a preset ratio. If the number of erroneous data bits in the low-performance flash memory block exceeds the preset ratio, the low-performance flash memory block does not meet the verification standard. If the number of erroneous data bits in the low-performance flash memory block does not exceed the preset ratio, the low-performance flash memory block meets the verification standard.

[0029] In one embodiment of the present invention, after writing data into the vacant low-performance flash memory block, it is monitored whether the remaining capacity of the storage chip is less than a third threshold value. When the capacity of the storage chip is less than the third threshold value, it is determined whether the number of error data bits in the low-performance flash memory block exceeds a preset ratio.

[0030] The present invention further provides a storage system, characterized in that the storage system includes an electronic device, and the electronic device includes:

[0031] a memory storing program instructions; and

[0032] The processor runs the program instructions to implement any one of the above methods for managing flash memory blocks.

[0033] In one embodiment of the present invention, the storage system includes a storage chip, and the storage chip includes:

[0034] Flash blocks;

[0035] a first power supply circuit, wherein the first power supply circuit includes a power supply and a control tube, one end of the control tube is electrically connected to the power supply, the other end of the control tube is electrically connected to the power supply end of the flash memory block, and the control end of the control tube is electrically connected to the controller of the memory chip; and

[0036] A second power supply circuit includes the power supply and a diode, wherein the anode of the diode is electrically connected to the power supply, and the cathode of the diode is electrically connected to the power supply end of the flash memory block.

[0037] In summary, the present invention provides a flash memory block management method and storage system that determines the state of a flash memory block based on the number of erroneous data in its flash memory pages. When the number of erroneous data in a flash memory page approaches the number of erroneous data set in the error correction capability, the flash memory block is switched to pseudo-single-layer cell mode and used as a low-performance flash memory block, thereby increasing the lifespan of the flash memory block. Furthermore, to avoid misjudgments of the number of erroneous data due to various factors, such as hardware-related factors, error correction algorithm limitations, and system and environmental factors, after switching the flash memory block from normal operating mode to pseudo-single-layer cell mode, vacant low-performance flash memory blocks are verified, and then the misjudged flash memory blocks are switched back to normal operating mode and used as regular flash memory blocks. Furthermore, during the verification of the low-performance flash memory blocks, the power supply voltage of the vacant low-performance flash memory blocks is lowered when writing data, thereby worsening the data storage environment of the low-performance flash memory blocks. This makes it easier to test the quality of the low-performance flash memory blocks during data writing, and prevents low-performance flash memory blocks with quality deviations from switching back to normal operating mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 It is a structural diagram of a storage system in one embodiment of the present application.

[0040] Figure 2 This is a power supply circuit diagram of a flash memory block in one embodiment of the present application.

[0041] Figure 3 This is a flow chart of a flash memory block management method in one embodiment of the present application.

[0042] Figure 4 This is a flow chart of a method for forming a low-performance flash memory block in one embodiment of the present application.

[0043] Figure 5 It is a structural diagram of an electronic device in one embodiment of the application. DETAILED DESCRIPTION

[0044] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by terms such as "center," "up," "down," "front," "back," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention. The degrees indicated by terms such as "high" and "low" are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or components referred to must have high or low, and therefore should not be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0047] See also Figure 1 As shown, compared to traditional magnetic disks, memory chip 100, which uses Nand flash memory as its storage medium, offers non-volatility, fast read / write speeds, shock resistance, low power consumption, and a compact size. It is currently widely used in embedded systems, consumer electronics, aerospace, and other fields. Depending on the communication protocol between memory chip 100 and host 200, it can be categorized into embedded multi-media card (eMMC), universal flash storage (UFS), serial ATA (SATA), and peripheral component interconnect express (PCIe).

[0048] See also Figure 1As shown, in one embodiment of the present invention, a memory chip 100 is provided with a controller 101, a buffer 102, and a non-volatile memory 103. The controller 101 can execute a plurality of logic gates or control instructions implemented in hardware or firmware, and perform operations such as writing, reading, and erasing data in the non-volatile memory 103 according to instructions from the host 200.

[0049] See also Figure 1 As shown, in one embodiment of the present invention, cache 102 is a high-speed storage device with a faster access speed than non-volatile memory 103. When host 200 needs to read a piece of data, it first searches cache 102. If the data is found, it is immediately read and sent to controller 101 for processing. If the data is not found in cache 102, it is read from the slower non-volatile memory 103 and sent to controller 101 for processing. Simultaneously, the data block containing the data is loaded into cache 102. This allows subsequent reads of the entire block of data to be performed from cache 102, eliminating the need to access memory. This significantly reduces data read time and eliminates the need for controller 101 to wait while reading data. Cache 102 is typically dynamic random access memory (DRAM). Both controller 101 and cache 102 have no specific lifespan expectations and can theoretically be used indefinitely. Therefore, the lifespan of memory chip 100 is primarily determined by the lifespan of non-volatile memory 103.

[0050] See also Figure 1As shown, the non-volatile memory 103 stores data written by the host 200 and other necessary data, such as mapping tables. The non-volatile memory 103 is NAND flash memory or vertical NAND (VNAND). The non-volatile memory 103 includes multiple flash blocks 1031, which can belong to the same memory die or to different memory dies. Each flash block 1031 has multiple flash pages, and each flash page has at least one physical sector. Flash pages belonging to the same flash block 1031 can be written independently and erased simultaneously. For example, each flash block 1031 consists of 128 flash pages, and each flash page has 8 physical sectors. In other words, if each physical sector is 512 bytes, the capacity of each flash page is 4 kilobytes (K). However, in one embodiment, each flash block 1031 can consist of 64 flash pages, 256 flash pages, or any other number of flash pages. Flash memory blocks 1031 are the smallest unit of erasure. That is, each flash memory block 1031 contains the minimum number of memory cells that are erased together. A flash memory page is the smallest programmable unit. That is, a flash memory page is the smallest unit for writing data. However, in some embodiments, the smallest unit for writing data may be a physical sector or other size. Each flash memory page typically includes a data bit area and a redundant bit area. The data bit area is used to store user data, while the redundant bit area is used to store system data (e.g., error checking and correction code).

[0051] See also Figure 1As shown, in one embodiment of the present invention, the flash memory block 1031 may include single-level cells (SLC), multi-level cells (MLC), triple-level cells (Triple-level cells), quad-level cells (QLC), or a combination of two or more of these types of cells. A single-level cell can store, for example, 1 bit of data; a multi-level cell can store, for example, 2 bits of data; a triple-level cell can store, for example, 3 bits of data; and a quad-level cell can store, for example, 4 bits of data. Compared to single-level cells and multi-level cells, triple-level cells and quad-level cells can store larger amounts of data, but have shorter erase and write lifespans and relatively poor read and write performance. The erase counts for single-level cells, multi-level cells, triple-level cells, and quad-level cells are approximately 80,000, 3,000, 3,000, and 1,000, respectively. For flash memory blocks 1031 with multi-layer storage cells, three-layer storage cells, and four-layer storage cells, the storage cells in the flash memory block 1031 can be configured to normal operating mode or pseudo-single-level cell (Pseudo-Single Level Cell, pSLC) mode. When the storage cells in the flash memory block 1031 are configured to normal operating mode, the number of bits of data that can be stored in each storage cell is equal to the set number of bits, that is, the multi-layer storage cell stores 2 bits of data, the three-layer storage cell stores 3 bits of data, and the four-layer storage cell stores 4 bits of data. When the cells in the flash memory block 1031 are configured to pseudo-single-level cell mode, each storage cell can only store 1 bit of data. The lifespan of the storage cell in pseudo-single-level cell mode will be much longer than that in normal operating mode.

[0052] Please combine Figure 1 and Figure 3 As shown, the present invention provides a flash memory block management method and storage system that can adjust the operating mode of the storage unit in the flash memory block 1031 between the normal operating mode and the single-layer unit mode according to the status of the flash memory block 1031, thereby maximizing the life of the flash memory block 1031 and improving the storage capacity of the flash memory block 1031. Specifically, the flash memory block management method provided by the present invention includes steps S110 to S190.

[0053] Step S110 , monitoring the number of erroneous data in each flash memory block. When the number of erroneous data in the flash memory pages in the flash memory block exceeds a set threshold, executing step S120 .

[0054] Step S120: Move the data in the flash memory block, and switch the storage cells in the flash memory block from the normal operation mode to the pseudo single-layer cell mode to form a low-performance flash memory block.

[0055] Step S130 , monitoring the verification trigger signal of the low-performance flash memory block. When the verification trigger signal of the low-performance flash memory block is received, executing step S140 .

[0056] Step S140: reduce the power supply voltage of the vacant low-performance flash memory block from the standard voltage to the weak voltage, switch the vacant low-performance flash memory block from the pseudo single-layer cell mode to the normal working mode, and write data into the low-performance flash memory block.

[0057] Step S150: Verify whether the low-performance flash memory block meets the verification standard based on the data written into the low-performance flash memory block. If the low-performance flash memory block meets the verification standard, execute step S160; if the low-performance flash memory block does not meet the verification standard, execute step S190.

[0058] Step S160: increment the number of times the low-performance flash memory block meets the verification standard by one.

[0059] Step S170, determine whether the number of times the low-performance flash memory block meets the verification standard reaches the preset number of times. If the number of times the low-performance flash memory block meets the verification standard reaches the preset number of times, execute step S180. If the number of times the low-performance flash memory block does not meet the verification standard reaches the preset number of times, return to step S130.

[0060] Step S180: Use the low-performance flash memory block as a regular flash memory block.

[0061] Step S190: Switch the storage cells in the low-performance flash memory block from the normal operation mode to the pseudo single-layer cell mode, and keep the low-performance flash memory block in the pseudo single-layer cell mode.

[0062] See also Figure 3As shown, in one embodiment of the present invention, the hardware error correction capability is calculated based on flash memory pages. Therefore, the number of erroneous data in each flash memory page within a flash memory block is used as the basis for determining whether the flash memory block needs to switch modes. Therefore, when determining whether a flash memory block needs to switch operating modes, the number of erroneous data in each flash memory page within the flash memory block is compared with the number of erroneous data set in the hardware error correction capability. In this application, the threshold set in step S110 is less than the number of erroneous data set in the hardware error correction capability and close to the number of erroneous data set in the hardware error correction capability. When the number of erroneous data in flash memory pages within a flash memory block exceeds the threshold, it indicates that the lifespan of the flash memory block is nearing its end. At this time, to avoid stored data errors and extend the lifespan of the flash memory block, the storage cells of the flash memory block are switched from normal operating mode to pseudo-single-level cell mode. In a specific embodiment, if the hardware error correction capability is, for example, 105 bits / 4k, the threshold is set in the range of 85 bits to 95 bits, specifically 90 bits. That is, when the number of erroneous data in a flash memory page within the flash memory block exceeds 90 bits, step S120 is executed. When the number of erroneous data in two or more flash memory pages in the flash memory block is greater than 90 bits, step S120 is also executed.

[0063] See also Figures 3 and 4 As shown, in one embodiment of the present invention, in step S120, when the number of erroneous data in the flash memory page within the flash memory block exceeds a set threshold, the data in the flash memory block is moved, and the storage cells of the flash memory block are switched from the normal operating mode to the pseudo single-layer cell mode, forming a low-performance flash memory block. Step S120 specifically includes steps S121 to S125.

[0064] Step S121: Detect the remaining capacity of the memory chip.

[0065] See also Figures 3 and 4 As shown, in one embodiment of the present invention, before switching the storage cells of a flash memory block from the normal operating mode to the pseudo single-layer cell mode, the data in the flash memory block needs to be moved to a free flash memory block. Furthermore, before moving the data in the flash memory block, the remaining capacity of the memory chip needs to be checked to avoid the situation where the remaining capacity of the memory chip is too low, resulting in the inability to move data, or the data move being aborted due to a lack of free flash memory blocks.

[0066] Step S122: determine whether the remaining capacity of the memory chip is less than a first threshold value. If the remaining capacity of the memory chip is less than the first threshold value, execute step S123; if the remaining capacity of the memory chip is greater than or equal to the first threshold value, execute step S125.

[0067] See also Figures 3 and 4As shown, in one embodiment of the present invention, the remaining capacity of the memory chip is the total capacity of the free flash memory blocks in the memory chip, wherein the first threshold is, for example, 100 Mb.

[0068] Step S123: Set the garbage collection flag and perform garbage collection.

[0069] See also Figures 3 and 4 As shown, in one embodiment of the present invention, when the remaining capacity of the memory chip is less than the first threshold value, the remaining capacity in the memory chip is already extremely small and insufficient to transfer data in a plurality of consecutive flash memory blocks. At this time, the data in the flash memory blocks will not be moved directly, but a garbage collection flag will be set to wait for the memory chip to perform garbage collection and release more free flash memory blocks. The garbage collection flag set is a self-defined variable Warning_Free. In normal working mode, the variable Warning_Free is set to 0. When the remaining capacity of the memory chip is less than the first threshold value, the variable Warning_Free is set to 1. The host periodically queries the status of the variable Warning_Free. When it is found that the variable Warning_Free is set to 1, the garbage collection flag is detected, the garbage collection function is started, and garbage collection is performed.

[0070] Step S124: determine whether the remaining capacity of the memory chip is greater than the second threshold. If the remaining capacity of the memory chip is greater than the second threshold, execute step S125; if the remaining capacity of the memory chip is less than or equal to the second threshold, execute step S123.

[0071] See also Figures 3 and 4 As shown, in one embodiment of the present invention, after the memory chip performs garbage collection, the capacity of the memory chip is tested again to determine whether the remaining capacity of the memory chip is greater than a second threshold. The second threshold is greater than the first threshold, for example, 300Mb. When the remaining capacity of the memory chip is greater than the second threshold, the number of free flash memory blocks in the memory chip is sufficient for data migration, so step S125 is executed to perform data migration. However, when the remaining capacity of the memory chip is less than or equal to the second threshold, the number of free flash memory blocks released by garbage collection is insufficient, so the process returns to step S123 again, sets the garbage collection flag, performs garbage collection, and releases more free flash memory blocks until the remaining capacity of the memory chip is greater than the second threshold. At this point, the remaining capacity of the memory chip can support continuous data migration of multiple flash memory blocks. By releasing multiple free flash memory blocks through multiple garbage collections, it is possible to avoid the need to perform garbage collection again immediately after the current data migration, and avoid frequently setting the garbage collection flag to notify the host to initiate garbage collection.

[0072] Step S125 : Move the data in the flash memory block to the free flash memory block, and switch the storage unit of the flash memory block from the normal operation mode to the pseudo single-layer cell mode to form a low-performance flash memory block.

[0073] See also Figures 3 and 4 As shown, in one embodiment of the present invention, when the remaining capacity of the memory chip is sufficient, the data in the flash memory block is moved to a free flash memory block, and the storage unit of the flash memory block is switched from normal operation mode to pseudo single-level unit mode, forming a low-performance flash memory block. A pseudo single-level unit mode flag is set at the location of the low-performance flash memory block in the physical address management table of the firmware.

[0074] See also Figure 3 As shown, in the present application, after the storage cells of the flash memory block are switched from the normal operating mode to the pseudo single-layer cell mode, the flash memory block is defined as a low-performance flash memory block. At this time, each storage cell in the low-performance flash memory block only stores 1 bit of data. However, the number of erroneous data in the low-performance flash memory block exceeds the set threshold. In addition to the fact that the life of the flash memory block is approaching the end of its life, it may also be due to hardware-related factors such as charge leakage, programming interference or read interference, error correction algorithm limitations such as insufficient error correction capability or soft decision errors, and system and environmental factors such as radiation or electromagnetic interference. Misjudgment. Therefore, in the present application, after the storage cells of the flash memory block are switched from the normal operating mode to the pseudo single-layer cell mode, the low-performance flash memory block will be verified regularly.

[0075] See also Figure 3 As shown, in one embodiment of the present invention, in step S130, the verification trigger signal of the low-performance flash memory block can be a power signal, or a time signal, or any other signal that can realize the trigger function. When the verification trigger signal of the low-performance flash memory block is a power signal, then when the number of power-on times of the memory chip reaches a set number, for example, the number of power-on times of the memory chip reaches 100 times, the host sends a verification trigger signal to the memory chip, and the memory chip can receive the verification trigger signal of the low-performance flash memory block. When the verification trigger signal of the low-performance flash memory block is a time signal, then when the system time reaches the set time signal, for example, the system time reaches 24 hours, and the memory chip is in working state, the host sends a verification trigger signal to the memory chip, and the memory chip can receive the verification trigger signal of the low-performance flash memory block. In this embodiment, the verification trigger signal of the low-performance flash memory block is set to a power signal, that is, when the number of power-on times of the memory chip reaches a set number, the low-performance flash memory block is verified.

[0076] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, each flash memory block 1031 is provided with two power supply circuits, namely a first power supply circuit and a second power supply circuit. The first power supply circuit includes a power supply V CCAnd control tube Q1. One end of the control tube Q1 is electrically connected to the power supply V CC The other end is electrically connected to the flash memory block 1031, and the control end of the control tube Q1 is electrically connected to the controller 101 of the memory chip 100. The second power supply circuit includes a power supply V CC And diode D1. The anode of diode D1 is electrically connected to the power supply V CC , the negative pole is electrically connected to the flash memory block 1031. When the controller 101 outputs a high level, the control tube Q1 is turned on, and the voltage provided by the first power supply circuit to the flash memory block 1031 is equal to the power supply voltage. The second power supply circuit remains in the on state. Since the diode D1 in the second power supply circuit will generate a voltage drop, the voltage provided by the second power supply circuit to the flash memory block 1031 is equal to the power supply voltage minus the voltage across the diode D1. At this time, the supply voltage of the flash memory block 1031 is equal to the supply voltage provided by the first power supply circuit to the flash memory block 1031, that is, the power supply voltage. When the controller 101 outputs a low level, the control tube Q1 is turned off, the first power supply circuit is turned off, and the second power supply circuit remains in the on state. At this time, the supply voltage of the flash memory block 1031 is equal to the supply voltage provided by the second power supply circuit to the flash memory block 1031, that is, the power supply voltage minus the voltage across the diode D1.

[0077] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, the power supply voltage is, for example, 3.3 V, then the supply voltage of the first power supply circuit is 3.3 V, and the supply voltage of the second power supply circuit is 2.7 V. In this application, the supply voltage of the first power supply circuit is defined as the standard voltage, and the supply voltage of the second power supply circuit is defined as the weak voltage.

[0078] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, when the memory chip 100 is operating normally, when the controller 101 outputs a high level, the control tube Q1 is turned on, the first power supply circuit and the second power supply circuit are turned on, and the power supply voltage of the flash memory block 1031 is equal to the standard voltage. When the memory chip 100 receives a verification trigger signal from the low-performance flash memory block 1031, the controller 101 provides a low level to the control end of the control tube Q1 in the first power supply circuit of the vacant low-performance flash memory block 1031, the control tube Q1 is turned off, the first power supply circuit is turned off, the second power supply circuit is turned on, and the power supply voltage of the vacant low-performance flash memory block 1031 is equal to the weak voltage. That is, the power supply voltage of the vacant low-performance flash memory block 1031 is reduced from the standard voltage to the weak voltage.

[0079] It should be noted that when verifying low-performance flash memory blocks, not all low-performance flash memory blocks are verified, but only vacant low-performance flash memory blocks are verified to avoid damage to data in low-performance flash memory blocks that have stored data.

[0080] See also Figure 2 and Figure 3 As shown, in the present application, when verifying an empty low-performance flash memory block, the power supply voltage of the empty low-performance flash memory block is reduced from the standard voltage to the weak voltage, which can worsen the environment for storing data in the low-performance flash memory block, make it easier to test the quality of the low-performance flash memory block when writing data, and avoid the low-performance flash memory block with quality deviation from switching back to normal working mode.

[0081] See also Figure 3 As shown, in one embodiment of the present invention, steps S140 to S190 are a process of performing multiple verifications on the vacant low-performance flash memory blocks, and steps S140 to S150 are a process of performing one verification on the vacant low-performance flash memory blocks.

[0082] See also Figure 3 As shown, in one embodiment of the present invention, in step S140, during the verification of the vacant low-performance flash memory block, after the vacant low-performance flash memory block is switched from the pseudo single-layer cell mode to the normal operating mode, the data written into the vacant low-performance flash memory block is repeated fixed data, which facilitates detection of whether the repeated fixed data written into the low-performance flash memory block is correct. Specifically, the repeated fixed data written is, for example, 5a5a5a5a.

[0083] See also Figure 2 and Figure 3 As shown, in one embodiment of the present invention, after executing step S140 to write data into the low-performance flash memory block 1031, the controller 101 is used to trigger the control transistor Q1 to turn on, so that the power supply voltage of the low-performance flash memory block 1031 returns to the standard voltage. The weak voltage is only used when writing repeated fixed data into the low-performance flash memory block 1031.

[0084] See also Figure 3 As shown, in one embodiment of the present invention, in step S150, the specific method for verifying whether the flash memory block meets the verification standard based on the data written to the low-performance flash memory block is as follows: determining whether the number of error data bits in the low-performance flash memory block exceeds a preset ratio; if the number of error data bits in the low-performance flash memory block exceeds the preset ratio, the low-performance flash memory block does not meet the verification standard; if the number of error data bits in the low-performance flash memory block does not exceed the preset ratio, the low-performance flash memory block meets the verification standard. The preset ratio ranges from 20% to 40%, and specifically is 30%, 35%, or 40%.

[0085] See also Figure 3As shown, in one embodiment of the present invention, when a low-performance flash memory block meets the verification criteria, the number of times the low-performance flash memory block meets the verification criteria is recorded. After the low-performance flash memory block meets the verification criteria a preset number of times, the low-performance flash memory block is switched to a normal operating mode and used as a regular flash memory block. The preset number of times is, for example, 3 to 5, specifically, 3, 4, or 5 times.

[0086] See also Figure 3 As shown, in one embodiment of the present invention, if after each vacant low-performance flash memory block is switched from the pseudo-single-layer cell mode to the normal working mode and data is written into the low-performance flash memory block, it is immediately verified whether the low-performance flash memory block meets the verification standard, then the verification is frequent. And regardless of whether the low-performance flash memory block meets the verification standard, it is necessary to erase the repeated fixed data written in the low-performance flash memory block. Therefore, in the present invention, after the vacant low-performance flash memory block is switched from the pseudo-single-layer cell mode to the normal working mode and data is written into the low-performance flash memory block, it is monitored whether the remaining capacity of the storage chip is less than the third threshold value. When the remaining capacity of the storage chip is less than the third threshold value, it is verified whether the low-performance flash memory block meets the verification standard. The third threshold value is, for example, 50Mb. At this time, multiple low-performance flash memory blocks can be verified simultaneously.

[0087] See also Figure 3 As shown, in one embodiment of the present invention, after each verification is completed, whether step S180 is executed and the low-performance flash memory block is used as a regular flash memory block, or step S190 is executed and the storage unit in the low-performance flash memory block is switched from the normal working mode to the pseudo single-layer cell mode and the low-performance flash memory block is kept in the pseudo single-layer cell mode, or step S130 is returned to monitor the verification trigger signal of the low-performance flash memory block, it is necessary to erase the duplicate fixed data written in the low-performance flash memory block.

[0088] See also Figure 3 As shown, in one embodiment of the present invention, in step S180, since the low-performance flash memory block has been switched from the pseudo single-layer cell mode to the normal operating mode during the verification process, it is only necessary to delete the pseudo single-layer cell mode mark of the low-performance flash memory block in the physical address management table of the firmware, and the low-performance flash memory block can be used as a regular flash memory block 1031.

[0089] See also Figure 3 As shown, in one embodiment of the present invention, in step S190, after the storage cells in the low-performance flash memory block are switched from the normal operating mode to the pseudo single-layer cell mode, the pseudo single-layer cell mode flag of the low-performance flash memory block can be set as a fixed flag in the physical address management table of the firmware. During the cyclic verification process of the low-performance flash memory block, the verification of the low-performance flash memory block is skipped, and the low-performance flash memory block is kept in the pseudo single-layer cell mode.

[0090] See also Figure 1 and Figure 5 As shown, an embodiment of the present application provides a storage system including a storage chip 100 and an electronic device, wherein the electronic device includes a processor 301 and a program stored in a memory 302 and executable on the processor, wherein the processor executes and implements the above-mentioned flash memory block management method. The electronic device is, for example, integrated into a host 200 or is the host 200.

[0091] See also Figure 5 As shown, the memory 302 includes at least one type of readable storage medium, including a flash memory, a mobile hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory can be an internal storage unit of the electronic device, such as a mobile hard disk of the electronic device. In other embodiments, the memory can also be an external storage device of the electronic device, such as a plug-in mobile hard disk, a smart memory card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device. Furthermore, the memory can also include both an internal storage unit of the electronic device and an external storage device. The memory can be used not only to store application software installed in the electronic device and various types of data, but also to temporarily store data that has been output or is about to be output.

[0092] See also Figure 5 As shown, in some embodiments, the processor 301 may be comprised of an integrated circuit, such as a single packaged integrated circuit or multiple packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and a combination of various control chips. The processor is the control core (Control Unit) of the vehicle-mounted device, connecting the various components of the vehicle-mounted device via various interfaces and circuits. It executes programs or modules stored in the memory and accesses data stored in the memory to perform various functions of the vehicle-mounted device and process data.

[0093] The processor executes the operating system of the vehicle-mounted device and various installed application programs. The processor executes the application programs to implement the steps in the above method embodiment.

[0094] For example, the program may be divided into one or more modules, which are stored in the memory and executed by the processor to implement the present invention. The one or more modules may be a series of program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the program in the in-vehicle device.

[0095] The above-mentioned integrated unit implemented in the form of a software functional module can be stored in a computer-readable storage medium. The above-mentioned software functional module stored in a storage medium includes a number of instructions for causing a computer device (which can be a personal computer, computer equipment, or network equipment, etc.) or a processor to perform some of the functions of the lithium battery cold solder joint detection method according to various embodiments of the present invention.

[0096] In summary, a flash memory block management method and storage system are provided, which include: when the number of erroneous data in the flash memory page in the flash memory block exceeds a set threshold, adjusting the operating mode of the flash memory block from the normal operating mode to the pseudo single-layer unit mode to form a low-performance flash memory block; upon receiving a verification trigger signal for the low-performance flash memory block, reducing the power supply voltage of the vacant low-performance flash memory block from the standard voltage to the weak voltage, switching the vacant low-performance flash memory block from the pseudo single-layer unit mode to the normal operating mode, and writing data to the vacant low-performance flash memory block to verify whether the low-performance flash memory block meets the verification standard; and repeatedly verifying whether the low-performance flash memory block meets the verification standard. When the number of times the low-performance flash memory block meets the verification standard reaches a preset number, the low-performance flash memory block is used as a regular flash memory block. The flash memory block management method and storage system provided by the present application can extend the life of the storage chip.

[0097] The embodiments of the present invention disclosed above are intended only to illustrate the present invention. They do not describe all details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A flash memory block management method, characterized in that: At least the following steps are included: When the number of erroneous data in the flash memory page in the flash memory block exceeds a set threshold, the operating mode of the flash memory block is adjusted from the normal operating mode to the pseudo single-layer cell mode to form a low-performance flash memory block; Upon receiving a verification trigger signal of a low-performance flash memory block, reducing the power supply voltage of the vacant low-performance flash memory block from a standard voltage to a weak voltage, switching the vacant low-performance flash memory block from a pseudo single-layer cell mode to a normal operating mode, and writing data into the vacant low-performance flash memory block to verify whether the low-performance flash memory block meets the verification standard; as well as Repeatedly verifying whether the low-performance flash memory block meets the verification standard, and when the number of times the low-performance flash memory block meets the verification standard reaches a preset number, using the low-performance flash memory block as a normal flash memory block.

2. The flash memory block management method according to claim 1, wherein: When the low-performance flash memory block fails to meet the verification standard, the low-performance flash memory block is switched from the normal operating mode to the pseudo single-layer cell mode, and the low-performance flash memory block is kept in the pseudo single-layer cell mode.

3. The flash memory block management method according to claim 1, wherein: Forming the low-performance flash memory block includes the following steps: Detect the remaining capacity of the memory chip; If the capacity of the memory chip is greater than or equal to a first threshold, the data in the flash memory block is moved to an idle flash memory block, and the storage unit of the flash memory block is switched from a normal working mode to a pseudo single-layer unit mode to form the low-performance flash memory block; If the capacity of the memory chip is less than a first threshold, a garbage collection flag is set to perform garbage collection until the capacity of the memory chip is greater than a second threshold, and then the data in the flash memory block is moved to an idle flash memory block, and the storage unit of the flash memory block is switched from a normal working mode to a pseudo single-layer unit mode to form the low-performance flash memory block; The second threshold is greater than the first threshold.

4. The flash memory block management method according to claim 1, wherein: The verification trigger signal is a power signal or a time signal; When the verification trigger signal is a power signal, when the number of times the memory chip is powered on reaches a set number, the host sends the verification trigger signal to the memory chip; When the verification trigger signal is a time signal, when the system time reaches a set time, the host sends the verification trigger signal to the storage chip.

5. The flash memory block management method according to claim 1, wherein: The flash memory block is provided with a first power supply circuit and a second power supply circuit, the first power supply circuit outputs the standard voltage, and the second power supply circuit outputs the weak voltage.

6. The flash memory block management method according to claim 5, characterized in that: The first power supply circuit includes: Power supply; and a control tube, one end of which is electrically connected to the power supply, the other end of which is electrically connected to the power supply end of the flash memory block, and the control end of which is electrically connected to the controller of the memory chip; When the memory chip is in a normal working mode, the controller outputs a high level, the control tube is turned on, and the first power supply circuit provides a standard voltage for the flash memory block.

7. A flash memory block management method according to claim 6, characterized in that: The second power supply circuit includes: the power supply; and a diode, wherein the anode of the diode is electrically connected to the power supply, and the cathode of the diode is electrically connected to the power supply end of the flash memory block; When the storage chip receives the verification trigger signal of the low-performance flash memory block, the controller provides a low level to the control end of the control tube in the first power supply circuit of the vacant low-performance flash memory block, the control tube is cut off, the first power supply circuit is cut off, and the second power supply circuit is turned on, and the second power supply circuit provides a weak voltage for the vacant low-performance flash memory block.

8. The flash memory block management method according to claim 1, wherein: Writing data into the vacant low-performance flash memory block to verify whether the low-performance flash memory block meets the verification standard includes the following steps: Repeated fixed data is written into the vacant low-performance flash memory block, and it is determined whether the number of erroneous data bits in the low-performance flash memory block exceeds a preset ratio. If the number of erroneous data bits in the low-performance flash memory block exceeds the preset ratio, the low-performance flash memory block does not meet the verification standard. If the number of erroneous data bits in the low-performance flash memory block does not exceed the preset ratio, the low-performance flash memory block meets the verification standard.

9. The flash memory block management method according to claim 8, characterized in that: After writing data into the vacant low-performance flash memory block, monitor whether the remaining capacity of the storage chip is less than a third threshold. When the capacity of the storage chip is less than the third threshold, determine whether the number of erroneous data bits in the low-performance flash memory block exceeds a preset ratio.

10. A storage system, characterized in that: The storage system includes an electronic device, and the electronic device includes: a memory storing program instructions; and A processor runs the program instructions to implement the flash memory block management method according to any one of claims 1 to 9.

11. The storage system according to claim 10, wherein: The storage system includes a storage chip, and the storage chip includes: Flash blocks; a first power supply circuit, wherein the first power supply circuit includes a power supply and a control tube, one end of the control tube is electrically connected to the power supply, the other end of the control tube is electrically connected to the power supply end of the flash memory block, and the control end of the control tube is electrically connected to the controller of the memory chip; and A second power supply circuit includes the power supply and a diode, wherein the anode of the diode is electrically connected to the power supply, and the cathode of the diode is electrically connected to the power supply end of the flash memory block.

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