Multi-event synchronous snapshot method and circuit of HPM under RISC-V architecture

Abstract

The invention discloses a multi-event synchronous snapshot method and circuit of an HPM under an RISC-V architecture. The method comprises the following steps: triggering a synchronous snapshot mechanism; event relevance classification and relevance event screening; and performing non-blocking type snapshot reading. The processing circuit comprises a snapshot controller and a snapshot register block, wherein the snapshot controller and the snapshot register block are integrated in a PMU (Power Management Unit); the snapshot controller is used for triggering detection of a synchronous snapshot mechanism, selecting related events when the synchronous snapshot mechanism is triggered, generating freezing signals and writing the freezing signals into the snapshot register group; and the snapshot register group is used for storing all the selected correlation event counter data when the freezing signal is valid. According to the method, information at different moments cannot be read by reading event information with correlation during performance analysis, the field of events of the same type is stored in a snapshot mode, it is ensured that correlated event data is captured at the same moment, time sequence errors are eliminated, and the accuracy of performance analysis is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-performance chip design, and particularly to a multi-event synchronous snapshot method and circuit for HPM under the RISC-V architecture. Background Art

[0002] A hardware performance counter (HPC) is a built-in counter commonly found in modern microprocessors, used to store hardware-related event information. These events typically include the number of clock cycles, the number of executed instructions, the number of branch prediction failures, the number of misses / hits in each level of cache (Cache), the number of misses / hits in the TLB (Translation Look-aside Buffer), etc.

[0003] According to the RISC-V privileged instruction specification, the processor provides two types of counters: fixed counters and programmable counters. Among them, two fixed counters are respectively used to count the number of clock cycles and the number of executed instructions, and the remaining twenty-nine are programmable counters, which can be used to capture selected events and complete counting. The selection of events is controlled by the Machine Performance-Monitoring Event Selector (Mhpmevent) register specified in the RISC-V privileged document, and one or several events can be selected.

[0004] In traditional methods, when using a performance analysis tool for performance analysis, the CSR instruction is used to read the corresponding event counter to obtain the corresponding data information. Usually, a set of related event counter information is read for performance analysis. For example, to calculate the accuracy rate of branch prediction, the number of executed instructions and the number of branch prediction failures need to be obtained simultaneously. This requires executing two CSR instructions to read the counters of the corresponding events. The first CSR instruction reads the number of branch prediction failures, and the second CSR instruction reads the number of instruction retirements. The performance analysis tool obtains two sets of data, and the accuracy rate information of branch prediction can be obtained through calculation. If more performance information is required, multiple CSR instructions need to be executed to read the corresponding performance counters.

[0005] Using this information can more efficiently monitor the system state, efficiently utilize hardware resources, reasonably manage power consumption, and optimize the computer system structure. Therefore, almost all modern processors are configured with this counter.

[0006] In the prior art, performance analysis requires reading multiple counters sequentially through multiple CSR (Control and Status Register) instructions. However, due to the continuous update of the counters, the difference in the read timestamps of related events will cause data deviation. For example, when calculating the branch prediction accuracy rate, it is necessary to read the "number of branch failures" and the "number of instructions retired" simultaneously. However, the counters have been updated during the interval between the two reads, resulting in inaccurate analysis results. The prior art lacks a multi-event synchronous capture mechanism, which limits the accuracy of performance analysis. Summary of the Invention

[0007] The object of the present invention is to provide a technical solution for the multi-event synchronous snapshot method and circuit of HPM under the RISC-V architecture in view of the deficiencies of the prior art. By reading relevant event information during performance analysis, information at different times will not be read. The scene of the same type of event is saved in the form of a snapshot to ensure that the associated event data is captured at the same moment, eliminate timing errors, and improve the accuracy of performance analysis. It can be applied to scenarios such as processor performance tuning and real-time system monitoring that require precise associated event analysis.

[0008] In order to solve the above technical problems, the present invention adopts the following technical solutions: A multi-event synchronous snapshot method for HPM under the RISC-V architecture, characterized by including the following steps: Step1. Trigger the synchronous snapshot mechanism; Step2. Classify event relevance and screen relevant events; Step3. Non-blocking snapshot reading.

[0009] A multi-event synchronous snapshot processing circuit for HPM under the RISC-V architecture, characterized in that: it includes a snapshot controller and a snapshot register group, and the snapshot controller and the snapshot register group are integrated in the PMU; The snapshot controller is used for triggering detection of the synchronous snapshot mechanism, selecting relevant events when triggering the synchronous snapshot mechanism, and generating a freeze signal to write to the snapshot register group; The snapshot register group is used for saving all the selected relevant event counter data when the freeze signal is valid.

[0010] Due to the adoption of the above technical solutions, the present invention has the following beneficial effects: By reading relevant event information during performance analysis, information at different times will not be read. The scene of the same type of event is saved in the form of a snapshot to ensure that the associated event data is captured at the same moment, eliminate timing errors, and improve the accuracy of performance analysis. It can be applied to scenarios such as processor performance tuning and real-time system monitoring that require precise associated event analysis. Description of the Drawings

[0011] The present invention will be further described below with reference to the accompanying drawings: Figure 1 It is a flowchart of the multi - event synchronous snapshot method of HPM under the RISC - V architecture of the present invention and the multi - event synchronous snapshot method in the circuit; Figure 2 It is a flowchart of the execution of the synchronous snapshot mechanism in the present invention; Figure 3 It is a circuit block diagram of the synchronous snapshot mechanism in the present invention. Specific embodiments

[0012] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0013] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0014] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above - mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non - exclusive inclusion.

[0015] Glossary of technical terms recorded in the present invention: .

[0016] As Figure 1 and Figure 2 shown, the multi - event synchronous snapshot method of HPM under the RISC - V architecture of the present invention includes the following steps: Step1. Trigger the synchronous snapshot mechanism; The triggering of the synchronous snapshot mechanism specifically includes: automatically detecting the CSR instruction to read the event counter. When it is necessary to trigger the synchronous snapshot mechanism to generate a freeze signal, ensure that the associated counter synchronously pauses updating, and store the current value into the snapshot register bank.

[0017] When automatically detecting the CSR instruction to read the event counter: If there is no current snapshot, or the event group stored in the snapshot does not include the current event, trigger the synchronous snapshot mechanism, store all current relevant counters into the snapshot register bank, and complete the reading of event information; If the current snapshot exists and the current event is stored in the snapshot, directly read the corresponding information in the snapshot register bank to complete the event reading.

[0018] Step2. Event correlation classification and relevant event screening; Event correlation classification and relevant event screening specifically include: according to the function or physical characteristics of the event, allocate relevant events to a group, assign a group number to each event group, automatically identify the associated event group based on the group number of the event coding rule, and store all the event data with the same group number into the snapshot register bank.

[0019] Step3. Non-blocking snapshot reading.

[0020] Non-blocking snapshot reading specifically includes: if the CSR instruction reads an event belonging to the event group stored in the current snapshot group, directly return the snapshot data to avoid repeatedly freezing the counter; if it is a non-associated event, trigger the generation of a new snapshot.

[0021] As Figure 3 shown, the multi-event synchronous snapshot processing circuit of HPM under the RISC-V architecture of the present invention includes a snapshot controller and a snapshot register bank, and the snapshot controller and the snapshot register bank are integrated in the PMU; The snapshot controller is used to synchronously detect the trigger of the snapshot mechanism, select relevant events when triggering the synchronous snapshot mechanism, and generate a freeze signal to write into the snapshot register bank; Selecting relevant events when triggering the synchronous snapshot mechanism for identification and classification according to the event classification rule specifically includes: according to the function or physical characteristics of the event (such as cache event, branch prediction event, etc.), allocate relevant events to a group, assign a group number (Group ID) to each event group, automatically identify the associated event group based on the group number of the event coding rule, and store all the event data with the same group number into the snapshot register bank.

[0022] The snapshot controller includes a snapshot event control register, a freeze signal generator, and a snapshot event selector; The snapshot event control register is implemented by a 1-bit control register and a 4-bit data register, and is used to update the data register according to the control bit of the control register; Updating the data register according to the control bit of the control register specifically includes: when the control register is 0, no snapshot information is saved; when the control register is 1, snapshot information is saved, and the data register saves the group number of the snapshot event.

[0023] A freeze signal generator is used to detect whether the snapshot event control register is valid when the CSR instruction is at the execution level and reads the performance counter, and to determine whether the stored event group is the same as the currently read event group. If the snapshot event is not saved, a freeze signal is generated for snapshot event screening and snapshot register group update. A snapshot event selector is used to select all relevant events when the freeze signal is valid.

[0024] When selecting all relevant events, the group number (Group ID) saved in the Mhpmevent register read by the current CSR instruction is read, and all Mhpmevents corresponding to this group number are selected.

[0025] For example, the L1 cache event group can be defined as Group 0, the branch prediction event can be defined as Group 1, …… The group number is configured through the reserved bit of Mhpmevent, and relevant events are automatically identified and classified by the snapshot-related event selector.

[0026] The trigger process of the synchronous snapshot mechanism includes the following steps: When the hardware detects that the CSR instruction reads the performance counter MhpmcounterX, it will read the control register of the snapshot event control register.

[0027] If the control bit is 0, it means that no snapshot information is currently saved. A freeze signal is generated, and the counter information read by the CSR instruction and the relevant performance counter information are frozen and stored in the snapshot register group. The control bit of the control register is set to 1, and the group number is updated to the data register.

[0028] If the control bit is 1 and the group number of the current event saved in Mhpmevent is equal to the group number saved in the current control register, it means that the currently accessed event belongs to the already saved snapshot event, and the corresponding event counter stored in the snapshot register group is read; otherwise, a new snapshot is triggered.

[0029] If the control bit is 1 and the group number of the current event saved in Mhpmevent is not equal to the group number saved in the current control register, a freeze signal is generated, and the counter information read by the CSR instruction and the relevant performance counter information are frozen and stored in the snapshot register group. The control bit of the control register is set to 1, and the group number is updated to the data register.

[0030] A snapshot register group is used to save all selected relevant event counter data when the freeze signal is valid.

[0031] Each snapshot register in the snapshot register group consists of a control bit and a data bit. The control bit is used to determine whether the data saved in the current snapshot register is valid, and the data bit is used to save the event number of the event and the data of the corresponding performance counter.

[0032] When the snapshot register group selects data, the event counter read by the current CSR instruction is saved in the snapshot register group. The event number of the current event is read and compared with the data saved in each snapshot register. If the control bit of the selected snapshot register is 1, the data to be read is selected. If the control bit of the selected snapshot register is 0, a value of 0 is read.

[0033] The above are only specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent replacements or modifications made based on the present invention to achieve substantially the same technical effects are all covered by the protection scope of the present invention.

Claims

1. A multi-event synchronous snapshot method for HPM under the RISC-V architecture, characterized in that It includes the following steps: Step 1: Trigger the synchronous snapshot mechanism; Step 2: Classify event correlations and filter relevant events; Step 3: Non-blocking snapshot reading.

2. The multi-event synchronous snapshot method of HPM under the RISC-V architecture according to claim 1, wherein: The triggering of the synchronous snapshot mechanism in Step 1 specifically includes: Automatically detecting the CSR instruction read event counter. When it is necessary to trigger the synchronous snapshot mechanism to generate a freeze signal, ensure that the associated counter is synchronously paused from being updated, and store the current value in the snapshot register bank.

3. The multi-event synchronous snapshot method of HPM under the RISC-V architecture according to claim 2, wherein: When automatically detecting the CSR instruction read event counter: If there is no current snapshot, or the event group stored in the snapshot does not include the current event, trigger the synchronous snapshot mechanism, store all current relevant counters in the snapshot register bank, and complete the event information reading; If the current snapshot exists and the current event is stored in the snapshot, directly read the corresponding information in the snapshot register bank to complete the event reading.

4. The multi-event synchronous snapshot method of HPM under the RISC-V architecture according to claim 1, wherein: The classification of event correlations and the filtering of relevant events in Step 2 specifically include: According to the function or physical characteristics of the events, allocate relevant events into a group, assign a group number to each event group, automatically identify the associated event group based on the group number of the event coding rule, and store all the event data with the same group number in the snapshot register bank.

5. The multi-event synchronous snapshot method of HPM under the RISC-V architecture according to claim 1, characterized in that: The non-blocking snapshot reading in Step 3 specifically includes: If the CSR instruction read event belongs to the event group stored in the current snapshot group, directly return the snapshot data to avoid repeatedly freezing the counter; if it is a non-associated event, trigger the generation of a new snapshot.

6. The multi-event synchronous snapshot processing circuit of HPM under the RISC-V architecture, characterized in that: It includes a snapshot controller and a snapshot register bank, and the snapshot controller and the snapshot register bank are integrated in the PMU; The snapshot controller is used for triggering detection of the synchronous snapshot mechanism, selecting relevant events when triggering the synchronous snapshot mechanism, and generating a freeze signal to write into the snapshot register bank; The snapshot register bank is used for saving all the selected relevant event counter data when the freeze signal is valid.

7. The multi-event synchronous snapshot processing circuit of HPM under the RISC-V architecture according to claim 6, wherein: The snapshot controller includes a snapshot event control register, a freeze signal generator, and a snapshot event selector; The snapshot event control register is implemented by a 1-bit control register and a 4-bit data register, and is used to update the data register according to the control bit of the control register; The freeze signal generator is used for detecting whether the snapshot event control register is valid when the CSR instruction is at the execution level and reading the performance counter, and judging whether the stored event group is the currently read event group. If the snapshot event is not saved, generate a freeze signal for snapshot event filtering and snapshot register bank update; The snapshot event selector is used for selecting all relevant events when the freeze signal is valid.

8. The multi-event synchronous snapshot processing circuit of HPM under the RISC-V architecture according to claim 7, characterized in that: Updating the data register according to the control bit of the control register specifically includes: When the control register is 0, no snapshot information is saved; when the control register is 1, snapshot information is saved, and the data register saves the group number of the snapshot event.

9. The multi-event synchronous snapshot processing circuit of HPM under the RISC-V architecture according to claim 7, characterized in that: When selecting all relevant events, read the group number saved in the Mhpmevent register read by the current CSR instruction, and select all the counters corresponding to the Mhpmevent with this group number.

10. The multi-event synchronous snapshot processing circuit of HPM under the RISC-V architecture according to claim 6, characterized in that: When triggering the synchronous snapshot mechanism, relevant events are selected and identified and classified according to the event classification rules, specifically including: according to the function or physical characteristics of the events, relevant events are assigned to a group, a group number is assigned to each event group, the associated event group is automatically identified based on the group number of the event coding rule, and the event data with the same group number is stored in the snapshot register group in its entirety.

11. The multi-event synchronous snapshot processing circuit of HPM under the RISC-V architecture according to claim 6, characterized in that: Each snapshot register in the snapshot register group consists of a control bit and a data bit. The control bit is used to determine whether the data saved in the current snapshot register is valid, and the data bit is used to save the event number of the event and the data of the corresponding performance counter.

12. The multi-event synchronous snapshot processing circuit of the HPM under the RISC-V architecture according to claim 11, characterized in that: When the snapshot register group performs data selection, the event counter read by the current CSR instruction is saved in the snapshot register group. The event number of the current event is read and compared with the data saved in each snapshot register. If the control bit of the selected snapshot register is 1, the data to be read is selected. If the control bit of the selected snapshot register is 0, a value of 0 is read.

Images