Multifunctional improved branch recording buffer system

Abstract

The invention provides a multifunctional improved branch record buffering system, which belongs to the technical field of CPU buffering and comprises a BRB hardware structure and a BRB hardware working process. The BRB hardware comprises a branch key information recording link and a multi-pointer collaborative management link; a work flow of BRB hardware comprises the following steps of S1, an allocation stage step, S2, an analysis stage step, S3, a submitting and releasing step and S4, an error processing step, the steps comprise a prediction error triggering link and an assembly line rollback link, and aiming at the problem that rollback and error positioning are difficult in a branch prediction management system in traditional CPU out-of-order execution, the method is simple and convenient to operate, and the efficiency is high. According to the invention, correct update data is uniformly sent to the BPU through the BRB, and when encountering a wrong branch, the BRB can accurately roll back and clear the entries of the younger branch.

Description

Technical Field

[0001] The present invention relates to the technical field of CPU buffering, and particularly to a multifunctional improved branch record buffering system. Background Art

[0002] Currently, as the demand for CPU performance continues to increase, higher requirements are also put forward for branch prediction performance. Currently, in order to maximize performance, many high-end CPU execution units parse branch instructions in an out-of-order manner, which brings the following problems: Uncertainty in updating components of the branch prediction unit: Traditional branch prediction structures assume that branches are parsed in order and the results are written back to the branch prediction unit (BPU). However, when out-of-order parsing occurs, it may cause younger but incorrect branches to update the BPU first, wasting prediction resources and potentially reducing the prediction accuracy.

[0003] Dispersed branch information and complex management: During the process from instruction fetching to final submission of a branch instruction, multiple prediction-related components (such as the global history register GHR, BTB, return address stack RAS, etc.) are accessed and updated. Lack of unified management easily leads to confusion in updating and rollback in out-of-order branches.

[0004] The need for rapid rollback and error location: When a branch prediction error occurs, the pipeline needs to be flushed and rolled back to the correct branch. Without unified recording of all branch information and the ability to quickly locate the position of the error branch, a large number of clock cycles are wasted, reducing the throughput efficiency of the processor.

[0005] The branch prediction management system in traditional CPU out-of-order execution has the following problems: 1. Prediction update confusion: When a younger branch completes first, it may incorrectly update the branch prediction unit (BPU), reducing the prediction accuracy.

[0006] 2. Dispersed branch information: Branch-related data (such as target addresses, historical records, etc.) are scattered in multiple components (BTB, RAS, GHR, etc.), making management complex.

[0007] 3. Low rollback efficiency: When a prediction error occurs, it takes multiple cycles to locate the error branch, dragging down the pipeline efficiency.

[0008] 4. Inability to balance out-of-order parsing and branch prediction update: When a younger branch completes first, it often needs to wait for the result of an older branch, or incorrect updates are written to the BPU first.

[0009] 5. Difficulty in rollback and error location: If a branch prediction error occurs, a large amount of searching or multiple pipeline signal interactions are required to find the original error branch.

[0010] 6. Lack of centralized management: Information related to branch prediction (branch type, target PC, direction information, history information, whether it is a mispredicted path, etc.) is often scattered in different components, which is not conducive to fast scheduling and resource reuse.

[0011] Modern CPUs increasingly adopt 4-way issue, 6-way issue, or even wider issue widths, which means that multiple instructions, including multiple branches, may be issued per cycle. The execution units may parse branch instructions in the order of actual completion time, not necessarily following the program order. This poses a challenge to the branch predictor components that need to be updated serially. A typical BPU contains various components such as BTB, branch predictor, return address stack (RAS), global history register (GHR), etc. Once a branch is parsed, the above resources need to be updated. Without unified management, it is easy to have incorrect writes, repeated updates, or resource waste.

[0012] The present invention proposes a multifunctional improved branch record buffer system to solve problems such as lack of unified management, easy occurrence of incorrect writes, repeated updates, or resource waste. Summary of the Invention

[0013] The present invention can centrally manage the branch information of all in-flight branches between the CPU front-end fetch unit and the execution unit, arbitrate the branch parsing order, update the BPU components, and precisely perform rollback processing when needed, thereby effectively improving the branch prediction accuracy and pipeline efficiency, and overcoming the problems in the above background technology.

[0014] Based on the above technical idea, the technical solution adopted by the present invention is as follows: A multifunctional improved branch record buffer system, including the BRB hardware structure and the working process of the BRB hardware; The BRB hardware includes a link for recording branch key information and a link for collaborative management by multiple pointers; The working process of the BRB hardware includes the following steps: Step S1: Allocation stage, which includes a link for the fetch unit to detect branches and a link for processing unrecognized branches; Step S2: Parsing stage, which includes a link for the execution unit to give feedback and a link for ensuring sequentiality; Step S3: Submission and release, which includes a link for the ROB to submit branch instructions and a link for resource release; Step S4: Error handling, which includes a link for triggering prediction errors and a link for pipeline rollback.

[0015] For further limitation of the above technical solution, the link for recording branch key information includes defining entry fields, and the field definitions include the following fields: Branch PC: The branch instruction address, which is used to match the branch resolution result returned by the execution unit; BrType: Branch type; Predicted Target: Predicted target address; Actual Target: The actual target address after the execution unit resolves the branch; Direction: Actual jump direction; BP Info: Additional information relied on by the predictor; Resolve Status: Marks the status of the entry; Checkpoint: Saves the critical status of the BPU before branch resolution.

[0016] For further limitation of the above technical solution, the multi-pointer collaborative management link includes: Branch Pointer: Points to the oldest branch entry that needs to be updated. Update condition: The execution unit sends a valid branch resolution signal and the branch is the entry pointed to by the pointer; Deallocation Pointer: Points to the oldest entry that can be released. Advancement condition: The branch has been committed and the BPU update is completed; Early Flush Pointer: Dynamically points to the earliest branch that may be incorrect. Clear range: All entries after this pointer; Commit Pointer: Advancement condition: The branch is committed through the reorder buffer and there is no exception.

[0017] For further limitation of the above technical solution, in the S1 allocation stage step, the instruction fetch unit's branch detection link includes pre-decoding to identify branch instructions, allocating idle BRB entries, and writing the Branch PC, BrType, and prediction information provided by the BPU. The unrecognized branch processing link includes that if the branch prediction unit does not predict a branch, still allocate BRB entries, mark the prediction information as invalid, and wait for the execution unit to supplement.

[0018] For further limitation of the above technical solution, in the S2 parsing stage step, the execution unit feedback link includes sending resolve_pc, actual_target, and direction signals, and the BRB matches the entry through the Branch PC and updates the Actual Target and Direction fields.

[0019] For further limitation of the above technical solution, the sequential guarantee link includes that if the parsed branch is not the entry currently pointed to by the BranchPointer, only the entry content is updated, and the BPU update is not triggered. When the Branch Pointer moves to this entry, the BPU update arbitration is triggered.

[0020] For further limitation of the above technical solution, in the S3 submission and release step, the ROB submission of the branch instruction link in this step includes sending a commit_pc signal, and the BRB marks the corresponding entry as "submitted", and advances the Commit Pointer to the next parsed but unsubmitted entry; the resource release link includes that when the entry pointed to by the Deallocation Pointer has been submitted and the BPU update is completed, the entry is released to the release queue.

[0021] For further limitation of the above technical solution, in the S4 error handling step, the prediction error trigger link in this step includes that the BPU or the execution unit sends a pc signal of the branch instruction with an error prediction, and the BRB locates the error branch entry through binary search or hardware-accelerated matching; the pipeline rollback link includes activating the Early Flush Pointer, clearing all subsequent entries, and if a Checkpoint is saved, restoring the branch prediction unit to the state before the error branch.

[0022] For further limitation of the above technical solution, it further includes a key circuit design, and the key circuit design includes a parallel matching logic and a performance optimization design. The parallel matching logic includes a PC matcher and a priority encoder. The PC matcher includes a comparator in the BRB entry, which parallelly matches the branch parsing pc or the error prediction pc. The priority encoder includes converting multiple matching results into the index of the entry with the highest priority.

[0023] For further limitation of the above technical solution, the performance optimization design includes that when the gap between the Deallocation Pointer and the Branch Pointer exceeds a threshold, some entries are pre-released to support priority allocation.

[0024] Compared with the prior art, the beneficial effects of the present invention are: 1. By setting up a unified branch record buffer BRB in the CPU front-end / mid-end stage, all branch instruction information in the pipeline is centrally recorded and managed.

[0025] 2. The BRB is provided with several pointers (pointers) for tracking the branch parsing order, recyclable entries, and the clearing range in case of early flush during pre-decoding.

[0026] 3. When a branch is parsed or committed, the BRB uniformly sends the correct updated data to the BPU and can accurately roll back and clear younger branch entries when an error branch is encountered. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 Schematic diagram of the improved BRB structure in a multifunctional improved branch record buffer system of the present invention; Figure 2 Schematic diagram of the process of the multi-pointer management mechanism in a multifunctional improved branch record buffer system of the present invention. Detailed Embodiments

[0029] The following will further elaborate on the present invention in conjunction with the attached Figure 1 - Figure 2 drawings.

[0030] Embodiment 1: This embodiment provides a multifunctional improved branch record buffer system, as Figure 1 - Figure 2 shown, including the BRB hardware structure and the working process of the BRB hardware; The BRB hardware includes a link for recording branch key information and a link for collaborative multi-pointer management; The working process of the BRB hardware includes the following steps: S1 Allocation stage step, which includes a branch detection link by the instruction fetch unit and an unrecognized branch processing link; S2 Parsing stage step, which includes an execution unit feedback link and a sequentiality guarantee link; S3 Commit and release step, which includes a branch instruction commit link in the instruction reorder buffer and a resource release link; S4 Error handling step, which includes a predicted error trigger link and a pipeline rollback link.

[0031] The link for recording branch key information includes the definition of entry fields, and the field definitions include the following fields: Branch PC: Branch instruction address, used to match the parsing result returned by the execution unit; BrType: Branch type; Predicted Target: Predicted target address; Actual Target: The actual target address after the execution unit parses the branch; Direction: The actual jump direction; BP Info: Additional information relied on by the predictor; Resolve Status: Marks the status of the entry; Checkpoint: Saves the key status of the branch prediction unit before branch resolution.

[0032] The multi-pointer collaborative management link includes: Branch Pointer: Points to the oldest branch entry that needs to be updated currently. Update condition: The execution unit sends a valid signal for branch resolution and this branch is the entry pointed to by the pointer; Deallocation Pointer: Points to the oldest entry that can be released. Advancement condition: The branch has been committed and the BPU update is completed; Early Flush Pointer: Dynamically points to the earliest branch that may be incorrect. Clear range: All entries after this pointer; Commit Pointer: Advancement condition: The branch is committed through the reorder buffer and there is no exception.

[0033] In the steps of the S1 allocation stage, the branch detection link in the instruction fetch unit includes pre-decoding to identify branch instructions, allocating idle BRB entries, and writing the Branch PC, BrType, and prediction information provided by the BPU. The unrecognized branch processing link includes that if the branch prediction unit does not predict a branch, still allocate BRB entries, mark the prediction information as invalid, and wait for the execution unit to supplement.

[0034] In the steps of the S2 parsing stage, the feedback link of the execution unit includes sending resolve_pc, actual_target, and direction signals, and the BRB matches the entry through the Branch PC and updates the Actual Target and Direction fields.

[0035] The sequentiality guarantee link includes that if the resolved branch is not the entry currently pointed to by the Branch Pointer, only update the entry content and do not trigger the update of the branch prediction unit. When the Branch Pointer moves to this entry, trigger the update arbitration of the branch prediction unit.

[0036] The S3 submission and release step. In this step, the ROB submission branch instruction link includes sending a commit_pc signal, the BRB marks the corresponding entry as "submitted", and advances the Commit Pointer to the next parsed but unsubmitted entry; the resource release link includes releasing the entry to the release queue when the entry pointed to by the Deallocation Pointer has been submitted and the branch prediction unit update is completed.

[0037] The S4 error handling step. In this step, the prediction error trigger link includes the branch prediction unit or the execution unit sending a branch pc signal of prediction error, and the BRB locates the error branch entry through binary search or hardware-accelerated matching; the pipeline rollback link includes activating the Early Flush Pointer, clearing all subsequent entries, and if a Checkpoint is saved, restoring the BPU to the state before the error branch.

[0038] It also includes a key circuit design, which includes a parallel matching logic and a performance optimization design. The parallel matching logic includes a PC matcher and a priority encoder. The PC matcher includes a comparator in the BRB entry, which matches the pc of the parallel matching branch parsing or the pc of the error prediction branch. The priority encoder includes converting multiple matching results into the index of the highest priority entry.

[0039] The performance optimization design includes pre-releasing some entries when the gap between the Deallocation Pointer and the Branch Pointer exceeds a threshold, to support priority allocation.

[0040] Embodiment 2: This embodiment provides a multifunctional improved branch record buffer system, as Figure 1 - Figure 2 shown, and also includes the hardware structure of the BRB: BRB Entry: Each entry can record the PC of this branch, branch type (Br Type), target PC, branch direction (taken / not-taken), and additional information (BP Info) required by the prediction component, etc. The branch instructions in the instructions provided by the instruction fetch stage are written into the BRB after pre-decoding, ensuring that even if the branch instruction is not recognized as a branch instruction by the branch prediction unit, it can still occupy a BRB entry first; BRB Pointers: 1. Branch Pointer: Points to the branch entry that is currently being parsed or will be parsed next. After the execution unit issues a branch parsing signal, this pointer moves to the corresponding entry; 2. Deallocation Pointer: Points to the BRB entries that can be deallocated, usually one entry behind the BranchPointer. It is used to update multiple branches simultaneously and release resources when certain conditions are met. 3. Early Flush Pointer: Points to the branch position that can be flushed early. If there are early error reports in some parts of the pipeline, the entries following this pointer are cleared.

[0041] Commit Pointer: Points to the branch instructions that have been sequentially committed. This pointer indicates that the current branch instruction has been successfully committed and will not be flushed on the wrong path.

[0042] Workflow: Branch Allocation: When the IFU recognizes a branch instruction, it writes the branch information into the idle entry of the BRB. If the branch is not recognized by the BPU and there is no prediction result, it can also register and occupy a position in the BRB first, and then supplement the complete information during subsequent parsing.

[0043] Branch Update (Resolve & Retire): When the execution unit finishes executing the branch instruction, it sends a branch resolution signal to the BRB, along with the actual jump result of the current branch, and compares it with the previous prediction. If the older branches have not been updated yet, then it needs to wait for the older ones to be updated first. When it's the turn of this branch, it will determine which components in the branch prediction unit need to be updated based on the branch result recorded in the BRB, and complete the update process according to the arbitration of the read and write ports.

[0044] Flush: If a branch is determined to be on the wrong path (mis-prediction), the BRB quickly locates the entry through the EarlyFlush Pointer or Retire Pointer. Clear all the younger branches after this entry to prevent the wrong path update caused by mis-prediction.

[0045] Deallocation: When the branch is committed and the update of each component in the branch prediction unit has been completed, there is no longer a need to occupy an entry in the BRB. The BRB makes corresponding releases according to the Deallocation Pointer to allow new branch instructions to continue to be allocated to this area.

[0046] Core Functions and Effects: Maintain the sequentiality of out-of-order branch resolution: Even if the subsequent younger branches are parsed first, the BRB can still arbitrate and schedule the update order of the BPU to avoid writing in the wrong order.

[0047] Centralized branch management: All information about branch types, targets, prediction information, and parsing status is uniformly recorded in the BRB.

[0048] Fast rollback and positioning: Once an incorrect branch appears, the pipeline can be immediately cleared and rolled back.

[0049] Improve prediction accuracy and resource utilization: Avoid wasting BPU resources on young incorrect branches.

[0050] Improved BRB structure: Allow out-of-order completed branch instructions to be written to corresponding entries successively, and retain all branch information until the instruction is committed.

[0051] Multi-pointer management mechanism: Collaboratively maintain branch parsing and rollback through Branch Pointer, Deallocation Pointer, and Early Flush Pointer.

[0052] Centralized update of BPU: During branch parsing, the BRB determines how and when to update or roll back components such as the BTB, return address stack RAS, and global history register Global History.

[0053] Flush rollback: After an incorrect branch is detected, the BRB can quickly locate the correct path according to different pointers and clear younger entries, improving the error handling efficiency.

[0054] Effectively support out-of-order parsing: There is no need to force branches to be parsed in age order, thus improving the parallelism of execution units.

[0055] Accurate and fast branch rollback: Based on the management of BRB pointers, the incorrect branch can be found and the incorrect path can be removed in the shortest time.

[0056] The prediction accuracy is more guaranteed: Further mispredictions will no longer be caused by incorrect updates of BPU components due to young incorrect branches.

[0057] Unified centralized management: Aggregate all branch information in the BRB to avoid difficulties in coordinating multiple scattered structures.

[0058] Stored content: Different prediction information can be stored according to different branch predictors.

[0059] Number and logical variants of pointers: According to the depth of the processor pipeline or the maximum concurrency of branch instructions, the number of pointers can be increased or decreased, or other pointers can be added to distinguish different types of flushes.

[0060] Branch merging: If it is desired to compress the records of two branches into the same entry in some cases, the BRB structure can also be fine-tuned. However, it is necessary to ensure that the update and rollback logics are consistent.

[0061] More flexible allocation strategies: For example, in high-pressure scenarios, BRB can adopt circular buffering or priority-based allocation to reduce allocation contention.

[0062] Adaptation to other prediction components: The present invention can be paired with various branch prediction algorithms such as TAGE and GShare. It is only necessary to report the corresponding information during branch parsing.

[0063] The above content is a further detailed description of the present invention in combination with specific preferred implementation embodiments, which is convenient for those skilled in the art of this technology to understand and apply the present invention. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions.

Claims

1. A multi-functional improved branch record buffer system, characterized in that, It includes the BRB hardware structure and the working process of the BRB hardware; The BRB hardware includes a link for recording branch key information and a link for collaborative management of multiple pointers; The working process of the BRB hardware includes the following steps: The S1 allocation stage step, which includes a branch detection link in the instruction fetch unit and an unrecognized branch processing link; The S2 parsing stage step, which includes an execution unit feedback link and a sequentiality guarantee link; The S3 submission and release step, which includes a branch instruction submission link during instruction reordering and a resource release link; The S4 error handling step, which includes a prediction error trigger link and a pipeline rollback link.

2. The multifunctional improved branch record buffer system according to claim 1, wherein The link for recording branch key information includes the definition of entry fields, and the field definitions include the following fields: Branch PC: The branch instruction address, used to match the branch parsing result returned by the execution unit; BrType: The branch type; Predicted Target: The predicted target address; Actual Target: The actual target address after branch parsing by the execution unit; Direction: The actual jump direction; BP Info: Additional information dependent on the predictor; Resolve Status: Marks the entry status; Checkpoint: Saves the key status of the BPU before branch parsing.

3. The multifunctional improved branch record buffer system according to claim 2, wherein, The link for collaborative management of multiple pointers includes: Branch Pointer: Points to the oldest branch entry that needs to be updated currently. Update condition: The execution unit sends a valid parsing signal and this branch is the entry pointed to by the pointer; Deallocation Pointer: Points to the oldest entry that can be released. Advancement condition: The branch has been submitted and the BPU update is completed; Early Flush Pointer: Dynamically points to the branch that may be in error earliest. Clear range: All entries after this pointer; Commit Pointer: Advancement condition: The branch is submitted through the reorder buffer and there is no exception.

4. A multifunctional improved branch record buffer system according to claim 3, characterized in that, In the S1 allocation stage step, the branch detection link in the instruction fetch unit includes pre-decoding to identify branch instructions, allocating idle BRB entries, and writing the Branch PC, BrType, and prediction information provided by the BPU. The unrecognized branch processing link includes that if the branch prediction unit does not predict a branch, still allocate a BRB entry, mark the prediction information as invalid, and wait for the execution unit to supplement it.

5. The multifunctional improved branch record buffer system according to claim 4, characterized in that In the S2 parsing stage step, the execution unit feedback link includes sending signals of resolve_pc, actual_target, and direction. The BRB matches the entry through the Branch PC and updates the Actual Target and Direction fields.

6. The multifunctional improved branch record buffer system according to claim 5, characterized in that, The sequentiality guarantee link includes that if the parsed branch is not the entry currently pointed to by the Branch Pointer, only update the entry content and do not trigger BPU update. When the Branch Pointer moves to this entry, trigger BPU update arbitration.

7. The multifunctional improved branch record buffer system according to claim 6, wherein The S3 submission and release step, in which the ROB submission of branch instructions includes sending a commit_pc signal, the BRB marks the corresponding entry as "submitted", and advances the Commit Pointer to the next parsed but unsubmitted entry; the resource release includes releasing the entry to the release queue when the entry pointed to by the Deallocation Pointer has been submitted and the BPU update is completed.

8. A multifunctional improved branch record buffer system according to claim 7, characterized in that, The S4 error handling step, in which the predicted error trigger includes the BPU or the execution unit sending a predicted error pc signal, and the BRB locates the error branch entry through binary search or hardware-accelerated matching; the pipeline rollback includes activating the EarlyFlush Pointer, clearing all subsequent entries of the pointer, and if a Checkpoint is saved, restoring the branch prediction unit to the state before the error branch.

9. A multifunctional improved branch record buffer system according to claim 8, characterized in that, It also includes key circuit design, which includes parallel matching logic and performance optimization design. The parallel matching logic includes a PC matcher and a priority encoder. The PC matcher includes a comparator in the BRB entry to parallelly match the pc of the parsed branch or the pc of the error-predicted branch. The priority encoder includes converting multiple matching results into the index of the highest-priority entry.

10. A multifunctional improved branch record buffer system according to claim 9, characterized in that, The performance optimization design includes pre-releasing some entries to support priority allocation when the gap between the Deallocation Pointer and the Branch Pointer exceeds a threshold.

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