Soft error injection method and FPGA chip

Abstract

The present invention discloses a soft error injection method and an FPGA chip. The method is applied to the soft core IP of an FPGA chip. The injection interface of a soft error correction (SEC) hard core in the FPGA chip is encapsulated in the soft core IP. The method comprises: receiving a setting signal from a user to obtain setting information; generating soft error injection information based on the setting information; and sending the soft error injection information to the SEC hard core via the injection interface, so that the SEC hard core injects soft errors according to the soft error injection information. The present invention does not rely on the JTAG interface when performing soft error injection, occupies less FPGA resources, and has high injection efficiency.

Description

Technical Field

[0001] The present invention belongs to the field of integrated technology, and in particular relates to a soft error injection method and an FPGA chip. Background Art

[0002] As field-programmable gate arrays (FPGAs) continue to expand in size, the number and density of their internal static random-access memory (SRAM) increase. Consequently, the probability of internal memory errors, caused by electromagnetic radiation, external environmental interference, and other factors, altering the system's programmed logic behavior also increases. However, these errors typically do not permanently damage the FPGA device and are referred to as soft errors. To mitigate the impact of soft errors on FPGA system functionality, larger FPGAs often integrate soft error injection, detection (SED), and correction (SEC) functions. These functions can detect and correct single-bit data errors as well as consecutive multi-bit data errors.

[0003] During FPGA development, soft error injection can be used to simulate hardware failures caused by external radiation. This not only tests and verifies soft error detection and correction capabilities, but also allows for evaluation and optimization of the FPGA system's fault tolerance, reliability, security, and performance to meet stringent industry standards in sectors such as automotive electronics and medical devices. By intentionally injecting different soft errors into the FPGA system to simulate circuit failures of varying types and severity, designers can evaluate the system's performance under various anomalies, thereby identifying and resolving potential design flaws, finding the most appropriate fault tolerance solutions for specific application scenarios, and improving the system's fault tolerance, thereby ensuring design stability and robustness. Furthermore, the impact of various soft errors on FPGA performance can be assessed. By simulating optimization strategies, optimal performance configurations and parameter settings can be identified, thereby improving the FPGA's overall performance and power efficiency.

[0004] To meet the high-standard industry requirements for evaluating and optimizing FPGA system fault tolerance, reliability, security, and performance, current popular soft error injection methods include independent soft error injection IP cores, EMR (Error Message Register) Unloader IP cores, ASD IP cores, and soft error injection debugger software interfaces. While users can inject single-bit or multi-bit soft errors into designated areas as needed and compare single-bit error locations with sensitivity maps to meet extremely stringent industry standards, the following drawbacks still exist when fully implementing soft error injection, detection, correction, and evaluation of FPGA system fault tolerance and reliability:

[0005] (1) In addition to instantiating the above three IP cores, users also need to instantiate the soft error detection and correction IP core when designing. This occupies a large amount of FPGA internal resources, thereby reducing the resource space required for actual system design. In addition, the interface is complex and increases the difficulty for users to use.

[0006] (2) The final soft error can only be injected through the software interface using the Joint Test Action Group (JTAG) interface. The JTAG interface can only inject soft errors into one location at a time. If soft errors are to be injected into multiple locations, repeated operations still need to be performed using JTAG, which is inefficient.

[0007] Therefore, the current soft error injection method occupies more FPGA internal resources during execution and has low efficiency. Summary of the Invention

[0008] The embodiments of the present invention provide a soft error injection method and system, which can solve the problem that the current soft error injection method occupies a large number of FPGA internal resources and has low efficiency during execution.

[0009] In a first aspect, an embodiment of the present invention provides a soft error injection method, which is applied to a soft core IP of an FPGA chip, wherein an injection interface of a soft error correction (SEC) hard core in the FPGA chip is encapsulated in the soft core IP. The method includes:

[0010] Receive a setting signal from the user and obtain setting information;

[0011] generating soft error injection information according to the setting information;

[0012] The soft error injection information is sent to the SEC hard core through the injection interface, so that the SEC hard core injects soft errors according to the soft error injection information.

[0013] In a second aspect, an embodiment of the present invention provides an FPGA chip, comprising a soft core IP and a soft error correction SEC hard core, wherein the injection interface of the SEC hard core is encapsulated in the soft core IP;

[0014] The soft core IP is used to: receive a setting signal from a user to obtain setting information; generate soft error injection information according to the setting information; and send the soft error injection information to the SEC hard core through the injection interface;

[0015] The SEC hard core is used to inject soft errors according to the soft error injection information.

[0016] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: the soft error injection method provided by the present invention, by encapsulating the injection interface of the SEC hard core in the FPGA chip on the soft core IP (similar to the scheduler of the traditional method), the soft core IP can send an enable signal to the SEC hard core through the injection interface, and the SEC hard core performs error injection at a soft error injection data address when detecting a rising edge of the enable signal. When performing multi-address error injection, the soft core IP only needs to send multiple enable signals, which can improve the injection efficiency. In addition, the generation process of the soft error injection address is executed by the soft core IP and does not occupy the resources of the FPGA. The number of soft error addresses to be injected can be set by the user according to the resource occupancy of the FPGA. Most importantly, the present invention does not rely on the JTAG interface and does not require the use of external tools such as JTAG downloaders and software real-time controllers for soft error injection, which can greatly improve the injection efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a soft error injection scenario provided by an embodiment of the present invention;

[0018] Figure 2 A schematic diagram of a remote soft error injection scenario provided by an embodiment of the present invention;

[0019] Figure 3 A schematic diagram of a generation interface provided by an embodiment of the present invention;

[0020] Figure 4 A schematic diagram of an interface of a SEC hard core provided in an embodiment of the present invention;

[0021] Figure 5 A flowchart of an implementation of a soft error injection method provided by an embodiment of the present invention;

[0022] Figure 6 A schematic diagram of an FPGA chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In the following description, specific details such as particular system structures and techniques are provided for purposes of illustration, not limitation, to facilitate a thorough understanding of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

[0024] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0025] It will also be understood that the term "and / or" used in the present description and appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0026] As used in the present specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0027] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0028] References to "one embodiment" or "some embodiments" in the present specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present invention. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in yet other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0029] Traditional soft error injection methods typically implement this through the JTAG interface. This requires connecting to the FPGA's JTAG pins, sending soft error information to the FPGA through the JTAG interface, and modifying the value of a specified address through the JTAG interface, for example, changing 0x00001234 to 0x00001235, to achieve soft error injection.

[0030] Since the JTAG interface can only send one address at a time, if you want to modify multiple addresses of the chip register, you need to transmit soft error injection information multiple times, which causes many repeated operations and low injection efficiency.

[0031] Moreover, when traditional soft error injection methods are based on the JTAG interface, in addition to relying on the software interface, they also require the soft error injection IP core, ASD IP core, Unloader IP core, and debugger assistance, which occupies a large amount of FPGA resources.

[0032] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0033] Figure 1 The figure shows a schematic diagram of a soft error injection scenario provided by an embodiment of the present invention.

[0034] As an example, see Figure 1 To perform soft error injection on the data 0x00001234, which is stored in the binary format of "00000000 00000000 0001001000110100," the SEC hard core reads this data. When it reaches the address to be injected, for example, the address where the last "0" is stored, the soft core IP sends an enable signal through the encapsulated injection interface, generating a rising edge. Upon detecting the rising edge, the SEC hard core injects an error at this address, changing the "0" to a "1" and, consequently, the "4" in 0x00001234 to a "5."

[0035] Figure 2 A schematic diagram of a remote soft error injection scenario provided by an embodiment of the present invention.

[0036] As an example, see Figure 2 ,A relatively large system is often composed of multiple small systems, and each ,has its own core control module to implement nested control, for example Figure 2The subsystem control centers and overall control center can all be composed of FPGAs. To ensure overall system reliability, SEC functions are typically invoked within each control center to ensure configuration data stability. For example, robots have complex control features such as hands and feet. These parts operate at high temperatures or in harsh environments, placing higher demands on system stability. Testing the fault tolerance and reliability of small systems by injecting soft errors into the robot's hands and feet individually is not conducive to testing the chain reactions of the entire robot.

[0037] Since the present invention encapsulates the injection interface of the SEC hard core in the soft core IP, the soft core IP sends soft error injection information to the SEC hard core based on the injection interface, and there is no need to connect the debugger to the JTAG pin of the FPGA through a wired connection. Figure 3 Based on the method provided by this invention, users can select the verification mode, error data, and soft error injection address as needed on a generation interface in an external remote control center. The remote control center then generates soft error injection information based on this configuration information and sends it to the robot's central control center in the form of an injection error instruction. The robot's highest-level central control center can then send the soft error injection information to the SEC hard core corresponding to the injection interface encapsulated in the soft core IP. The SEC hard core within the subsystem then performs soft error injection based on the soft error injection information.

[0038] For example, a user can click Figure 3 In the generation interface, select Continuous Verification Mode, check the SEC hard core's automatic error correction function, check Enable Error Injection via Enable Signal, select Gaussian Distribution as the random algorithm for generating soft error injection addresses, and inject errors into 150 addresses at a time.

[0039] Therefore, the soft error injection method provided by the present invention is to encapsulate the injection interface of the SEC hard core in the FPGA chip on the soft core IP (similar to the scheduler of the traditional method), and the soft core IP can send an enable signal to the SEC hard core through the injection interface. The SEC hard core performs error injection at a soft error injection data address when a rising edge of the enable signal is detected. When performing multi-address error injection, the soft core IP only needs to send multiple enable signals, and the data volume of the enable signal is much smaller than the soft error injection information, so that the injection efficiency can be improved. In addition, the generation process of the soft error injection address is executed by the soft core IP and does not occupy the resources of the FPGA. The injection number of the soft error address can be set by the user according to the resource occupancy of the FPGA. Most importantly, the present invention does not rely on the JTAG interface and does not need to be injected with the help of external tools such as JTAG downloaders and software real-time controllers, which can greatly improve the injection efficiency.

[0040] Figure 4 Shown is a schematic diagram of an interface of a SEC hard core provided by an embodiment of the present invention.

[0041] For example, the SEC hard core is an existing hardware module in the FPGA, whose functions include verification, soft error injection and correction. Its core interface can include Figure 4 SEDENABLE, SEDERR, SEDFRCERR, SEDDONE, ECCERR_INJECT_I, SEDINPROG, ECCERR_INJECT_SHF, AUTODONE in .

[0042] For example, the SEDENABLE interface, SEDFRCERR interface, ECCERR_INJECT_I interface, and ECCERR_INJECT_SHF interface are all input interfaces. The SEDENABLE interface is used to start and stop SED verification. When this interface detects a rising edge of the signal, the SED verification is started, and when it detects a falling edge of the signal, the verification is stopped. The SEDFRCERR interface is an injection interface encapsulated in the soft core IP and is used to receive an enable signal. The ECCERR_INJECT_I interface is the input end of the soft error injection address, and the ECCERR_INJECT_SHF interface is the error address information shift enable interface. After detecting the enable signal, this interface can enable the SEC hard core to perform error injection on the next address.

[0043] Illustratively, the SEDERR interface, SEDDONE interface, SEDINPROG interface, and AUTODONE interface are all output interfaces. The SEDERR interface is used to output an error flag signal. When this signal is high, it indicates that the SEC hard core has detected an unrecoverable SED error. The SEDDONE interface is used to output a first working flag signal, which indicates that a round of SED verification has been completed. The SEDINPROG interface is used to output a second working flag signal. When this signal is high, it indicates that verification is in progress. The AUTODONE interface is used to output a third working flag signal. When this signal is high, it indicates that automatic repair is complete or no error has been detected; when it is low, it indicates that automatic repair is in progress.

[0044] Figure 5 The following is a flowchart illustrating an implementation of a soft error injection method provided by an embodiment of the present invention. By way of example and not limitation, this method can be applied to a soft-core IP in an FPGA chip, where the injection interface of the SEC hard core in the FPGA chip is encapsulated within the soft-core IP. The method may include steps S501-S503, each of which is described below.

[0045] S501: Receive a setting signal from a user and obtain setting information.

[0046] For example, see Figure 3 , users can click the corresponding area in the generated interface to send setting signals to the soft core IP.

[0047] In one possible implementation, see Figure 3 ,The setting information may include: verification mode, soft error injection quantity, specified address or soft error injection address generation algorithm.

[0048] Exemplarily, the user may select a random algorithm as a soft error injection location generation algorithm to generate a soft error injection address, or directly input a designated address for soft error injection.

[0049] In one example, the soft error injection position generation algorithm may include various random algorithms such as Gaussian distribution, exponential distribution, Beta distribution, and triangular distribution.

[0050] Exemplarily, the distribution of the generated soft error injection addresses is related to the type of the random algorithm. For example, the distribution of the soft error injection addresses generated based on the Gaussian distribution algorithm satisfies the Gaussian distribution.

[0051] Optionally, the soft error injection address in the present invention does not include a non-functional area (ie, a mask area).

[0052] When conventional technologies inject soft errors into non-functional areas, the feedback result is always that no soft errors are detected, regardless of whether the injection is successful or not. The present invention avoids such areas when injecting soft errors, which is beneficial to improving the accuracy of the verification results.

[0053] S502: Generate soft error injection information according to the setting information.

[0054] Exemplarily, the soft error injection information may include at least one soft error injection address and a soft error injection logic control file. The soft error injection logic control file may control the SEC hard core to perform soft error injection at the soft error address.

[0055] S503 : Sending soft error injection information to the SEC hard core through the injection interface, so that the SEC hard core injects soft errors according to the soft error injection information.

[0056] In one example, the soft error injection address may be sent from the injection interface to the SEC hard core via an enable signal.

[0057] For example, see Figure 1, the SEC hard core can read the data at the soft error injection address under the instruction of the soft error injection logic control file. The enable signal received by the injection interface will have a rising edge when the SEC hard core reads the soft error injection address. The injection interface detects this rising edge and can instruct the SEC hard core to perform error injection.

[0058] The present invention encapsulates the injection interface of the SEC hard core in the FPGA chip on the soft core IP (similar to the scheduler of the traditional method). The soft core IP can send an enable signal to the SEC hard core through the injection interface. The SEC hard core performs error injection at a soft error injection data address when detecting a rising edge of the enable signal. When performing multi-address error injection, the soft core IP only needs to send multiple enable signals, which can improve the injection efficiency. In addition, the generation process of the soft error injection address is executed by the soft core IP and does not occupy the resources of the FPGA. The injection number of the soft error address can be set by the user according to the resource occupancy of the FPGA. Most importantly, the present invention does not rely on the JTAG interface and does not need to use external tools such as JTAG downloaders and software real-time controllers to perform soft error injection, which can greatly improve the injection efficiency.

[0059] Figure 6 Shown is a schematic diagram of an FPGA chip provided in an embodiment of the present invention.

[0060] In some embodiments, chip 600 may include a soft IP core 610 and a SEC hard core 620 .

[0061] For example, the soft core IP 610 can be configured to receive a setting signal from a user to obtain setting information; generate soft error injection information based on the setting information; and send the soft error injection information to the SEC hard core 620 via an injection interface. The SEC hard core 620 can be configured to inject soft errors based on the soft error injection information.

[0062] The present invention encapsulates the injection interface of the SEC hard core in the FPGA chip on the soft core IP (similar to the scheduler of the traditional method). The soft core IP can send an enable signal to the SEC hard core through the injection interface. The SEC hard core performs error injection at a soft error injection data address when detecting a rising edge of the enable signal. When performing multi-address error injection, the soft core IP only needs to send multiple enable signals, which can improve the injection efficiency. In addition, the generation process of the soft error injection address is executed by the soft core IP and does not occupy the resources of the FPGA. The injection number of the soft error address can be set by the user according to the resource occupancy of the FPGA. Most importantly, the present invention does not rely on the JTAG interface and does not need to use external tools such as JTAG downloaders and software real-time controllers to perform soft error injection, which can greatly improve the injection efficiency.

[0063] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

Claims

1. A soft error injection method, characterized in that: The method is applied to a soft core IP of an FPGA chip, wherein an injection interface of a soft error correction (SEC) hard core in the FPGA chip is encapsulated in the soft core IP. The method includes: receiving a setting signal from a user and obtaining setting information, wherein the user sends the setting signal to the soft core IP by clicking a corresponding area in a generation interface; generating soft error injection information according to the setting information; Sending the soft error injection information to the SEC hard core through the injection interface, so as to enable the SEC hard core to inject soft errors according to the soft error injection information; The soft error injection information includes at least one soft error injection address and a soft error injection logic control file, wherein the soft error injection logic control file is used to control the SEC hard core to perform soft error injection at the soft error injection address; The setting information includes: verification mode, soft error injection quantity, designated address or soft error injection address generation algorithm; The soft error injection address is the designated address, or is generated according to the soft error injection address generation algorithm; The soft error injection address generation algorithm includes Gaussian distribution, exponential distribution, Beta distribution and triangular distribution random algorithms; The soft error injection address does not include a non-functional area of ​​the FPGA chip; The injection interface is an enable signal interface, which is used to receive an enable signal and instruct the SEC hard core to inject a soft error when a rising edge of the enable signal is detected.

2. The method according to claim 1, characterized in that Before receiving a setting signal from a user and obtaining setting information, the method further includes: A generation interface for soft error injection information is displayed to the user, so that the user sends the setting signal based on the generation interface.

3. An FPGA chip, characterized in that: The invention comprises a soft core IP and a soft error correction SEC hard core, wherein the injection interface of the SEC hard core is encapsulated in the soft core IP; The soft core IP is used to: receive a setting signal from a user and obtain setting information, wherein the user sends the setting signal to the soft core IP by clicking a corresponding area in a generation interface; generate soft error injection information according to the setting information; and send the soft error injection information to the SEC hard core through the injection interface; wherein the soft error injection information includes at least one soft error injection address and a soft error injection logic control file, and the setting information includes: a verification mode, a soft error injection quantity, a specified address or a soft error injection address generation algorithm; the soft error injection logic control file is used to control the SEC hard core to perform soft error injection at the soft error injection address; the soft error injection address is the specified address, or is generated according to the soft error injection address generation algorithm; the soft error injection address generation algorithm includes Gaussian distribution, exponential distribution, Beta distribution and triangular distribution random algorithms; the soft error injection address does not include a non-functional area of ​​the FPGA chip; the injection interface is an enable signal interface, used to receive an enable signal, and instruct the SEC hard core to inject a soft error when a rising edge of the enable signal is detected; The SEC hard core is used to inject soft errors according to the soft error injection information.

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