Single-channel PLC high-speed data acquisition method and system suitable for industrial workshop

Abstract

The invention relates to a single-channel PLC high-speed data acquisition method and system suitable for an industrial workshop, and the method comprises the steps: obtaining the information of a plurality of data nodes configured in a PLC, and determining the minimum continuous address range of all nodes in a PLC memory; obtaining a whole piece of byte data from the minimum continuous address range through single communication interaction, and storing the whole piece of byte data in an acquisition terminal memory; establishing memory mapping based on the whole byte data, wherein the memory mapping reflects a corresponding relation between a PLC memory data area and a terminal memory; adopting a first thread to continuously collect whole byte data of the PLC memory data area according to a preset frequency, and updating the whole byte data to the memory mapping; and extracting the updated whole byte data from the memory mapping, and analyzing the whole byte data by adopting a second thread according to the length and the data type of each data node to obtain converted numerical data.

Description

Technical Field

[0001] The present invention relates to the technical field of data acquisition, and particularly relates to a single-channel PLC high-speed data acquisition method and system suitable for industrial workshops. Background Art

[0002] In the automated production scenarios of industrial workshops, the processing process is highly automated, and the processing frequency can reach the millisecond level. In such an environment, there is an urgent need to collect various key parameter data such as the production volume and process parameters of the PLC at a millisecond-level time rhythm and store them in a database, so as to analyze and monitor the overall processing situation in the upper-layer system. At the same time, corresponding data processing and applications are also required.

[0003] However, the existing acquisition technologies have many limitations. Currently, the vast majority of acquisition gateways can only achieve second-level data acquisition, which is difficult to meet the high-speed acquisition requirements of industrial workshops. Even if some gateways claim to be able to achieve millisecond-level acquisition, they usually adopt the method of single-point polling and timing acquisition. Under the limitation of a single-channel single-core CPU, since the PLC response speed is restricted by various factors, according to different PLC types or communication protocols, through actual tests, the time required to collect data for a single point is between 3 - 10 ms. If the acquisition frequency requirement is 200 ms, it is conservatively estimated that at most only about 40 nodes can be configured for acquisition, and the acquisition speed faces a serious bottleneck.

[0004] In addition, in the actual production scenarios required by customers, the fastest processing rhythm batch time interval is about 200 ms, and dozens to more than 100 PLC data nodes need to be acquired within this extremely short time interval. In terms of hardware, a single-core CPU device hlk - 7688A with a main frequency of 580 MHZ is uniformly used, and the PLC only provides a single-channel connection. The traditional single-point polling processing method is greatly limited in acquisition ability when dealing with different types of PLCs. For example, for certain PLC types, the number of nodes that can be acquired within 200 ms is, for a certain common PLC, its acquisition ability is 40 - 45 nodes / 200 ms, another type is 50 - 55 nodes / 200 ms, and another type of PLC using the modbusTcp protocol is 55 - 60 nodes / 200 ms. It can be seen that the existing data acquisition methods are difficult to meet the increasing high-speed and efficient data acquisition requirements of industrial workshops. Summary of the Invention

[0005] The main object of the present invention is to provide a single-channel PLC high-speed data acquisition method and system suitable for industrial workshops, so as to achieve the purpose of quickly acquiring, storing in a database, analyzing and monitoring, and data processing of multiple parameters of the PLC under the millisecond-level processing frequency in industrial workshops.

[0006] To achieve the above object, the present invention provides a single-channel PLC high-speed data acquisition method applicable to industrial workshops, comprising the following steps: Obtain multiple data node information configured in the PLC, where the data node information includes address, length, and data type, and determine the smallest continuous address range in the PLC memory that includes all nodes according to the data node information; Obtain the entire block of byte data from the smallest continuous address range through a single communication interaction and save it to the memory of the acquisition terminal; Establish a memory mapping based on the entire block of byte data, where the memory mapping reflects the correspondence between the PLC memory data area and the terminal memory; Use the first thread to continuously collect the entire block of byte data in the PLC memory data area at a preset frequency and update it to the memory mapping; Extract the updated entire block of byte data from the memory mapping, and use the second thread to parse the entire block of byte data according to the length and data type of each data node to obtain the converted numerical data; Process the converted numerical data according to the rule strategy of the data node to generate the final data acquisition result.

[0007] Further, the step of determining the smallest continuous address range in the PLC memory that includes all nodes includes: Based on the single-core CPU platform and single-channel communication constraint conditions, scan the address distribution of all data nodes in the PLC memory, and identify the starting address with the smallest address value and the ending address with the largest address value; Calculate the length of the smallest continuous address interval covering all nodes according to the starting address and the ending address; If there is a discontinuous address interval, include all addresses between the starting address and the ending address in the reading range; Generate a whole-memory reading instruction corresponding to the smallest continuous address range, and determine the smallest continuous address range corresponding to all nodes.

[0008] Further, the step of obtaining the entire block of byte data from the smallest continuous address range through a single communication interaction and saving it to the memory of the acquisition terminal includes: Send a single reading instruction to the PLC to request all byte data within the smallest continuous address range; Receive the byte data stream returned by the PLC, where the length of the byte data stream is the same as the length of the smallest continuous address range; Write the byte data stream into the continuous memory space of the acquisition terminal in the original order.

[0009] Further, the step of establishing a memory mapping based on the entire block of byte data includes: Partition a dedicated buffer area in the acquisition terminal memory that is the same length as the entire PLC memory data area; Establish a linear mapping relationship between the PLC address offset and the terminal memory offset. The linear mapping relationship includes the starting address of the PLC memory corresponding to the starting address of the terminal memory, and the address offset of each data node is converted into the relative offset of the terminal memory, generating a memory mapping configuration file containing the starting address, total data length, and offset mapping table.

[0010] Further, the step of continuously collecting the entire block of byte data in the PLC memory data area at a preset frequency by the first thread and updating it to the memory mapping includes: Create an independent first communication thread and configure the polling cycle parameter of the first communication thread; Execute operations in each polling cycle: Send a read instruction for the entire block of memory data area to the PLC; Receive the updated byte data returned by the PLC; Determine the storage location of the updated byte data in the terminal memory through memory mapping; Use atomic operations to write the updated byte data into the corresponding terminal memory area.

[0011] Further, the step of parsing the entire block of byte data according to the length and data type of each data node by the second thread to obtain the converted numerical data includes: Traverse the configuration information of all data nodes; Locate the starting offset of the node in the terminal memory according to the memory mapping relationship; Extract a continuous block of byte data, and the extraction length is the same as the data length configured by the node; Perform a data type conversion operation on the continuous block of byte data to obtain the converted numerical data and temporarily store it in the non-volatile memory queue.

[0012] Further, the step of processing the converted numerical data according to the rule policy of the data node to generate the final data acquisition result includes: Configure at least one processing rule for each data node. The processing rules include data scaling rules, data filtering rules, status mapping rules, and dead zone rules; Encapsulate the processed data into a JSON format message and transfer it to the upper-layer application through the shared memory pool; Add a timestamp and a node identifier to the processed numerical data, generate a structured data packet as the final acquisition result, and write it into the message queue.

[0013] The present invention also provides a single-channel PLC high-speed data acquisition system applicable to industrial workshops, including: A data acquisition unit, configured to acquire information of a plurality of data nodes configured in a PLC, and determine a minimum continuous address range including all nodes in the PLC memory according to the data node information; A data collection unit, configured to obtain a block of byte data from the minimum continuous address range through a single communication interaction and save it to the memory of a collection terminal; A mapping establishment unit, configured to establish a memory mapping based on the block of byte data; A data update unit, configured to continuously collect the block of byte data in the PLC memory data area at a preset frequency by using a first thread and update it to the memory mapping; A data parsing unit, configured to extract the updated block of byte data from the memory mapping, and use a second thread to parse the block of byte data according to the length and data type of each data node to obtain converted numerical data; A result generation unit, configured to process the converted numerical data according to the rule strategy of the data node to generate a final data acquisition result.

[0014] The present invention also provides a computer device, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps of the above-mentioned single-channel PLC high-speed data acquisition method applicable to industrial workshops are implemented.

[0015] The present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned single-channel PLC high-speed data acquisition method applicable to industrial workshops are implemented.

[0016] The single-channel PLC high-speed data acquisition method and system applicable to industrial workshops provided by the present invention have the following beneficial effects: Through address merging and block data reading, the present invention eliminates the cumulative delay of traditional node-by-node communication, and realizes millisecond-level high-speed acquisition of high-density nodes under limited hardware conditions. The operation of obtaining all node data through a single interaction avoids the repeated overhead of multi-node polling, decouples the communication time consumption from the number of nodes, and increases the throughput by dozens of times. The acquisition thread and the parsing thread are decoupled and parallel, and zero-copy sharing of data is achieved through memory mapping, maximizing the utilization rate of the single-core CPU resources and ensuring real-time performance. At the same time, the memory mapping area is updated through atomic operations to ensure data consistency in a multi-threaded environment and avoid data loss or read-write conflicts in the traditional polling mode. In addition, the local data processing of the present invention supports dynamic loading of diverse rules (such as filtering, scaling, status mapping), and can adapt to the requirements of complex industrial scenarios without additional hardware modification. Description of the Drawings

[0017] Figure 1 It is a schematic flow chart of a single-channel PLC high-speed data acquisition method applicable to industrial workshops in an embodiment of the present invention; Figure 2 It is a structural block diagram of a single-channel PLC high-speed data acquisition system applicable to industrial workshops in an embodiment of the present invention; Figure 3 It is a schematic structural block diagram of a computer device in an embodiment of the present invention; Figure 4 It is a schematic diagram of node address distribution and operation timing log in the PLC monitoring project of industrial workshops in an embodiment of the present invention; Figure 5 It is a schematic diagram of the structure of a single read of data stream based on the Modbus TCP protocol in an embodiment of the present invention; Figure 6 It is a schematic diagram of the analysis of the time-consuming of the optimization algorithm in the 57-node scenario in an embodiment of the present invention; Figure 7 It is a schematic diagram of the time-consuming test of data acquisition and parsing in the 500-node scenario in an embodiment of the present invention; Figure 8 It is a schematic diagram of the time-consuming comparison of the traditional polling method in the 57-node scenario in an embodiment of the present invention; Figure 9 It is a schematic diagram of the performance failure of the traditional polling method in the 500-node scenario in an embodiment of the present invention; Figure 10 It is a schematic diagram of the efficiency comparison and analysis between the optimization algorithm and the traditional method in an embodiment of the present invention.

[0018] The realization of the purpose, functional features and advantages of the present invention will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0019] In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0020] Referring to Figure 1 , it is a schematic flow chart of a single-channel PLC high-speed data acquisition method proposed by the present invention, including the following steps: S1, obtain information of multiple data nodes configured in the PLC, where the data node information includes address, length and data type, and determine the smallest continuous address range including all nodes in the PLC memory according to the data node information; S2. Obtain the entire block of byte data from the minimum continuous address range through a single communication interaction and save it to the memory of the acquisition terminal; S3. Establish a memory mapping based on the entire block of byte data, where the memory mapping reflects the correspondence between the PLC memory data area and the terminal memory; S4. Use the first thread to continuously collect the entire block of byte data in the PLC memory data area at a preset frequency and update it to the memory mapping; S5. Extract the updated entire block of byte data from the memory mapping, and use the second thread to parse the entire block of byte data according to the length and data type of each data node to obtain the converted numerical data; S6. Process the converted numerical data according to the rule strategy of the data node to generate the final data acquisition result.

[0021] As described in step S1 above, under the hardware constraints of a single-core CPU and single-channel communication, by scanning the address distribution of all data nodes, the minimum starting address (such as 0x0000) and the maximum ending address (such as 0x00FF) are dynamically identified, and the length of the continuous address range covering all nodes is calculated. For non-continuous addresses (such as the gap between 0x0005 - 0x0008), the forced extended reading range is set to the complete continuous range (0x0000 - 0x00FF), rather than the traditional method where multiple independent read requests (such as 1 time for each of node 1, node 2, and node 3) are combined into a single read, thereby eliminating the additional communication overhead caused by the address gap. Through step S1, it is ensured that even if the node distribution is discrete, the entire block of data can be read with a minimized address span.

[0022] As described in step S2 above, based on the minimum address range (such as 0x0000 - 0x00FF) generated in step S1, a communication connection is established through a single channel, a single read instruction is sent to the PLC (such as Modbus function code 03, starting address 0x0002, length 7), the byte data stream returned by the PLC (7-byte original data stream) is received, and it is completely written into the continuous memory space of the acquisition terminal in the original order to form a mirror image that is exactly the same as the PLC memory layout. Step S2 realizes "one communication, full quantity acquisition". Compared with the traditional multiple interactions for each node (such as 500 ms for 100 nodes), step S2 only requires a single communication (such as 30 ms), significantly reducing the communication delay.

[0023] As described in step S3 above, a dedicated buffer area of the same length as the PLC memory area (the size strictly corresponds to the PLC data block) is divided in the memory of the acquisition terminal, and a linear mapping relationship with two-way addresses is established. The linear mapping relationship includes address mapping and offset conversion. The address mapping is such that the PLC starting address 0x0002 corresponds to the starting address 0x1000 of the terminal memory, and the PLC starting address 0x0003 corresponds to the starting address 0x1001 of the terminal memory. The offset conversion is such that the node address 0x000A is mapped to the terminal memory 0x100A. A configuration file including the base address and the total data length and a node offset scale table are generated based on the mapping address mapping relationship for subsequent threads to quickly locate data. The mapping mechanism in step S3 realizes the mirror synchronization between the PLC memory and the terminal memory, laying a foundation for subsequent real-time updates and avoiding the overhead of multiple data transfers in traditional methods.

[0024] As described in step S4 above, based on the memory mapping established in S3, a first acquisition thread (Thread1) with high priority is created, and a synchronous cycle configuration adjustable from 10 to 50 ms is configured (it can be set to 10 ms in scenarios with high-frequency real-time requirements). During each cycle polling, the storage location is directly located through the memory mapping, avoiding thread blocking caused by the traditional lock mechanism; atomic operations are used to complete data updates (to avoid lock contention), ensuring that the entire data update operation is indivisible and preventing read-write conflicts; and the last update timestamp is recorded. If the communication is interrupted, the last valid data position is automatically restored based on the memory mapping. Through step S4, stable and reliable millisecond-level data synchronization can still be achieved in a single-core CPU environment.

[0025] As described in step S5 above, based on the data synchronized in step S4, a second acquisition thread (Thread2) is independently parsed to traverse all node configurations. Based on the memory mapping table, the data is quickly located (such as node address 1: 0x1000 - terminal memory 0x1001, node address 2: 0x1003 - terminal memory 0x1006); A data type conversion operation is performed on the continuous byte data block. If it is an integer type, it is parsed into a signed integer value in little-endian order; if it is a floating-point type, it is decoded into a single-precision floating-point number according to the IEEE 754 standard; if it is a boolean type, the binary state value of the specified offset bit is extracted. The parsed result is temporarily stored in a non-volatile memory queue to avoid frequent I / O operations in traditional methods.

[0026] As described in step S6 above, perform in-depth processing on the parsing result of step S5, and dynamically load rule policies for each node. Support multi-rule pipeline processing such as scaling, filtering, and state mapping. Among them, the data scaling rule is to substitute the converted numerical data into a predefined linear formula (target value = original value * scale factor + offset) to generate standardized numerical values; the data filtering rule is to calculate the moving average of a continuous sequence of numerically acquired data using a sliding window of length N to suppress high-frequency noise; the state mapping rule is to match the numerical data with a predefined set of discrete states. If it is floating-point data, perform interval mapping, and if it is integer data, perform look-up table mapping; perform dead zone optimization by setting a threshold (for example, ignore updates when the temperature change < 0.5 °C). When the difference between the numerical data and the previous acquired value is less than the set threshold, it is determined as invalid fluctuation and the current data is discarded to reduce the amount of invalid data processing. Add a millisecond-level timestamp (such as 2023-08-20T14:35:00.123Z) and a node ID (such as DI003) to the processed data to generate a standard JSON message (including metadata, numerical values, and status codes). The data processing result is directly transmitted to the upper-layer application through a shared memory pool to avoid the transmission delay of the traditional TCP / IP protocol stack.

[0027] When the data node information changes, re-determine the minimum continuous address range according to the changed data node information; continuously output the final acquisition result through a memory mapping and thread separation mechanism.

[0028] In one embodiment, in an industrial workshop PLC monitoring project, 57 data nodes are configured, and their address distributions cover discontinuous intervals from PLC memory address 0 to 890 (as Figure 4 shown, the node address distributions are extremely uneven). By automatically scanning the node address distributions by the system, the starting address 0 and the ending address 890 are identified, and the length of the minimum continuous address interval is calculated to be 891 bytes. Although there are address gaps between nodes (such as the address interval 100 - 200 is not configured with nodes), the system still combines the entire 0 - 890 interval into a single read range, thus optimizing the 57 independent communications (taking 574 ms, as Figure 8 shown) in the traditional method to a single read (taking 48 + 5 = 53 ms), and the communication efficiency is increased by 12 times.

[0029] For the above configuration of 57 nodes, the system sends a single read instruction (Modbus function code 03, starting address 0, length 891 bytes) to the PLC through the Modbus TCP protocol, and receives an 891-byte data stream containing all node data (as Figure 5 shown). Through direct memory writing technology, the data stream is completely stored in the continuous memory space (address 0x1000 - 0x147F) of the acquisition terminal in the original order, taking 48 ms (asFigure 6 as shown). Compared with the traditional per-node reading method (such as Figure 8 as shown, it took 574 ms for 57 nodes), this method reduces the communication time by 92%.

[0030] Divide an 891-byte dedicated buffer in the acquisition terminal memory, establish a linear mapping relationship with the PLC memory. For example, PLC address 0 corresponds to terminal memory 0x1000, and PLC address 890 corresponds to terminal memory 0x147F; and generate a mapping configuration file containing the base address (0x1000), the total data length (891 bytes), and the node offset table (such as offset 0x0002 for node 1, offset 0x0005 for node 2, etc.).

[0031] Cooperate with two threads to update and parse data in real time. The first thread (data synchronization thread) takes 50 ms as the polling period and updates the memory mapping area through atomic operations. As Figure 7 shown, in the 500-node test, each synchronization takes 49 ms (including communication and writing), and there is no data tearing or loss. The second thread (data parsing), the second thread (data parsing thread) traverses all node configurations, quickly locates the memory offset based on the mapping table (such as node address 0x0030 corresponding to terminal memory 0x1030), and parses the data according to the data type conversion rules. 16-bit integers are parsed in little-endian order (taking 0.8 μs / node), 32-bit floating-point numbers are decoded according to IEEE 754 (taking 2.1 μs / node), boolean values are extracted through bit masks (taking 0.2 μs / node), the total parsing time for 57 nodes is 5 ms, and the parsing time for 500 nodes is 52 ms (as Figure 7 shown), the average single-node processing time is less than 0.1 ms, there is no blockage throughout the process, and the CPU utilization rate is less than 15%.

[0032] Perform rule-based policy processing on the parsed data. Apply a 5-point moving average filter to the temperature node (address 0x0030) (such as the filtering rule in Figure 9 ), suppress fluctuations of ±0.5 °C, perform status mapping on the pressure node (address 0x0100), and convert the value to the preset {low pressure, normal, high pressure} status (such as Figure 10 comparison result). The threshold interval is dynamically loaded through the configuration file. When the change amount of the flow node (address 0x0200) < 1 m³ / h, discard the current data. The processed data is encapsulated into a structured JSON message, including a millisecond-level timestamp (such as 2023-08-20T14:35:00.123Z) and the device ID, and is transmitted to the monitoring platform through the shared memory pool. The total rule processing time < 2 ms, and the end-to-end data delay is controlled within 55 ms. (57 nodes) or 101 ms (500 nodes).

[0033] Figure 10 The comparison data shows that the traditional method takes 5056 ms in the 500-node scenario (as Figure 9 shown), while this solution only takes 101 ms, with the efficiency increased by 50 times. When the number of nodes increases, the time-consuming growth trend of this technical solution is sub-linear (from 57 nodes to 500 nodes, the time-consuming increases by about 1 time), while the traditional method shows a linear growth (the time-consuming increases by nearly 10 times), verifying the high scalability of the algorithm.

[0034] In this embodiment, through address merging, block reading, memory mapping, and dual-thread coordination, in the environment of a single-core CPU and a single-channel PLC, data acquisition and processing at the 53-ms level in the 57-node scenario and the 101-ms level in the 500-node scenario are achieved. When the number of nodes increases, the efficiency advantage is further amplified, fully meeting the core requirements of industrial scenarios for real-time performance and scalability.

[0035] Refer to Figure 2 , which is the structural block diagram of a single-channel PLC high-speed data acquisition system applicable to an industrial workshop in an embodiment of the present invention, including: A data acquisition unit, configured to acquire information of multiple data nodes configured in the PLC, and determine the smallest continuous address range including all nodes in the PLC memory according to the data node information; A data collection unit, configured to acquire a block of byte data from the smallest continuous address range through a single communication interaction and save it to the memory of the collection terminal; A mapping establishment unit, configured to establish a memory mapping based on the block of byte data; A data update unit, configured to continuously collect the block of byte data in the PLC memory data area at a preset frequency by using a first thread and update it to the memory mapping; A data parsing unit, configured to extract the updated block of byte data from the memory mapping, and use a second thread to parse the block of byte data according to the length and data type of each data node to obtain the converted numerical data; A result generation unit, configured to process the converted numerical data according to the rule strategy of the data node to generate a final data acquisition result.

[0036] For the specific implementation of each unit in the above device instance, please refer to that described in the above method embodiment, and details are not described herein again.

[0037] Refer to Figure 3 , an embodiment of the present invention also provides a computer device, which may be a server, and its internal structure may be as Figure 3As shown in the figure. The computer device includes a processor, a memory, a display screen, an input device, a network interface, and a database connected through a system bus. Among them, the processor of the computer design is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0038] Those skilled in the art can understand that Figure 3 the structure shown in is only a block diagram of some structures related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0039] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0040] In summary, obtain multiple data node information configured in the PLC. The data node information includes address, length, and data type. According to the data node information, determine the smallest continuous address range in the PLC memory that includes all nodes; obtain the entire block of byte data from the smallest continuous address range through a single communication interaction and save it to the memory of the acquisition terminal; establish a memory mapping based on the entire block of byte data. The memory mapping reflects the correspondence between the PLC memory data area and the terminal memory; use the first thread to continuously collect the entire block of byte data in the PLC memory data area at a preset frequency and update it to the memory mapping; extract the updated entire block of byte data from the memory mapping, and use the second thread to parse the entire block of byte data according to the length and data type of each data node to obtain the converted numerical data; process the converted numerical data according to the rule strategy of the data node to generate the final data acquisition result, so as to achieve the purpose of quickly collecting, storing, analyzing, monitoring, and data processing requirements of multiple parameters of the PLC under the millisecond-level processing frequency in the industrial workshop.

[0041] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium provided by the present invention and used in the embodiments can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM, etc.

[0042] It should be noted that in this article, the terms "include", "comprise", or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that includes a series of elements includes not only those elements but also other elements not expressly listed, or elements that are inherent to such process, apparatus, article, or method. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, apparatus, article, or method that includes the element.

[0043] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structural or equivalent process transformation made by using the specification and drawings of the present invention, or directly or indirectly applied to other related technical fields, shall equally be included in the patent protection scope of the present invention.

Claims

1. A single-channel PLC high-speed data acquisition method applicable to industrial workshops, characterized in that, Including the following steps: Obtain multiple data node information configured in the PLC. The data node information includes address, length, and data type. According to the data node information, determine the smallest continuous address range in the PLC memory that includes all nodes; Through a single communication interaction, obtain the entire block of byte data from the smallest continuous address range and save it to the acquisition terminal memory; Based on the entire block of byte data, establish a memory mapping, and the memory mapping reflects the corresponding relationship between the PLC memory data area and the terminal memory; Use the first thread to continuously collect the entire block of byte data in the PLC memory data area at a preset frequency and update it to the memory mapping; Extract the updated entire block of byte data from the memory mapping, and use the second thread to parse the entire block of byte data according to the length and data type of each data node to obtain the converted numerical data; Process the converted numerical data according to the rule strategy of the data node to generate the final data acquisition result.

2. The single-channel PLC high-speed data acquisition method applicable to industrial workshops according to claim 1, wherein The step of determining the smallest continuous address range in the PLC memory that includes all nodes includes: Based on the single-core CPU platform and single-channel communication constraint conditions, scan the address distribution of all data nodes in the PLC memory, and identify the starting address with the smallest address value and the ending address with the largest address value; Calculate the length of the smallest continuous address interval covering all nodes according to the starting address and the ending address; If there is a discontinuous address interval, include all addresses between the starting address and the ending address in the reading range; Generate a whole-memory reading instruction corresponding to the smallest continuous address range, and determine the smallest continuous address range corresponding to all nodes.

3. The single-channel PLC high-speed data acquisition method applicable to industrial workshops according to claim 1, wherein The step of obtaining the entire block of byte data from the smallest continuous address range through a single communication interaction and saving it to the acquisition terminal memory includes: Send a single reading instruction to the PLC to request all byte data within the smallest continuous address range; Receive the byte data stream returned by the PLC, and the length of the byte data stream is the same as the length of the smallest continuous address range; Write the byte data stream into the continuous memory space of the acquisition terminal in the original order.

4. The single-channel PLC high-speed data acquisition method applicable to industrial workshops according to claim 1, wherein The step of establishing a memory mapping based on the entire block of byte data includes: Divide a dedicated buffer area of the same length as the entire PLC memory data area in the acquisition terminal memory; Establish a linear mapping relationship between the PLC address offset and the terminal memory offset. The linear mapping relationship includes the PLC memory starting address corresponding to the terminal memory starting address, and the address offset of each data node is converted into the relative offset of the terminal memory, and generate a memory mapping configuration file including the starting address, the total data length, and the offset mapping table.

5. The single-channel PLC high-speed data acquisition method applicable to industrial workshops according to claim 1, characterized in that The step of using the first thread to continuously collect the entire block of byte data in the PLC memory data area at a preset frequency and update it to the memory mapping includes: Create an independent first communication thread and configure the polling cycle parameter of the first communication thread; Execute operations in each polling cycle: Send a reading instruction for the entire PLC memory data area to the PLC; Receive the updated byte data returned by the PLC; Determine the storage location of the updated byte data in the terminal memory through memory mapping; Use atomic operations to write the updated byte data into the corresponding terminal memory area.

6. The single-channel PLC high-speed data acquisition method applicable to industrial workshops according to claim 1, wherein The step of using the second thread to parse the whole block of byte data according to the lengths and data types of each data node to obtain the converted numerical data includes: Traverse the configuration information of all data nodes; Locate the starting offset of the node in the terminal memory according to the memory mapping relationship; Extract a continuous byte data block, and the extraction length is the same as the data length configured by the node; Perform a data type conversion operation on the continuous byte data block to obtain the converted numerical data and temporarily store it in the non-volatile memory queue.

7. The single-channel PLC high-speed data acquisition method applicable to industrial workshops according to claim 1, characterized in that The step of processing the converted numerical data according to the rule policy of the data node to generate the final data acquisition result includes: Configure at least one processing rule for each data node, and the processing rules include data scaling rules, data filtering rules, status mapping rules, and dead zone rules; Encapsulate the processed data into a JSON format message and transfer it to the upper-layer application through the shared memory pool; Add a timestamp and a node identifier to the processed numerical data, generate a structured data packet as the final acquisition result, and write it into the message queue.

8. A single-channel PLC high-speed data acquisition system applicable to industrial workshops, characterized in that, Include: A data acquisition unit, configured to acquire information of a plurality of data nodes configured in the PLC, and determine the smallest continuous address range including all nodes in the PLC memory according to the data node information; A data collection unit, configured to obtain a whole block of byte data from the smallest continuous address range through a single communication interaction and save it to the collection terminal memory; A mapping establishment unit, configured to establish a memory mapping based on the whole block of byte data; A data update unit, configured to continuously collect the whole block of byte data in the PLC memory data area at a preset frequency by using a first thread and update it to the memory mapping; A data parsing unit, configured to extract the updated whole block of byte data from the memory mapping, and use a second thread to parse the whole block of byte data according to the lengths and data types of each data node to obtain the converted numerical data; A result generation unit, configured to process the converted numerical data according to the rule policy of the data node to generate the final data acquisition result.

9. A computer device, comprising a memory and a processor, wherein a computer program is stored in the memory, characterized in that, When the processor executes the computer program, it implements the steps of the single-channel PLC high-speed data acquisition method applicable to industrial workshops according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the single-channel PLC high-speed data acquisition method applicable to industrial workshops according to any one of claims 1 to 7.

Images