Serial multi-chip communication device applied to signal chain chip and corresponding method

Abstract

The invention provides a serial multi-chip communication device applied to a signal chain chip and a corresponding method. Relates to the technical field of chip serial communication, and solves the problems of circuit design complexity and increase of occupied hardware resources in the prior art. The device is characterized in that a chip selection differential negative end of a main controller is connected with a chip selection input end of a first-stage chip; the second-stage chips form a chip selection series structure; the slave chip selection output end of the first-stage chip is connected with the chip selection input end of the first second-stage chip of the chip selection series structure; and a serial differential positive end, a clock signal output end and a feedback signal input end of the main controller are respectively connected with the first-stage chip as well as a slave input end, a clock signal input end and a slave output end of each second-stage chip. According to the invention, resource overhead can be reduced, access to different slave chips is realized, and adjustment and expansion are easy.

Description

Technical Field

[0001] The present invention relates to the technical field of chip serial communication, and particularly relates to a serial multi-chip communication device and corresponding method applied to a signal chain chip. Background Art

[0002] Currently, the inter-chip communication bus based on SPI (Serial Peripheral Interface) is increasingly widely used in the field of communication technology because of its relatively fast communication rate. As shown in Figure 1 , in the face of the scenario of multi-chip interconnection, the master chip is interconnected with the corresponding interfaces of each slave chip through multiple interfaces respectively to achieve access and data transmission. However, with the increase in the number of chip select lines, the complexity of circuit design and hardware design is increased, resulting in an increase in the complexity of circuit design and the occupied hardware resources, which can no longer meet the current requirements for high-efficiency and low-cost communication in the field of communication technology. Summary of the Invention

[0003] A brief overview of the present invention is given below to provide a basic understanding of certain aspects of the present invention. It should be understood that this overview is not an exhaustive overview of the present invention. It is not intended to identify the key or important parts of the present invention, nor is it intended to limit the scope of the present invention. Its purpose is only to present certain concepts in a simplified form as a prelude to the more detailed description to be discussed later.

[0004] In view of this, in order to solve the above problems, the present invention provides a serial multi-chip communication device and corresponding method applied to a signal chain chip, which can reduce the hardware resources occupied by the signal chain chip and achieve a high communication rate.

[0005] The present invention provides a serial multi-chip communication device applied to a signal chain chip, comprising:

[0006] A master controller, a first-level chip and at least one second-level chip;

[0007] The chip select differential negative terminal of the master controller is interconnected with the chip select input terminal of the first-level chip;

[0008] Each chip in the second-level chips is sequentially connected to the chip select input terminal of the next chip through the slave chip select output terminal to form a chip select series structure of the at least one second-level chip;

[0009] The slave chip select output terminal of the first-level chip is interconnected with the chip select input terminal of the first second-level chip in the chip select series structure;

[0010] The serial differential positive terminal of the master controller is interconnected with the slave input terminal of the first-level chip and the slave input terminal of each second-level chip;

[0011] The clock signal output terminal of the main controller is interconnected with the clock signal input terminals of the first - stage chip and the clock signal input terminals of each second - stage chip;

[0012] The feedback signal input terminal of the main controller is interconnected with the slave output terminals of the first - stage chip and the slave output terminals of each second - stage chip.

[0013] In a possible implementation, the first - stage chip and each second - stage chip use the same chip.

[0014] In a possible implementation, the main controller is connected to the first - stage chip and each second - stage chip through a serial peripheral interface.

[0015] In a second aspect, the present invention also provides a serial multi - chip communication method applied to a signal - chain chip, which is applied to the above - mentioned communication device. The method includes:

[0016] The first - stage chip monitors the addressing address information of the main controller, and when receiving the addressing address information, detects the addressing address information;

[0017] According to the detection result of the addressing address information, determine whether to select the first - stage chip as the communication chip.

[0018] In a possible implementation, according to the detection result of the addressing address information, determining whether to select the first - stage chip as the communication chip includes:

[0019] When it is detected that the addressing address information is valid and correct, the subsequent received addressing address information is transparently transmitted from the first - stage chip to the first second - stage chip in the chip - select series structure;

[0020] When it is detected that the addressing address information is valid and incorrect, determine to select the first - stage chip as the communication chip;

[0021] When it is detected that the addressing address information is invalid, the first - stage chip feeds back that the address is invalid or the main controller obtains the feedback of invalid address.

[0022] In a possible implementation, the addressing addresses corresponding to the first - stage chip and each second - stage chip are the same.

[0023] In a possible implementation, the communication method further includes:

[0024] The second - stage chip in the chip - select series structure that has not received the addressing address information transparently transmitted by the previous chip monitors the addressing address information transparently transmitted by the previous chip;

[0025] When the addressing address information transmitted transparently by the previous chip is not received, it is determined to select the current second-level chip as the communication chip;

[0026] When the addressing address information transmitted transparently by the previous chip is received, the subsequent addressing address information transmitted transparently is transmitted from the current second-level chip to the next second-level chip in the chip select series structure.

[0027] In a possible implementation, detecting the addressing address information includes:

[0028] The addressing address information includes a chip select start signal, differential address information, and a chip select end signal;

[0029] When the correct chip select start signal sent by the main controller is received, it is determined to start receiving the differential address information sent by the main controller;

[0030] When the length of the received differential address information conforms to the protocol length of the preset address and the correct chip select end signal sent by the main controller is received, it is determined that the addressing address information is valid;

[0031] When the received differential address information is the same as the addressing address corresponding to the first-level chip and each second-level chip, and the correct chip select end signal sent by the main controller is received, it is determined that the addressing address information is correct;

[0032] Otherwise, it is determined that the addressing address information is invalid.

[0033] In a possible implementation, when the time length and timing of the received chip select start signal meet the preset start flag requirements, it is determined that the correct chip select start signal is received;

[0034] When the time length and timing of the received chip select end signal meet the preset end flag requirements, it is determined that the correct chip select end signal is received.

[0035] The serial multi-chip communication device and corresponding method applied to the signal chain chip of the present invention are specially designed and developed in view of the increased complexity of the signal chain chip circuit design and the occupied hardware resources in the prior art; the present invention can reduce resource overhead to meet the requirements of chip products: through a custom communication protocol, the complexity of the bus is reduced; using the SPI interface can ensure a high communication rate, and different slave chips can be accessed through address addressing, and it is easy to adjust and expand.

[0036] Through the following detailed description of the best embodiments of the present invention in conjunction with the drawings, these and other advantages of the present invention will become more obvious. Brief Description of the Drawings

[0037] The present invention can be better understood by referring to the description given below in conjunction with the accompanying drawings, in which the same or similar reference numerals are used throughout the drawings to denote the same or similar components. The accompanying drawings, together with the following detailed description, are included in this specification and form a part of this specification, and are further used to illustrate the preferred embodiments of the present invention and to explain the principles and advantages of the present invention. In the drawings:

[0038] Figure 1 is a schematic structural diagram showing a multi-chip interconnection device of the prior art;

[0039] Figure 2 is a schematic diagram showing a serial multi-chip communication device applied to a signal chain chip according to an embodiment of the present invention;

[0040] Figure 3 is a flowchart showing a serial multi-chip communication method applied to a signal chain chip according to an embodiment of the present invention;

[0041] Figure 4 is a schematic diagram showing the timing relationship of addressing address information according to an embodiment of the present invention;

[0042] Figure 5 is a flowchart showing the realization of serial multi-chip communication of signal chain chips by using a bus according to an embodiment of the present invention.

[0043] Those skilled in the art should understand that the elements in the drawings are shown only for simplicity and clarity, and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to help improve the understanding of the embodiments of the present invention. Detailed Embodiments

[0044] In the following, exemplary embodiments of the present invention will be described in conjunction with the accompanying drawings. For clarity and conciseness, not all features of the actual embodiments are described in the specification. However, it should be understood that many specific implementation decisions must be made during the development of any such actual embodiment to achieve the specific goals of the developer, for example, to comply with those system- and business-related constraints, and these constraints may vary with different embodiments. In addition, it should also be understood that although the development work may be very complex and time-consuming, for those skilled in the art who benefit from the present disclosure, such development work is only a routine task.

[0045] Here, it should also be noted that, in order to avoid obscuring the present invention with unnecessary details, only the device structures closely related to the solution according to the present invention are shown in the drawings, and other details less related to the present invention are omitted. As Figure 2As shown in the figure, an embodiment of the present invention provides a serial multi-chip communication device applied to a signal chain chip, including: a main controller, a first-level chip, and at least one second-level chip.

[0046] Wherein, the chip select differential negative terminal of the main controller is interconnected with the chip select input terminal of the first-level chip;

[0047] Each chip in the second-level chips is sequentially connected to the chip select input terminal of the next chip through the slave chip select output terminal, forming a chip select series structure of the at least one second-level chip;

[0048] The slave chip select output terminal of the first-level chip is interconnected with the chip select input terminal of the first second-level chip in the chip select series structure;

[0049] The serial differential positive terminal of the main controller is interconnected with the slave input terminal of the first-level chip and the slave input terminal of each second-level chip;

[0050] The clock signal output terminal of the main controller is interconnected with the clock signal input terminal of the first-level chip and the clock signal input terminal of each second-level chip;

[0051] The feedback signal input terminal of the main controller is interconnected with the slave output terminal of the first-level chip and the slave output terminal of each second-level chip.

[0052] As Figure 2 shown, in the embodiment of the present invention, the chip select differential negative terminal (serial_n port) of the main controller is connected to the chip select input terminal (SPI_CS port) of the first-level chip. The serial differential positive terminal (serial_p port) of the main controller is connected to the slave input terminal (SPI_MOSI port) of the first-level chip. At the same time, the serial differential positive terminal (serial_p port) of the main controller is connected to the slave input terminal (SPI_MOSI port) of each second-level chip. The clock signal output terminal of the main controller is connected to the clock signal input terminal (SPI_CLK port) of the first-level chip. At the same time, the clock signal output terminal of the main controller is connected to the clock signal input terminal (SPI_CLK port) of each second-level chip. The feedback signal input terminal of the main controller is connected to the slave output terminal (SPI_MISO port) of the first-level chip. At the same time, the feedback signal input terminal of the main controller is connected to the slave output terminal (SPI_MISO port) of each second-level chip.

[0053] Table 1 illustrates the pins and signals of the serial multi-chip communication device applied to the signal chain chip in the embodiment of the present invention.

[0054] Table 1

[0055] Signal Name Bit Width Direction Description serial_n (connected to SPI_CS) 1 I Negative terminal of chip select differential serial_p (connected to SPI_MOSI) 1 I Positive terminal of serial differential serial_o (connected to CSB_SW) 1 O Positive terminal of serial differential output

[0056] Each second - level chip is connected to the chip - select input terminal (SPI_CS port) of the next second - level chip through the slave chip - select output terminal (CSB_SW port). At least one second - level chip is successively connected through the slave chip - select output terminal (CSB_SW port) and the chip - select input terminal (SPI_CS port) to form a chip - select series structure of the second - level chips. The slave chip - select output terminal CSB_SW of the first - level chip is connected to the chip - select input terminal (SPI_CS port) of the first second - level chip in the chip - select series structure, forming a serial signal chain of the slave chips including the first - level chip and the second - level chips.

[0057] In a possible implementation, the first - level chip and each second - level chip use the same chip.

[0058] In a possible implementation, the main controller is connected to the first - level chip and each second - level chip through SPI (Serial Peripheral Interface).

[0059] In a second aspect, as Figure 3 shown, the present invention also provides a serial multi - chip communication method applied to signal - chain chips, which is applied to the above - mentioned communication device. The method includes:

[0060] S100. The first - level chip monitors the addressing address information of the main controller, and when receiving the addressing address information, detects the addressing address information.

[0061] S200. According to the detection result of the addressing address information, determine whether to select the first - level chip as the communication chip.

[0062] In the embodiment of the present invention, a serial signal chain of slave chips is adopted. The main controller is directly connected to the chip - select input terminal of the first - level chip and not directly connected to the chip - select input terminal of the second - level chip. The chip - select signal needs to be transmitted through the slave chip - select output terminal of the first - level chip. First, the first - level chip monitors whether it receives the addressing address information sent by the main controller. When receiving the addressing address information, it detects the addressing address information to determine whether to determine that the first - level chip is the communication chip.

[0063] Particularly, in the embodiment of the present invention, it is default that the first - level chip is the communication chip. That is, when the host does not send the addressing address information, at this time the first - level chip does not receive the addressing address information, and the host can also directly communicate with the first - level chip and use the first - level chip as the communication chip.

[0064] When it is determined that the first - stage chip is a communication chip, activate or enable the slave output terminal (SPI_MISO port) of the first - stage chip, and pull up the slave chip - select output terminal (CSB_SW port) of the first - stage chip, so that the addressing address information sent by the master controller is only transmitted to the chip - select input terminal (SPI_CS port) of the first - stage chip. After being detected by the first - stage chip, the addressing address information sent by the master controller will not be forwarded to the slave chip - select output terminal (CSB_SW port) of the first - stage chip.

[0065] When it is determined that the first - stage chip is not a communication chip, the first - stage chip transparently transmits the addressing address information sent by the master controller from the chip - select input terminal (SPI_CS port) of the first - stage chip to the slave chip - select output terminal (CSB_SW port) of the first - stage chip, and then transmits it to the chip - select input terminal (SPI_CS port) of the first - level second - stage chip at the head of the chip - select cascade structure. The signal line of the positive end of the serial differential output (serial_p) of the master controller is connected to the slave input terminal (SPI_MOSI port) of all slave devices (the first - stage chip and each second - stage chip). At this time, for the transparently transmitted first - stage chip, the master controller sends and receives data or addresses as usual. The transparently transmitted first - stage chip releases the control of the signal line of the slave output terminal (SPI_MISO port), and only listens to the addressing address information of serial_n and serial_p, so that the addressing address information sent by the master controller is transparently transmitted from the chip - select input terminal (SPI_CS port) of the first - stage chip to the slave chip - select output terminal (CSB_SW port) of the first - stage chip, and then transmitted to the chip - select input terminal (SPI_CS port) of the first - level second - stage chip at the head.

[0066] In a possible implementation, determining whether to select the first - stage chip as a communication chip according to the detection result of the addressing address information includes:

[0067] When it is detected that the addressing address information is valid and correct, transparently transmit the subsequent received addressing address information from the first - stage chip to the first - level second - stage chip at the head of the chip - select cascade structure;

[0068] When it is detected that the addressing address information is valid and incorrect, determine to select the first - stage chip as a communication chip;

[0069] When it is detected that the addressing address information is invalid, the first - stage chip feeds back to the master controller that the address is invalid or the master controller obtains the feedback that the address is invalid.

[0070] In the embodiment of the present invention, when it is detected that the addressing address information is invalid, the error flag bit in the register inside the first - stage chip is set. The master controller can access the register inside the first - stage chip through the SPI bus to obtain the status of the error flag bit, so as to obtain the feedback that the address is invalid.

[0071] In a possible implementation, the addressing addresses corresponding to the first-level chip and each second-level chip are the same.

[0072] In the embodiments of the present invention, the keys of each slave chip are the same, and the access strategies for different chips are as follows:

[0073] 1. When a valid addressing address information (key) is received and the key is correct, the function of the first-level chip is transparently passed through; the subsequently received key is forwarded from the SPI_CS port forwarded by the first-level chip to the CSB_SW port, and the control of the SPI_MISO signal line by the first-level chip is released.

[0074] 2. When a valid key is received but the key is incorrect, the function of the first-level chip is activated (at this time, the subsequent key will not be forwarded from the first-level chip, and the control of the SPI_MISO signal line by the first-level chip is activated).

[0075] 3. When an invalid key is received (for example, not meeting the protocol length or time requirements corresponding to the key), the address error flag of the first-level chip is used for marking, or it is fed back to the main controller that the address addressing information is invalid or no response is made.

[0076] In a possible implementation, the communication method further includes:

[0077] The second-level chip in the chip select series structure that does not receive the addressing address information transparently transmitted by the previous chip listens for the addressing address information transparently transmitted by the previous chip;

[0078] When the addressing address information transparently transmitted by the previous chip is not received, it is determined to select the current second-level chip as the communication chip;

[0079] When the addressing address information transparently transmitted by the previous chip is received, the subsequently transparently transmitted addressing address information is transparently transmitted from the current second-level chip to the next second-level chip in the chip select series structure.

[0080] In the embodiments of the present invention, the second-level chips all receive the transparently transmitted addressing address information. Among them, the first second-level chip in the chip select series structure receives the addressing address information transparently transmitted by the first-level chip, and the other second-level chips (except the first second-level chip) in the chip select series structure receive the addressing address information transparently transmitted by the previous second-level chip.

[0081] The second-level chip that has not received the addressed address information continues to listen for the transparently transmitted addressed address information. If the transparently transmitted addressed address information is not received, it is determined to select the current second-level chip as the communication chip. If the transparently transmitted addressed address information is received, it will not be selected as the communication chip, and the subsequent transparently transmitted addressed address information will be forwarded from the SPI_CS port of the current second-level chip to the CSB_SW port and transparently transmitted to the SPI_CS port of the next second-level chip.

[0082] The first-level chip always listens for the key of the main controller. When a valid key is received but the key is incorrect, the first-level chip is reselected as the communication chip to activate the function of the first-level chip.

[0083] The second-level chip also always listens for the key transmitted by the previous second-level chip (the first second-level chip listens for the key transmitted by the first-level chip). When a valid and correct key is received, the current second-level chip is in the transparent transmission state and the key is passed to the next second-level chip. If the current second-level chip is in the non-transparent transmission state, the key received this time will not be passed to the next second-level chip, and the signal received at the SPI_CS port of the second-level chip will not be transparently transmitted to the CSB_SW port, that is, the serial_n signal of the second-level chip will not be transparently transmitted to the serial_o signal.

[0084] In the embodiment of the present invention, the main controller switches to different second-level chips for communication by sending the correct key (the number of times different second-level chips send the correct key is different). The main controller switches back to the first-level chip by sending an incorrect key.

[0085] In the embodiment of the present invention, the first-level chip and the second-level chips use the same addressed address, that is, the key of the first-level chip and each second-level chip is the same. When the main controller sends a valid but incorrect key, the first-level chip is selected as the communication chip. When the main controller sends a valid and correct key once, the first second-level chip is selected as the communication chip. When the main controller continuously sends a valid and correct key twice, the second second-level chip is selected as the communication chip. When the main controller continuously sends a valid and correct key three times, the third second-level chip is selected as the communication chip, and so on. The main controller switches to different second-level chips for communication by continuously sending a valid and correct key multiple times. By sending a valid but incorrect key, it switches back to the first-level chip for communication.

[0086] In a possible implementation, the detection of the addressed address information includes:

[0087] The addressed address information includes a chip select start signal, differential address information, and a chip select end signal (as Figure 4 shown);

[0088] When receiving the correct chip select start signal sent by the master controller, determine to start receiving the differential address information sent by the master controller;

[0089] When the length of the received differential address information conforms to the protocol length of the preset address and the correct chip select end signal sent by the master controller is received, determine that the addressed address information is valid;

[0090] When the received differential address information is the same as the addressed address corresponding to the first-level chip and each second-level chip, and the correct chip select end signal sent by the master controller is received, determine that the addressed address information is correct;

[0091] Otherwise, determine that the addressed address information is invalid.

[0092] In the embodiment of the present invention, it is detected whether the differential address information is valid and / or correct according to the protocol length and time requirements corresponding to the key.

[0093] In a possible implementation, when the time length and timing of the received chip select start signal meet the preset start flag requirements, it is determined that the correct chip select start signal is received;

[0094] When the time length and timing of the received chip select end signal meet the preset end flag requirements, it is determined that the correct chip select end signal is received.

[0095] As Figure 4 shown, the master controller sends the chip select start signal to the chip select input terminal SPI_CS of the first-level chip through the chip select differential negative terminal serial_n, and presets the rule of the timing sequence of the correct chip select start signal (start flag requirements), as Figure 4 shown, the preset correct chip select start signal is that serial_n maintains a high pulse and serial_p maintains a low pulse and lasts for a duration of Tstart (since serial_p is the inverted signal of serial_n and forms a differential pair, ideally there is no time difference between the transition edges of the differential pair serial_p and serial_n. In actual situations, due to various reasons, there may be a time difference between the transition edges of the differential pair serial_p and serial_n. Tskew represents the time difference between the transition edges of serial_p and serial_n. The protocol requires that this value must be less than the specified maximum value. Figure 4Among them, there is a time difference Tskew between the transition edges of the differential pair serial_p and serial_n, which is shown before Tstart. In actual situations, as long as the differential signal transitions, there may be a time difference between the differential pair serial_p and serial_n. For example, there will be time differences in the START signal, the intermediate data transmission process, and the STOP signal, and each time difference also needs to meet the corresponding protocol requirements. In other embodiments, other correct rules for the timing sequence of the chip select start signal can be set. For example, the correct chip select start signal is that serial_n maintains a low pulse and serial_p maintains a high pulse and lasts for a preset duration, or serial_n alternates between high and low pulses and the durations of the high and low pulses are the same and are t, or serial_n alternates between high and low pulses and the duration of the high pulse is twice the duration of the low pulse (serial_p is the inverted signal of serial_n, and the corresponding low and high pulses alternate).

[0096] The first-level chip judges the chip select start signal received at the chip select input end SPI_CS using the rules of the preset timing sequence. When it is determined that the correct chip select start signal is received, it starts to receive the differential address information sent by the master controller to the chip select input end SPI_CS of the first-level chip through the chip select differential negative end serial_n. In the embodiments of the present invention, the addressing addresses corresponding to the first-level chip and each second-level chip are the same, and the timing sequence of the preset valid and correct differential address information (the same as the addressing addresses corresponding to the first-level chip and each second-level chip) is set. Among them, the addressing address is valid and correct, indicating that the length of the addressing address meets the requirements, and for each corresponding address bit, its bit period meets the Tperiod requirement, the pulse widths for sending high and low levels meet the requirements of Tpulse_0 or Tpuls_1, and the offset Tsekw between the differential signals meets the requirements. Figure 4 Among them, the cycle time for transmitting a single bit of data is represented as Tperiod. Among them, Tpulse_1 represents the time when serial_p or SPI_MOSI is a high pulse when the data is 1, and Tpulse_0 represents the time when serial_p or SPI_MOSI is a high pulse when the data is 0.

[0097] The identifier for receiving all the differential address information is that the master controller sends a correct chip select termination signal. In the embodiments of the present invention, the rules for the timing sequence of the correct chip select termination signal (termination flag requirements) are preset, such as Figure 4Among them, the preset correct chip select termination signal is that serial_n maintains a low pulse and serial_p maintains a low pulse and lasts for a duration of Tstop. In other embodiments, other rules for the timing sequence of the correct chip select termination signal can be set. For example, the correct chip select termination signal is that serial_n maintains a high pulse and serial_p maintains a low pulse and lasts for a preset duration, or serial_n alternates between high and low pulses and the durations of the high and low pulses are the same and are t, or serial_n alternates between high and low pulses and the duration of the high pulse is twice the duration of the low pulse (serial_p is the inverted signal of serial_n, and the corresponding low and high pulses alternate).

[0098] Table 2 illustrates the parameters and meanings of the addressing address information in the embodiments of the present invention.

[0099] Table 2

[0100]

[0101] Among them, Tclk is a clock signal with a fixed time. In the embodiments of the present invention, Tclk can be an 8mhz clock.

[0102] As Figure 5 shown, the process of the first-level chip detecting the addressing address information is described as follows:

[0103] First, determine whether the flag of the chip select start signal is detected. Specifically, detect that the duration of serial_n = 1 and serial_p = 0 meets the time requirement of Tstart.

[0104] Second, when the flag is detected, start receiving the chip select start signal. Specifically, wait for the differential signal serial_n = 0, serial_p = 1. If the waiting time for the differential signal serial_n = 0, serial_p = 1 exceeds the maximum allowable time, it is determined that the differential signal is not waited for, the reception of the addressing address information fails, the corresponding error flag bit is set, and the initial state is returned.

[0105] Thirdly, if the differential signal is received within the maximum allowed time, it is determined whether the correct chip select start signal is received. Specifically, the stable time of the differential signal serial_n = 1 and serial_p = 0 is timed, and it is determined whether the stable time of the differential signal meets the requirements of the high / low level stable time; when the stable time of the differential signal meets the requirements of the high / low level stable time, it is determined that the correct chip select start signal is received, otherwise (the stable time of the differential signal does not meet the requirements of the high / low level stable time), it is determined that the correct chip select start signal is not received, the reception of the addressing address information fails, the corresponding error flag bit is set, and the initial state is returned. It should be noted that in the embodiments of the present invention, only when the chip select start signal is detected and an error occurs later will the corresponding error flag bit be set. If the chip select start signal is not detected, the corresponding error flag bit will not be set.

[0106] Fourthly, when the correct chip select start signal is received, it is determined whether the valid differential address information is received. Specifically, it is determined whether the sum of the differential signal transmission times of the received differential address information meets the requirements of the single-bit data cycle. When the sum of the transmission times is greater than the specified maximum duration or less than the specified minimum duration, the reception of the addressing address information fails, the corresponding error flag bit is set, and the initial state is returned.

[0107] Fifthly, when the sum of the transmission times meets the requirements of the single-bit data cycle, it is determined whether the length of the received data reaches the length of the key (the length of the addressing addresses corresponding to the first-level chip and the second-level chip). If the length does not reach the length of the key, the process returns to start receiving the chip select start signal.

[0108] Sixthly, when it is determined that the length of the received data reaches the length of the key, it is determined whether the correct chip select end signal is received. Specifically, it is waited for and detected whether the duration of the chip select end signal meets the minimum duration of the stop flag (or whether the stable time of the chip select end signal meets the requirements of the high / low level stable time). If the duration of the chip select end signal is less than the specified minimum duration of the stop flag, it is determined that the incorrect chip select end signal is received, the reception of the addressing address information fails, and the initial state is returned.

[0109] Seventhly, when the correct chip select end signal is received, it is further determined whether the correct differential address information is received, that is, it is determined whether the received key is correct. When the correct differential address information is received, the input of serial_n is passed through to serial_o, and at the same time, the SPI function of the first-level chip is passed through; when the incorrect differential address information is received, the SPI function of the first-level chip is activated, and the output of serial_o is set to 1.

[0110] The serial multi-chip communication device and corresponding method applied to the signal chain chip according to the embodiments of the present application can better meet the requirements of the interconnection communication bus between signal chain chips, and reduce the number of ports and complexity of the interconnection bus between chips; the number of serial slave chips is not limited, and flexible adjustment and expansion can be achieved; the device and method according to the embodiments of the present invention have a highly reliable communication mechanism for address addressing.

[0111] It should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application.

[0112] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined.

[0113] In the present application, unless otherwise clearly defined and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be directly connected, or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0114] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

[0115] Although the present invention has been described in terms of a limited number of embodiments, those skilled in the art of the present technology will appreciate that other embodiments can be contemplated within the scope of the present invention as thus described. Additionally, it should be noted that the language used in this specification has been principally selected for readability and teaching purposes rather than for the purpose of explaining or limiting the subject matter of the present invention. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. For the scope of the present invention, the disclosure of the present invention is illustrative and not restrictive, and the scope of the present invention is defined by the appended claims.

Claims

1. A serial multi-chip communication device applied to a signal chain chip, characterized in that Including: A main controller, a first-level chip, and at least one second-level chip; The chip select differential negative terminal of the main controller is interconnected with the chip select input terminal of the first-level chip; Each chip in the at least one second-level chip is sequentially connected to the chip select input terminal of the next chip through the slave chip select output terminal, forming a chip select series structure of the at least one second-level chip; The slave chip select output terminal of the first-level chip is interconnected with the chip select input terminal of the first second-level chip in the chip select series structure; The serial differential positive terminal of the main controller is interconnected with the slave input terminal of the first-level chip and the slave input terminal of each second-level chip; The clock signal output terminal of the main controller is interconnected with the clock signal input terminal of the first-level chip and the clock signal input terminal of each second-level chip; The feedback signal input terminal of the main controller is interconnected with the slave output terminal of the first-level chip and the slave output terminal of each second-level chip.

2. The communication device according to claim 1, wherein, The first-level chip and each second-level chip use the same chip.

3. The communication device according to claim 1, wherein, The main controller is connected to the first-level chip and each second-level chip through a serial peripheral interface.

4. Serial multi-chip communication method applied to signal chain chips, characterized in that Applied to the communication device according to any one of claims 1 to 3, the method includes: The first-level chip listens to the addressing address information of the main controller, and when receiving the addressing address information, detects the addressing address information; According to the detection result of the addressing address information, determine whether to select the first-level chip as the communication chip.

5. The communication method according to claim 4, wherein Determining whether to select the first-level chip as the communication chip according to the detection result of the addressing address information includes: When it is detected that the addressing address information is valid and correct, the subsequent received addressing address information is transparently transmitted from the first-level chip to the first second-level chip in the chip select series structure; When it is detected that the addressing address information is valid and incorrect, determine to select the first-level chip as the communication chip; When it is detected that the addressing address information is invalid, the first-level chip feeds back that the address is invalid or the main controller obtains the feedback of invalid address to the main controller.

6. The communication method according to claim 5, wherein The addressing addresses corresponding to the first-level chip and each second-level chip are the same.

7. The communication method according to claim 6, wherein Further including: The second-level chip in the chip select series structure that does not receive the addressing address information transparently transmitted by the previous chip listens to the addressing address information transparently transmitted by the previous chip; When not receiving the addressing address information transparently transmitted by the previous chip, determine to select the current second-level chip as the communication chip; When receiving the addressing address information transparently transmitted by the previous chip, the subsequent transparently transmitted addressing address information is transparently transmitted from the current second-level chip to the next second-level chip in the chip select series structure.

8. The communication method according to claim 6, characterized in that, Detecting the addressing address information includes: The addressing address information includes a chip select start signal, differential address information, and a chip select end signal; When receiving the correct chip select start signal sent by the main controller, determine to start receiving the differential address information sent by the main controller; When the length of the received differential address information meets the protocol length of the preset address and the correct chip select end signal sent by the main controller is received, determine that the addressing address information is valid; When the received differential address information is the same as the addressing addresses corresponding to the first-level chip and each second-level chip, and a correct chip select termination signal sent by the main controller is received, it is determined that the addressing address information is correct; Otherwise, it is determined that the addressing address information is invalid.

9. The communication compatibility method according to claim 8, wherein When the time length and timing of the received chip select start signal meet the preset start flag requirements, it is determined that a correct chip select start signal is received; When the time length and timing of the received chip select termination signal meet the preset termination flag requirements, it is determined that a correct chip select termination signal is received.

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