Serial multi-chip communication device and corresponding method for application in signal chain chips

Abstract

The application provides a serial multi-chip communication device applied to a signal chain chip and a corresponding method. It relates to the technical field of chip serial communication and solves the problems of line design complexity and increased hardware resource occupation in the prior art. The device comprises: a chip select differential negative end of a master controller and a chip select input end of a first-level chip are interconnected; a second-level chip forms a chip select series connection structure; a slave chip select output end of the first-level chip and a chip select input end of a first second-level chip of the chip select series connection structure are interconnected; a serial differential positive end, a clock signal output end and a feedback signal input end of the master controller are respectively interconnected with a slave input end, a clock signal input end and a slave output end of the first-level chip and each second-level chip. The application can reduce resource consumption, realize access to different slave chips and is easy to adjust and expand.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip serial communication, and in particular to a serial multi-chip communication device applied to a signal chain chip and a corresponding method. BACKGROUND

[0002] At present, the inter-chip communication bus based on SPI (Serial Peripheral Interface) is applied more and more widely in the communication technical field because of its high communication rate, such as Figure 1 As shown in the figure, when facing the multi-chip interconnection scene, the master chip is interconnected with the interface of each slave chip through multiple interfaces, and access and data transmission are realized, but with the increase of the number of chip selection lines, the complexity of the line and hardware design is increased, which leads to the increase of the complexity of the line design and the occupied hardware resources, and the demand for high efficiency and low cost communication in the communication technical field cannot be met. SUMMARY

[0003] In the following, a brief summary of the present application is given in order to provide a basic understanding of some aspects of the present application. It should be understood that this summary is not a comprehensive summary of the present application. It is not intended to determine the key or important parts of the present application, nor to limit the scope of the present application. Its purpose is only to give some concepts in a simplified form as a prelude to the more detailed description discussed later.

[0004] In view of this, the present application proposes a serial multi-chip communication device applied to a signal chain chip and a corresponding method, which can reduce the hardware resources occupied by the signal chain chip and realize high efficient communication rate.

[0005] The present application provides a serial multi-chip communication device applied to a signal chain chip, comprising:

[0006] a master controller, a first-level chip and at least one second-level chip;

[0007] the chip selection differential negative end of the master controller is interconnected with the chip selection input end of the first-level chip;

[0008] each chip in the second-level chip is connected with the chip selection input end of the next chip through the slave chip selection output end in sequence, forming a chip selection series structure of the at least one second-level chip;

[0009] the slave chip selection output end of the first-level chip is interconnected with the chip selection input end of the first second-level chip of the chip selection series structure;

[0010] the serial differential positive end of the master controller is interconnected with the slave input end of the first-level chip and the slave input end of each second-level chip.

[0011] The clock signal output end of the main controller is interconnected with the clock signal input end of the first-level chip and the clock signal input end of each second-level chip;

[0012] The feedback signal input end of the main controller is interconnected with the slave output end of the first-level chip and the slave output end of each second-level chip.

[0013] In a possible implementation manner, the first-level chip and each second-level chip adopt the same chip.

[0014] In a possible implementation manner, the main controller is connected with the first-level chip and each second-level chip through a serial peripheral interface.

[0015] In a second aspect, the present application further provides a serial multi-chip communication method applied to a signal chain chip, which is applied to the communication device described above, and the method comprises:

[0016] The first-level chip listens to the addressing address information of the main controller, and detects the addressing address information when the addressing address information is received;

[0017] According to the detection result of the addressing address information, it is determined whether to select the first-level chip as a communication chip.

[0018] In a possible implementation manner, according to the detection result of the addressing address information, it is determined whether to select the first-level chip as a communication chip, which comprises:

[0019] When it is detected that the addressing address information is valid and correct, the subsequently received addressing address information is transmitted from the first-level chip to the first second-level chip in the chip select series connection structure;

[0020] When it is detected that the addressing address information is valid and incorrect, it is determined to select the first-level chip as a communication chip;

[0021] When it is detected that the addressing address information is invalid, the first-level chip feeds back to the main controller that the address is invalid or the main controller obtains the feedback that the address is invalid.

[0022] In a possible implementation manner, the addressing address corresponding to the first-level chip and each second-level chip is the same.

[0023] In a possible implementation manner, the communication method further comprises:

[0024] The second-level chip in the chip select series connection structure which does not receive the addressing address information transmitted by the previous chip listens to the addressing address information transmitted by the previous chip;

[0025] When the addressing address information transparently transmitted by the previous chip is not received, it is determined that the current second chip is selected as the communication chip;

[0026] When the addressing address information transparently transmitted by the previous chip is received, the addressing address information transparently transmitted by the subsequent chip is transmitted from the current second chip to the next second chip in the chip selection series structure.

[0027] In a possible implementation, the detection on the addressing address information comprises:

[0028] The addressing address information comprises a chip selection start signal, differential address information and a chip selection end signal;

[0029] When the correct chip selection start signal sent by the host controller is received, it is determined that the differential address information sent by the host controller is started to be received;

[0030] When the length of the received differential address information meets the protocol length of the preset address, and the correct chip selection end signal sent by the host controller is received, it is determined that the addressing address information is valid;

[0031] When the received differential address information is the same as the addressing address corresponding to the first chip and each second chip, and the correct chip selection end signal sent by the host controller is received, it is determined that the addressing address information is correct;

[0032] Otherwise, it is determined that the addressing address information is invalid.

[0033] In a possible implementation, when the time length and timing of the received chip selection start signal meet the preset start flag requirement, it is determined that the correct chip selection start signal is received;

[0034] When the time length and timing of the received chip selection end signal meet the preset end flag requirement, it is determined that the correct chip selection end signal is received.

[0035] The serial multi-chip communication device applied to the signal chain chip and the corresponding method are specially designed and developed in view of the complexity of the signal chain chip line design and the increase of the occupied hardware resources in the prior art. The application can reduce resource consumption to meet the needs of chip products: through a self-defined communication protocol, the complexity of the bus is reduced; the use of the SPI interface can ensure a high communication rate, and the access to different slave chips is realized through address addressing, and the application is easy to adjust and expand.

[0036] These and other advantages of the application will become apparent from the following detailed description of the preferred embodiment, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0037] The present application can be better understood with reference to the following description in conjunction with the accompanying drawings, in which like reference numerals are used to indicate like elements in the detailed drawings. The accompanying drawings constitute a part of this specification and include exemplary embodiments of the present application and illustrate preferred embodiments of the present application and, together with the detailed description, serve to explain the principles and advantages of the present application. In the drawings:

[0038] Figure 1 is a structural schematic diagram showing a multi-chip interconnection device of the prior art;

[0039] Figure 2 is a schematic diagram showing a serial multi-chip communication device applied to a signal chain chip according to an embodiment of the present application;

[0040] Figure 3 is a flowchart showing a serial multi-chip communication method applied to a signal chain chip according to an embodiment of the present application;

[0041] Figure 4 is a schematic diagram showing a timing relationship of address information according to an embodiment of the present application;

[0042] Figure 5 is a flowchart showing a serial multi-chip communication method applied to a signal chain chip using a bus according to an embodiment of the present application.

[0043] Those skilled in the art will appreciate that the elements in the figures are merely for the purpose of illustration and that they are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures can be exaggerated relative to others for purposes of more readily showing and describing the present application. DETAILED DESCRIPTION

[0044] Exemplary embodiments of the present application will be described hereinafter with reference to the accompanying drawings. In the description, all the features of the actual implementation are not described in the specification for the sake of clarity and conciseness. However, it should be appreciated that many implementation-specific decisions can have to be made in order to develop any such actual implementation, to achieve the developer's specific goals, such as compliance with system- and business-related constraints, which will vary from one implementation to another. It should also be appreciated that such a development effort might be very complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

[0045] It is also to be understood that the application is not limited in its application to the details of construction and the arrangement of components set forth in the description or illustrated in the drawings. The application is capable of other embodiments and of being practiced or being carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should in no way be regarded as limiting. As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, can readily be utilized as a basis for the designing of other structures, methods and systems for carrying out the several purposes of the present application. Figure 2As shown, an embodiment of the present invention provides a serial multi-chip communication device applied to a signal chain chip, comprising: a main controller, a first-level chip, and at least one second-level chip.

[0046] The chip select differential negative terminal of the main controller is interconnected with the chip select input terminal of the first-stage chip;

[0047] Each chip in the second-level chip is sequentially connected to the chip select input of the next chip via the slave chip select output terminal, forming a chip select series structure of at least one second-level chip;

[0048] The slave chip select output terminal of the first-level chip is interconnected with the chip select input terminal of the first second-level chip in the chip select serial structure;

[0049] The serial differential positive terminal of the main controller is interconnected with the slave input terminal of the first-stage chip and the slave input terminal of each second-stage chip;

[0050] The clock signal output terminal of the main controller is interconnected with the clock signal input terminal of the first-stage chip and the clock signal input terminal of each second-stage chip;

[0051] The feedback signal input terminal of the master controller is interconnected with the slave output terminal of the first-level chip and the slave output terminal of each second-level chip.

[0052] like Figure 2 As shown, in this embodiment of the invention, the negative terminal of the chip select differential of the master controller (serial_n port) is connected to the chip select input of the first-stage chip (SPI_CS port). The positive terminal of the serial differential of the master controller (serial_p port) is connected to the slave input of the first-stage chip (SPI_MOSI port), and simultaneously, the positive terminal of the serial differential of the master controller (serial_p port) is connected to the slave input of each second-stage chip (SPI_MOSI port). The clock signal output of the master controller is connected to the clock signal input of the first-stage chip (SPI_CLK port), and simultaneously, the clock signal output of the master controller is connected to the clock signal input of each second-stage chip (SPI_CLK port). The feedback signal input of the master controller is connected to the slave output of the first-stage chip (SPI_MISO port), and simultaneously, the feedback signal input of the master controller is connected to the slave output of each second-stage chip (SPI_MISO port).

[0053] Table 1 illustrates the pins and signals of the serial multi-chip communication device applied to the signal chain chip in the embodiments of the present invention.

[0054] Table 1

[0055] Signal Name Bit Width Direction Description serial_n (connects to SPI_CS) 1 I Chip Select differential negative serial_p (connects to SPI_MOSI) 1 I Serial differential positive serial_o (connects to CSB_SW) 1 O Serial differential output positive

[0056] Each second-level chip is connected with the chip select input end (SPI_CS port) of the next second-level chip through the slave chip select output end (CSB_SW port), and at least one second-level chip is connected in sequence through the slave chip select output end (CSB_SW port) and the chip select input end (SPI_CS port), so that a chip select series connection structure of the second-level chips is formed; the slave chip select output end CSB_SW of the first-level chip is connected with the chip select input end (SPI_CS port) of the first second-level chip in the chip select series connection structure, so that a serial signal chain of the slave chips including the first-level chip and the second-level chips is formed.

[0057] In a possible implementation manner, the first-level chip and each second-level chip are the same chip.

[0058] In a possible implementation manner, the master controller is connected with the first-level chip and each second-level chip through an SPI (Serial Peripheral Interface).

[0059] In a second aspect, as shown in the accompanying drawings, Figure 3 The application further provides a serial multi-chip communication method applied to the signal chain chip, which is applied to the communication device.

[0060] S100, the first-level chip listens to the addressing address information of the master controller, and detects the addressing address information when receiving the addressing address information;

[0061] S200, whether the first-level chip is selected as a communication chip is determined according to the detection result of the addressing address information.

[0062] The serial signal chain of the slave chips is adopted in the embodiment of the application, the master controller is directly connected with the chip select input end of the first-level chip, and is not directly connected with the chip select input end of the second-level chip, and needs to transmit the chip select signal through the slave chip select output end of the first-level chip. First, the first-level chip listens to whether the addressing address information sent by the master controller is received, and when the addressing address information is received, the addressing address information is detected to determine whether the first-level chip is determined as a communication chip.

[0063] In particular, in the embodiment of the application, the first-level chip is determined as a communication chip by default, that is, when the master does not send the addressing address information, the first-level chip does not receive the addressing address information, and the master can directly communicate with the first-level chip, and the first-level chip is used as a communication chip.

[0064] When it is determined that the first-level chip is a communication chip, a slave output end (SPI_MISO port) of the first-level chip is activated or enabled, and a slave chip select output end (CSB_SW port) of the first-level chip is pulled high, so that the addressing address information sent by the master controller is only transmitted to a chip select input end (SPI_CS port) of the first-level chip, and the addressing address information sent by the master controller will not be forwarded to the slave chip select output end (CSB_SW port) of the first-level chip through detection of the first-level chip.

[0065] When it is determined that the first-level chip is not a communication chip, the first-level chip transmits the addressing address information sent by the master controller from the chip select input end (SPI_CS port) of the first-level chip to the slave chip select output end (CSB_SW port) of the first-level chip, and then to a chip select input end (SPI_CS port) of a first second-level chip in the chip select series structure. A signal line of a serial differential positive end (output serial_p) of the master controller is connected to slave input ends (SPI_MOSI ports) of all slave devices (the first-level chip and each second-level chip), at this time, the first-level chip transmits the addressing address information as usual, the master controller transmits or receives data or an address, and the first-level chip transmits the addressing address information, and the first-level chip releases control of the slave output end (SPI_MISO port) signal line and only listens to serial_n and serial_p, so that the addressing address information sent by the master controller is transmitted from the chip select input end (SPI_CS port) of the first-level chip to the slave chip select output end (CSB_SW port) of the first-level chip, and then to the chip select input end (SPI_CS port) of the first second-level chip.

[0066] In a possible implementation manner, the determining whether to select the first-level chip as the communication chip according to the detection result of the addressing address information comprises:

[0067] When it is detected that the addressing address information is valid and correct, subsequently received addressing address information is transmitted from the first-level chip to the first second-level chip in the chip select series structure;

[0068] When it is detected that the addressing address information is valid and incorrect, it is determined to select the first-level chip as the communication chip;

[0069] When it is detected that the addressing address information is invalid, the first-level chip feeds back to the master controller that the address is invalid or the master controller obtains feedback that the address is invalid.

[0070] In the embodiment of the application, when it is detected that the addressing address information is invalid, an error flag bit in a register in the first-level chip is set, and the master controller can access the register in the first-level chip through the SPI bus to obtain the state of the error flag bit, so as to obtain feedback that the address is invalid.

[0071] In a possible implementation, the first chip and each second chip correspond to the same addressing address.

[0072] In the embodiment of the application, the keys of each slave chip are the same, and the access strategies of different chips are as follows:

[0073] 1. When valid addressing address information (key) is received and the key is correct, the function of the first chip is transparently transmitted; the subsequently received key is forwarded from the SPI_CS port of the first chip to the CSB_SW port, and the control of the SPI_MISO signal line by the first chip is released.

[0074] 2. When valid key is received but the key is incorrect, the function of the first chip is activated (at this time, the subsequent key is not forwarded from the first chip, and the control of the SPI_MISO signal line by the first chip is activated).

[0075] 3. When invalid key (for example, not meeting the protocol length or time requirement corresponding to the key) is received, the address error flag error flag of the first chip is marked, or the invalidity of the address addressing information is fed back to the main controller or no reaction is made.

[0076] In a possible implementation, the communication method further includes:

[0077] The second chip of the chip select series structure which does not receive the addressing address information transparently transmitted by the previous chip listens to the addressing address information transparently transmitted by the previous chip.

[0078] When the addressing address information transparently transmitted by the previous chip is not received, it is determined that the current second chip is selected as the communication chip.

[0079] When the addressing address information transparently transmitted by the previous chip is received, the subsequently transparently transmitted addressing address information is transparently transmitted from the current second chip to the next second chip of the chip select series structure.

[0080] In the embodiment of the application, the second chip receives the transparently transmitted addressing address information, wherein the first second chip of the chip select series structure receives the addressing address information transparently transmitted by the first chip, and the other second chips (except the first second chip) of the chip select series structure receive the addressing address information transparently transmitted by the previous second chip.

[0081] The second level chip which does not receive the addressing address information continues to listen to the transmitted addressing address information, if the transmitted addressing address information is not received, the current second level chip is determined as the communication chip, if the transmitted addressing address information is received, the current second level chip will not be selected as the communication chip, and the subsequent transmitted addressing address information is forwarded from the SPI_CS port of the current second level chip to the CSB_SW port and then transmitted to the SPI_CS port of the next second level chip.

[0082] The first level chip always listens to the key of the main controller, when the valid key is received but the key is incorrect, the first level chip is reselected as the communication chip and the function of the first level chip is activated.

[0083] The second level chip also always listens to the key transmitted by the previous second level chip (the first second level chip listens to the key transmitted by the first level chip), when the valid and correct key is received, the current second level chip is in the transmission state and the key is transmitted to the next second level chip, if the current second level chip is in the non-transmission state, the received key is not transmitted to the next second level chip, the signal received by the SPI_CS port of the second level chip is not transmitted to the CSB_SW port, that is, the serial_n signal of the second level chip is not transmitted to the serial_o signal.

[0084] In the embodiment of the application, the main controller switches to different second level chips for communication by transmitting correct keys (the number of times of transmitting correct keys by different second level chips is different). The main controller switches back to the first level chip by transmitting incorrect keys.

[0085] In the embodiment of the application, the first level chip and the second level chip use the same addressing address, that is, the key of the first level chip and the key of each second level chip are the same. When the main controller transmits the valid but incorrect key, the first level chip is selected as the communication chip, when the main controller transmits the valid and correct key once, the first second level chip is selected as the communication chip, when the main controller transmits the valid and correct key twice continuously, the second second level chip is selected as the communication chip, when the main controller transmits the valid and correct key three times continuously, the third second level chip is selected as the communication chip, and so on. The main controller switches to different second level chips for communication by transmitting the valid and correct key continuously multiple times. The main controller switches back to the first level chip for communication by transmitting the valid but incorrect key.

[0086] In a possible implementation manner, the detecting the addressing address information comprises:

[0087] The addressing address information comprises a chip select start signal, differential address information and a chip select end signal (as shown in Figure 4 Fig. 2).

[0088] Upon receiving the correct chip select start signal from the main controller, determine to begin receiving differential address information sent by the main controller;

[0089] When the length of the received differential address information conforms to the protocol length of the preset address, and the correct chip select termination signal is received from the main controller, the addressing address information is determined to be valid.

[0090] When the received differential address information is the same as the addressing address corresponding to the first-level chip and each second-level chip, and the correct chip select termination signal sent by the main controller is received, it is determined that the addressing address information is correct.

[0091] Otherwise, the address information is determined to be invalid.

[0092] In this embodiment of the invention, the validity and / or correctness of the differential address information are detected based on the protocol length and time requirements corresponding to the key.

[0093] In one possible implementation, if the duration and timing of the received chip select start signal meet the preset start flag requirements, then it is determined that the correct chip select start signal has been received.

[0094] If the duration and timing of the received chip select termination signal meet the preset termination flag requirements, then it is determined that the correct chip select termination signal has been received.

[0095] like Figure 4 As shown, the main controller sends a chip select start signal to the chip select input SPI_CS of the first-stage chip via the chip select differential negative terminal serial_n, and pre-sets the correct timing sequence rules for the chip select start signal (start flag requirements), such as... Figure 4 In the protocol, the correct chip select start signal is set to a high pulse for serial_n and a low pulse for serial_p for a duration of Tstart. Since serial_p is the inverted signal of serial_n, forming a differential pair, there is ideally no time difference between the transition edges of the differential pair serial_p and serial_n. In reality, due to various reasons, there may be a time difference between the transition edges of the differential pair serial_p and serial_n. Tskew represents the time difference between the transition edges of serial_p and serial_n. The protocol requires that this value must be less than the specified maximum value. Figure 4In the example, there is a time difference Tskew between the transition edges of the differential pair serial_p and serial_n, which is displayed before Tstart. In reality, whenever the differential signal transitions, there may be a time difference between the differential pair serial_p and serial_n. For example, there will be a time difference during the START signal, intermediate data transmission process, and STOP signal. Each time difference must also meet the corresponding protocol requirements. In other embodiments, other rules for the timing sequence of the correct chip select start signal can be set. For example, the correct chip select start signal is that serial_n holds a low pulse and serial_p holds a high pulse for a preset duration, or serial_n alternates between high and low pulses and the duration of the high and low pulses is the same and is t, or serial_n alternates between high and low pulses and the duration of the high pulse is twice the duration of the low pulse (serial_p is the inverted signal of serial_n, and the corresponding low and high pulses alternate).

[0096] The first-level chip receives the chip select start signal from the chip select input terminal SPI_CS and uses a preset timing sequence rule to determine whether a correct chip select start signal has been received. When it is determined that a correct chip select start signal has been received, it begins to receive the differential address information sent by the main controller to the chip select input terminal SPI_CS of the first-level chip through the chip select differential negative terminal serial_n. In this embodiment of the invention, the addressing address corresponding to the first-level chip and each second-level chip is the same. A timing sequence of valid and correct differential address information (which is the same as the addressing address corresponding to the first-level chip and each second-level chip) is preset. The addressing address is valid and correct, which means that the addressing address length meets the requirements, and the bit period of each address bit meets the Tperiod requirement, the pulse width of the high and low level transmission meets the Tpulse_0 or Tpuls_1 requirement, and the offset Tsekw between differential signals meets the requirements. Figure 4 In this context, the period for transmitting a single bit of data is denoted as Tperiod, where Tpulse_1 represents the time when serial_p or SPI_MOSI is a high pulse when the data is 1, and Tpulse_0 represents the time when serial_p or SPI_MOSI is a high pulse when the data is 0.

[0097] The identifier that receives all differential address information is that the master controller sends the correct chip select termination signal. In this embodiment of the invention, the timing sequence rules (termination flag requirements) for the correct chip select termination signal are pre-defined, such as... Figure 4In the embodiment, the correct chip select termination signal is serial_n low pulse and serial_p low pulse and lasts for Tstop, in other embodiments, other correct chip select termination signal time sequence rules can be set, for example, the correct chip select termination signal is serial_n high pulse and serial_p low pulse and lasts for a preset time, or serial_n high-low pulse alternates and the high-low pulse lasts for t, or serial_n high-low pulse alternates and the high pulse lasts for twice the low pulse (serial_p is the inverse signal of serial_n, and the low-high pulse alternates accordingly).

[0098] Table 2 illustrates the parameters and meanings of the addressing address information in the embodiment of the application.

[0099] Table 2

[0100]

[0101] Wherein, Tclk is a fixed time clock signal, in the embodiment of the application, Tclk can be an 8mhz clock.

[0102] As shown in the figure, the process of detecting the addressing address information by the first chip is illustrated: Figure 5

[0103] First, determine whether the chip select start signal is detected, specifically, detect whether the duration of serial_n=1 and serial_p=0 meets the time requirement of Tstart.

[0104] Second, when the flag is detected, start receiving the chip select start signal, specifically, wait for the differential signal serial_n=0 and serial_p=1, if the time of waiting for the differential signal serial_n=0 and serial_p=1 exceeds the maximum allowable time, it is judged that the differential signal is not waited for, the receiving of the addressing address information fails, the corresponding error flag bit is set, and the initial state is returned.

[0105] ​Thirdly, if the differential signal is waited for within the maximum allowed time, it is judged whether the correct chip select start signal is received, specifically, the stable time of the differential signal serial_n=1, serial_p=0 is timed, and it is judged whether the stable time of the differential signal meets the high / low level stable time requirement; when the stable time of the differential signal meets the high / low level stable time requirement, it is determined that the correct chip select start signal is received, otherwise (the stable time of the differential signal does not meet the high / low level stable time requirement), it is determined that the correct chip select start signal is not received, the addressing address information is not received successfully, the corresponding error flag bit is set, and the initial state is returned. It needs to be explained that in the embodiment of the application, the corresponding error flag bit is only set when the chip select start signal is checked and the subsequent reception error is set, and if the chip select start signal is not checked, the corresponding error flag bit will not be set.

[0106] Fourthly, when the correct chip select start signal is received, it is judged whether the valid differential address information is received, specifically, it is determined whether the sum of the differential signal transmission time of the received differential address information meets the single bit data cycle requirement, when the sum of the transmission time is greater than the specified maximum duration or less than the specified minimum duration, the addressing address information is not received successfully, the corresponding error flag bit is set, and the initial state is returned.

[0107] Fifthly, when the sum of the transmission time meets the single bit data cycle requirement, it is determined whether the length of the received data reaches the length of the key (the length of the addressing address corresponding to the first level chip and the second level chip), if the length of the received data does not reach the length of the key, the chip select start signal is returned to be received.

[0108] Sixthly, it is determined that the length of the received data reaches the length of the key, and it is judged whether the correct chip select termination signal is received, specifically, it is waited for and detected whether the duration of the chip select termination signal meets the minimum duration of the stop flag (or whether the stable time of the chip select termination signal meets the high / low level stable time requirement), if the duration of the chip select termination signal is less than the specified minimum duration of the stop flag, it is judged that the incorrect chip select termination signal is received, the addressing address information is not received successfully, and the initial state is returned.

[0109] Seventhly, when the correct chip select termination signal is received, it is further judged whether the correct differential address information is received, that is, it is judged whether the received key is correct, when the correct differential address information is received, the input of serial_n is transparently transmitted to serial_o, and the SPI function of the first level chip is transparently transmitted; when the incorrect differential address information is received, the SPI function of the first level chip is activated, and the output of serial_o is set to 1.

[0110] The serial multi-chip communication device and the corresponding method applied to the signal chain chip can better adapt to the demand of the interconnection communication bus between the signal chain chips, and reduce the port number and complexity of the interconnection bus between the chips; the number of serial slave chips is not limited, and flexible adjustment and expansion can be realized; the device and the method have a high reliability communication mechanism of address addressing.

[0111] It should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0112] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly specified and limited.

[0113] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or can be integrated; can be directly connected, or can be indirectly connected through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0114] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include these modifications and variations.

[0115] While the application has been described in accordance with the various embodiments shown and described, it is to be understood that the application is not limited to those precise embodiments, and that various modifications and changes can be made by those skilled in the art without departing from the scope of the present application. Furthermore, the language used in this specification has been principally selected for readability and instructional purposes and can not have been selected to delineate or circumscribe the patent rights to which it refers. Accordingly, the present application is intended to be illustrative, but not limiting, of the scope of the application, which is set forth with particularity in the claims that follow.

Claims

1. A serial multi-chip communication device applied to signal chain chips, characterized in that, include: The main controller, the first-level chip, and at least one second-level chip; The chip select differential negative terminal of the main controller is interconnected with the chip select input terminal of the first-stage chip; Each chip in the second-level chip is sequentially connected to the chip select input of the next chip via the slave chip select output terminal, forming a chip select series structure of at least one second-level chip; The slave chip select output terminal of the first-level chip is interconnected with the chip select input terminal of the first second-level chip in the chip select serial structure; The serial differential positive terminal of the main controller is interconnected with the slave input terminal of the first-stage chip and the slave input terminal of each second-stage chip; The clock signal output terminal of the main controller is interconnected with the clock signal input terminal of the first-stage chip and the clock signal input terminal of each second-stage chip; The feedback signal input terminal of the main controller is interconnected with the slave output terminal of the first-level chip and the slave output terminal of each second-level chip; When the communication device is in operation: The first-level chip listens to the addressing address information of the main controller and detects the addressing address information when it receives it. Based on the detection results of the address information, determine whether to select the first-level chip as the communication chip; Determining whether to select the first-level chip as the communication chip based on the detection results of the address information includes: When the addressing address information is detected to be valid and correct, the subsequently received addressing address information will be transparently transmitted from the first-level chip to the first second-level chip in the chip select cascade structure. When the addressing address information is detected to be valid or incorrect, the first-level chip is selected as the communication chip. When the addressing address information is detected to be invalid, the first-level chip sends feedback to the main controller that the address is invalid or the main controller obtains an invalid address. The addressing address corresponding to the first-level chip and each second-level chip is the same; The second-level chip in the chip select cascade structure that has not received the address address information passed through by the previous chip is listening to the address address information passed through by the previous chip. If the address information transmitted by the previous chip is not received, the current second-level chip is selected as the communication chip. When the address information passed through by the previous chip is received, the address information to be passed through from the current second-level chip to the next second-level chip in the chip select serial structure.

2. The communication device as described in claim 1, characterized in that, The first-level chip and each second-level chip use the same chip.

3. The communication device as described in claim 1, characterized in that, The main controller is connected to the first-level chip and each second-level chip via a serial peripheral interface.

4. A serial multi-chip communication method applied to signal chain chips, characterized in that, Based on a serial multi-chip communication device applied to a signal chain chip, the serial multi-chip communication device applied to the signal chain chip includes: a main controller, a first-level chip, and at least one second-level chip; The chip select differential negative terminal of the main controller is interconnected with the chip select input terminal of the first-stage chip; Each chip in the second-level chip is sequentially connected to the chip select input of the next chip via the slave chip select output terminal, forming a chip select series structure of at least one second-level chip; The slave chip select output terminal of the first-level chip is interconnected with the chip select input terminal of the first second-level chip in the chip select serial structure; The serial differential positive terminal of the main controller is interconnected with the slave input terminal of the first-stage chip and the slave input terminal of each second-stage chip; The clock signal output terminal of the main controller is interconnected with the clock signal input terminal of the first-stage chip and the clock signal input terminal of each second-stage chip; The feedback signal input terminal of the main controller is interconnected with the slave output terminal of the first-level chip and the slave output terminal of each second-level chip; The method includes: The first-level chip listens to the addressing address information of the main controller and detects the addressing address information when it receives it. Based on the detection results of the address information, determine whether to select the first-level chip as the communication chip; Determining whether to select the first-level chip as the communication chip based on the detection results of the address information includes: When the addressing address information is detected to be valid and correct, the subsequently received addressing address information will be transparently transmitted from the first-level chip to the first second-level chip in the chip select cascade structure. When the addressing address information is detected to be valid or incorrect, the first-level chip is selected as the communication chip. When the addressing address information is detected to be invalid, the first-level chip sends feedback to the main controller that the address is invalid or the main controller obtains an invalid address. The addressing address corresponding to the first-level chip and each second-level chip is the same; The second-level chip in the chip select cascade structure that has not received the address address information passed through by the previous chip is listening to the address address information passed through by the previous chip. If the address information transmitted by the previous chip is not received, the current second-level chip is selected as the communication chip. When the address information passed through by the previous chip is received, the address information to be passed through from the current second-level chip to the next second-level chip in the chip select serial structure.

5. The communication method as described in claim 4, characterized in that, Detecting the address information includes: The addressing information includes a chip select start signal, differential address information, and a chip select stop signal; Upon receiving the correct chip select start signal from the main controller, determine to begin receiving differential address information sent by the main controller; When the length of the received differential address information conforms to the protocol length of the preset address, and the correct chip select termination signal is received from the main controller, the addressing address information is determined to be valid. When the received differential address information is the same as the addressing address corresponding to the first-level chip and each second-level chip, and the correct chip select termination signal sent by the main controller is received, it is determined that the addressing address information is correct. Otherwise, the address information is determined to be invalid.

6. The communication method as described in claim 5, characterized in that, If the duration and timing of the received chip select start signal meet the preset start flag requirements, then it is determined that the correct chip select start signal has been received. If the duration and timing of the received chip select termination signal meet the preset termination flag requirements, then it is determined that the correct chip select termination signal has been received.

Images