A storage structure and a memory

Abstract

The application discloses a storage structure and a memory, wherein the storage structure comprises: a first storage chip and a second storage chip; the first storage chip is stacked on one side of the second storage chip, and the first storage chip and the second storage chip are connected in three dimensions; the first storage chip is provided with a plurality of pins for being connected to a preset circuit board, a signal transmission line of the first storage chip is connected with the pins, and a signal transmission line of the second storage chip is connected with the pins through the first storage chip; the storage structure is configured to read or write the first storage chip through the signal transmission line of the first storage chip after receiving a preset first chip select signal; and the storage structure is further configured to read or write the second storage chip through the signal transmission line of the second storage chip after receiving a preset second chip select signal. In the process of realizing storage capacity expansion, the application avoids increasing the wiring resources of the PCB board and reduces the packaging cost.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a storage structure and a memory. Background Technology

[0002] Currently, when using two or more memory chips to expand capacity, existing technologies typically involve arranging these chips on a PCB (Printed Circuit Board), and then routing the circuitry on the PCB to connect the command lines and address lines of the memory chips together. This achieves the expansion of storage capacity.

[0003] While existing technologies can expand storage capacity, this method wastes wiring resources on the PCB board and has high packaging costs. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a storage structure and memory that avoids increasing the wiring resources of the PCB board and reduces the packaging cost during the process of expanding storage capacity.

[0005] In a first aspect, a storage structure is provided, comprising: a first storage chip and a second storage chip; the first storage chip is stacked on one side of the second storage chip, and the first storage chip and the second storage chip are three-dimensionally connected; the first storage chip is provided with a plurality of pins for connecting to a preset circuit board, a signal transmission line of the first storage chip is connected to the pins, and a signal transmission line of the second storage chip passes through the first storage chip and is connected to the pins; the storage structure is configured to read or write to the first storage chip through the signal transmission line of the first storage chip after receiving a preset first chip select signal; and is further configured to read or write to the second storage chip through the signal transmission line of the second storage chip after receiving a preset second chip select signal.

[0006] Optionally, the signal transmission lines of the first memory chip include a first address command line and a first data line; the signal transmission lines of the second memory chip include a second address command line and a second data line; the plurality of pins include a command pin group and a data pin group.

[0007] Optionally, the second address command line is connected to the first address command line, and the second data line is connected to the first data line; the first address command line is connected to the command pin group; and the first data line is connected to the data pin group.

[0008] Optionally, the second address command line passes through the first memory chip and is connected to the command pin group; the second data line passes through the first memory chip and is connected to the data pin group; the first address command line is connected to the command pin group; and the first data line is connected to the data pin group.

[0009] Optionally, the second address command line is connected to the first address command line, and the second data line passes through the first memory chip and is connected to the data pin group; the first address command line is connected to the command pin group; and the first data line is connected to the data pin group.

[0010] Optionally, the first memory chip is provided with a first chip select interface and a second chip select interface; the first chip select interface receives the first chip select signal, so that the memory structure can read or write to the first memory chip based on the first chip select signal; the second chip select interface receives the second chip select signal, so that the memory structure can read or write to the second memory chip based on the second chip select signal.

[0011] Optionally, the first memory chip is provided with a first chip select interface and a multiplexer. The multiplexer is connected to the first chip select interface and configured to receive an initial chip select signal and a control signal. The multiplexer is configured to output a first chip select signal to the first chip select interface based on the control signal and the initial chip select signal, so that the memory structure can read or write to the first memory chip based on the first chip select signal. The multiplexer is also configured to output a second chip select signal to the first chip select interface based on the control signal and the initial chip select signal, so that the memory structure can read or write to the second memory chip based on the second chip select signal.

[0012] Optionally, the multiplexer includes an inverter, a first AND gate, and a second AND gate; the output of the inverter is connected to the first input of the first AND gate, the input of the inverter is configured to receive the control signal, and the second input of the first AND gate is configured to receive the initial chip select signal; the first input of the second AND gate is configured to receive the initial chip select signal, and the second input of the second AND gate is configured to receive the control signal; the outputs of both the first AND gate and the second AND gate are connected to the first chip select interface.

[0013] Optionally, a third memory chip is also included; the third memory chip is stacked on the side of the second memory chip away from the first memory chip, and the second memory chip and the third memory chip are three-dimensionally connected; the signal transmission line of the third memory chip passes through the second memory chip and the first memory chip and is connected to the pin; the memory structure is configured to read or write to the third memory chip through the signal transmission line of the third memory chip after receiving a preset third chip select signal.

[0014] In a second aspect, a memory is provided, comprising: a memory structure as described in any of the preceding first aspects; and a logic chip disposed on a side of the second memory chip away from the first memory chip, and the logic chip and the second memory chip are three-dimensionally connected.

[0015] The technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0016] This invention provides a storage structure and memory, wherein the storage structure includes: a first storage chip and a second storage chip; the first storage chip is stacked on one side of the second storage chip, and the first and second storage chips are three-dimensionally connected; the first storage chip is provided with multiple pins for connecting to a preset circuit board, and signal transmission lines of the first storage chip are connected to the pins, and signal transmission lines of the second storage chip pass through the first storage chip and are connected to the pins; the storage structure is configured to read or write to the first storage chip through the signal transmission lines of the first storage chip after receiving a preset first chip select signal; and is further configured to read or write to the second storage chip through the signal transmission lines of the second storage chip after receiving a preset second chip select signal. In the storage structure of this invention, by three-dimensionally connecting the first and second storage chips and reading and writing to the first and second storage chips respectively through the first and second chip select signals, the capacity of the storage structure is expanded; simultaneously, the signal transmission lines of the second storage chip pass through the first storage chip and are connected to the pins on the circuit board, thereby saving circuit board wiring area and pin occupation area, reducing packaging costs and material costs.

[0017] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0019] Figure 1 This is a schematic diagram of the first embodiment of the storage structure of the present invention;

[0020] Figure 2 This is a schematic diagram of the second embodiment of the storage structure of the present invention;

[0021] Figure 3 This is a schematic diagram of the third embodiment of the storage structure of the present invention;

[0022] Figure 4 for Figure 3 The corresponding memory structure's chip select signal control timing diagram;

[0023] Figure 5 This is a schematic diagram of the fourth embodiment of the storage structure of the present invention;

[0024] Figure 6 for Figure 5 A schematic diagram of the structure of a multiplexer in the image;

[0025] Figure 7 This is a schematic diagram of the fifth embodiment of the storage structure of the present invention;

[0026] Figure 8 This is a schematic diagram of one embodiment of the memory in this invention. Detailed Implementation

[0027] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0028] This invention provides a storage structure that stacks multiple memory chips and leads out the metal lines of these chips through a single chip, thereby reducing the wiring area on the PCB board, decreasing the number of pins, and lowering packaging costs. The concept of this invention will be explained in detail below through specific examples.

[0029] Please see Figure 1In one embodiment of the present invention, a storage structure 10 is provided, including: a first storage chip 11 and a second storage chip 12; the first storage chip 11 is stacked on one side of the second storage chip 12, and the first storage chip 11 and the second storage chip 12 are three-dimensionally connected; the first storage chip 11 is provided with a plurality of pins (not shown in the figure) for connecting to a preset circuit board, and it is understood that the plurality of pins are disposed on the surface of the first storage chip 11 away from the second storage chip 12. The signal transmission line 110 of the first storage chip 11 is connected to the pins, and the signal transmission line 120 of the second storage chip 12 passes through the first storage chip 11 and is connected to the pins; the storage structure 10 is configured to read or write to the first storage chip 11 through the signal transmission line 110 of the first storage chip 11 after receiving a preset first chip select signal; and is also configured to read or write to the second storage chip 12 through the signal transmission line 120 of the second storage chip 12 after receiving a preset second chip select signal, thereby realizing capacity expansion. Since the signal transmission line of the second memory chip passes through the first memory chip 11, multiple common pins can be set, and the connection can be achieved by leading metal wires from the first memory chip 11 to the pins on the PCB board. In other words, only the corresponding pin area and contact of one memory chip need to be set on the PCB board, which saves the area of ​​wiring on the PCB and reduces material costs.

[0030] The first storage chip 11 and the second storage chip 12 can be random access memory (RAM), such as dynamic random access memory; or they can be read-only memory (ROM), without restriction.

[0031] Furthermore, the signal transmission line 110 of the first memory chip 11 includes a first address command line 111 and a first data line 112; the signal transmission line 120 of the second memory chip 12 includes a second address command line 121 and a second data line 122; and the multiple pins include a command pin group and a data pin group.

[0032] In some implementations, the second address command line 121 is connected to the first address command line 111, and the second data line 122 is connected to the first data line 112, such as... Figure 1As shown, the first address command line 111 is connected to the command pin group; the first data line 112 is connected to the data pin group. With this design, the second address command line 121 and the second data line 122 of the second memory chip 12 can be partially shared with the first address command line 111 and the first data line 112 in the first memory chip 11, achieving capacity expansion and saving wiring costs. When the address command line and the data line are shared, the chip select signal can control the reading or writing of data on the first memory chip 11 at different times, or the reading or writing of data on the second memory chip 12; it is also possible to read or write the same data simultaneously.

[0033] For example, when a data write command is received: if the storage structure 10 receives a valid first chip select signal, it parses the command and address in the first storage chip 11 and receives the written data; at this time, the second chip select signal is invalid, the second storage chip 12 does not parse the command and address, and does not receive the written data; if the storage structure 10 receives a valid second chip select signal, it parses the command and address in the second storage chip 12 and receives the written data; at this time, the first chip select signal is invalid, the first storage chip 11 does not parse the command and address, and does not receive the written data. When a data read command is received: if the storage structure 10 receives a valid first chip select signal, it parses the command and address in the first storage chip 11 and sends out the read data; at this time, the second chip select signal is invalid, the second storage chip 12 does not parse the command and address, and does not send out the read data; if the storage structure 10 receives a valid second chip select signal, it parses the command and address in the second storage chip 12 and sends out the read data; at this time, the first chip select signal is invalid, the first storage chip 11 does not parse the command and address, and does not send out the read data. Thus, time-sharing access can be achieved through the above control process while sharing a data transmission line.

[0034] In some implementations, such as Figure 2 As shown, the second address command line 121 passes through the first memory chip 11 and connects to the command pin group, and the second data line 122 passes through the first memory chip 11 and connects to the data pin group, as shown. Figure 2As shown, the first address command line 111 is connected to the command pin group; the first data line 112 is connected to the data pin group. That is, the command pin group can be configured with pins for connecting the first address command line 111 and pins for connecting the second address command line 121, thus separating the first address command line 111 and the second address command line 121; similarly, the data pin group can be configured with pins for connecting the first data line 112 and pins for connecting the second data line 122, thus separating the first data line 112 and the second data line 122. In this case, the first memory chip 11 and the second memory chip 12 can be controlled to perform simultaneous or time-division multiplexing read or write operations via the chip select signal, and the read or write operations of the first memory chip 11 and the second memory chip 12 do not interfere with each other, thereby improving data transmission performance.

[0035] For example, when a data operation command is received: if the memory structure 10 receives a valid first chip select signal and a valid second chip select signal, it can send commands and addresses to the first memory chip 11 and the second memory chip 12 via independent first and second address command lines, respectively. The first memory chip 11 and the second memory chip 12 can simultaneously parse the received commands and addresses and simultaneously read or write to the first memory chip 11 and the second memory chip 12 via independent first data lines 112 and second data lines 122. Specifically, both the first memory chip 11 and the second memory chip 12 can receive write data; both can send read data; or one of the first memory chip 11 and the second memory chip 12 can receive write data while the other sends read data.

[0036] In some implementations, such as Figure 3 As shown, the second address command line 121 is connected to the first address command line 111, and the second data line 122 passes through the first memory chip 11 and connects to the data pin group; the first address command line 111 is connected to the command pin group; and the first data line 112 is connected to the data pin group. Please refer to [link / reference]. Figure 4 This design allows address command lines to be shared while data lines remain independent. By providing corresponding chip select signals (chip select 1, chip select 2) to the first memory chip 11 and the second memory chip 12 in a time-division manner, and providing corresponding address command signals (command / address) in a time-division manner, continuous write operations can be achieved in the two memory chips. The written data in the two memory chips do not affect each other, and the bandwidth can be doubled when reading or writing data.

[0037] For example, when a data write command is received: if the first chip select signal is valid, the first memory chip 11 parses the command and address and receives the written data; when the first chip select signal is valid, the second chip select signal is invalid; after the first memory chip 11 completes the parsing, the second chip select signal can be made valid and the first chip select signal invalid, at which point the second memory chip 12 parses the command and address and can receive the written data. Since the first data line 112 and the second data line 122 are independent of each other, the data received by the first memory chip 11 and the second memory chip 12 can be different, realizing time-sharing processing, and doubling the bandwidth when writing data. When a data read command is received: if the first chip select signal is valid, the first memory chip 11 parses the command and address and sends out the read data; when the first chip select signal is valid, the second chip select signal is invalid; after the first memory chip 11 completes the parsing, the second chip select signal can be made valid and the first chip select signal invalid, at which point the second memory chip 12 parses the command and address and can send out the read data; since the first data line 112 and the second data line 122 are independent of each other. Since the first data line 112 and the second data line 122 are independent of each other, the read data sent by the first memory chip 11 and the second memory chip 12 can be different, realizing time-sharing processing and doubling the bandwidth when reading data.

[0038] Understandably, the following are some ways to implement selecting a memory chip using a chip select signal:

[0039] Please see Figures 1-3 A first chip select interface 101 and a second chip select interface 102 can be provided on the first memory chip 11. The first chip select interface 101 can be connected to the first memory chip 11, and the second chip select interface 102 can be connected to the second memory chip 12. The first chip select interface 101 can be configured to receive a first chip select signal, so that the memory structure 10 can read or write to the first memory chip 11 based on the first chip select signal. The second chip select interface 102 receives a second chip select signal, so that the memory structure 10 can read or write to the second memory chip 12 based on the second chip select signal. Read / write selection control of the two memory chips is achieved through two chip select interfaces, and both chip select interfaces are located on the first memory chip 11, which is beneficial for PCB board routing and connection. It should be noted that, for a scheme where data lines are shared, the corresponding chip select signals can be given to the first memory chip 11 and the second memory chip 12 in a time-sharing manner. For a scheme where data lines are not shared, there is no time limit for giving chip select signals to the first memory chip 11 and the second memory chip 12.

[0040] In addition, please see Figure 5In some implementations, only the first chip select interface 101 may be provided, and the chip select signal may be controlled by a multiplexer 103. Specifically, the first memory chip 11 is provided with a first chip select interface 101 and a multiplexer 103. The multiplexer 103 is connected to the first chip select interface 101 and is configured to receive an initial chip select signal (chip select 0) and a control signal based on the first chip select interface 101. The multiplexer 103 is configured to output a first chip select signal (chip select 1) to the first memory chip 11 based on the control signal and the initial chip select signal, so that the memory structure 10 can read or write to the first memory chip 11 based on the first chip select signal. The multiplexer 103 is also configured to output a second chip select signal (chip select 2) to the second memory chip 12 based on the control signal and the initial chip select signal, so that the memory structure 10 can read or write to the second memory chip 12 based on the second chip select signal.

[0041] For further details, please refer to Figure 6 The multiplexer 103 can be implemented as follows, but is not limited to this. The multiplexer 103 may include an inverter, a first AND gate, and a second AND gate; the output of the inverter is connected to the first input of the first AND gate, and the input of the inverter is configured to receive the control signal; the second input of the first AND gate is configured to receive the initial chip select signal; the first input of the second AND gate is configured to receive the initial chip select signal, and the second input of the second AND gate is configured to receive the control signal; the outputs of both the first and second AND gates are connected to the first chip select interface 101. That is, in this implementation, an initial chip select signal can be input to the multiplexer 103, and the control signal can control the output of the first chip select signal and / or the second chip select signal. For example, when the selector outputs a low level, it can be used as the first chip select signal to select the first memory chip 11; when the selector outputs a high level, it can be used as the second chip select signal to select the second memory chip 12. Similarly, for a scheme where data lines are shared, the corresponding chip select signals for the first memory chip 11 and the second memory chip 12 can be provided in a time-division manner. For a scheme where data lines are not shared, there is no time limit for providing chip select signals for the first memory chip 11 and the second memory chip 12. This implementation method can achieve the selection control of two memory chips with only one chip select interface.

[0042] For further details, please refer to Figure 7In some embodiments, a third memory chip 13 may also be stacked. Specifically, the third memory chip 13 is stacked on the side of the second memory chip 12 away from the first memory chip 11, and the second memory chip 12 and the third memory chip 13 are three-dimensionally connected. The signal transmission line of the third memory chip 13 passes through the second memory chip 12 and the first memory chip 11 and is connected to a pin. The memory structure 10 is configured to read or write to the third memory chip 13 through the signal transmission line 130 of the third memory chip 13 after receiving a preset third chip select signal. Similarly, the relationship between the signal transmission line 130 of the third memory chip 13 and the signal transmission line 120 of the second memory chip 12 can be designed with reference to the relationship between the signal transmission line 120 of the second memory chip 12 and the signal transmission line 110 of the first memory chip 11, which will not be repeated in this embodiment. In addition, the implementation of stacking three or more memory chips can also be deduced by analogy. For example, the memory structure 10 of this embodiment may also include a fourth memory chip three-dimensionally connected to the third memory chip 13, a fifth memory chip three-dimensionally connected to the fourth memory chip, and so on.

[0043] It should be noted that in this embodiment, three-dimensional connections can be achieved using TSV (Through-Silicon-Via) technology and / or Hybrid bonding technology.

[0044] In summary, in this embodiment, by three-dimensionally connecting the first memory chip 11 and the second memory chip 12, and controlling the read and write operations of the first memory chip 11 and the second memory chip 12 through the first chip select signal and the second chip select signal respectively, the capacity expansion of the storage structure 10 is achieved. Furthermore, by passing all the signal transmission lines 120 of the second memory chip 12 through the first memory chip 11 and connecting them to the pins, only the pins of the first memory chip 11 need to be set, thereby saving the wiring area and pin area of ​​the circuit board and reducing the packaging cost and material cost.

[0045] Please see Figure 8 Based on the same inventive concept, another embodiment of the present invention provides a memory 400, including any of the memory structures 10 described in the foregoing embodiments, and a logic chip 40. The logic chip 40 is disposed on the side of the second memory chip 12 away from the first memory chip 11, and the logic chip 40 and the second memory chip 12 are three-dimensionally connected. It should be noted that the memory 400 in the embodiments of the present invention all include the memory structure 10 in the foregoing embodiments. Its beneficial effects and implementation methods have been described in the foregoing embodiments, so they can be understood by referring to the embodiments of the foregoing memory structure 10. Further details will not be repeated in the embodiments of the memory and electronic device.

[0046] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0047] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0048] Those skilled in the art will understand that the modules in the apparatus corresponding to the memory control method in the embodiments can be adaptively changed and placed in one or more apparatuses different from those in the embodiments. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0049] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0050] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

Claims

1. A storage structure, characterized by, include: A first memory chip and a second memory chip; the first memory chip is stacked on one side of the second memory chip, and the first memory chip and the second memory chip are three-dimensionally connected; the first memory chip is provided with multiple pins for connecting to a preset circuit board, the signal transmission line of the first memory chip is connected to the pins, and the signal transmission line of the second memory chip passes through the first memory chip and is connected to the pins; The storage structure is configured to read or write to the first storage chip through the signal transmission line of the first storage chip after receiving a preset first chip select signal; and is further configured to read or write to the second storage chip through the signal transmission line of the second storage chip after receiving a preset second chip select signal.

2. The memory structure of claim 1, wherein, The signal transmission lines of the first memory chip include a first address command line and a first data line; The signal transmission lines of the second memory chip include a second address command line and a second data line; The plurality of pins includes a command pin group and a data pin group.

3. The storage structure according to claim 2, characterized in that, The second address command line is connected to the first address command line, and the second data line is connected to the first data line; the first address command line is connected to the command pin group; and the first data line is connected to the data pin group.

4. The storage structure according to claim 2, characterized in that, The second address command line passes through the first memory chip and is connected to the command pin group; the second data line passes through the first memory chip and is connected to the data pin group; the first address command line is connected to the command pin group; and the first data line is connected to the data pin group.

5. The storage structure according to claim 2, characterized in that, The second address command line is connected to the first address command line, and the second data line passes through the first memory chip and is connected to the data pin group; the first address command line is connected to the command pin group; and the first data line is connected to the data pin group.

6. The storage structure according to any one of claims 3 to 5, characterized in that, The first memory chip is provided with a first chip select interface and a second chip select interface; The first chip select interface receives the first chip select signal, so that the memory structure can read or write to the first memory chip based on the first chip select signal; The second chip select interface receives the second chip select signal, so that the memory structure can read or write the second memory chip based on the second chip select signal.

7. The storage structure according to any one of claims 3 to 5, characterized in that, The first memory chip is provided with a first chip select interface and a multiplexer. The multiplexer is connected to the first chip select interface and is configured to receive an initial chip select signal and a control signal based on the first chip select interface. The multiplexer is configured to output a first chip select signal to the first memory chip based on the control signal and the initial chip select signal, so that the memory structure can read or write to the first memory chip based on the first chip select signal. The multiplexer is configured to output a second chip select signal to the second memory chip based on the control signal and the initial chip select signal, so that the memory structure can read or write to the second memory chip based on the second chip select signal.

8. The memory structure of claim 7, wherein, The multiplexer includes an inverter, a first AND gate, and a second AND gate; the output of the inverter is connected to the first input of the first AND gate, the input of the inverter is configured to receive the control signal, and the second input of the first AND gate is configured to receive the initial chip select signal; the first input of the second AND gate is configured to receive the initial chip select signal, and the second input of the second AND gate is configured to receive the control signal; the outputs of the first AND gate and the second AND gate are both connected to the first chip select interface.

9. The memory structure of claim 1, wherein, It also includes a third memory chip; the third memory chip is stacked on the side of the second memory chip away from the first memory chip, and the second memory chip and the third memory chip are three-dimensionally connected; the signal transmission line of the third memory chip passes through the second memory chip and the first memory chip and is connected to the pin; The storage structure is configured to read or write to the third storage chip via the signal transmission line of the third storage chip after receiving a preset third chip select signal.

10. A memory, comprising: include: The storage structure described in any one of claims 1-9; as well as A logic chip is disposed on the side of the second memory chip away from the first memory chip, and the logic chip and the second memory chip are three-dimensionally connected.

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