Semiconductor device, manufacturing method thereof, and memory device

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and a memory device. The semiconductor device comprises a word line; the word lines extend along a first direction; a bit line; the bit lines extend along a second direction; the second direction intersects with the first direction; a first conductive connection structure; the first conductive connection structure is located between the first surface and the word line; one end of the first conductive connection structure is connected with the word line; the first surface and the second surface are two opposite surfaces of the semiconductor device along the first direction; a second conductive connection structure; the second conductive connection structure is located between the second surface and the bit line; one end of the second conductive connection structure is connected with the bit line.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, such as to a semiconductor device and a method for manufacturing the same, and a memory device. Background Technology

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and products. For example, Dynamic Random Access Memory (DRAM), as a volatile memory, is a commonly used semiconductor memory device in computers. Summary of the Invention

[0003] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: a word line extending along a first direction; a bit line extending along a second direction intersecting the first direction; a first conductive connection structure located between a first surface and the word line; one end of the first conductive connection structure being connected to the word line; the first surface and the second surface being two surfaces of the semiconductor device opposite to each other along the first direction; and a second conductive connection structure located between the second surface and the bit line; one end of the second conductive connection structure being connected to the bit line.

[0004] In some optional embodiments, the semiconductor device includes a plurality of word lines and a plurality of first conductive connection structures, the plurality of word lines being arranged in an array along the second direction and a third direction, and one word line being connected to one first conductive connection structure; the third direction intersects the second direction and the first direction.

[0005] In some optional embodiments, the semiconductor device further includes: a plurality of first conductive connection lines; the plurality of first conductive connection lines are arranged along the second direction, the first conductive connection lines extend along the third direction, and the first conductive connection lines are connected to the plurality of first conductive connection structures arranged along the third direction.

[0006] In some alternative embodiments, the semiconductor device includes a plurality of memory blocks arranged along the third direction; the first conductive connection line is connected to a plurality of first conductive connection structures arranged along the third direction in the plurality of memory blocks.

[0007] In some alternative embodiments, the first conductive connection line is located between the first conductive connection structure and the first surface.

[0008] In some optional embodiments, the dimension of the end of the first conductive connection structure that is closer to the word line at the two opposite ends along the first direction is a first dimension in a direction perpendicular to the first direction, and the dimension of the end of the first conductive connection structure that is farther from the word line at the two opposite ends along the first direction is a second dimension in a direction perpendicular to the first direction, wherein the first dimension is larger than the second dimension.

[0009] In some optional embodiments, the dimension of the end of the first conductive connection structure closest to the word line at both ends along the first direction is a first dimension in a direction perpendicular to the first direction, and the dimension of the portion of the first conductive connection structure away from the word line along the first direction in a direction perpendicular to the first direction is a second dimension, wherein the first dimension is smaller than the second dimension.

[0010] In some alternative embodiments, the semiconductor device further includes a first bonding layer, the first bonding layer including a first bonding structure; the first bonding layer is located on one side of the word line opposite to each other along the first direction, closer to the second surface; the first bonding structure is coupled to the word line and the bit line.

[0011] In some optional embodiments, the semiconductor device further includes a third conductive connection structure; the two ends of the third conductive connection structure are respectively connected to the first conductive connection line and the first bonding structure.

[0012] In some alternative embodiments, the semiconductor device further includes a pad structure and a first interconnect structure; the pad structure is located on the side of the first conductive connection line near the first surface; the pad structure and the first bonding structure are connected through the first interconnect structure.

[0013] In some optional embodiments, the semiconductor device includes a memory layer comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; the memory cells include capacitor structures and transistor structures arranged along a third direction; the plurality of memory cells constitute a plurality of memory cell groups arranged along the third direction, the memory cell groups including a plurality of memory cell subgroups arranged in an array along the first direction and the second direction, the memory cell subgroups including first memory cells and second memory cells arranged along the third direction; a word line is connected to the first memory cell or the second memory cell of the plurality of memory cell subgroups arranged along the first direction, and a bit line is connected to the first memory cell and the second memory cell of the plurality of memory cell subgroups arranged along the second direction.

[0014] In some optional embodiments, the transistor structure includes: a semiconductor body; the semiconductor body extending along the third direction, and the two opposite ends of the semiconductor body along the third direction being connected to the bit line and the capacitor structure, respectively; a gate structure; the gate structure surrounding the semiconductor body, and a plurality of gate structures arranged along the first direction being connected to each other to form the word line.

[0015] According to a second aspect of the present disclosure, a memory device is provided, the memory device including a first semiconductor structure and a second semiconductor structure stacked along a first direction; the first semiconductor structure includes peripheral circuitry; the second semiconductor structure includes: a word line extending along the first direction; a bit line extending along a second direction; the second direction intersecting the first direction; a first conductive connection structure located on one side of the word line opposite to it along the first direction, away from the first semiconductor structure; one end of the first conductive connection structure being connected to the word line.

[0016] In some optional embodiments, the second semiconductor structure further includes: a second conductive connection structure; the second conductive connection structure is located between the bit line and the first semiconductor structure; one end of the second conductive connection structure is connected to the bit line.

[0017] In some optional embodiments, the first semiconductor structure further includes a second bonding layer, the second bonding layer including a second bonding structure, the second bonding layer being located between the peripheral circuit and the second semiconductor structure; the second semiconductor structure further includes a first bonding layer, the first bonding layer including a first bonding structure, the first bonding layer being located between the first semiconductor structure and the word line or bit line; the second bonding structure is coupled to the peripheral circuit, the first bonding structure is coupled to the word line and the bit line, and the first bonding structure is connected to the second bonding structure.

[0018] In some optional embodiments, the second semiconductor structure includes a plurality of word lines and a plurality of first conductive connection structures, the plurality of word lines being arranged in an array along the second direction and a third direction, and one word line being connected to one first conductive connection structure; the third direction intersects the second direction and the first direction.

[0019] In some optional embodiments, the second semiconductor structure further includes: a plurality of first conductive connection lines; the plurality of first conductive connection lines are arranged along the second direction, the first conductive connection lines extend along the third direction, and the first conductive connection lines are connected to the plurality of first conductive connection structures arranged along the third direction.

[0020] In some alternative embodiments, the second semiconductor structure includes a plurality of memory blocks arranged along the third direction; the first conductive connection line is connected to a plurality of the first conductive connection structures arranged along the third direction in the plurality of memory blocks.

[0021] In some alternative embodiments, the first conductive connection line and the first bonding layer are located on opposite sides of the word line along the first direction.

[0022] In some optional embodiments, the dimension of the end of the first conductive connection structure that is closer to the word line at the two opposite ends along the first direction is a first dimension in a direction perpendicular to the first direction, and the dimension of the end of the first conductive connection structure that is farther from the word line at the two opposite ends along the first direction is a second dimension in a direction perpendicular to the first direction, wherein the first dimension is larger than the second dimension.

[0023] In some optional embodiments, the dimension of the end of the first conductive connection structure closest to the word line at both ends along the first direction is a first dimension in a direction perpendicular to the first direction, and the dimension of the portion of the first conductive connection structure away from the word line along the first direction in a direction perpendicular to the first direction is a second dimension, wherein the first dimension is smaller than the second dimension.

[0024] In some optional embodiments, the second semiconductor structure further includes a third conductive connection structure; the two ends of the third conductive connection structure are respectively connected to the first conductive connection line and the first bonding structure.

[0025] In some optional embodiments, the second semiconductor structure further includes a pad structure and a first interconnect structure; the first conductive connection line is located between the pad structure and the first conductive connection structure; the pad structure and the first bonding structure are connected through the first interconnect structure.

[0026] In some optional embodiments, the second semiconductor structure includes a memory layer comprising a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; the memory cells include capacitor structures and transistor structures arranged along the third direction; the plurality of memory cells constitute a plurality of memory cell groups arranged along the third direction, the memory cell groups including a plurality of memory cell subgroups arranged in an array along the first direction and the second direction, the memory cell subgroups including first memory cells and second memory cells arranged along the third direction; a word line is connected to the first memory cell or the second memory cell of the plurality of memory cell subgroups arranged along the first direction, and a bit line is connected to the first memory cell and the second memory cell of the plurality of memory cell subgroups arranged along the second direction.

[0027] In some optional embodiments, the transistor structure includes: a semiconductor body; the semiconductor body extending along the third direction, and the two opposite ends of the semiconductor body along the third direction being connected to the bit line and the capacitor structure, respectively; a gate structure; the gate structure surrounding the semiconductor body, and a plurality of gate structures arranged along the first direction being connected to each other to form the word line.

[0028] According to a third aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a word line; the word line extending along a first direction; forming a bit line; the bit line extending along a second direction; the second direction intersecting the first direction; forming a first conductive connection structure; the first conductive connection structure being located between a first surface and the word line; one end of the first conductive connection structure being connected to the word line; the first surface and the second surface being two surfaces of the semiconductor device opposite to each other along the first direction; forming a second conductive connection structure; the second conductive connection structure being located between the second surface and the bit line; one end of the second conductive connection structure being connected to the bit line.

[0029] In some optional embodiments, the semiconductor device includes a plurality of word lines and a plurality of first conductive connection structures, the plurality of word lines being arranged in an array along the second direction and a third direction, and one word line being connected to one first conductive connection structure; the third direction intersects the second direction and the first direction.

[0030] In some optional embodiments, forming word lines, bit lines, a first conductive connection structure, and a second conductive connection structure includes: providing a semiconductor layer; the semiconductor layer including a first side and a second side opposite to each other along the thickness direction of the semiconductor layer; forming the first conductive connection structure in the semiconductor layer from the first side; forming the bit line and the word line on the semiconductor layer from the first side; and forming the second conductive connection structure on the bit line from the first side.

[0031] In some optional embodiments, the method further includes: forming a plurality of first conductive connection lines in the semiconductor layer from the first side before forming the first conductive connection structure in the semiconductor layer from the first side; the plurality of first conductive connection lines are arranged along the second direction, the first conductive connection lines extend along the third direction, and the first conductive connection lines are connected to the plurality of first conductive connection structures arranged along the third direction; the step of forming the first conductive connection structure in the semiconductor layer from the first side includes: forming the first conductive connection structure from the first conductive connection lines in the semiconductor layer from the first side.

[0032] In some optional embodiments, forming word lines, bit lines, a first conductive connection structure, and a second conductive connection structure includes: providing a semiconductor layer; the semiconductor layer including a first side and a second side opposite to each other along the thickness direction of the semiconductor layer; forming the bit lines and the word lines on the semiconductor layer from the first side; forming the second conductive connection structure on the bit lines from the first side; thinning the semiconductor layer from the second side; and forming the first conductive connection structure on the word lines from the second side.

[0033] In some optional embodiments, the method further includes: forming a plurality of first conductive connection lines on the first conductive connection structure from the second side; the plurality of first conductive connection lines are arranged along the second direction, the first conductive connection lines extend along the third direction, and the first conductive connection lines are connected to the plurality of first conductive connection structures arranged along the third direction.

[0034] In some optional embodiments, the method further includes: forming a first bonding layer from the first side; the first bonding layer including a first bonding structure; a second conductive connection structure located between the bit line and the first bonding layer; and the first bonding structure coupled to the word line and the bit line.

[0035] In some optional embodiments, the method further includes: forming a third conductive connection structure; the two ends of the third conductive connection structure are respectively connected to the first conductive connection line and the first bonding structure.

[0036] In some optional embodiments, the method further includes: forming a pad structure on the first conductive connection line from the second side; forming a first interconnect structure; the pad structure and the first bonding structure being connected through the first interconnect structure.

[0037] In the technical solution provided in this disclosure, one end of the first conductive connection structure is connected to the word line, and one end of the second conductive connection structure is connected to the bit line. The first conductive connection structure is located between the first surface and the word line, and the second conductive connection structure is located between the second surface and the bit line. That is to say, in the embodiments of this disclosure, the word line and the bit line are led out from opposite directions, which can reduce the wiring difficulty and save the wiring area. Attached Figure Description

[0038] Figure 1 A schematic diagram of an electronic device provided in an embodiment of this disclosure;

[0039] Figure 2 A schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0040] Figure 3A three-dimensional structural schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0041] Figure 4a Cross-section of a semiconductor device along the XZ plane provided in embodiments of this disclosure Figure 1 ;

[0042] Figure 4b for Figure 4a Cross-sectional view along the AA' direction;

[0043] Figure 4c A partial three-dimensional structural diagram of a semiconductor device provided in the embodiments of this disclosure. Figure 1 ;

[0044] Figure 5 A partial three-dimensional structural diagram of a semiconductor device provided in the embodiments of this disclosure. Figure 2 ;

[0045] Figure 6 Cross-section of a semiconductor device along the XZ plane provided in embodiments of this disclosure Figure 2 ;

[0046] Figure 7 This is a schematic diagram of the distribution structure of the storage unit group provided in an embodiment of the present disclosure;

[0047] Figure 8 This is a schematic diagram of the distribution structure of the storage unit subgroups provided in the embodiments of this disclosure;

[0048] Figure 9 Schematic diagram of the structure of the storage device provided in the embodiments of this disclosure Figure 1 ;

[0049] Figure 10 Schematic diagram of the structure of the storage device provided in the embodiments of this disclosure Figure 2 ;

[0050] Figure 11 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0051] Figures 12 to 18 A schematic diagram of the manufacturing process of a semiconductor device provided in an embodiment of this disclosure;

[0052] Figures 19 to 25 This is a schematic diagram of the manufacturing process of a semiconductor device provided in another embodiment of the present disclosure. Detailed Implementation

[0053] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0054] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0055] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0056] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0057] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0058] Figure 1This is a schematic diagram of an electronic device provided in an embodiment of this disclosure. The electronic device 1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0059] like Figure 1 As shown, electronic device 1 may include a memory system 10 and a host 20. The memory system 10 may include a controller 110 and a memory 120. The host 20 may include a processor of electronic device 1, such as a central processing unit (CPU) or a system-on-chip (SoC) (e.g., an application processor (AP)). The controller 110 is coupled to both the host 20 and the memory 120, and the controller 110 may be configured to communicate with the host 20 and control the memory 120.

[0060] In some embodiments, controller 110 may be configured to control operations of memory 120, such as read operations, erase operations, write operations, refresh operations, etc. In some embodiments, controller 110 is also configured to process error correction codes (ECCs) regarding data read from or written to memory 120. In other embodiments, controller 110 may also be configured to perform any other suitable operation, such as formatting memory 120.

[0061] In some embodiments, controller 110 can receive data, commands, and addresses from host 20, and can send data, commands, and addresses to memory 120. Specifically, controller 110 may include command generator 111, address generator 112, device interface 113, and host interface 114. Controller 110 can receive data, commands, and addresses from host 20 through host interface 114, decode commands received from host 20 through command generator 111 to generate access command CMD, and provide access command CMD to memory 120 through device interface 113. Controller 110 can decode addresses received from host interface 114 through address generator 112 to generate address ADDR to be accessed in memory array 121, and provide the address ADDR to be accessed to memory 120 through device interface 113. The access command may be a signal instructing memory 120 to write or read data by accessing one or more memory cells in memory array 121 corresponding to address ADDR. In addition, the controller 110 can also send a refresh command to the memory 120. The refresh command can be a signal instructing the memory 120 to read and rewrite data by accessing one or more memory cells of the memory array 121 corresponding to the address ADDR.

[0062] In some specific examples, memory 120 can be random access memory (RAM), such as dynamic random access memory, synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), double data rate SDRAM (DDR SDRAM), phase-change random access memory (PRAM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), etc. The following explanation will use DRAM as an example.

[0063] In some embodiments, Figure 2 This is a schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure. (Referring to...) Figure 1 and Figure 2The semiconductor device includes a memory array 121 and peripheral circuitry 122 coupled to the memory array 121. The peripheral circuitry 122 may include a sense amplifier circuit, a row decoder, a column decoder, a data input / output buffer, etc. The memory array 121 includes multiple memory cells arranged in an array. Multiple memory cells in the same row are coupled to a word line WL, and multiple memory cells in the same column are coupled to a bit line BL. Each memory cell includes a transistor T and a capacitor C. The word line WL is connected to the gate of transistor T, the bit line BL is connected to one of the source and drain of transistor T, and the other of the source and drain of transistor T is connected to one electrode of capacitor C. The other electrode of capacitor C is connected to a fixed voltage. The memory cell is configured to store 1 or 0 by using more or less charge stored in capacitor C. By specifying the row address and column address, each memory cell in the DRAM chip can be accessed independently, and read, write, or refresh operations can be performed on the stored data.

[0064] With the development of DRAM technology, the size of memory cells is getting smaller and smaller, and their array architecture has evolved from 8F... 2 Go to 6F 2 Then go to 4F 2 In addition, based on the requirements for ions and leakage current in DRAM, the architecture of memory has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried saddle fin array transistors, and finally from buried saddle fin array transistors to vertical gate transistors.

[0065] Figure 3 This is a three-dimensional structural schematic diagram of a semiconductor device according to an embodiment of the present disclosure. In some embodiments, such as Figure 3 As shown, word lines extend along the Z-axis, bit lines extend along the Y-axis, and the semiconductor body of the vertical gate transistor extends along the X-axis. In this architecture, the size of a single memory block along the X-axis is small, making it impossible to place the corresponding sensing amplifier circuit and word line driving circuit below the memory array. In some embodiments, the word lines of multiple memory blocks can be connected in parallel by conductive lines extending along the X-axis, allowing the word lines of multiple memory blocks to operate simultaneously. How to rationally configure these conductive lines becomes a problem that urgently needs to be solved.

[0066] The present disclosure provides the following implementation methods.

[0067] This disclosure provides a semiconductor device, such as... Figure 4a , Figure 4b as well as Figure 4c As shown, the semiconductor device includes: a word line 300 extending along a first direction; a bit line 301 extending along a second direction intersecting the first direction; a first conductive connection structure 302 located between a first surface 306 and the word line 300; one end of the first conductive connection structure 302 connected to the word line 300; the first surface 306 and the second surface 307 being two opposing surfaces of the semiconductor device along the first direction; a second conductive connection structure 303 located between the second surface 307 and the bit line 301; one end of the second conductive connection structure 303 connected to the bit line 301.

[0068] Figure 4a A cross-sectional view along the XZ plane of a semiconductor device provided in an embodiment of this disclosure; Figure 4b for Figure 4a Cross-sectional view along the AA' direction; Figure 4c This is a partial three-dimensional structural diagram of a semiconductor device provided in an embodiment of this disclosure.

[0069] In this embodiment of the present disclosure, one end of the first conductive connection structure 302 is connected to the word line 300, and one end of the second conductive connection structure 303 is connected to the bit line 301. The first conductive connection structure 302 is located between the first surface 306 and the word line 300, and the second conductive connection structure 303 is located between the second surface 307 and the bit line 301. That is to say, in this embodiment of the present disclosure, the word line 300 and the bit line 301 are led out from opposite directions, which can reduce the wiring difficulty and save the wiring area.

[0070] The first direction intersects with the second direction, and the third direction (described later) intersects with both the first and second directions. In this embodiment, the first direction is perpendicular to the second direction, and the third direction is perpendicular to both the second and first directions; however, this disclosure is not limited thereto. In this embodiment, the first direction is the Z-axis direction in the accompanying drawings, the second direction is the Y-axis direction, and the third direction is the X-axis direction.

[0071] In this embodiment of the disclosure, such as Figure 4a As shown, the first conductive connection structure 302 extends along the first direction, and one end of the first conductive connection structure 302 at opposite ends along the first direction is connected to the word line 300. The second conductive connection structure 303 extends along the first direction, and one end of the second conductive connection structure 303 at opposite ends along the first direction is connected to the bit line 301.

[0072] The materials of the first conductive connection structure 302, the second conductive connection structure 303, the word line 300, and the bit line 301 are all conductive materials. The conductive material can be one of the following: doped semiconductor material (e.g., doped silicon, doped germanium, etc.), conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), metal material (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0073] In some embodiments, such as Figure 4a , Figure 4b as well as Figure 4c As shown, the semiconductor device includes a plurality of word lines 300 and a plurality of first conductive connection structures 302. The plurality of word lines 300 are arranged in an array along the second direction and the third direction. One word line 300 is connected to one first conductive connection structure 302. The third direction intersects the second direction and the first direction.

[0074] In this embodiment of the disclosure, a plurality of word lines 300 are arranged in an array along a second direction and a third direction, and one word line 300 is connected to a first conductive connection structure 302. The plurality of first conductive connection structures 302 are arranged in an array along the second direction and the third direction.

[0075] In some embodiments, such as Figure 4a as well as Figure 5 As shown, the semiconductor device further includes: a plurality of first conductive connection lines 304; the plurality of first conductive connection lines 304 are arranged along the second direction, the first conductive connection lines 304 extend along the third direction, and the first conductive connection lines 304 are connected to a plurality of first conductive connection structures 302 arranged along the third direction.

[0076] The material of the first conductive connection line 304 is a conductive material, which can be one of the following: doped semiconductor material (e.g., doped silicon, doped germanium, etc.), conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), metallic material (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0077] In this embodiment of the disclosure, the first conductive connection line 304 connects to a plurality of first conductive connection structures 302 arranged along a third direction, so that a plurality of word lines 300 arranged along a third direction can operate simultaneously.

[0078] In some embodiments, such as Figure 4c and Figure 5As shown, the semiconductor device includes a plurality of memory blocks 305 arranged along the third direction; the first conductive connection line 304 is connected to a plurality of first conductive connection structures 302 arranged along the third direction in the plurality of memory blocks 305.

[0079] In this embodiment of the disclosure, each of the plurality of memory blocks 305 in the semiconductor device includes a plurality of word lines 300 and a plurality of first conductive connection structures 302. The plurality of word lines 300 within the memory block 305 are arranged in an array along a second direction and a third direction, and the plurality of word lines 300 included in the plurality of memory blocks 305 as a whole are arranged in an array along the second direction and a third direction. Figure 5 As shown, the first conductive connection line 304 is connected to the multiple first conductive connection structures 302 of the multiple memory blocks 305 arranged along the third direction, so that the first conductive connection line 304 is connected to the word lines 300 of the multiple memory blocks 305 arranged along the third direction, thereby enabling the multiple word lines 300 of the multiple memory blocks 305 arranged along the third direction to operate simultaneously.

[0080] It should be noted that, Figure 4c and Figure 5 The number of storage blocks 305 in the semiconductor device described herein is merely an example and is not intended to limit the number of storage blocks 305 in the embodiments of this disclosure.

[0081] In some specific examples, the second conductive connection structure 303 is located as follows: Figure 5 On the steps shown.

[0082] In some embodiments, such as Figure 4a As shown, the first conductive connection line 304 is located between the first conductive connection structure 302 and the first surface 306.

[0083] In this embodiment, the first conductive connection structure 302 is located between the first surface 306 and the word line 300, and the second conductive connection structure 303 is located between the second surface 307 and the bit line 301. The word line 300 and the bit line 301 are led out from opposite directions, so that the first conductive connection line 304 connected to the plurality of first conductive connection structures 302 arranged along the third direction can be disposed between the first surface 306 and the first conductive connection structure 302, thereby reducing the wiring difficulty and saving the wiring area.

[0084] In some embodiments, such as Figure 4aAs shown, the dimension of the end of the first conductive connection structure 302 closest to the word line 300 along the first direction is a first dimension, and the dimension of the portion of the first conductive connection structure 302 away from the word line 300 along the first direction is a second dimension, and the first dimension is smaller than the second dimension.

[0085] The direction perpendicular to the first direction here includes the third direction and the second direction.

[0086] In the above embodiments, such as Figure 4a As shown, the dimension of the first conductive connection structure 302 in the third direction gradually increases in the direction from the second surface 307 to the first surface 306.

[0087] In some embodiments, such as Figure 6 As shown, the dimension of the end of the first conductive connection structure 302 closest to the word line 300 at the two ends opposite to each other along the first direction is a first dimension, and the dimension of the end of the first conductive connection structure 302 furthest from the word line 300 at the two ends opposite to each other along the first direction is a second dimension, and the first dimension is larger than the second dimension.

[0088] In the above embodiments, such as Figure 6 As shown, the dimension of the first conductive connection structure 302 in the third direction gradually decreases in the direction from the second surface 307 to the first surface 306.

[0089] In some embodiments, such as Figure 4a and Figure 6 As shown, the semiconductor device further includes a first bonding layer 308, the first bonding layer 308 including a first bonding structure 309; the first bonding layer 308 is located on one side of the word line 300 opposite to each other along the first direction, closer to the second surface 307; the first bonding structure 309 is coupled to the word line 300 and the bit line 301.

[0090] In some specific examples, the first bonding layer 308 is a hybrid bonding layer, and the material of the first bonding structure 309 includes metallic materials, including but not limited to aluminum, copper, tungsten, titanium, and tantalum.

[0091] In some embodiments, such as Figure 4a and Figure 6 As shown, the semiconductor device further includes a third conductive connection structure 310.

[0092] In some specific examples, the third conductive connection structure 310 extends along the first direction, and its two opposite ends along the first direction are respectively connected to the first conductive connection line 304 and the first bonding structure 309. In other specific examples, such as Figure 4a and Figure 6 As shown, the two ends of the third conductive connection structure 310 along the first direction are respectively connected to the first conductive connection line 304 and the second interconnection structure 312, and the second interconnection structure 312 is connected to the first bonding structure 309.

[0093] In some embodiments, such as Figure 4a and Figure 6 As shown, the semiconductor device further includes a pad structure 311 and a first interconnect structure; the pad structure 311 is located on the side of the first conductive connection line 304 near the first surface 306; the pad structure 311 and the first bonding structure 309 are connected through the first interconnect structure.

[0094] In some specific examples, the materials of the pad structure 311, the first interconnect structure, the second interconnect structure, and the third conductive connection structure 310 all include conductive materials. Here, the conductive material can be one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0095] In some embodiments, such as Figure 4a and Figure 6 As shown, the semiconductor device includes a memory layer 313, which includes a plurality of word lines 300, a plurality of bit lines 301, and a plurality of memory cells; the memory cells include capacitor structures 314 and transistor structures 315 arranged along the third direction; as Figure 7 As shown, the plurality of storage cells constitute a plurality of storage cell groups 316 arranged along the third direction, such as Figure 8 As shown, the storage cell group 316 includes multiple storage cell subgroups 317 arranged in an array along the first direction and the second direction, such as... Figure 4a and Figure 6 As shown, the storage cell subgroup 317 includes a first storage cell 318 and a second storage cell 319 arranged along the third direction; a word line 300 is connected to the first storage cell 318 or the second storage cell 319 of the plurality of storage cell subgroups 317 arranged along the first direction, and a bit line 301 is connected to the first storage cell 318 and the second storage cell 319 of the plurality of storage cell subgroups 317 arranged along the second direction.

[0096] In this embodiment of the present disclosure, each storage block 305 includes multiple storage cells, and the multiple storage cells within the storage block 305 constitute a storage cell group 316. Each storage cell group 316 includes multiple storage cell subgroups 317 arranged in an array along a first direction and a second direction. Each storage cell subgroup 317 includes a first storage cell 318 and a second storage cell 319 arranged along a third direction. The first storage cell 318 and the second storage cell 319 within the storage cell subgroup 317 share the same bit line 301, and the multiple storage cell subgroups 317 arranged along the second direction also share the same bit line 301. In the plurality of storage cell subgroups 317 arranged along the first direction, a plurality of first storage cells 318 are arranged along the first direction, and the plurality of first storage cells 318 in the plurality of storage cell subgroups 317 arranged along the first direction share a word line 300; in the plurality of storage cell subgroups 317 arranged along the first direction, a plurality of second storage cells 319 are arranged along the first direction, and the plurality of second storage cells 319 in the plurality of storage cell subgroups 317 arranged along the first direction share a word line 300.

[0097] In the embodiments disclosed herein, such as Figure 4b As shown, the transistor structure 315 is a vertical transistor, including a semiconductor body 320 extending along a third direction, and the first memory cell 318 and the second memory cell 319 in the memory cell subgroup 317 share a bit line 301, which is beneficial to reducing the area of ​​the semiconductor device and increasing the storage density.

[0098] In some embodiments, such as Figure 4b As shown, the transistor structure 315 includes: a semiconductor body 320; the semiconductor body 320 extends along the third direction, and the two opposite ends of the semiconductor body 320 along the third direction are respectively connected to the bit line 301 and the capacitor structure 314; a gate structure 321; the gate structure 321 surrounds the semiconductor body 320, and a plurality of gate structures 321 arranged along the first direction are connected to each other to form the word line 300.

[0099] In some specific examples, the semiconductor body 320 includes a first electrode structure, a channel structure, and a second electrode structure arranged sequentially along a third direction. Here, the first electrode structure can be either the source or the drain of the transistor structure 315, and the second electrode structure can be either the source or the drain of the transistor structure 315. The gate structure 321 is located on both sides of the channel structure opposite to each other along the first direction and on both sides opposite to each other along the second direction, that is, the gate structure 321 surrounds the channel structure, forming a full-ring gate vertical transistor.

[0100] In some specific examples, the material of the semiconductor body 320 includes, but is not limited to, elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), etc.), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. The material of the gate structure 321 includes at least one of conductive materials, such as doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0101] It should be noted that, Figure 4a and Figure 4b The arrangement of the gate structure 321 is merely an example. In other embodiments, the gate structure 321 is located on at least one side of the channel structure in a direction perpendicular to a third direction. The gate structure 321 may be located on one, two, or three sides of the channel structure. This disclosure does not impose any specific limitations on this.

[0102] In some specific examples, such as Figure 4b As shown, the transistor structure 315 further includes a gate dielectric layer 329, which is located between the gate structure 321 and the channel structure of the semiconductor body 320. The gate dielectric layer 329 may include at least one of a high dielectric constant material, silicon oxide, silicon nitride, and silicon oxynitride. The high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0103] In some specific examples, capacitor structure 314 includes a first electrode, a second electrode, and a dielectric layer located between the first electrode and the second electrode. In other embodiments, capacitor structure 314 may also have any other suitable structure, and this disclosure does not impose any specific limitations on it. One end of semiconductor body 320 at opposite ends along a third direction is connected to the first electrode of capacitor structure 314, the second electrodes of a plurality of capacitor structures 314 arranged along a first direction are connected, and the second electrodes of adjacent capacitor structures 314 in two adjacent memory cell subgroups 317 along a third direction are connected. The second electrodes of capacitor structure 314 are connected to, for example,... Figure 4a and Figure 6 The fourth conductive connection structure 327 shown is connected.

[0104] Based on a concept similar to the aforementioned semiconductor devices, this disclosure also provides a storage device, such as... Figure 9 and Figure 10 As shown, the memory device includes a first semiconductor structure 322 and a second semiconductor structure 323 stacked along a first direction; the first semiconductor structure 322 includes peripheral circuitry 324; the second semiconductor structure 323 includes: a word line 300 extending along the first direction; a bit line 301 extending along a second direction intersecting the first direction; a first conductive connection structure 302 located on one side of the word line 300 opposite to it along the first direction, away from the first semiconductor structure 322; one end of the first conductive connection structure 302 is connected to the word line 300.

[0105] In this embodiment of the present disclosure, one end of the first conductive connection structure 302 is connected to the word line 300. The first conductive connection structure 302 is located on the side of the word line 300 that is far away from the first semiconductor structure 322 on both sides opposite to each other along the first direction. This reduces the wiring pressure between the memory array and the peripheral circuit 324, reduces the wiring difficulty, and saves wiring area.

[0106] In some embodiments, such as Figure 9 and Figure 10 As shown, the second semiconductor structure 323 further includes: a second conductive connection structure 303; the second conductive connection structure 303 is located between the bit line 301 and the first semiconductor structure 322; one end of the second conductive connection structure 303 is connected to the bit line 301.

[0107] In some embodiments, such as Figure 9 and Figure 10 As shown, the first semiconductor structure 322 further includes a second bonding layer 325, which includes a second bonding structure 326. The second bonding layer 325 is located between the peripheral circuit 324 and the second semiconductor structure 323. The second semiconductor structure 323 further includes a first bonding layer 308, which includes a first bonding structure 309. The first bonding layer 308 is located between the first semiconductor structure 322 and the word line 300 or the bit line 301. The second bonding structure 326 is coupled to the peripheral circuit 324, and the first bonding structure 309 is coupled to the word line 300 and the bit line 301. The first bonding structure 309 is connected to the second bonding structure 326.

[0108] In some specific examples, the first bonding layer 308 and the second bonding layer 325 can be hybrid bonding layers, and the first bonding structure 309 and the second bonding structure 326 can both be metal-metal bonding structures.

[0109] In this embodiment of the present disclosure, the first semiconductor structure 322 and the second semiconductor structure 323 are stacked along a first direction. Thus, the memory array and the peripheral circuit 324 can be arranged along the stacking direction of the memory devices. On the one hand, the length of the connection between the memory array and the peripheral circuit 324 can be reduced, and the reliability of signal transmission can be improved. On the other hand, the area occupied by the memory array can be reduced, which is conducive to the miniaturization of memory devices.

[0110] In some embodiments, the second semiconductor structure 323 includes a plurality of word lines 300 and a plurality of first conductive connection structures 302. The plurality of word lines 300 are arranged in an array along the second direction and a third direction, and one word line 300 is correspondingly connected to one first conductive connection structure 302. The third direction intersects the second direction and the first direction.

[0111] In some embodiments, such as Figure 9 and Figure 10 As shown, the second semiconductor structure 323 further includes: a plurality of first conductive connection lines 304; the plurality of first conductive connection lines 304 are arranged along the second direction, the first conductive connection lines 304 extend along the third direction, and the first conductive connection lines 304 are connected to the plurality of first conductive connection structures 302 arranged along the third direction.

[0112] In some embodiments, such as Figure 5 As shown, the second semiconductor structure 323 includes a plurality of memory blocks 305 arranged along the third direction; the first conductive connection line 304 is connected to a plurality of first conductive connection structures 302 arranged along the third direction in the plurality of memory blocks 305.

[0113] In some embodiments, such as Figure 9 and Figure 10 As shown, the first conductive connection line 304 and the first bonding layer 308 are located on opposite sides of the word line 300 along the first direction.

[0114] In some embodiments, such as Figure 10 As shown, the dimension of the end of the first conductive connection structure 302 closest to the word line 300 at the two ends opposite to each other along the first direction is a first dimension, and the dimension of the end of the first conductive connection structure 302 furthest from the word line 300 at the two ends opposite to each other along the first direction is a second dimension, and the first dimension is larger than the second dimension.

[0115] In some embodiments, such as Figure 9As shown, the dimension of the end of the first conductive connection structure 302 closest to the word line 300 along the first direction is a first dimension, and the dimension of the portion of the first conductive connection structure 302 away from the word line 300 along the first direction is a second dimension, and the first dimension is smaller than the second dimension.

[0116] In some embodiments, such as Figure 9 and Figure 10 As shown, the second semiconductor structure 323 further includes a third conductive connection structure 310. The two ends of the third conductive connection structure 310 are respectively connected to the first conductive connection line 304 and the first bonding structure 309.

[0117] In some embodiments, such as Figure 9 and Figure 10 As shown, the second semiconductor structure 323 further includes a pad structure 311 and a first interconnect structure; the first conductive connection line 304 is located between the pad structure 311 and the first conductive connection structure 302; the pad structure 311 and the first bonding structure 309 are connected through the first interconnect structure.

[0118] In some embodiments, such as Figure 7 , Figure 8 , Figure 9 and Figure 10 As shown, the second semiconductor structure 323 includes a storage layer 313, which includes a plurality of word lines 300, a plurality of bit lines 301, and a plurality of storage cells. The storage cells include a capacitor structure 314 and a transistor structure 315 arranged along the third direction. The plurality of storage cells form a plurality of storage cell groups 316 arranged along the third direction. The storage cell group 316 includes a plurality of storage cell subgroups 317 arranged in an array along the first direction and the second direction. The storage cell subgroups 317 include a first storage cell 318 and a second storage cell 319 arranged along the third direction. One word line 300 is connected to the first storage cell 318 or the second storage cell 319 of the plurality of storage cell subgroups 317 arranged along the first direction, and one bit line 301 is connected to the first storage cell 318 and the second storage cell 319 of the plurality of storage cell subgroups 317 arranged along the second direction.

[0119] In some embodiments, such as Figure 4bAs shown, the transistor structure 315 includes: a semiconductor body 320; the semiconductor body 320 extends along the third direction, and the two opposite ends of the semiconductor body 320 along the third direction are respectively connected to the bit line 301 and the capacitor structure 314; a gate structure 321; the gate structure 321 surrounds the semiconductor body 320, and a plurality of gate structures 321 arranged along the first direction are connected to each other to form the word line 300.

[0120] Based on a concept similar to the semiconductor device described above, this disclosure also provides a method for manufacturing a semiconductor device. Figure 11 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure, such as... Figure 11 As shown, the method for manufacturing a semiconductor device includes the following steps:

[0121] Step S10: Forming character lines; the character lines extend along a first direction;

[0122] Step S20: Form a bit line; the bit line extends along a second direction; the second direction intersects with the first direction;

[0123] Step S30: Form a first conductive connection structure; the first conductive connection structure is located between the first surface and the word line; one end of the first conductive connection structure is connected to the word line; the first surface and the second surface are two surfaces of the semiconductor device opposite to each other along the first direction;

[0124] Step S40: Form a second conductive connection structure; the second conductive connection structure is located between the second surface and the bit line; one end of the second conductive connection structure is connected to the bit line.

[0125] It should be understood that Figure 11 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 11 The steps shown can be adjusted in order according to actual needs.

[0126] Figures 12 to 18 This is a schematic diagram of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure. The following will be combined with... Figures 12 to 18 A method for manufacturing a semiconductor device according to embodiments of this disclosure will be described.

[0127] In some embodiments, forming word lines, bit lines, a first conductive connection structure, and a second conductive connection structure includes: as follows Figure 12 as well as Figure 13As shown, a semiconductor layer 328 is provided; the semiconductor layer 328 includes a first side and a second side opposite to each other along the thickness direction of the semiconductor layer 328; the bit line 301 and the word line 300 are formed on the semiconductor layer 328 from the first side; as shown Figure 14 As shown, the second conductive connection structure 303 is formed on the bit line 301 from the first side; as Figure 17 As shown, the semiconductor layer 328 is thinned from the second side; the first conductive connection structure 302 is formed on the word line 300 from the second side.

[0128] In some specific examples, the semiconductor layer 328 can be a substrate, and the substrate material can include at least one of semiconductor materials such as silicon, germanium, and silicon germanide.

[0129] In some embodiments, the method further includes: Figure 14 As shown, a first bonding layer 308 is formed from the first side; the first bonding layer 308 includes a first bonding structure 309. The second conductive connection structure is located between the bit line and the first bonding layer; the first bonding structure is coupled to the word line and the bit line.

[0130] In some embodiments, such as Figure 15 As shown, forming a memory device includes providing a first semiconductor structure 322, the first semiconductor structure 322 including peripheral circuitry 324 and a second bonding layer 325. For example... Figure 16 As shown, after the first bonding layer 308 is formed, the first bonding layer 308 can be bonded to the second bonding layer 325, thereby making the first semiconductor structure 322 and the semiconductor device stacked along the first direction.

[0131] In some embodiments, such as Figure 17 As shown, the method further includes: forming a plurality of first conductive connection lines 304 on the first conductive connection structure 302 from the second side; the plurality of first conductive connection lines 304 are arranged along the second direction, the first conductive connection lines 304 extend along the third direction, and the first conductive connection lines 304 are connected to the plurality of first conductive connection structures 302 arranged along the third direction.

[0132] In some embodiments, such as Figure 17 As shown, the method further includes: forming a third conductive connection structure 310; the two ends of the third conductive connection structure 310 are respectively connected to the first conductive connection line 304 and the first bonding structure 309.

[0133] In some embodiments, such as Figure 18As shown, the method further includes: forming a pad structure 311 on the first conductive connection line 304 from the second side; forming a first interconnect structure; the pad structure 311 and the first bonding structure 309 are connected through the first interconnect structure.

[0134] In some specific examples, the bit line 301, word line 300, first conductive connection structure 302, second conductive connection structure 303, third conductive connection structure 310, pad structure 311, first interconnect structure, and first conductive connection line 304 can be formed through etching and deposition processes. In embodiments of this disclosure, deposition processes include, but are not limited to, Chemical Vapor Deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD). Etching processes include, but are not limited to, wet etching, plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE).

[0135] Figures 19 to 25 This is a schematic diagram of the manufacturing process of a semiconductor device according to another embodiment of the present disclosure. The following will be combined with... Figures 19 to 25 A method for manufacturing a semiconductor device according to embodiments of this disclosure will be described.

[0136] In some embodiments, forming word lines, bit lines, a first conductive connection structure, and a second conductive connection structure includes: as follows Figure 19 As shown, a semiconductor layer 328 is provided; the semiconductor layer 328 includes a first side and a second side opposite to each other along the thickness direction of the semiconductor layer 328; the first conductive connection structure 302 is formed in the semiconductor layer 328 from the first side.

[0137] In some embodiments, the method further includes: Figure 19As shown, before forming the first conductive connection structure 302 in the semiconductor layer 328 from the first side, a plurality of first conductive connection lines 304 are formed in the semiconductor layer 328 from the first side; the plurality of first conductive connection lines 304 are arranged along the second direction, the first conductive connection lines 304 extend along the third direction, and the first conductive connection lines 304 are connected to the plurality of first conductive connection structures 302 arranged along the third direction; the formation of the first conductive connection structure 302 in the semiconductor layer 328 from the first side includes: forming the first conductive connection structure 302 on the first conductive connection lines 304 in the semiconductor layer 328 from the first side.

[0138] In this embodiment of the present disclosure, a first conductive connection structure 302 and a first conductive connection line 304 can be formed in the semiconductor layer 328 by pre-embedding.

[0139] In some embodiments, the formation of word line 300, bit line 301, first conductive connection structure 302, and second conductive connection structure 303 includes: as Figure 20 as well as Figure 21 As shown, the bit line 301 and the word line 300 are formed on the semiconductor layer 328 from the first side; as Figure 22 As shown, the second conductive connection structure 303 is formed on the bit line 301 from the first side.

[0140] In some embodiments, the method further includes: Figure 22 As shown, a first bonding layer 308 is formed from the first side; the first bonding layer 308 includes a first bonding structure 309; the second conductive connection structure is located between the bit line and the first bonding layer; the first bonding structure is coupled to the word line and the bit line.

[0141] In some embodiments, such as Figure 23 As shown, forming a memory device includes providing a first semiconductor structure 322, the first semiconductor structure 322 including peripheral circuitry 324 and a second bonding layer 325. For example... Figure 24 As shown, after the first bonding layer 308 is formed, the first bonding layer 308 can be bonded to the second bonding layer 325, thereby making the first semiconductor structure 322 and the semiconductor device stacked along the first direction.

[0142] In some embodiments, such as Figure 24 As shown, the method further includes: forming a third conductive connection structure 310; the two ends of the third conductive connection structure 310 are respectively connected to the first conductive connection line 304 and the first bonding structure 309.

[0143] In some embodiments, such as Figure 25 As shown, the method further includes: forming a pad structure 311 on the first conductive connection line 304 from the second side; forming a first interconnect structure; the pad structure 311 and the first bonding structure 309 are connected through the first interconnect structure.

[0144] In some embodiments, the semiconductor device includes a plurality of word lines 300 and a plurality of first conductive connection structures 302. The plurality of word lines 300 are arranged in an array along the second direction and a third direction, and one word line 300 is correspondingly connected to one first conductive connection structure 302. The third direction intersects the second direction and the first direction.

[0145] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0146] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0147] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Word lines; The letter line extends along a first direction; Bit line; The bit line extends along the second direction; The second direction intersects with the first direction; A first conductive connection structure; the first conductive connection structure is located between the first surface and the word line; One end of the first conductive connection structure is connected to the word line; the first surface and the second surface are two surfaces of the semiconductor device that are opposite to each other along the first direction. A second conductive connection structure; the second conductive connection structure is located between the second surface and the bit line; one end of the second conductive connection structure is connected to the bit line.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a plurality of word lines and a plurality of first conductive connection structures. The plurality of word lines are arranged in an array along the second direction and the third direction. Each word line is connected to a corresponding first conductive connection structure. The third direction intersects the second direction and the first direction.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: Multiple first conductive connecting lines; the multiple first conductive connecting lines are arranged along the second direction, the first conductive connecting lines extend along the third direction, and the first conductive connecting lines are connected to the multiple first conductive connecting structures arranged along the third direction.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor device includes a plurality of memory blocks arranged along the third direction; the first conductive connection line is connected to a plurality of first conductive connection structures arranged along the third direction in the plurality of memory blocks.

5. The semiconductor device according to claim 3, characterized in that, The first conductive connection line is located between the first conductive connection structure and the first surface.

6. The semiconductor device according to claim 1, characterized in that, The dimension of the end of the first conductive connection structure that is closer to the word line at the two opposite ends along the first direction is a first dimension in a direction perpendicular to the first direction, and the dimension of the end of the first conductive connection structure that is farther from the word line at the two opposite ends along the first direction is a second dimension in a direction perpendicular to the first direction, wherein the first dimension is larger than the second dimension.

7. The semiconductor device according to claim 1, characterized in that, The dimension of the end of the first conductive connection structure closest to the word line at its two opposite ends along the first direction is a first dimension, and the dimension of the portion of the first conductive connection structure away from the word line along the first direction is a second dimension, wherein the first dimension is smaller than the second dimension.

8. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes a first bonding layer, the first bonding layer including a first bonding structure; the first bonding layer is located on one side of the word line opposite to each other along the first direction, closer to the second surface; the first bonding structure is coupled to the word line and the bit line.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes a third conductive connection structure; the two ends of the third conductive connection structure are respectively connected to the first conductive connection line and the first bonding structure.

10. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes a pad structure and a first interconnect structure; the pad structure is located on the side of the first conductive connection line near the first surface; the pad structure and the first bonding structure are connected through the first interconnect structure.

11. The semiconductor device according to claim 2, characterized in that, The semiconductor device includes a memory layer, which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; the memory cells include capacitor structures and transistor structures arranged along the third direction. The plurality of storage cells constitute a plurality of storage cell groups arranged along the third direction. The storage cell group includes a plurality of storage cell subgroups arranged in an array along the first direction and the second direction. The storage cell subgroups include a first storage cell and a second storage cell arranged along the third direction. A word line is connected to the first or second memory cell of a plurality of memory cell subgroups arranged along the first direction, and a bit line is connected to the first and second memory cells of a plurality of memory cell subgroups arranged along the second direction.

12. The semiconductor device according to claim 11, characterized in that, The transistor structure includes: A semiconductor body; the semiconductor body extends along the third direction, and the two opposite ends of the semiconductor body along the third direction are respectively connected to the bit line and the capacitor structure; Gate structure; the gate structure surrounds the semiconductor body, and a plurality of gate structures arranged along the first direction are connected to each other to form the word line.

13. A storage device, characterized in that, The storage device includes a first semiconductor structure and a second semiconductor structure stacked along a first direction; the first semiconductor structure includes peripheral circuitry. The second semiconductor structure includes: Character line; the character line extends along the first direction; Bit line; the bit line extends along a second direction; the second direction intersects the first direction; A first conductive connection structure; the first conductive connection structure is located on the side of the word line opposite to each other along the first direction that is away from the first semiconductor structure; one end of the first conductive connection structure is connected to the word line.

14. The storage device according to claim 13, characterized in that, The second semiconductor structure further includes: a second conductive connection structure; the second conductive connection structure is located between the bit line and the first semiconductor structure; one end of the second conductive connection structure is connected to the bit line.

15. The storage device according to claim 14, characterized in that, The first semiconductor structure further includes a second bonding layer, which includes a second bonding structure, and is located between the peripheral circuit and the second semiconductor structure; the second semiconductor structure further includes a first bonding layer, which includes a first bonding structure, and is located between the first semiconductor structure and the word line or bit line; the second bonding structure is coupled to the peripheral circuit, the first bonding structure is coupled to the word line and the bit line, and the first bonding structure is connected to the second bonding structure.

16. The storage device according to claim 15, characterized in that, The second semiconductor structure includes a plurality of word lines and a plurality of first conductive connection structures. The plurality of word lines are arranged in an array along the second direction and a third direction, and one word line is connected to one first conductive connection structure. The third direction intersects the second direction and the first direction.

17. The storage device according to claim 16, characterized in that, The second semiconductor structure also includes: Multiple first conductive connecting lines; the multiple first conductive connecting lines are arranged along the second direction, the first conductive connecting lines extend along the third direction, and the first conductive connecting lines are connected to the multiple first conductive connecting structures arranged along the third direction.

18. The storage device according to claim 17, characterized in that, The second semiconductor structure includes a plurality of memory blocks arranged along the third direction; the first conductive connection line is connected to a plurality of the first conductive connection structures arranged along the third direction in the plurality of memory blocks.

19. The storage device according to claim 17, characterized in that, The first conductive connection line and the first bonding layer are located on opposite sides of the word line along the first direction.

20. The storage device according to claim 13, characterized in that, The dimension of the end of the first conductive connection structure that is closer to the word line at the two opposite ends along the first direction is a first dimension in a direction perpendicular to the first direction, and the dimension of the end of the first conductive connection structure that is farther from the word line at the two opposite ends along the first direction is a second dimension in a direction perpendicular to the first direction, wherein the first dimension is larger than the second dimension.

21. The storage device according to claim 13, characterized in that, The dimension of the end of the first conductive connection structure closest to the word line at its two opposite ends along the first direction is a first dimension, and the dimension of the portion of the first conductive connection structure away from the word line along the first direction is a second dimension, wherein the first dimension is smaller than the second dimension.

22. The storage device according to claim 17, characterized in that, The second semiconductor structure further includes a third conductive connection structure; the two ends of the third conductive connection structure are respectively connected to the first conductive connection line and the first bonding structure.

23. The storage device according to claim 17, characterized in that, The second semiconductor structure further includes a pad structure and a first interconnect structure; the first conductive connection line is located between the pad structure and the first conductive connection structure; the pad structure and the first bonding structure are connected through the first interconnect structure.

24. The storage device according to claim 16, characterized in that, The second semiconductor structure includes a memory layer, which includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; the memory cells include capacitor structures and transistor structures arranged along the third direction. Multiple storage cells constitute multiple storage cell groups arranged along the third direction. The storage cell group includes multiple storage cell subgroups arranged in an array along the first direction and the second direction. The storage cell subgroups include a first storage cell and a second storage cell arranged along the third direction. A word line is connected to the first or second memory cell of a plurality of memory cell subgroups arranged along the first direction, and a bit line is connected to the first and second memory cells of a plurality of memory cell subgroups arranged along the second direction.

25. The storage device according to claim 24, characterized in that, The transistor structure includes: A semiconductor body; the semiconductor body extends along the third direction, and the two opposite ends of the semiconductor body along the third direction are respectively connected to the bit line and the capacitor structure; Gate structure; the gate structure surrounds the semiconductor body, and a plurality of gate structures arranged along the first direction are connected to each other to form the word line.

26. A method for manufacturing a semiconductor device, characterized in that, include: Forming character lines; The letter line extends along a first direction; Form bit lines; The bit line extends along the second direction; The second direction intersects with the first direction; Forming the first conductive connection structure; The first conductive connection structure is located between the first surface and the word line; One end of the first conductive connection structure is connected to the word line; the first surface and the second surface are two surfaces of the semiconductor device that are opposite to each other along the first direction. A second conductive connection structure is formed; the second conductive connection structure is located between the second surface and the bit line; one end of the second conductive connection structure is connected to the bit line.

27. The manufacturing method according to claim 26, characterized in that, The semiconductor device includes a plurality of word lines and a plurality of first conductive connection structures. The plurality of word lines are arranged in an array along the second direction and the third direction. Each word line is connected to a corresponding first conductive connection structure. The third direction intersects the second direction and the first direction.

28. The manufacturing method according to claim 27, characterized in that, The formation of word lines, bit lines, a first conductive connection structure, and a second conductive connection structure includes: A semiconductor layer is provided; the semiconductor layer includes a first side and a second side opposite to each other along the thickness direction of the semiconductor layer; The first conductive connection structure is formed in the semiconductor layer from the first side; The bit lines and word lines are formed on the semiconductor layer from the first side; The second conductive connection structure is formed on the bit line from the first side.

29. The manufacturing method according to claim 28, characterized in that, The method further includes: Before forming the first conductive connection structure in the semiconductor layer from the first side, a plurality of first conductive connection lines are formed in the semiconductor layer from the first side; the plurality of first conductive connection lines are arranged along the second direction, the first conductive connection lines extend along the third direction, and the first conductive connection lines are connected to the plurality of first conductive connection structures arranged along the third direction; The formation of the first conductive connection structure in the semiconductor layer from the first side includes: The first conductive connection structure is formed from the first conductive connection line in the semiconductor layer from the first side.

30. The manufacturing method according to claim 27, characterized in that, The formation of word lines, bit lines, a first conductive connection structure, and a second conductive connection structure includes: A semiconductor layer is provided; the semiconductor layer includes a first side and a second side opposite to each other along the thickness direction of the semiconductor layer; The bit lines and word lines are formed on the semiconductor layer from the first side; The second conductive connection structure is formed on the bit line from the first side; The semiconductor layer is thinned from the second side; The first conductive connection structure is formed on the word line from the second side.

31. The manufacturing method according to claim 30, characterized in that, The method further includes: A plurality of first conductive connection lines are formed on the first conductive connection structure from the second side; the plurality of first conductive connection lines are arranged along the second direction, the first conductive connection lines extend along the third direction, and the first conductive connection lines are connected to the plurality of first conductive connection structures arranged along the third direction.

32. The manufacturing method according to claim 29 or 31, characterized in that, The method further includes: A first bonding layer is formed from the first side; the first bonding layer includes a first bonding structure; the second conductive connection structure is located between the bit line and the first bonding layer; the first bonding structure is coupled to the word line and the bit line.

33. The manufacturing method according to claim 32, characterized in that, The method further includes: A third conductive connection structure is formed; the two ends of the third conductive connection structure are respectively connected to the first conductive connection line and the first bonding structure.

34. The manufacturing method according to claim 33, characterized in that, The method further includes: A pad structure is formed on the first conductive connection line from the second side; A first interconnect structure is formed; the pad structure and the first bonding structure are connected through the first interconnect structure.

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