Board card and interconnection method

Abstract

The invention provides a board card and an interconnection method, which can be applied to the technical field of hardware. The board card at least comprises a first mainboard and a second mainboard. The first mainboard comprises a central processing unit, and a mainboard interface, a memory and a management controller which are electrically connected with the central processing unit, and the memory is used for deploying an operating system of the central processing unit; the second main board comprises a first exchange interface, an exchange unit and a controller which are electrically connected, and the first main board is arranged on the second main board and is electrically connected to the second main board through the first exchange interface and the main board interface.

Description

Technical Field

[0001] This application relates to the field of hardware technologies, and more particularly to a board card and an interconnection method. Background Art

[0002] As one of the core components of a server, the central processing unit is of great importance for the normal operation of the server. On this basis, in the related technologies, servers are mainly manufactured around the architecture of the central processing unit. Thus, the manufactured servers have a high degree of dependence on the central processing unit and it is difficult to adapt to central processing units of multiple architectures. Summary of the Invention

[0003] In view of the above problems, this application provides a board card and an interconnection method.

[0004] According to the first aspect of this application, there is provided a board card, which at least includes a first main board and a second main board; the first main board includes a central processing unit, a main board interface electrically connected to the central processing unit, a memory, and a management controller, and the memory is used to deploy the operating system of the central processing unit; and the second main board includes a first switching interface, a switching unit, and a controller that are electrically connected, wherein the first main board is disposed on the second main board and electrically connected to the second main board through the first switching interface and the main board interface.

[0005] The second aspect of this application provides an interconnection method executed by the above board card, including: the central processing unit of the first main board is interconnected with the switching unit and the controller of the second main board via the main board interface of the first main board and the first switching interface of the second main board based on the memory and the management controller of the first main board.

[0006] According to the embodiments of this application, the central processing unit, the main board interface electrically connected to the central processing unit, the management controller, and the memory deploying the operating system of the central processing unit are separately integrated on the first main board, and the electrically connected first switching interface, switching unit, and controller are integrated on the second main board. Thus, when the first main board is disposed on the second main board, the first main board can be electrically connected to the second main board through the first switching interface and the main board interface, and thus can be used as a server architecture. On this basis, this application decouples the complete server architecture into the first main board and the second main board, and can realize the replacement of the first main board. In this case, first main boards of different architectures can be electrically connected to the second main board, thereby realizing the compatibility of the second main board with first main boards of different architectures, that is, the compatibility of the server architecture with central processing units of different architectures, and enabling the server to adapt to central processing units of different architectures. Description of the Drawings

[0007] Through the following description of the embodiments of the present application with reference to the accompanying drawings, the above content of the present application and other objects, features, and advantages will become clearer. In the drawings:

[0008] Figure 1 A schematic diagram of a board card according to the first embodiment of the present application is shown.

[0009] Figure 2 A schematic diagram of a first main board according to an embodiment of the present application is shown.

[0010] Figure 3 A schematic diagram of a first main board and a second main board according to the first embodiment of the present application is shown.

[0011] Figure 4 A schematic diagram of a first main board and a second main board according to the second embodiment of the present application is shown.

[0012] Figure 5 A schematic diagram of a first main board and a second main board according to the third embodiment of the present application is shown.

[0013] Figure 6 A schematic diagram of a first main board and a second main board according to the fourth embodiment of the present application is shown.

[0014] Figure 7A A schematic diagram of the interconnection between a board card and a remote server according to the first embodiment of the present application is shown.

[0015] Figure 7B A schematic diagram of the interconnection between a board card and a remote server according to the second embodiment of the present application is shown.

[0016] Figure 8A A schematic diagram of the connection of a controller according to an embodiment of the present application is shown.

[0017] Figure 8B A schematic diagram of the connection of a controller according to an embodiment of the present application is shown.

[0018] Figure 9 A schematic diagram of an interconnection method according to an embodiment of the present application is shown. Detailed Embodiments

[0019] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present application. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is obvious that one or more embodiments can be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0020] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present application. The terms "including", "comprising" and the like as used herein indicate the presence of the stated features, steps, operations and / or components, but do not preclude the presence or addition of one or more other features, steps, operations or components.

[0021] All terms used herein (including technical and scientific terms) have the meanings commonly understood by one of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0022] In the case of using expressions such as "at least one of A, B, and C, etc.", generally it should be interpreted according to the meaning commonly understood by one of ordinary skill in the art (for example, "a system having at least one of A, B, and C" should include, but is not limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0023] It should be noted that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. The terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. The terms "parallel", "perpendicular", "equal" include the described situations and situations similar to the described situations, and the range of the similar situations is within the acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and approximate parallel, where the acceptable deviation range of approximate parallel can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicular and approximate perpendicular, where the acceptable deviation range of approximate perpendicular can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range of approximate equality can be, for example, that the difference between the two equal ones is less than or equal to 5% of either one. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0024] In some solutions, the hardware architecture of the server uses a large central processing unit (CPU) motherboard as the baseboard, and various devices are designed based on the capabilities of the central processing unit to achieve different functions. In this way, the device performance will be limited by the motherboard parameters. On this basis, after the server is produced, the central processing unit is tightly bound to the hardware system of the server, making it difficult for the server to be compatible with different architectures. In this way, if the motherboard is damaged, more devices need to be replaced, and more resources are consumed for replacement. Moreover, the computing performance and data processing ability of the server are limited by the central processing unit. In this case, once the server is deployed, when the processing ability is insufficient, additional servers need to be added or more advanced servers need to be replaced, also facing the problems of complex operations and increased resource consumption. In addition, the server is overly dependent on a certain series of central processing units of a single manufacturer. Once problems such as difficult supply or natural disasters occur, the server products corresponding to the central processing unit will face production difficulties.

[0025] In view of the above problems, the present invention proposes a design solution for a new server architecture, which integrates the basic circuits of the first main board on which the central processing unit is deployed onto a single physical card, enabling the first main board to be used as a flexible and scalable expansion card in various scenarios like a computing card. In this way, the central processing unit of the server system becomes a replaceable component, no longer limited to a central processing unit of a certain fixed architecture, nor to a certain manufacturer and system.

[0026] Figure 1 A schematic diagram of a board card according to the first embodiment of the present application is shown.

[0027] As Figure 1 shown, the board card of this embodiment at least includes a first main board B1 and a second main board B2. It should be understood that the board card of the embodiment of the present application may also include other main boards electrically connected to at least one of the first main board B1 and the second main board B2, and the present application does not limit this.

[0028] The first main board B1 may include a central processing unit 110. The central processing unit 110 is the core component of the server, responsible for processing computing tasks and running programs. For example, the first main board B1 may also include other devices, and the central processing unit 110 may be electrically connected to other devices on the first main board B1 and interconnected with other devices to complete tasks. For example, the central processing unit 110 of the first main board B1 may belong to the X86 architecture (The X86 architecture), and the embodiment of the present application is not limited thereto. The central processing unit 110 of the first main board B1 may also belong to a non-X86 architecture, such as the Microprocessor without Interlocked Pipeline Stages (MIPS) architecture, Alpha architecture, Advanced RISC Machine (ARM) architecture, or RISC-V architecture, etc. In addition, the central processing unit 110 may support multiple memory module slots to expand the memory.

[0029] The first main board B1 may further include a memory 130 electrically connected to the central processing unit 110. The memory 130 may be disposed on the above-mentioned memory module slot. The memory 130 may serve as the memory of the central processing unit 110 to store programs and data. The central processing unit 110 may perform read operations or write operations on the memory 130 to write data to the memory 130 or read data from the memory 130. The operating system of the central processing unit 110 may be deployed on the memory 130 to support the normal operation of the central processing unit 110. Thus, the central processing unit 110 may execute tasks based on the operating system deployed on the memory 130, such as computing tasks and the like. The memory 130 may be an M.2 solid-state drive (SSD) that supports the M.2 protocol. However, it should be understood that the embodiments of the present application are not limited thereto. In other embodiments of the present application, hard drives that support other protocols may also be used. In addition, the memory 130 may also store other data, such as the results of computing tasks and the like.

[0030] The first main board B1 may further include a management controller 120 electrically connected to the central processing unit 110. For example, the management controller 120 may be a Baseboard Management Controller (BMC). The management controller 120 may send task instructions to the central processing unit 110 to enable the central processing unit 110 to execute various tasks based on the task instructions, such as computing tasks and the like. In addition, the management controller 120 may also collect information such as the log information of the central processing unit 110 to monitor the working state of the central processing unit 110, etc., and the present application does not make any limitations thereto. Similarly to the foregoing description, the management controller 120 may be adapted to the X86 architecture. For example, it may send instruction sets in this architecture to the central processing unit 110 to enable the central processing unit 110 to execute tasks. And, the embodiments of the present application are not limited thereto. The central processing of the first main board B1 may also belong to a non-X86 architecture, such as the MIPS architecture, Alpha architecture, ARM, or RISC-V architecture, etc.

[0031] The first main board B1 may further include a main board interface 140 electrically connected to the central processing unit 110. The first main board B1 may be electrically connected to the second main board B2 through the main board interface 140, so as to realize the interconnection of the devices on the first main board B1 and the devices on the second main board B2. However, it should be understood that the embodiments of the present application are not limited thereto. In other embodiments of the present application, the first main board B1 may also be provided with an interface electrically connected to other external devices, and the present application does not make any limitations thereto.

[0032] The second main board B2 may include a first switching interface 221. For example, the first switching interface 221 may support the Peripheral Component Interconnect Express (PCIE) protocol. When the first main board B1 is disposed on the second main board B2, the main board interface 140 of the first main board B1 may be electrically connected to the first switching interface 221 of the second main board B2, thereby realizing the electrical connection between the first main board B1 and the second main board B2. For example, the first switching interface 221 of the second main board B2 may be provided in the form of a slot. The main board interface 140 of the first main board B1 may be designed in the form of a gold finger. In this way, by inserting the main board interface 140 of the first main board B1 into the first switching interface 221 of the second main board B2, the electrical connection can be realized in a plugging manner, so that the first main board B1 can be fixed on the second main board B2. However, it should be understood that the embodiments of the present application are not limited thereto, and the main board interface 140 of the first main board B1 may also be connected to the first switching interface 221 of the second main board B2 in other ways, which will not be elaborated herein.

[0033] The second main board B2 may further include a switching unit 210. For example, the switching unit 210 may be a PCIE Switch unit or the like. The switching unit 210 may be electrically connected to the first switching interface 221 and may be interconnected with the central processing unit 110 via the first switching interface 221 of the second main board B2 and the main board interface 140 of the first main board B1. The number of the switching units 210 of the second main board B2 in the present application may be one or more, and the present application does not limit this.

[0034] The second main board B2 may further include a controller 230. For example, the controller 230 may be a programmable controller 230, specifically a Complex Programmable Logic Device (CPLD) or the like. The controller 230 may also be electrically connected to the first switching interface 221 of the second main board B2, so that when the first main board B1 is disposed on the second main board B2, it is interconnected with the central processing unit 110 via the first switching interface 221 of the second main board B2 and the main board interface 140 of the first main board B1. Based on this, when the first main board B1 is disposed on the second main board B2 (for example, plugged into the first switching interface 221 of the second main board B2 in a plugging manner), the first main board B1 can be electrically connected to the second main board B2 and thus interconnected with the second main board B2. In one embodiment, the controller 230 may also be connected to the switching unit 210, and the present application does not limit this.

[0035] Based on this, by separately integrating the central processing unit 110, the motherboard interface 140 electrically connected to the central processing unit 110, the management controller 120, and the memory 130 on which the operating system of the central processing unit 110 is deployed on the first motherboard B1, a minimum system supporting the central processing unit 110 is formed. And the electrically connected first switching interface 221, switching unit 210, and controller 230 are integrated on the second motherboard B2. In this way, when the first motherboard B1 is disposed on the second motherboard B2, the first motherboard B1 can be electrically connected to the second motherboard B2 via the first switching interface 221 and the motherboard interface 140, and thus can be used as a server architecture. On this basis, the present application decouples the complete server architecture into the first motherboard B1 and the second motherboard B2, and can realize the replacement of the first motherboard B1. In this case, the first motherboards B1 of different architectures can be electrically connected to the second motherboard B2, thereby realizing the compatibility of the second motherboard B2 with the first motherboards B1 of different architectures, that is, the compatibility of the server architecture with the central processing units 110 of different architectures, so that the server can be adapted to central processing units of different architectures.

[0036] Figure 2 FIG. shows a schematic diagram of the first motherboard B1 according to an embodiment of the present application.

[0037] As Figure 2 shown, the first motherboard B1 of this embodiment may include a central processing unit 110, a management controller 120, a memory 130, a motherboard interface 140, a first expansion interface, a data interface, and a power supply. It should be noted that, for the sake of clear illustration Figure 2 of the central processing unit 110, management controller 120, memory 130, power supply, and each interface in, the connection lines of the central processing unit 110, management controller 120, memory 130, power supply, and each interface are not shown. In addition to the central processing unit 110 being electrically connected to the central processing unit 110, management controller 120, memory 130, and motherboard interface 140 described above, the central processing unit 110 may also be electrically connected to the data interface and the first expansion interface provided on the first motherboard B1. In the present application, the first expansion interface may support protocols such as the multi-channel input / output (MCIO) protocol. Similarly, the second expansion interface and the third expansion interface described later may also support the MCIO protocol for PCIE expansion or CXL (Compute Express Link) expansion, which will not be elaborated later.

[0038] The data interface can be, but is not limited to, an RJ45 interface, a Universal Serial Bus (USB) interface, a High Definition Multimedia Interface (HDMI) interface, etc. The data interface can be one or multiple, and this application does not make any limitations in this regard. The data interface can be used to connect external devices. For example, the RJ45 interface can be used to connect devices such as remote servers. The USB interface can connect USB external devices, such as a mouse and a keyboard. The HDMI interface can connect devices such as a display. In this way, the central processing unit 110 on the first main board B1 can be independently interconnected with external devices via the data interface on the first main board B1. As an independent board card, the first main board B1 can be interconnected with other devices independently of the second main board B2, reducing the dependence between the first main board B1 and the second main board B2, so that the second main board B2 can be adapted to central processing units 110 with different architectures. Based on this, in a typical blade server design, the design architecture of the present invention is still applicable. The power module interface design and the interface design of each external expansion device can be designed according to the general connector interface definition, so the peripherals in the server architecture in the related art can be universal. In this way, even if the first main board B1 is replaced, it does not affect the expansion function and device compatibility of the server.

[0039] The first expansion interface can be, but is not limited to, a multi-channel input / output interface (Mini Cool Edge I / O, MCIO), etc. The first expansion interface can be one or multiple, and this application does not make any limitations in this regard. For example, the first expansion interface can be electrically connected to the expansion memory 130 to expand the memory of the central processing unit 110. Specifically, the central processing unit 110 can write data into the expansion memory 130 via the first expansion interface, or read the stored data from the expansion memory 130. For example, the expansion memory 130 can be a memory 130 such as a hard disk, specifically, a hard disk provided on the hard disk backplane. Here, the data format of the hard disk needs to be updated due to the different software architectures of the central processing unit 110. Therefore, it is necessary to try to select a data format that can be compatible with different systems to avoid the hard disk compatibility problem caused by replacing the first main board B1, such as the File Allocation Table 32 (FAT32) data format and the Extended File Allocation Table file system (exFAT) data format. In addition, only the first main board B1 that belongs to the same architecture as the original first main board B1 can be replaced. In this way, the compatible replacement of the first main board B1 can also be achieved, and the hard disk data on the second main board B2 will not change due to the replacement of the first main board B1, and the system can still continue to run.

[0040] In addition, the first main board B1 may further include a power supply, which can supply power to the central processing unit 110, the management controller 120, the memory 130, the power supply, and each interface on the first main board B1. In this way, the first main board B1 can work independently based on its own power supply. It should be noted that Figure 2 the interfaces shown in Figure 2 are only for illustration. In addition to

[0041] the implementation manners shown, other types and quantities of interfaces may be set, or the positions of the interfaces may be adaptively adjusted. The present application does not limit this. Figure 2 Continuing to refer to

[0042] Figure 3 , the management controller 120 is adapted to the architecture of the central processing unit 110. For example, when the architecture of the central processing unit 110 belongs to the X86 architecture, the management controller 120 should also be adapted to the central processing unit 110 of the X86 architecture; when the architecture of the central processing unit 110 belongs to the MIPS architecture, the management controller 120 should also be adapted to the central processing unit 110 of the MIPS architecture; when the architecture of the central processing unit 110 belongs to the Alpha architecture, the management controller 120 should also be adapted to the central processing unit 110 of the Alpha architecture; when the architecture of the central processing unit 110 belongs to the ARM architecture, the management controller 120 should also be adapted to the central processing unit 110 of the ARM architecture; when the architecture of the central processing unit 110 belongs to the RISC-V architecture, the management controller 120 should also be adapted to the central processing unit 110 of the RISC-V architecture, and so on. Specifically, the management controller 120 can send instructions to the central processing unit 110 through the instruction set under this architecture, so that the central processing unit 110 can execute tasks and so on. In this way, by setting the management controller 120 on the first board that can be adapted to the architecture of the central processing unit 110, the management controller 120 can be replaced simultaneously when the first board is replaced, avoiding the problem that the management controller 120 on the server motherboard is not adapted to the central processing unit 110 due to only replacing the central processing unit 110, reducing the dependence of the second main board B2 on the central processing unit 110, and thus enabling the second main board B2 to be adapted to central processing units 110 of different architectures.

[0043] As Figure 3 shown, the second main board B2 of this embodiment may include a switching unit 210, a first switching interface 221, a second switching interface 222, a clock unit, and a controller 230. Supplementary note that in Figure 3In this case, only one first switching interface 221 and one second switching interface 222 are shown, which is not used to limit the solution of this application. In other embodiments of this application, the number of the first switching interface 221 and the second switching interface 222 can also be other numbers. For example, the second switching interface 222 can support the PCIE protocol. For example, the clock signal frequency of the clock unit can be 100 MHz, and it is not limited thereto. The number of pins of the first switching interface 221 and the second switching interface 222 can be 16, and it is not limited thereto.

[0044] The first port of the switching unit 210 can be electrically connected to the first switching interface 221, and the second port can be electrically connected to the second switching interface 222, so that the data of the first switching interface 221 and the second switching interface 222 can be exchanged. For example, the first port can be used as the upstream port (Root Complex, RC) of the switching unit 210 and be electrically connected to the first switching interface 221. The first switching interface 221 is electrically connected to the first main board B1 and receives data from the central processing unit 110 of the first main board B1. Then, the switching unit 210 can send the data received via the first switching interface 221 to the second switching interface 222 via the second port serving as the downstream port (End Point, EP). For example, the second switching interface 222 can be electrically connected to a device serving as a downstream device, such as a computing card or a communication card and other devices. For example, the computing card can be a Graphics Processing Unit (GPU) or a Data Processing Unit. The communication card can be a Network Interface Card (NIC). On this basis, the main board interface 140 of the first main board B1 and the first switching interface 221 of the second main board B2 are electrically connected, so that the central processing unit 110 of the first main board B1 with different architectures can be interconnected with the computing card or the communication card via the main board interface 140, the first switching interface 221, the switching unit 210, and the second switching interface 222, thereby realizing the functions of the server and realizing the server's compatibility with the central processing unit 110 of different architectures.

[0045] Moreover, the embodiments of the present application are not limited thereto. In other embodiments of the present application, the second switching interface 222 may also be electrically connected to devices such as a disk redundancy card. For example, the second switching interface 222 may be in the form of a slot. In this way, the gold finger interface of a card-type device such as a computing card or a communication card can be plugged into the second switching interface 222 and electrically connected to the second switching interface 222, so as to be electrically connected to the second main board B2. In this way, by using the switching unit 210 to electrically connect the first switching interface 221 and the second switching interface 222, when the first switching interface 221 is electrically connected to the main board interface 140, the central processing unit 110 electrically connected to the first switching interface 221 and the devices electrically connected to the second switching interface 222 can be interconnected. In this way, even if the first main board B1 of a different architecture is replaced, the central processing unit 110 of the replaced different first main board B1 and the devices at the second switching interface 222 can still be interconnected through the switching unit 210, reducing the dependence of the second main board B2 on the central processing unit 110, so that the second main board B2 can be adapted to different architectures of the first main board B1. In addition, the central processing unit 110 of the first main board B1 can also send a reset signal to the device via the main board interface 140, the first switching interface 221, the switching unit 210, and the second switching interface 222 to control the reset of the device as a downstream device.

[0046] Further, the first switching interface 221 and the second switching interface 222 are of the same type of interface, and each has a different identifier to distinguish them from each other in appearance. For example, in addition to the same communication protocol, the first switching interface 221 and the second switching interface 222 may also have the same size, depth, etc. However, in the case where the first switching interface 221 and the second switching interface 222 are similar in appearance, different identifiers can be designed on the surfaces of the first switching interface 221 and the second switching interface 222 for distinction, so as to facilitate identifying which of the switching interfaces provided on the second main board B2 is the first switching interface 221 for connecting an upstream device such as the first main board B1, and which is the second switching interface 222 for connecting a downstream device such as a computing card, a communication card, or a disk redundancy card. In this way, it helps to accurately electrically connect the main board interface 140 of the replaced first main board B1 to the first switching interface 221 of the second main board B2, so as to facilitate the server to support central processing units 110 of different architectures. For example, the identifier may be a color. Specifically, the first switching interface 221 may be blue, and the second switching interface 222 may be black. However, it should be understood that the embodiments of the present application are not limited thereto, and the first switching interface 221 and the second switching interface 222 may also be other colors, or other identifiers may be designed for distinction.

[0047] For example, both the first switching interface 221 and the second switching interface 222 are Peripheral Component Interconnect Express (PCIe) interfaces. For the PCIe protocol, the switching unit 210 does not need to identify which of the above architectures the architecture via the first switching interface 221 belongs to, and can directly transmit the signals of the PCIe interface, thereby realizing the interconnection between the second main board B2 and the first main board B1 of different architectures. In this way, the second main board B2 is made compatible with the first main board B1 of different architectures.

[0048] In addition, a clock unit may also be included on the second main board B2. The clock unit may be electrically connected to the first switching interface 221, the second switching interface 222, and the switching unit 210, and provide clock signals to the first switching interface 221, the second switching interface 222, and the switching unit 210. In this way, when the first main board B1 is disposed on the second main board B2, the first main board B1 may receive a clock signal from the clock unit via the first switching interface 221 and use the received clock signal as its own operating clock. Similarly, when a downstream device is disposed on the second main board B2, the downstream device may receive a clock signal from the clock unit via the second switching interface 222 and use the received clock signal as its own operating clock. Similarly, the switching unit 210 may use the received clock signal as its own operating clock. In this way, the first main board B1, the switching unit 210, and the downstream device may operate based on a common clock, thereby improving the quality of data interconnected between the first main board B1 and the downstream device.

[0049] On this basis, by integrating the central processing unit 110 onto the first main board B1 independent of the second main board B2, when the first main board B1 is disposed on the second main board B2, the central processing unit 110 may receive a clock signal homologous to the downstream device and the switching unit 210 from the clock unit of the second main board B2 as its own operating clock, thereby forming a complete server architecture with the entire backplane. When the first main board B1 is separated from the second main board B2, since the clock unit of the second main board B2 can still provide clock signals for the downstream device and the switching unit 210 connected to the second switching interface 222, and the central processing unit 110 may independently perform data interaction with the devices electrically connected to the first main board B1 based on its own clock signal. In this way, regardless of whether the first main board B1 is disposed on the second main board B2, the central processing unit 110, the switching unit 210, and the downstream device can all operate normally based on their respective clocks, realizing the decoupling of the central processing unit 110 from the second main board B2, reducing the dependence of the second main board B2 on the central processing unit 110, and thus enabling the second main board B2 to adapt to the first main board B1 of different architectures.

[0050] The controller 230 can be electrically connected to the first switching interface 221, and based on the signal received from the first switching interface 221, determine whether the motherboard interface 140 of the first switching interface 221 and the first motherboard B1 is electrically connected. And the controller 230 can also be electrically connected to the clock unit, and for different connection conditions of the first switching interface 221 and the motherboard interface 140 of the first motherboard B1, the controller 230 can control the clock unit to perform different operations.

[0051] For example, when the controller 230 detects that the motherboard interface 140 is electrically connected to the first switching interface 221, it can control the clock unit to send a clock signal to the first switching interface 221; or when it detects that the motherboard interface 140 is disconnected from the first switching interface 221, it controls the clock unit to stop sending a clock signal to the first switching interface 221. When the controller 230 detects that the first motherboard B1 is electrically connected to the first switching interface 221, it controls the clock unit to send a first clock signal to the first switching interface 221. In this case, even if the first motherboard B1 is replaced, the controller 230 can still control the clock unit to provide a clock signal to the replaced first motherboard B1. In this way, the dependence of the second motherboard B2 on the central processing unit 110 is reduced. And when the controller 230 detects that the motherboard interface 140 of the first motherboard B1 is disconnected from the first switching interface 221, it controls the clock unit to stop sending a clock signal to the first switching interface 221, reducing resource consumption. Furthermore, after the first motherboard B1 is replaced, it can still control the clock unit to send a clock signal to the replaced first motherboard B1. That is, even if the first motherboard B1 is replaced, the second motherboard B2 can still work properly. In this way, even though the present application reduces the dependence of the second motherboard B2 on the central processing unit 110, it does not affect the function of the server jointly formed by the first motherboard B1 and the second motherboard B2, achieving the compatibility of the second motherboard B2 with the first motherboard B1 of different architectures. Among them, the replaced first motherboard B1 can belong to a different architecture from the original motherboard.

[0052] In addition, when the controller 230 detects that the motherboard interface 140 is electrically connected to the first switching interface 221, it can collect the log information of the devices managed by the controller 230 and send the log information to the first switching interface 221. For example, the log information of the devices managed by the controller 230 can be the log information of the devices electrically connected to the controller 230. For example Figure 2The log information of the fan and the signal lamp shown in []. Or, when the controller 230 detects that the motherboard interface 140 is disconnected from the first switch interface 221, it can stop sending log information to the first switch interface 221. In this way, when it is detected that the motherboard interface 140 is disconnected from the first switch interface 221, stopping sending log information to the first switch interface 221 reduces resource consumption. Furthermore, after replacing the first motherboard B1 and after the motherboard interface 140 of the replaced first motherboard B1 is electrically connected to the first switch interface 221, the switching unit 210 can still send the first clock signal to the replaced first motherboard B1. That is, even if the first motherboard B1 is replaced, the second motherboard B2 can still work properly. In this way, even if the present application reduces the dependence of the second motherboard B2 on the central processing unit 110, it does not affect the function of the server jointly formed by the first motherboard B1 and the second motherboard B2, and realizes the compatibility of the second motherboard B2 with the first motherboard B1 of different architectures.

[0053] In an embodiment of the present application, when the central processing unit 110 receives the log information, it can send a control signal to the controller 230 based on the log information, so that the performance or working state of the controller 230 components is controlled under the control of this control signal. For example, the performance of the fan can be controlled. Specifically, it can refer to controlling the rotation speed of the fan. In addition, the working state of the signal lamp can also be controlled, such as constant on, flashing, etc. In this way, when it is detected that the motherboard interface 140 of the first motherboard B1 is electrically connected to the first switch interface 221, the controller 230 collects the log information of the components it manages and sends the log information to the central processing unit 110, so that the central processing unit 110 can send a control signal to the programmable controller 230, and further make the controller 230 control the working state of the controller 230 components. In this way, even if the present application reduces the dependence of the second motherboard B2 on the central processing unit 110, it does not affect the function of the server jointly formed by the first motherboard B1 and the second motherboard B2, and realizes the compatibility of the second motherboard B2 with the first motherboard B1 of different architectures.

[0054] In another embodiment of the present application, when the central processing unit 110 receives the log information, it sends the log information to the management controller 120. The management controller 120 can send a control signal to the controller 230 based on the log information via the central processing unit 110 and the motherboard interface 140, so that the performance or working state of the controller 230 components is controlled under the control of this control signal. Or, the management controller 120 can directly send a control signal to the controller 230 based on the log information via the motherboard interface 140, so that the performance or working state of the controller 230 components is controlled under the control of this control signal.

[0055] In another embodiment of the present application, a performance monitoring device may also be provided on the second main board B2. The performance monitoring device can be used to detect the heat dissipation performance of the fan. For example, the performance monitoring device can be a temperature sensor. The controller 230 can be electrically connected to the performance monitoring device to collect the log information of the performance monitoring device for managing the performance monitoring device. For example, the controller 230 can send the log information of the performance monitoring device to the central processing unit 110. The log information may include the temperature detected by the temperature sensor. Then, under the control of the control signal, the controller 230 can control the fan speed to increase or decrease to reasonably dissipate heat from the entire second main board B2.

[0056] In yet another embodiment of the present application, when the controller 230 sends log information to the central processing unit 110 and the original central processing unit 110 is replaced, the main board interface 140 of the first main board B1 can be disconnected from the first switching interface 221. When it is detected that the main board interface 140 of the first main board B1 is disconnected from the switching unit 210, the controller 230 can also stop sending log information to the first switching interface 221. Then, when it is detected that the first switching interface 221 is reconnected to another first main board B1, the log information can be sent to the other central processing unit 110 of the other first main board B1 via the first switching interface 221 and the main board interface 140, and under the control of the other central processing unit 110 of the other first main board B1, the performance or working state of the controller 230 can be adjusted. For example, the log information may include temperature information. The central processing unit 110 or the management controller 120 can generate a control signal based on the temperature information through a pre-set program and send the control signal to the controller 230 via the main board interface 140 of the first main board B1 and the first switching interface 221. In this way, when the processor board is replaced with another processor board, the controller 230 can still send log information to the first switching interface 221. Furthermore, even though the present application reduces the dependence of the second main board B2 on the central processing unit 110, it does not affect the function of the server jointly formed by the first main board B1 and the second main board B2, realizing the compatibility of the second main board B2 with the first main board B1 of different architectures.

[0057] In addition to the fan for global cooling, an additional cooling unit may be provided on the second main board B2. In some solutions, since the central processing unit 110 is not decoupled from the server, generally, a fan is used to cool the server globally to reduce the temperature of the central processing unit 110. However, in the embodiments of the present application, since the central processing unit 110 is integrated on the first main board B1, a cooling unit specifically for the central processing unit 110 may also be provided on the first main board B1. Hereinafter, the cooling unit of the first main board B1 is referred to as the first cooling unit, and the cooling unit of the second main board B2 is referred to as the second cooling unit. On this basis, the first main board B1 further includes a first cooling unit for cooling the central processing unit 110, and the second main board B2 further includes a second cooling unit provided at the second switching interface 222. The first cooling unit and the second cooling unit are of the same type of cooling unit.

[0058] For example, the second cooling unit provided at the second switching interface 222 may be a liquid cooling unit for cooling the computing card, etc. Correspondingly, the first cooling unit may also be a cooling unit for cooling the card-shaped structure. Thus, since the central processing unit 110 is provided on the first main board B1, a cooling unit of the same type as the computing card can be used to cool the central processing unit 110, avoiding the difficulty of cooling the central processing unit 110 by devices such as the fan for global cooling deployed on the second main board B2 after the first main board B1 is detached from the second main board B2, which helps to replace the second main board B2 and thus reduces the dependence between the first main board B1 and the second main board B2. Furthermore, even though the present application reduces the dependence of the second main board B2 on the central processing unit 110, it does not affect the function of the server jointly formed by the first main board B1 and the second main board B2, realizing the compatibility of the second main board B2 with the first main board B1 of different architectures.

[0059] However, it should be understood that the embodiments of the present application are not limited thereto. In other embodiments of the present application, the first cooling unit and the second cooling unit may also be respectively disposed at the first switching interface 221 and the second switching interface 222 of the second main board B2. Since the central processing unit 110 is inserted into a specific position in the form of a card, the same heat dissipation design solution as that of the high-density computing card can be adopted. On this basis, the heat dissipation design of the central processing unit 110 and the computing card adopts the same magnitude design. For the case where the two first main boards B1 are respectively plugged into the two first switching interfaces 221 of the second main board B2, the first cooling unit can be designed as a double-slot passive heat dissipation design, and the overall heat dissipation of the machine is controlled by the fan group of the whole machine through the controller 230 for heat dissipation. On this basis, an active heat dissipation design with a maximum support for a three-slot mode can be designed according to the actual central processing unit 110. In this way, when the main board interface 140 of the first main board B1 is plugged into the first switching interface 221 and / or devices such as a computing card are plugged into the second switching interface 222, the central processing unit 110 and / or devices such as a computing card of the first main board B1 are cooled specifically.

[0060] Figure 4 FIG. shows a schematic diagram of a first main board B1 and a second main board B2 according to a second embodiment of the present application.

[0061] As Figure 4 shown, in addition to the central processing unit 110, the management controller 120, the memory 130, and the main board interface 140 described above, the first main board B1 of this embodiment may also be provided with a first expansion interface. The second main board B2 may include a switching unit 210, two first switching interfaces 221, a plurality of second switching interfaces 222, a controller 230, a control interface, and a power module. It should be understood that the number of the two first switching interfaces 221 is only for illustration and is not used to limit the solution of the present application. For example, the second expansion interface may be an MCIOX16 connector interface to distinguish it from the PCIE interfaces of other MCIOX8 interfaces on the second main board B2, and it can support up to 24 pairs of high-speed serial transceiver pairs at most. It should be understood that this is only an example. For example, the control interface may support the MCIO protocol.

[0062] In this embodiment, the motherboard interface 140 of the first motherboard B1 can be electrically connected to a first switching interface 221 of the second motherboard B2. The first expansion interface of the first motherboard B1 can be electrically connected to the second expansion interface of the second motherboard B2, and the second expansion interface of the second motherboard B2 can also be electrically connected to another first switching interface 221. The other first switching interface 221 is not connected to the motherboard interface 140 of the first motherboard B1, but is electrically connected to a memory expansion card. The memory expansion card can be used to expand the memory of the central processing unit 110. In this way, the central processing unit 110 can write data to the memory expansion card via the first expansion interface, the second expansion interface, and the first switching interface 221, or read data from the memory expansion card via the first expansion interface, the second expansion interface, and the first switching interface 221. On this basis, by providing multiple first switching interfaces 221 on the second motherboard B2, when the first motherboard B1 is disposed on the second motherboard B2, the memory of the central processing unit 110 can be expanded by providing an expansion memory card on the other first switching interface 221 that is not electrically connected to the motherboard interface 140 of the first motherboard B1, avoiding the problem of insufficient memory of the central processing unit 110 caused by integrating the central processing unit 110 on the card-type first motherboard B1 independent of the second motherboard B2, so that the central processing unit 110 can ensure sufficient memory even when independent of the second motherboard B2. In this way, even if the present application reduces the dependence of the second motherboard B2 on the central processing unit 110, it does not affect the function of the server jointly formed by the first motherboard B1 and the second motherboard B2, realizing the compatibility of the second motherboard B2 with the first motherboard B1 of different architectures.

[0063] However, it should be understood that the embodiments of the present application are not limited thereto. In other embodiments of the present application, the switching unit 210 can also be electrically connected to the first switching interface 221. In this way, the computing card or communication card connected to the second switching interface 222 can write data to the memory expansion card or read data from the memory expansion card via the second switching interface 222, the switching unit 210, and the above-mentioned other first switching interface 221, etc.

[0064] Further, the distance between the second expansion interface and the first switching interface 221 is determined based on a multiple of the size of the first switching interface 221. In this way, by setting the distance between the second expansion interface and the first switching interface 221 to a multiple of the size of the first switching interface 221 (for example, three times the width), it is possible to ensure a certain distance position between the first switching interface 221 and the second expansion interface, so that a heat dissipation unit can be arranged at the first switching interface 221 to facilitate the heat dissipation of the central processing unit 110. And the embodiments of the present application are not limited to this. In other embodiments of the present application, the distance between multiple first switching interfaces 221 can also be set to a multiple of the size of the first switching interface 221 (for example, three times the width), so that a heat dissipation unit can be arranged at the first switching interface 221 to facilitate heat dissipation.

[0065] The control interface of the second main board B2 can be electrically connected to devices such as a host computer. In this way, the host computer can send a control signal to the switching unit 210 via this control interface to control the operation of the switching unit 210. Alternatively, the host computer can also send control signals to the sending controller 230, the first switching interface 221, and the second switching interface 222 via this control interface and the switching unit 210 to control the operation of the controller 230, the first main board B1 electrically connected to the first switching interface 221, and the downlink device electrically connected to the second switching interface 222, etc.

[0066] In addition, the power module of the second main board B2 can be used to supply power to the switching unit 210, two first switching interfaces 221, multiple second switching interfaces 222, the controller 230, the control interface, and other devices on the second main board B2.

[0067] Figure 5 A schematic diagram of the first main board B1 and the second main board B2 according to the third embodiment of the present application is shown.

[0068] As Figure 5 shown, the first main board B1 can include a central processing unit 110, a management controller 120, a memory 130, a main board interface 140, and a first expansion interface. The second main board B2 can include a switching unit 210, a first switching interface 221, multiple second switching interfaces 222, and a third expansion interface.

[0069] The first expansion interface can be electrically connected to the expansion memory 130, specifically, it can be electrically connected to the expansion memory 130 via a hard disk expansion interface. This expansion memory 130 can also be used to expand the memory of the central processing unit 110. In this way, the first main board B1 can write data to the expansion memory 130 via the first expansion interface and the hard disk expansion interface to store the data, and can also read the data from the expansion memory 130 via the first expansion interface and the hard disk expansion interface and process it.

[0070] For example, the extended memory 130 may be a hard disk. The extended memory 130 may be disposed on the hard disk backplane or on the second main board B2. When the extended memory 130 is disposed on the hard disk backplane, the hard disk expansion interface may be electrically connected to the third expansion interface of the second main board B2. In this way, a computing card or a communication card electrically connected to the second switching interface 222 may write data to the extended memory 130 via the second switching interface 222, the switching unit 210, the third expansion interface, and the hard disk expansion interface to store the data, or may read the data from the extended memory 130 and process it. In this way, by disposing the extended memory 130 on the second main board B2, it can be ensured that the central processing unit 110 has sufficient memory to operate normally. In this way, even if the present application reduces the dependence of the second main board B2 on the central processing unit 110, it does not affect the function of the server jointly formed by the first main board B1 and the second main board B2, and realizes the compatibility of the second main board B2 with the first main board B1 of different architectures.

[0071] Figure 6 FIG. shows a schematic diagram of the first main board B1 and the second main board B2 according to the fourth embodiment of the present application.

[0072] As Figure 6 shown, the second main board B2 may include a switching unit 210, a plurality of first switching interfaces 221, a plurality of second switching interfaces 222, and a third expansion interface. Among them, the third expansion interface is electrically connected to the hard disk expansion interface of the hard disk backplane to be electrically connected to the hard disk of the hard disk backplane.

[0073] The respective main board interfaces 140 of the plurality of first main boards B1 may be electrically connected to the plurality of first switching interfaces 221 respectively. Among them, the plurality of first main boards B1 may adopt a full-height and full-length PCIE card design. Based on this, in an embodiment of the present application, the central processing units 110 of the plurality of first main boards B1 all expand their own memory through the extended memory 130. For example, the central processing unit 110 of any one of the plurality of first main boards B1 may write stored data to a device via the main board interface 140 of any one of the first main boards B1, the corresponding first switching interface 221 (i.e., the first switching interface 221 connected to the main board interface 140 of this first main board B1), the switching unit 210, and the second switching interface 222. The central processing unit 110 of another first main board B1 other than any one of the plurality of first main boards B1 reads the stored data of the device via the main board interface 140 of another first main board B1, the corresponding first switching interface 221 (i.e., the first switching interface 221 connected to the main board interface 140 of this first main board B1), the switching unit 210, and the second switching interface 222.

[0074] In another embodiment of the present application, multiple first switching interfaces 221 are electrically connected to each other. For example, multiple first switching interfaces 221 can be electrically connected to each other via a Universal Peripheral Interface (UPI) or an Advanced eXtensible Interface (AXI). In this way, the central processors 110 of multiple first main boards B1 provided on the second main board B2 can call each other's memory resources to process data, so as to achieve mutual redundancy of the dual main boards and provide higher core computing capabilities. In the case of a failure of the central processor 110, it can be quickly replaced. For example, the central processor 110 of any one of the multiple first main boards B1 can receive calculation data from a calculation card or a communication card via the main board interface 140 of any one of the first main boards B1, the corresponding first switching interface 221, the switching unit 210, and the second switching interface 222. Then, the calculation data can be written into the memory of the central processor 110 of other first main boards B1 among the multiple first main boards B1, or the calculation data can also be read from the memory of the central processor 110 of other first main boards B1.

[0075] In this way, by providing multiple first main boards B1 on the second main board B2, and the central processor 110 of any one of the multiple first main boards B1 can call the memory of other central processors 110 to store the calculation data from the communication card or the calculation card. In this way, since the dependence of the server backplane on the central processor 110 is reduced, multiple first main boards B1 can be flexibly deployed on the second main board B2, enabling multiple independent first main boards B1 to be cascaded and process the calculation data. On this basis, the architectures of the multiple first main boards B1 can be different. In this way, even though the present application reduces the dependence of the second main board B2 on the central processor 110, it does not affect the function of the server jointly formed by the multiple first main boards B1 with different architectures and the second main board B2, realizing the compatibility of the second main board B2 with the first main boards B1 of different architectures.

[0076] In another embodiment of the present application, the central processor 110 of any one of the multiple first main boards B1 writes the stored data into the extended memory 130 via the first expansion interface of any one of the first main boards B1 described above. The central processor 110 of another first main board B1 among the multiple first main boards B1 other than any one of the first main boards B1 reads the stored data in the extended memory 130 via the first expansion interface of the other first main board B1.

[0077] In addition, in Figure 6In the second main board B2 shown, it may further include a second expansion interface and an independent second switching interface 222 electrically connected to the second expansion interface. Similar to the foregoing description, the second expansion interface in this embodiment can also be used to connect the first expansion interfaces of two first main boards B1 for PCIE expansion or CXL memory expansion.

[0078] Figure 7A The schematic diagram of the interconnection between the board card and the remote server according to the first embodiment of the present application is shown.

[0079] As Figure 7A shown, in this embodiment, when two first main boards B1 are arranged on the second main board B2, the two first main boards B1 can be electrically connected to the switching unit 210. In this way, the central processors of the two first main boards B1 can be interconnected with the computing card or the disk array card via the switching unit 210, or the two first main boards B1 can be interconnected with the remote server via the switching unit 210 and the communication card. Each of the two first main boards B1 is used as an independent single-way server, and two independent computing systems are realized by controlling the configuration of the switching unit 210, independently processing different data from the network, and classifying and processing the network data as needed. The dual-way first main board B1 non-interconnected redundancy mode can achieve fast system backup and online replacement of the first main board B1.

[0080] In addition, the first expansion interfaces of the two first main boards B1 can be electrically connected to the hard disks arranged on the second main board B2. In this way, the two first main boards B1 can each expand their own memory through the hard disks they are connected to.

[0081] Figure 7B The schematic diagram of the interconnection between the board card and the remote server according to the second embodiment of the present application is shown.

[0082] As Figure 7B shown, in this embodiment, when two first main boards B1 are arranged on the second main board B2, the two first main boards B1 can be electrically connected to the switching unit 210. The central processors of the two first main boards B1 can be interconnected with the computing card or the disk array card via the switching unit 210, or the two first main boards B1 can be interconnected with the remote server via the switching unit 210 and the communication card. Different from the foregoing description, the two first main boards B1 can be electrically connected to each other and interconnected on the second main board B2. The central processors of the two first main boards B1 can be interconnected through an interconnection serial bus. Using a unified serial interface, the data format adopts a general serial protocol, which requires the support of the central processor of the first main board B1.

[0083] In this way, the central processors of the two first main boards B1 can call each other's memory resources to process data interacting with the computing card, disk array card, or remote server. In this case, the present application supports the interconnection of two first main boards B1 with the same specifications, realizing an application system of a dual-path interconnection server and providing higher kernel computing power. At the same time, it supports one of the two first main boards B1 combined with the second main board B2 as the main server, and the other first main board B1 serves as a redundant backup synchronously. Since all peripherals and important stored data can be shared through the switching unit 210, a quick replacement can be achieved when any one of the first main boards B1 fails, reducing the risk of service interruption. It should be understood that this is not used to limit the embodiments of the present application. The embodiments of the present application can support up to 7 first main boards B1 to be set on the second main board B2 at the same time. Considering the implementation of sufficient storage and external expansion interfaces in a server, the dual-path server has greater advantages in this architecture. When only a calculator that needs to provide computing power is externally connected to a storage server, the multi-path design and development of more first main boards B1 can be carried out in accordance with the present invention.

[0084] The components on the first main board B1 and the second main board B2 have been described in detail above. On this basis, in the present application, the controller 230 can control multiple components on the second main board B2, and the clock unit can provide clock signals to multiple components on the second main board B2.

[0085] The following is combined with Figure 8A and Figure 8B for illustration. Figure 8A The connection schematic diagram of the controller 230 according to an embodiment of the present application is shown.

[0086] As Figure 8AAs shown, the controller 230 can be electrically connected to the switching unit 210, the first switching interface 221, the second switching interface 222, the control interface, the control module of the power supply module, the clock unit, and the third expansion interface. For example, the controller 230 can provide control signals to at least one of the switching unit 210, the first switching interface 221, the second switching interface 222, the control interface, the control module of the power supply module, the clock unit, and the third expansion interface, and collect log information from at least one of the switching unit 210, the first switching interface 221, the second switching interface 222, the control interface, the control module of the power supply module, the clock unit, and the third expansion interface. Among them, the control module of the power supply module is used to control the voltage of the power supply to increase or decrease. It should be understood that the embodiments of the present application are not limited thereto, and the controller 230 can also be electrically connected to other devices on the second main board B2, which is not limited herein. For example, the controller 230 can be interconnected with the first switching interface 221 and the second switching interface 222 through a bus such as the System Management Bus (SMBus) of the PCIE bus. The controller 230 can be interconnected with the switching unit 210 through buses such as the I / O (Input / Output) bus, the I2C bus, and the General-purpose input / output (GPIO) bus. The controller 230 can also be interconnected with the second expansion interface, the third expansion interface, and the clock unit through buses such as the I2C bus. The controller 230 can also be interconnected with the control module of the power supply module through buses such as the I / O bus.

[0087] On this basis, the controller 230 controls low-speed I / O signals such as system management, power circuit monitoring, fan control, and signal lights of the second main board B2. The power circuit design of all uses the power design of the general server system. Since almost all variable peripherals rely on the power supply of the main board, the main power design of the server is still the same as the general design. For the power design of the first main board B1, we also use a general connector power supply that complies with the PCIe specification for design. There are sufficient PCIE device external power supply interfaces designed on the second main board B2 to meet the power requirements of the PCIE devices.

[0088] Figure 8B The connection schematic diagram of the controller 230 according to the embodiment of the present application is shown.

[0089] As Figure 8BAs shown, the clock unit can be electrically connected to the switching unit 210, the first switching interface 221, the second switching interface 222, the control interface, the second expansion interface, and the third expansion interface, and provide a clock signal of the same source to the switching unit 210, the first switching interface 221, the second switching interface 222, the control interface, the second expansion interface, and the third expansion interface. For example, the clock unit can include, but is not limited to, a crystal oscillator, a clock buffer, and the like. It should be understood that the embodiments of the present application are not limited thereto. The clock unit can also be electrically connected to other devices on the second main board B2 and provide a clock signal to other devices or receive a control signal for controlling the clock unit from other devices, which is not limited in the present application.

[0090] In addition, when multiple first main boards B1 are provided on the second main board B2, the central processing unit of any one of the multiple main boards can also provide a clock signal to each device of the second main board B2. In the case of a failure of the central processing unit of this main board, the central processing unit of another first main board B1 can be switched to provide a clock signal. Alternatively, the controller 230 of the second main board B2 can control the clock unit to provide a clock signal.

[0091] This application is mainly applied inside servers such as desktop, rack-mounted, and blade servers, and is designed to enable the same server to support architectures of different central processing units, so that the central processing unit can be replaced. The present invention can also be applied to the architecture design of other similar services or computer hosts, and is not limited to single-way servers and two-way servers. Even the architecture can be used to support the design of supercomputing servers with more paths. And this design can also be applied to switches, which will not be elaborated here.

[0092] Figure 9 The figure shows a schematic diagram of an interconnection method according to an embodiment of the present application.

[0093] As Figure 9 shown, the interconnection method of this embodiment includes operation S910.

[0094] In operation S910, the central processing unit of the first main board is interconnected with the switching unit and the controller of the second main board via the main board interface of the first main board and the first switching interface of the second main board based on the memory and the management controller of the first main board.

[0095] In the embodiments of the present application, the interconnection method is similar to the operations performed by the board cards described above.

[0096] For example, the interconnection with the switching unit of the second main board includes: the central processing unit of the first main board is interconnected with the device via the main board interface, the first switching interface, the switching unit, and the second switching interface.

[0097] For example, the above interconnection method further includes: central processors of multiple first mainboards are interconnected with each other via mainboard interfaces and multiple first switching interfaces of the multiple first mainboards respectively.

[0098] For example, the above interconnection method further includes: the central processor of the first mainboard sends a reset signal to the device via the mainboard interface, the first switching interface, the switching unit, and the second switching interface to reset the device.

[0099] For example, the above interconnection method further includes: the central processor of any one of the multiple first mainboards writes stored data into the device via the mainboard interface of any one of the first mainboards, the corresponding first switching interface, the switching unit, and the second switching interface; the central processor of another first mainboard other than any one of the multiple first mainboards reads the stored data of the device via the mainboard interface of another first mainboard, the corresponding first switching interface, the switching unit, and the second switching interface.

[0100] For example, the above interconnection method further includes: the central processor of any one of the multiple first mainboards writes stored data into the extended memory via the first expansion interface of any one of the first mainboards; the central processor of another first mainboard other than any one of the multiple first mainboards reads the stored data in the extended memory via the first expansion interface of another first mainboard.

[0101] For example, the second mainboard further includes a clock unit; the clock unit is electrically connected to the controller and the first switching interface; the above interconnection method further includes: when the controller detects that the first switching interface is electrically connected to the mainboard interface, the controller controls the clock unit to provide a clock signal to the first switching interface.

[0102] For example, the above interconnection method further includes: when the controller detects that the first switching interface is disconnected from the mainboard interface, the controller controls the clock unit to stop providing a clock signal to the first switching interface.

[0103] For example, the above interconnection method further includes: when the controller detects that the first switching interface is electrically connected to the mainboard interface, the controller sends log information to the central processor via the first switching interface and the mainboard interface.

[0104] For example, the above interconnection method further includes: when the central processor receives the log information, based on the log information, the central processor sends a control signal to the controller to control the working state of the device managed by the controller.

[0105] For example, the above interconnection method further includes: when the mainboard interface is electrically connected to the first switching interface, the central processor uses the clock signal received via the mainboard interface and the first switching interface as its own working clock.

[0106] For example, the above interconnection method further includes: when the main board interface is disconnected from the first switching interface, the central processing unit uses the clock signal generated by itself as its own working clock.

[0107] It should be understood that the method of the embodiments of the present application is not limited thereto. For specific reference, please refer to the foregoing description and details will not be repeated herein.

[0108] Those skilled in the art can understand that the features described in the various embodiments of the present application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present application. In particular, without departing from the spirit and teachings of the present application, the features described in the various embodiments of the present application can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present application.

[0109] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and not for limiting the scope of the present application. Although the embodiments have been described separately above, this does not mean that the measures in the various embodiments cannot be used in combination advantageously. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present application.

Claims

1. A board card, characterized in that, At least including a first main board and a second main board; The first main board includes a central processing unit, a main board interface, a memory, and a management controller that are electrically connected to the central processing unit. The memory is used to deploy the operating system of the central processing unit; And The second main board includes a first switching interface, a switching unit, and a controller that are electrically connected; Wherein, the first main board is disposed on the second main board and is electrically connected to the second main board through the first switching interface and the main board interface.

2. The board card according to claim 1, characterized in that, The second main board further includes a second switching interface; The first port of the switching unit is electrically connected to the first switching interface, and the second port is electrically connected to the second switching interface.

3. The board card according to claim 2, wherein The first main board further includes a first cooling unit for cooling the central processing unit; the second main board further includes a second cooling unit disposed at the second switching interface; the first cooling unit and the second cooling unit are of the same type of cooling unit.

4. The board card according to claim 2, wherein The first switching interface and the second switching interface are of the same type of interface.

5. The board card according to claim 2, characterized in that, The first switching interface and the second switching interface are both Peripheral Component Interconnect Express (PCIe) interfaces.

6. The board card according to claim 2, wherein The second switching interface is used to set a computing card or a communication card.

7. The board card according to claim 2, characterized in that, There are multiple first switching interfaces; there are multiple first main boards, and each of the multiple first main boards includes a main board interface; the main board interfaces of each of the multiple first main boards are respectively electrically connected to the multiple first switching interfaces.

8. The board card according to claim 7, characterized in that, The multiple first switching interfaces are electrically connected to each other.

9. The board card according to any one of claims 1 to 8, characterized in that The management controller adapts to the architecture of the central processing unit.

10. The board card according to any one of claims 1 to 8, characterized in that, The second main board further includes a clock unit, and the clock unit is electrically connected to the controller, the first switching interface, and the switching unit.

11. The board card according to any one of claims 1 to 8, characterized in that, The second main board further includes an extended memory; the first main board further includes a first expansion interface, the central processing unit is electrically connected to the first expansion interface, and the first expansion interface is electrically connected to the extended memory.

12. The board card according to any one of claims 1 to 8, characterized in that, There are multiple first switching interfaces; the second main board further includes a second expansion interface; the second expansion interface is electrically connected to the first expansion interface of the first main board and another first switching interface among the multiple first switching interfaces that is not connected to the main board interface, and the another first switching interface is electrically connected to a memory expansion card.

13. The board card according to claim 12, characterized in that, The interval between the second expansion interface and the first switching interface is determined based on a multiple of the size of the first switching interface.

14. The board card according to any one of claims 1 to 8, characterized in that, The first main board further includes a data interface, and the data interface is used to connect an external device.

15. An interconnection method performed by a board card as described in any one of claims 1 to 14, including: The central processing unit of the first main board, based on the memory and management controller of the first main board, is interconnected with the switching unit and the controller of the second main board via the main board interface of the first main board and the first switching interface of the second main board.

16. The interconnection method according to claim 15, characterized in that, The second switching interface of the switching unit is electrically connected to the devices of the second main board; Wherein, the interconnection with the switching unit of the second main board includes: The central processing unit of the first main board is interconnected with the devices via the main board interface, the first switching interface, the switching unit, and the second switching interface.

17. The interconnection method according to claim 16, characterized in that The interconnection method further includes: The central processing unit of the first main board sends a reset signal to the device via the main board interface, the first switching interface, the switching unit, and the second switching interface to control the reset of the device.

18. The interconnection method according to claim 16, characterized in that, There are multiple first switching interfaces; there are multiple first main boards, and each of the multiple first main boards includes a main board interface; the main board interfaces of each of the multiple first main boards are respectively electrically connected to the multiple first switching interfaces; The multiple first switching interfaces are electrically connected to each other; The interconnection method further includes: The central processing units of each of the multiple first main boards are interconnected with each other via the main board interfaces of each of the multiple first main boards and the multiple first switching interfaces.

19. The interconnection method according to claim 18, wherein The interconnection method further includes: The central processing unit of any one of the multiple first main boards writes stored data into the device via the main board interface of the any one first main board, the corresponding first switching interface, the switching unit, and the second switching interface; The central processing unit of another first main board other than the any one first main board among the multiple first main boards reads the stored data of the device via the main board interface of the another first main board, the corresponding first switching interface, the switching unit, and the second switching interface.

20. The interconnection method according to any one of claims 15 to 19, characterized in that The second main board further includes an extended memory; the first main board further includes a first extended interface, the central processing unit is electrically connected to the first extended interface, and the first extended interface is electrically connected to the extended memory; The interconnection method further includes: The central processing unit of any one of the multiple first main boards writes stored data into the extended memory via the first extended interface of the any one first main board; The central processing unit of another first main board other than the any one first main board among the multiple first main boards reads the stored data in the extended memory via the first extended interface of the another first main board.

21. The interconnection method according to any one of claims 15 to 19, characterized in that, The second main board further includes a clock unit; the clock unit is electrically connected to the controller and the first switching interface; The interconnection method further includes: When the controller detects that the first switching interface is electrically connected to the main board interface, the controller controls the clock unit to provide a clock signal to the first switching interface.

22. The interconnection method according to claim 21, wherein The interconnection method further includes: When the controller detects that the first switching interface is disconnected from the main board interface, the controller controls the clock unit to stop providing the clock signal to the first switching interface.

23. The interconnection method according to claim 21, characterized in that, The interconnection method further includes: When the controller detects that the first switching interface is electrically connected to the main board interface, the controller sends log information to the central processing unit via the first switching interface and the main board interface.

24. The interconnection method according to claim 23, wherein The interconnection method further includes: When the central processing unit receives the log information, based on the log information, the central processing unit sends a control signal to the controller to control the working state of the device managed by the controller.

25. The interconnection method according to claim 21, wherein The interconnection method further includes: When the motherboard interface is electrically connected to the first switching interface, the central processing unit uses the clock signal received via the motherboard interface and the first switching interface as its own operating clock.

26. The interconnection method according to claim 25, wherein The interconnection method further includes: When the motherboard interface is disconnected from the first switching interface, the central processing unit uses the clock signal generated by itself as its own operating clock.

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