FPGA comprehensive tool trigger synchronous control signal extraction method, storage medium and electronic equipment

Abstract

The invention provides an FPGA comprehensive tool trigger synchronous control signal extraction method, which comprises the following steps: traversing each trigger unit in a trigger unit set, searching whether an input D end signal of the trigger unit exists in a multiplexer output mapping set, if so, executing synchronous signal extraction, and if not, executing synchronous signal extraction. If not, quitting the processing of the current trigger unit; the synchronous signal extraction comprises the steps of acquiring a multiplexer unit a of which an output Y-end signal is an input D-end signal of the trigger in the multiplexer output mapping set, and acquiring an input A-end signal, an input B-end signal and an input S-end signal of the multiplexer unit a; setting a synchronization signal value and assigning a synchronization signal polarity value according to whether the input A-end signal and the input B-end signal are constant signals or not; and according to the synchronization signal value and the synchronization signal polarity value, a trigger synchronization zero clearing signal or a synchronization number setting signal is generated. The invention further provides a storage medium and electronic equipment.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA synthesis tools, and particularly relates to a method for extracting trigger synchronization control signals of an FPGA synthesis tool, a storage medium, and an electronic device. Background Art

[0002] Logic synthesis is an important step in the FPGA EDA software design process. It converts the Verilog / VHDL circuit file at the behavioral level or register transfer level (RTL) input by the user into a netlist file composed of basic logic units of the FPGA, such as look-up tables (Luts) and flip-flops (FFs). FPGA logic synthesis includes two stages: synthesis and mapping. Synthesis is to convert the circuit file at the behavioral level or RTL into a logic netlist composed of gate circuits; mapping is to map the logic netlist composed of gate circuits into a netlist file composed of basic logic units of the FPGA.

[0003] Area optimization (i.e., reducing resource occupancy) is one of the core objectives of logic synthesis, which directly affects the routing success rate and timing performance of FPGA designs. Among them, as a basic logic unit of the FPGA, the extraction and optimization of the synchronization control signal of the flip-flop (FF) are crucial for reducing the overall logic resource occupancy. Synchronization control signals include synchronous clear signals and synchronous set signals, etc. They are the basic control signals for realizing the functions of flip-flops. Extracting control signals such as synchronous clear signals and synchronous set signals for flip-flop units is not only a necessary process for correctly realizing the functions of flip-flops, but also helps to reduce the overhead of other logic resources.

[0004] The existing FPGA EDA synthesis tools have the problem of insufficient optimization of trigger control signals, resulting in area waste, which in turn affects the routing success rate and timing performance of FPGA designs. Summary of the Invention

[0005] The present invention provides a method for extracting trigger synchronization control signals of an FPGA synthesis tool, which can realize the extraction and optimization of trigger synchronization control signals.

[0006] The present invention also provides a storage medium and an electronic device for implementing the steps in a method for extracting trigger synchronization control signals of an FPGA synthesis tool.

[0007] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one or some or all of the above purposes or other purposes, a method for extracting a trigger synchronization control signal of an FPGA synthesis tool provided by a technical solution of the present invention traverses logic units in a circuit netlist, stores the logic units of the trigger type into a trigger unit set; stores the mapping relationship between the signal of each output Y terminal of the logic unit of the multiplexer type and the corresponding logic unit into a multiplexer output mapping set; traverses each trigger unit in the trigger unit set, and checks whether there is a signal of the input D terminal of the trigger unit in the multiplexer output mapping set. If it exists, perform synchronization signal extraction; otherwise, exit the processing of the current trigger unit and process the next trigger unit; the synchronization signal extraction includes obtaining a multiplexer unit a whose output Y terminal signal is the input D terminal signal of the trigger in the multiplexer output mapping set, and obtaining the input A terminal signal, the input B terminal signal, and the input S terminal signal of the multiplexer unit a; according to whether the input A terminal signal and the input B terminal signal of the multiplexer unit a are constant signals, set the synchronization signal value and assign 0 or 1 to the synchronization signal polarity value; and generate a trigger synchronous clear signal or a synchronous set signal according to the synchronization signal value and the synchronization signal polarity value.

[0009] If the input A terminal signal of the multiplexer unit a is a constant signal, the synchronization signal value is the input A terminal signal of the multiplexer unit a; if the input A terminal signal of the multiplexer unit a is not a constant signal, confirm whether the input B terminal signal of the multiplexer unit a is a constant signal. When the input B terminal signal of the multiplexer unit a is a constant signal, set the synchronization signal value to the input B terminal signal of the multiplexer unit a; if the input B terminal signal of the multiplexer unit a is not a constant signal, compare the number of right value signals of the input A terminal signal and the input B terminal signal of the multiplexer unit a, and take the signal with fewer right value signals as the synchronization signal value.

[0010] If the synchronization signal value is set to the input A terminal signal of the multiplexer unit a, set the input D terminal signal of the trigger unit to the input B terminal signal of the multiplexer unit a; if the synchronization signal value is set to the input B terminal signal of the multiplexer unit a, set the input D terminal signal of the trigger unit to the input A terminal signal of the multiplexer unit a.

[0011] If the synchronization signal value is the input A terminal signal of the multiplexer unit a, set the synchronization signal polarity value to 0; if the synchronization signal value is the input B terminal signal of the multiplexer unit a, set the synchronization signal polarity value to 1.

[0012] When the synchronization signal value is a constant 0 signal, if the synchronization polarity signal is 0, then the inverted signal of the input S terminal signal of the newly created multiplexer unit a is used as the synchronous clear signal of the flip-flop unit; if the synchronization polarity signal is 1, then the input S terminal signal of the multiplexer unit a is used as the synchronous clear signal of the flip-flop unit. When the synchronization signal value is a constant 1 signal or a non-constant signal, if the synchronization polarity signal is 0, then the inverted signal of the input S terminal signal of the newly created multiplexer unit a is used as the synchronous set signal of the flip-flop unit; if the synchronization polarity signal is 1, then the input S terminal signal of the multiplexer unit a is used as the synchronous set signal of the flip-flop unit.

[0013] When the synchronization signal value is a constant 0 signal, if the synchronization polarity signal is 0, then create a logic unit of the logic NOT type. The input signal of the logic unit of the logic NOT type is set to the input S terminal signal of the multiplexer unit a, and the output signal is the inverted signal of the input S terminal signal of the multiplexer unit a, and set the synchronous clear input terminal signal of the flip-flop unit to the inverted signal of the input S terminal signal of the multiplexer unit a; if the synchronization polarity signal is 1, then set the synchronous clear input terminal signal of the flip-flop unit to the input S terminal signal of the multiplexer unit a.

[0014] If the flip-flop unit type is DFF, then update the flip-flop unit type to DFFS; if the flip-flop unit type is DFFE, then update the flip-flop unit type to DFFSE.

[0015] When the synchronization signal value is a constant 1 signal or a non-constant signal, if the synchronization polarity signal is 0, then create a logic unit of the logic NOT type. The input signal of the logic unit of the logic NOT type is set to the input S terminal signal of the multiplexer unit a, and the output signal is the inverted signal of the input S terminal signal of the multiplexer unit a, and set the synchronous set input terminal signal of the flip-flop unit to the inverted signal of the input S terminal signal of the multiplexer unit a; if the synchronization polarity signal is 1, then set the synchronous set input terminal signal of the flip-flop unit to the input S terminal signal of the multiplexer unit a; at the same time, set the synchronous set value of the flip-flop unit to the synchronization signal value, and modify the flip-flop unit type according to the synchronization signal value.

[0016] If the synchronous set value of the trigger unit is the constant 1 and the type of the trigger unit is DFFE, then update the type of the trigger unit to DFFSE; if the synchronous set value of the trigger unit is a non-constant signal and the type of the trigger unit is DFF, then update the type of the trigger unit to DFFSV; if the synchronous set value of the trigger unit is a non-constant signal and the type of the trigger unit is DFFE, then update the type of the trigger unit to DFFSVE.

[0017] The method for counting the number of right-value signals of the input A terminal signal of the multiplexer unit a includes: Step 1: Search in the multiplexer output mapping set whether the input A terminal signal of the multiplexer unit a exists. If it exists, search in the multiplexer output mapping set for the multiplexer unit b whose output signal is the input A terminal signal of the multiplexer unit a, and obtain the input A terminal signal and the input B terminal signal of the multiplexer unit b; if it does not exist, insert the input A terminal signal of the multiplexer unit a into the right-value signal set; Step 2: Search in the multiplexer output mapping set whether the input A terminal signal of the multiplexer unit b exists. If it exists, recursively perform the right-value signal counting process on the input A terminal signal of the multiplexer unit b. If it does not exist, insert the input A terminal signal of the multiplexer unit b into the right-value signal set; Step 3: Search in the multiplexer output mapping set whether the input B terminal signal of the multiplexer unit b exists. If it exists, recursively perform the right-value signal counting process on the input B terminal signal of the multiplexer unit b. If it does not exist, insert the input B terminal signal of the multiplexer unit b into the right-value signal set; the number of signals in the right-value signal set is the number of right-value signals of the input A terminal signal of the multiplexer unit a.

[0018] The method for counting the number of right-value signals of the input B terminal signal of the multiplexer unit a is the same as the method for counting the number of right-value signals of the input A terminal signal of the multiplexer unit a.

[0019] A storage medium provided by another technical solution of the present invention stores program code in the storage medium, and the program code is called by a processor to execute the above-mentioned method for extracting the trigger synchronization control signal of an FPGA synthesis tool.

[0020] An electronic device provided by another technical solution of the present invention includes one or more processors; a memory; one or more application programs, wherein the one or more application programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more application programs are configured to execute the above-mentioned method for extracting the trigger synchronization control signal of an FPGA synthesis tool.

[0021] Compared with the prior art, the beneficial effects of the present invention mainly include that the synchronous control signal extraction method of the present invention can automatically generate synchronous control signals (such as synchronous reset or synchronous set) for the sequential logic unit, which can effectively simplify the combinational logic complexity at the input end of the flip-flop. By extracting the synchronous signal, the present invention can reduce the area overhead of the synthesized circuit and improve the timing convergence at the same time, which conforms to the optimization strategy of the EDA tool for the synchronous design paradigm.

[0022] To make the above and other objects, features and advantages of the present invention more obvious and understandable, the following specific preferred embodiments are given and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0024] Figure 1 It is a schematic flowchart of the method for extracting the synchronous control signal of the flip-flop in the FPGA synthesis tool of the present invention.

[0025] Figure 2 It is a flowchart of the method for counting the number of right value signals of a signal in the present invention.

[0026] Figure 3 It is a flowchart of the method for generating a synchronous clear signal for the flip-flop unit in the present invention.

[0027] Figure 4 It is a flowchart of the method for generating a synchronous preset signal for the flip-flop unit in the present invention. Detailed Description of the Specific Embodiments

[0028] Regarding the foregoing and other technical contents, features and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0029] Embodiment 1 Embodiment 1 provides a method for extracting a trigger synchronization control signal of an FPGA synthesis tool. Traverse the logic units in the circuit netlist, and store the logic units of the trigger type into the trigger unit set; store the mapping relationship between each output Y-terminal signal of the logic unit of the multiplexer type and the corresponding logic unit into the multiplexer output mapping set; traverse each trigger unit in the trigger unit set, and check whether there is an input D-terminal signal of the trigger unit in the multiplexer output mapping set. If it exists, perform synchronization signal extraction; otherwise, exit the processing of the current trigger unit and process the next trigger unit; the synchronization signal extraction includes obtaining a multiplexer unit a whose output Y-terminal signal is the input D-terminal signal of the trigger in the multiplexer output mapping set, and obtaining the input A-terminal signal, input B-terminal signal, and input S-terminal signal of the multiplexer unit a; set the synchronization signal value and assign 0 or 1 to the synchronization signal polarity value according to whether the input A-terminal signal and input B-terminal signal of the multiplexer unit a are constant signals; and generate a trigger synchronization clear signal or a synchronization set signal according to the synchronization signal value and the synchronization signal polarity value.

[0030] The following explains in detail a method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to the present invention with reference to the accompanying drawings.

[0031] See Figure 1 , a method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to the present invention includes the following steps: Step S1: Traverse each logic unit c in the circuit netlist, store the logic units of the trigger type into the trigger unit set dffs, and store the mapping relationship between each output Y-terminal signal of the logic unit of the multiplexer type and the corresponding logic unit into the multiplexer output mapping set y2mux; Step S2: Traverse each trigger unit d in the set dffs, and check whether the input D-terminal signal sig_d of the trigger unit d exists in y2mux. If it exists, perform Step S3; otherwise, exit the processing of the current trigger unit d and enter the processing of the next trigger unit; Step S3: Obtain a multiplexer Mux unit a whose output Y-terminal signal is sig_d in y2mux, and obtain the input A-terminal signal sig_a, input B-terminal signal sig_b, and input S-terminal signal sig_s of the Mux unit a; Step S4: If sig_a is a constant signal, set the input D-terminal signal of the trigger unit d to sig_b, the synchronization signal value sr_v = sig_a, and the synchronization signal polarity p = 0, and transfer to Step S7; otherwise, transfer to Step S5; Step S5: If sig_b is a constant signal, set the signal at the input D terminal of the flip-flop unit d to sig_a, the synchronous signal value sr_v = sig_b, the synchronous signal polarity p = 1, and go to Step S7; otherwise, go to Step S6; Step S6: Count the number of right-value signals n1 and n2 of sig_a and sig_b. If n1 < n2, set the signal at the input D terminal of the flip-flop unit d to sig_b, the synchronous signal value sr_v = sig_a, and the synchronous signal polarity p = 0; otherwise, set the signal at the input D terminal of the flip-flop unit d to sig_a, the synchronous signal value sr_v = sig_b, and the synchronous signal polarity p = 1; Step S7: If the synchronous signal value sr_v is a constant 0 signal, generate a synchronous clear signal sclr for the synchronous clear port of the flip-flop unit d according to the value of the synchronous signal polarity p. If the polarity p = 0, create an inverted signal sr of a signal sig_s, and sr is used as the synchronous clear signal sclr of the flip-flop unit d; otherwise, the signal sig_s is used as the synchronous clear signal sclr of the flip-flop unit d; Step S8: If the synchronous signal value sr_v is a constant 1 signal or a non-constant signal, generate a synchronous load signal sload for the synchronous load port of the flip-flop unit d according to the value of the synchronous signal polarity p. If the polarity p = 0, create an inverted signal sr of a signal sig_s, and sr is used as the synchronous load signal sload of the flip-flop unit d; otherwise, the signal sig_s is used as the synchronous load signal sload of the flip-flop unit d. Set the synchronous load value of the flip-flop unit d = the synchronous signal value sr_v. Finally, modify the type of the flip-flop unit d according to the synchronous signal value sr_v.

[0032] The method for counting the number of right-value signals n1 and n2 of sig_a and sig_b in Step S6 is as follows Figure 2 , where Figure 2 gives the method for counting the right-value signals of a signal (sig_a). The method for counting the number of right-value signals of the signal sig_b is the same as that of sig_a, and specifically includes the following steps: Step S6-1: Check if sig_a exists in y2mux. If it exists, go to Step S6-2; otherwise, insert sig_a into the right-value signal set out and go to Step S6-5; Step S6-2: Obtain the multiplexer Mux unit b with the output signal sig_a in y2mux, and obtain the input A-terminal signal sig_a1 and the input B-terminal signal sig_b1 of the Mux unit b; Step S6-3: Check if sig_a1 exists in y2mux. If it exists, recursively execute Step S6-1 on sig_a1. Recursively executing Step S6-1 on sig_a1 means checking if sig_a1 exists in y2mux. If it exists, then execute Step S6-2; otherwise, insert sig_a1 into the set out of right-value signals and transfer to Step S6-5; Step S6-4: Check if sig_b1 exists in y2mux. If it exists, recursively execute Step S6-1 on sig_b1 (the recursive operation steps are the same as those for recursively executing Step S6-1 on sig_a1 in Step S6-3); otherwise, insert sig_b1 into the set out of right-value signals and transfer to Step S6-5; Step S6-5: The number of right-value signals of sig_a is equal to the number of signals in the set out.

[0033] In Step S7, if the synchronous signal value sr_v is a constant 0 signal, then generate a synchronous clear signal sclr for the synchronous clear port of the flip-flop unit d according to the value of the synchronous signal polarity p. See Figure 3 , which specifically includes the following steps: S7-1: If the polarity p = 0, then execute Step S7-2; otherwise, execute Step S7-4; S7-2: Create a new logic unit c1 of the logical NOT type (inverter logic unit). The input signal of c1 = sig_s, and the output signal is the inverted signal sr of signal sig_s.

[0034] S7-3: Set the signal of the synchronous clear input port of the flip-flop d = signal sr.

[0035] S7-4: Set the signal of the synchronous clear input port of the flip-flop d = signal sig_s.

[0036] S7-5: If the type of the flip-flop unit d = DFF (D-type flip-flop), then update d's type = DFFS (D Flip-Flop with Synchronous Set).

[0037] S7-6: If the type of the flip-flop unit d = DFFE (D Flip-Flop with Enable), then update d's type = DFFSE (D Flip-Flop with Synchronous Set).

[0038] In step S8, if the synchronization signal value sr_v is a constant 1 signal or a non-constant signal, a synchronous set signal sload is generated for the synchronous set port of the flip-flop unit d according to the value of the synchronization signal polarity p. See Figure 4 , which specifically includes the following steps: Step S8-1: If the polarity p = 0, then execute step S8-2; otherwise, execute step S8-4.

[0039] Step S8-2: Create a new logic unit c1 of the logical NOT type (inverter logic unit), where the input signal of c1 = sig_s and the output signal is the inverted signal sr of the signal sig_s.

[0040] Step S8-3: Set the signal of the synchronous set input port of the flip-flop d = signal sr.

[0041] Step S8-4: Set the signal of the synchronous set input port of the flip-flop d = sig_s.

[0042] Step S8-5: Set the synchronous set value of the flip-flop unit d = synchronization signal value sr_v.

[0043] Step S8-6: If the synchronization signal value sr_v is a constant 1 signal and the type of the flip-flop unit d = DFF (D-type flip-flop), then update the type of d = DFFS (D-type flip-flop with synchronous set function, D Flip-Flop with Synchronous Set).

[0044] Step S8-7: If the synchronization signal value sr_v is a constant 1 signal and the type of the flip-flop unit d = DFFE (D-type flip-flop with enable), then update the type of d = DFFSE (D-type flip-flop with synchronous set function, D Flip-Flop with Synchronous Set).

[0045] Step S8-8: If the synchronization signal value sr_v is a non-constant signal and the type of the flip-flop unit d = DFF (D-type flip-flop), then update the type of d = DFFSV (D-type flip-flop with synchronous set and synchronous reset functions, D Flip-Flop with Synchronous Set and Reset).

[0046] Step S8-9: If the synchronization signal value sr_v is a non-constant signal and the type of the flip-flop unit d = DFFE (D Flip-Flop with Enable), then update the type of d = DFFSVE (D Flip-Flop with Synchronous Set, Reset, and Enable).

[0047] Embodiment 2 Embodiment 2 provides a storage medium in which program code is stored. The program code is called and executed by a processor to perform the steps in a method for extracting a trigger synchronization control signal of an FPGA synthesis tool as described in Embodiment 1.

[0048] Storing program code using a storage medium and calling and executing the program through a processor to implement the steps in the method for extracting a trigger synchronization control signal of an FPGA synthesis tool in Embodiment 1 can improve the efficiency of extracting the trigger synchronization control signal.

[0049] Embodiment 3 Embodiment 3 provides an electronic device, including one or more processors; a memory; one or more application programs, where one or more application programs are stored in the memory and configured to be executed by the one or more processors, and the one or more application programs are configured to perform the steps in a method for extracting a trigger synchronization control signal of an FPGA synthesis tool as described in Embodiment 1.

[0050] The above has introduced in detail a method for extracting a trigger synchronization control signal of an FPGA synthesis tool, a storage medium, and an electronic device provided by the present invention. Specific examples are used in this article to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for extracting a trigger synchronization control signal of an FPGA synthesis tool, characterized in that, Traverse the logic units in the circuit netlist and store the logic units of the flip-flop type into the flip-flop unit set; Store the mapping relationship between the signal of each output Y terminal of the logic unit of the multiplexer type and the corresponding logic unit into the multiplexer output mapping set; Traverse each flip-flop unit in the flip-flop unit set, and check whether there is a signal at the input D terminal of the flip-flop unit in the multiplexer output mapping set. If it exists, perform synchronous signal extraction; otherwise, exit the processing of the current flip-flop unit and process the next flip-flop unit; The synchronous signal extraction includes obtaining a multiplexer unit a whose output Y terminal signal is the input D terminal signal of the flip-flop in the multiplexer output mapping set, and obtaining the input A terminal signal, input B terminal signal, and input S terminal signal of the multiplexer unit a; According to whether the input A terminal signal and input B terminal signal of the multiplexer unit a are constant signals, set the synchronous signal value and assign 0 or 1 to the synchronous signal polarity value; And generate a flip-flop synchronous clear signal or synchronous set signal according to the synchronous signal value and synchronous signal polarity value.

2. The method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to claim 1, wherein If the input A terminal signal of the multiplexer unit a is a constant signal, the synchronous signal value is the input A terminal signal of the multiplexer unit a; If the input A terminal signal of the multiplexer unit a is not a constant signal, confirm whether the input B terminal signal of the multiplexer unit a is a constant signal. When the input B terminal signal of the multiplexer unit a is a constant signal, set the synchronous signal value to the input B terminal signal of the multiplexer unit a; If the input B terminal signal of the multiplexer unit a is not a constant signal, compare the number of right value signals of the input A terminal signal and input B terminal signal of the multiplexer unit a, and take the signal with fewer right value signals as the synchronous signal value.

3. A method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to claim 2, characterized in that If the synchronous signal value is set to the input A terminal signal of the multiplexer unit a, set the input D terminal signal of the flip-flop unit to the input B terminal signal of the multiplexer unit a; if the synchronous signal value is set to the input B terminal signal of the multiplexer unit a, set the input D terminal signal of the flip-flop unit to the input A terminal signal of the multiplexer unit a.

4. A method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to claim 2, characterized in that, If the synchronous signal value is the input A terminal signal of the multiplexer unit a, set the synchronous signal polarity value to 0; if the synchronous signal value is the input B terminal signal of the multiplexer unit a, set the synchronous signal polarity value to 1.

5. A method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to claim 1, characterized in that, When the synchronous signal value is the constant 0 signal, if the synchronous polarity signal is 0, create the inverted signal of the input S terminal signal of the multiplexer unit a as the synchronous clear signal of the flip-flop unit; if the synchronous polarity signal is 1, use the input S terminal signal of the multiplexer unit a as the synchronous clear signal of the flip-flop unit; When the synchronization signal value is a constant 1 signal or a non-constant signal, if the synchronization polarity signal is 0, a negated signal of the input S terminal signal of the multiplexer unit a is newly created as the synchronous preset signal of the flip-flop unit; if the synchronization polarity signal is 1, the input S terminal signal of the multiplexer unit a is used as the synchronous preset signal of the flip-flop unit.

6. A method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to claim 5, characterized in that When the synchronization signal value is a constant 0 signal, if the synchronization polarity signal is 0, a logic unit of the logical NOT type is newly created. The input signal of the logic unit of the logical NOT type is set to the input S terminal signal of the multiplexer unit a, and the output signal is the negated signal of the input S terminal signal of the multiplexer unit a. The synchronous clear input terminal signal of the flip-flop unit is set to the negated signal of the input S terminal signal of the multiplexer unit a. If the synchronization polarity signal is 1, the synchronous clear input terminal signal of the flip-flop unit is set to the input S terminal signal of the multiplexer unit a.

7. A method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to claim 6, characterized in that, If the flip-flop unit type is DFF, update the flip-flop unit type to DFFS. If the flip-flop unit type is DFFE, update the flip-flop unit type to DFFSE.

8. A method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to claim 5, characterized in that When the synchronization signal value is a constant 1 signal or a non-constant signal, if the synchronization polarity signal is 0, a logic unit of the logical NOT type is newly created. The input signal of the logic unit of the logical NOT type is set to the input S terminal signal of the multiplexer unit a, and the output signal is the negated signal of the input S terminal signal of the multiplexer unit a. The synchronous preset input terminal signal of the flip-flop unit is set to the negated signal of the input S terminal signal of the multiplexer unit a. If the synchronization polarity signal is 1, the synchronous preset input terminal signal of the flip-flop unit is set to the input S terminal signal of the multiplexer unit a. At the same time, set the synchronous preset value of the flip-flop unit to the synchronization signal value, and modify the flip-flop unit type according to the synchronization signal value.

9. A method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to claim 8, characterized in that, If the synchronous preset value of the flip-flop unit is a constant 1 and the type of the flip-flop unit is DFFE, update the type of the flip-flop unit to DFFSE. If the synchronous preset value of the flip-flop unit is a non-constant signal and the type of the flip-flop unit is DFF, update the type of the flip-flop unit to DFFSV. The synchronous preset value of the flip-flop unit is a non-constant signal and the type of the flip-flop unit is DFFE, then update the type of the flip-flop unit to DFFSVE.

10. A method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to claim 2, characterized in that, The method for counting the number of right value signals of the input A terminal signal of the multiplexer unit a includes Step 1: Check whether the input A terminal signal of the multiplexer unit a exists in the multiplexer output mapping set. If it exists, find the multiplexer unit b whose output signal is the input A terminal signal of the multiplexer unit a in the multiplexer output mapping set, and obtain the input A terminal signal and the input B terminal signal of the multiplexer unit b. If it does not exist, insert the input A terminal signal of the multiplexer unit a into the right value signal set. Step 2: Check whether the input A - end signal of the multiplexer unit b exists in the multiplexer output mapping set. If it exists, recursively perform right - value signal statistical processing on the input A - end signal of the multiplexer unit b. If it does not exist, insert the input A - end signal of the multiplexer unit b into the right - value signal set; Step 3: Check whether the input B - end signal of the multiplexer unit b exists in the multiplexer output mapping set. If it exists, recursively perform right - value signal statistical processing on the input B - end signal of the multiplexer unit b. If it does not exist, insert the input B - end signal of the multiplexer unit b into the right - value signal set; The number of signals in the right - value signal set is the number of right - value signals of the input A - end signal of the multiplexer unit a.

11. A method for extracting a trigger synchronization control signal of an FPGA synthesis tool according to claim 10, characterized in that, The method for counting the number of right - value signals of the input B - end signal of the multiplexer unit a is the same as the method for counting the number of right - value signals of the input A - end signal of the multiplexer unit a.

12. A storage medium, characterized in that, The program code is stored in a storage medium, and the program code is called by a processor to execute a method for extracting a trigger synchronization control signal of an FPGA synthesis tool as described in any one of claims 1 - 11.

13. An electronic device, characterized in that, Comprising one or more processors; A memory; One or more application programs, wherein the one or more application programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more application programs are configured to execute a method for extracting a trigger synchronization control signal of an FPGA synthesis tool as described in any one of claims 1 - 11.

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