FPGA synthesis tool trigger synchronization control signal extraction method, storage medium and electronic device

Abstract

The present invention provides a method for extracting synchronous control signals from triggers in an FPGA synthesis tool. The method traverses each trigger unit in a trigger unit set, searches the multiplexer output mapping set for the presence of the trigger unit's input D-terminal signal, and executes synchronization signal extraction if the trigger unit's input D-terminal signal exists. Otherwise, the method exits processing of the current trigger unit. The synchronization signal extraction includes obtaining a multiplexer unit a in the multiplexer output mapping set whose output Y-terminal signal is the trigger's input D-terminal signal, and obtaining the multiplexer unit a's input A-terminal signal, input B-terminal signal, and input S-terminal signal. Based on whether the input A-terminal signal and the input B-terminal signal are constant signals, the synchronization signal value is set and the synchronization signal polarity value is assigned. Furthermore, based on the synchronization signal value and the synchronization signal polarity value, a trigger synchronization clear signal or a synchronization set signal is generated. The present invention also provides a storage medium and an electronic device.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA synthesis tools, and in particular relates to a method for extracting synchronous control signals of a trigger of an FPGA synthesis tool, a storage medium and an electronic device. Background Art

[0002] Logic synthesis is a crucial step in the FPGA EDA software design process. It converts user-entered behavioral-level or register-transfer-level (RTL) Verilog / VHDL circuit files into a netlist consisting of basic FPGA logic elements, such as lookup tables (LUTs) and flip-flops (FFs). FPGA logic synthesis consists of two phases: synthesis and mapping. Synthesis converts the behavioral-level or RTL circuit file into a logic netlist consisting of gates; mapping maps the gate-based logic netlist into a netlist consisting of basic FPGA logic elements.

[0003] Area optimization (i.e., reducing resource usage) is one of the core goals of logic synthesis, directly impacting the routing success rate and timing performance of FPGA designs. For flip-flops (FFs), the fundamental logic units of FPGAs, extracting and optimizing their synchronous control signals is crucial for reducing overall logic resource usage. Synchronous control signals, such as synchronous clear and synchronous set, are essential for implementing flip-flop functionality. Extracting these signals for flip-flops is not only essential for correctly implementing flip-flops but also helps reduce the overhead of other logic resources.

[0004] The existing FPGA EDA synthesis tools have the problem of insufficient optimization of trigger control signals, resulting in area waste, which in turn affects the routing rate and timing performance of FPGA design. Summary of the Invention

[0005] The present invention provides a method for extracting synchronous control signals of triggers of FPGA synthesis tools, which can realize the extraction and optimization of synchronous control signals of triggers.

[0006] The present invention also provides a storage medium and electronic equipment for implementing the steps in a method for extracting synchronous control signals of a trigger of an FPGA synthesis tool.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one, part, or all of the above purposes or other purposes, a technical solution of the present invention provides a method for extracting synchronous control signals from triggers in an FPGA synthesis tool. The method traverses the logic units in a circuit netlist and stores logic units of the trigger type in a trigger unit set; stores the mapping relationship between each output Y-end signal of a logic unit of the multiplexer type and the corresponding logic unit in a multiplexer output mapping set; traverses each trigger unit in the trigger unit set, searches the multiplexer output mapping set for whether there is an input D-end signal of the trigger unit, and performs synchronization signal extraction if so. Otherwise, exit the processing of the current trigger unit and process the next trigger unit; the synchronization signal extraction includes obtaining the multiplexer unit a whose output Y-end signal is the trigger input D-end signal in the multiplexer output mapping set, and obtaining the input A-end signal, input B-end signal and input S-end signal of the multiplexer unit a; according to whether the input A-end signal and input B-end signal of the multiplexer unit a are constant signals, setting the synchronization signal value and assigning 0 or 1 to the synchronization signal polarity value; and generating a trigger synchronization clear signal or a synchronization set signal according to the synchronization signal value and the synchronization signal polarity value.

[0009] If the input A-end signal of the multiplexer unit a is a constant signal, the synchronization signal value is the input A-end signal of the multiplexer unit a; if the input A-end signal of the multiplexer unit a is not a constant signal, confirm whether the input B-end signal of the multiplexer unit a is a constant signal, and when the input B-end signal of the multiplexer unit a is a constant signal, set the synchronization signal value to the input B-end signal of the multiplexer unit a; if the input B-end signal of the multiplexer unit a is not a constant signal, compare the number of right-value signals of the input A-end signal and the input B-end signal of the multiplexer unit a, and take the signal with the smaller right-value signal as the synchronization signal value.

[0010] If the synchronization signal value is set to the input A-end signal of the multiplexer unit a, the input D-end signal of the trigger unit is set to the input B-end signal of the multiplexer unit a; if the synchronization signal value is set to the input B-end signal of the multiplexer unit a, the input D-end signal of the trigger unit is set to the input A-end signal of the multiplexer unit a.

[0011] If the synchronization signal value is the input A-end signal of the multiplexer unit a, the synchronization signal polarity value is set to 0; if the synchronization signal value is the input B-end signal of the multiplexer unit a, the synchronization signal polarity value is set to 1.

[0012] When the synchronization signal value is a constant 0 signal, if the synchronization signal polarity value is 0, then the inverted signal of the input S-end signal of the new multiplexer unit a is created as the synchronization clear signal of the trigger unit; if the synchronization signal polarity value is 1, then the input S-end signal of the multiplexer unit a is used as the synchronization clear signal of the trigger unit; when the synchronization signal value is a constant 1 signal or a non-constant signal, if the synchronization signal polarity value is 0, then the inverted signal of the input S-end signal of the new multiplexer unit a is created as the synchronization set signal of the trigger unit; if the synchronization signal polarity value is 1, then the input S-end signal of the multiplexer unit a is used as the synchronization set signal of the trigger unit.

[0013] When the synchronization signal value is a constant 0 signal, if the synchronization signal polarity value is 0, a new logic unit of a logical NOT type is created, the input signal of the logic NOT type logic unit is set to the input S-end signal of the multiplexer unit a, the output signal is the inverted signal of the input S-end signal of the multiplexer unit a, and the synchronization clear input end signal of the trigger unit is set to the inverted signal of the input S-end signal of the multiplexer unit a; if the synchronization signal polarity value is 1, the synchronization clear input end signal of the trigger unit is set to the input S-end signal of the multiplexer unit a.

[0014] If the trigger cell type is DFF, update the trigger cell type to DFFS; if the trigger cell type is DFFE, update the trigger cell type to DFFSE.

[0015] When the synchronization signal value is a constant 1 signal or a non-constant signal, if the synchronization signal polarity value is 0, a new logic unit of a logical NOT type is created, the input signal of the logic NOT type logic unit is set to the input S-end signal of the multiplexer unit a, the output signal is the inverted signal of the input S-end signal of the multiplexer unit a, and the synchronization set input end signal of the trigger unit is set to the inverted signal of the input S-end signal of the multiplexer unit a; if the synchronization signal polarity value is 1, the synchronization set input end signal of the trigger unit is set to the input S-end signal of the multiplexer unit a; at the same time, the synchronization set value of the trigger unit is set to the synchronization signal value, and the trigger unit type is modified according to the synchronization signal value.

[0016] If the synchronous set value of the trigger unit is a constant 1, and the type of the trigger unit is DFFE, the type of the trigger unit is updated to DFFSE; if the synchronous set value of the trigger unit is a non-constant signal, and the trigger unit type is DFF, the type of the trigger unit is updated to DFFSV; if the synchronous set value of the trigger unit is a non-constant signal, and the trigger unit type is DFFE, the type of the trigger unit is updated to DFFSVE.

[0017] The method for counting the number of right-value signals of the input A-end signal of the multiplexer unit a comprises the following steps: step 1: searching within the multiplexer output mapping set whether the input A-end signal of the multiplexer unit a exists; if so, searching within the multiplexer output mapping set for a multiplexer unit b whose output signal is the input A-end signal of the multiplexer unit a, and obtaining the input A-end signal and input B-end signal of the multiplexer unit b; if not, inserting the input A-end signal of the multiplexer unit a into the right-value signal set; step 2: searching within the multiplexer output mapping set for the input A-end signal of the multiplexer unit b Does it exist? If so, recursively perform right-value signal statistical processing on the input A-end signal of the multiplexer unit b; if not, insert the input A-end signal of the multiplexer unit b into the right-value signal set; Step three: search in the multiplexer output mapping set whether the input B-end signal of the multiplexer unit b exists; if so, recursively perform right-value signal statistical processing on the input B-end signal of the multiplexer unit b; if not, insert the input B-end signal of the multiplexer unit b into the right-value signal set; the number of signals in the right-value signal set is the number of right-value signals of the input A-end signal of the multiplexer unit a.

[0018] The method for counting the number of right-hand side signals of the input B-end signal of the multiplexer unit a is the same as the method for counting the number of right-hand side signals of the input A-end signal of the multiplexer unit a.

[0019] Another technical solution of the present invention provides a storage medium in which program code is stored. The program code is called by a processor to execute the above-mentioned method for extracting synchronous control signals from triggers of FPGA synthesis tools.

[0020] Another technical solution of the present invention provides an electronic device, comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the FPGA synthesis tool trigger synchronous control signal extraction method described above.

[0021] Compared with existing technologies, the present invention's significant advantages include automated generation of synchronous control signals (such as synchronous reset or synchronous set) for sequential logic units, effectively simplifying the complexity of the combinational logic at the trigger inputs. By extracting synchronous signals, the present invention reduces the area overhead of the synthesized circuit while improving timing closure, conforming to the optimization strategies of EDA tools for the synchronous design paradigm.

[0022] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 The present invention is a flowchart of a method for extracting synchronous control signals from a trigger of an FPGA synthesis tool.

[0025] Figure 2 The present invention is a flowchart of a method for counting the number of right-hand side signals of a signal.

[0026] Figure 3 The present invention is a flow chart of a method for generating a synchronous clear signal for a trigger unit.

[0027] Figure 4 The present invention is a flow chart of a method for generating a synchronous set signal for a trigger unit. DETAILED DESCRIPTION

[0028] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0029] Example 1

[0030] Embodiment 1 provides a method for extracting synchronous control signals of triggers of an FPGA synthesis tool. The method traverses logic units in a circuit netlist and stores logic units of a trigger type into a trigger unit set. The method stores a mapping relationship between each output Y-end signal of a logic unit of a multiplexer type and a corresponding logic unit into a multiplexer output mapping set. The method traverses each trigger unit in the trigger unit set and searches the multiplexer output mapping set for whether an input D-end signal of the trigger unit exists. If so, the method performs synchronization signal extraction. Otherwise, the method exits the processing of the current trigger unit and processes the next trigger unit. The method comprises obtaining a multiplexer unit a whose output Y-end signal is the trigger input D-end signal from the multiplexer output mapping set, and obtaining an input A-end signal, an input B-end signal, and an input S-end signal of the multiplexer unit a. The method sets a synchronization signal value and assigns a synchronization signal polarity value of 0 or 1 based on whether the input A-end signal and the input B-end signal of the multiplexer unit a are constant signals. The method further generates a trigger synchronization clear signal or a synchronization set signal based on the synchronization signal value and the synchronization signal polarity value.

[0031] The following is a detailed explanation of a method for extracting synchronous control signals of a trigger of an FPGA synthesis tool according to the present invention with reference to the accompanying drawings.

[0032] See also Figure 1 , a method for extracting synchronous control signals from a trigger of an FPGA synthesis tool of the present invention comprises the following steps:

[0033] Step S1: traverse each logic cell c in the circuit netlist, store the logic cells of the flip-flop type into the flip-flop cell set dffs, and store the mapping relationship between each output Y-terminal signal of the logic cell of the multiplexer type and the corresponding logic cell into the multiplexer output mapping set y2mux;

[0034] Step S2: traverse each trigger unit d in the set dffs, and for the input D-terminal signal sig_d of the trigger unit d, search in y2mux whether sig_d exists. If so, execute step S3; otherwise, exit the processing of the current trigger unit d and proceed to the processing of the next trigger unit;

[0035] Step S3: obtaining the multiplexer Mux unit a whose output Y-end signal is sig_d in y2mux, and obtaining the input A-end signal sig_a, the input B-end signal sig_b, and the input S-end signal sig_s of the Mux unit a;

[0036] Step S4: If sig_a is a constant signal, set the signal at the input D terminal of the flip-flop unit d to sig_b, the synchronous signal value sr_v = sig_a, the synchronous signal polarity p = 0, and go to step S7; otherwise go to step S5;

[0037] Step S5: If sig_b is a constant signal, set the signal at the input D terminal of the flip-flop unit d to sig_a, the synchronous signal value sr_v = sig_b, the synchronous signal polarity p = 1, and go to step S7; otherwise go to step S6;

[0038] Step S6: Count the number of right-value signals n1 and n2 of sig_a and sig_b. If n1 < n2, set the signal at the input D terminal of the flip-flop unit d to sig_b, the synchronous signal value sr_v = sig_a, the synchronous signal polarity p = 0; otherwise set the signal at the input D terminal of the flip-flop unit d to sig_a, the synchronous signal value sr_v = sig_b, the synchronous signal polarity p = 1;

[0039] Step S7: If the synchronous signal value sr_v is a constant 0 signal, generate a synchronous clear signal sclr for the synchronous clear port of the flip-flop unit d according to the value of the synchronous signal polarity p. If the polarity p = 0, create an inverted signal sr of a signal sig_s, and sr serves as the synchronous clear signal sclr of the flip-flop unit d; otherwise the signal sig_s serves as the synchronous clear signal sclr of the flip-flop unit d;

[0040] Step S8: If the synchronous signal value sr_v is a constant 1 signal or a non-constant signal, generate a synchronous load signal sload for the synchronous load port of the flip-flop unit d according to the value of the synchronous signal polarity p. If the polarity p = 0, create an inverted signal sr of a signal sig_s, and sr serves as the synchronous load signal sload of the flip-flop unit d; otherwise the signal sig_s serves as the synchronous load signal sload of the flip-flop unit d. Set the synchronous load value of the flip-flop unit d = the synchronous signal value sr_v. Finally, modify the type of the flip-flop unit d according to the synchronous signal value sr_v.

[0041] The method for counting the number of right-value signals n1 and n2 of sig_a and sig_b in step S6 is as follows Figure 2 where Figure 2 gives the method for counting the right-value signals of a signal (sig_a), and the method for counting the number of right-value signals of the signal sig_b is the same as that of sig_a, which specifically includes the following steps:

[0042] Step S6-1: Check whether sig_a exists in y2mux. If so, execute step S6-2; otherwise, insert sig_a into the right value signal set out and go to step S6-5;

[0043] Step S6-2: obtaining the multiplexer Mux unit b whose output signal is sig_a in y2mux, and obtaining the input A-end signal sig_a1 and the input B-end signal sig_b1 of the Mux unit b;

[0044] Step S6-3: Check whether sig_a1 exists in y2mux. If so, recursively execute step S6-1 on sig_a1. Recursively executing step S6-1 on sig_a1 means determining whether sig_a1 exists in y2mux. If so, execute step S6-2; otherwise, insert sig_a1 into the right value signal set out and go to step S6-5.

[0045] Step S6-4: Check whether sig_b1 exists in y2mux. If so, recursively execute step S6-1 on sig_b1 (the recursive operation steps are the same as the recursive execution of step S6-1 on sig_a1 in step S6-3); otherwise, insert sig_b1 into the right value signal set out and go to step S6-5;

[0046] Step S6-5: The number of sig_a right-value signals is equal to the number of signals in the set out.

[0047] In step S7, if the synchronization signal value sr_v is a constant 0 signal, a synchronization clear signal sclr is generated for the synchronization clear port of the trigger unit d according to the value of the synchronization signal polarity p. Figure 3 , specifically including the following steps:

[0048] S7-1: If polarity p=0, execute step S7-2, otherwise execute step S7-4;

[0049] S7-2: Create a new logic NOT type logic unit c1 (NOT gate logic unit), the input signal of c1 = sig_s, and the output signal is the inverted signal sr of the signal sig_s.

[0050] S7-3: Set the synchronous clear input port signal of trigger d = signal sr.

[0051] S7-4: Set the synchronous clear input port signal of trigger d = signal sig_s.

[0052] S7-5: If the type of the flip-flop unit d = DFF (D flip-flop), then update the type of d = DFFS (D flip-flop with synchronous set function, D flip-flop with synchronous set).

[0053] S7-6: If the type of the flip-flop unit d = DFFE (D flip-flop with enable), then update the type of d to DFFSE (D flip-flop with synchronous set function).

[0054] In step S8, if the synchronization signal value sr_v is a constant 1 signal or a non-constant signal, a synchronization set signal sload is generated for the synchronization set port of the trigger unit d according to the value of the synchronization signal polarity p. Figure 4 , specifically including the following steps:

[0055] Step S8-1: If polarity p=0, execute step S8-2; otherwise, execute step S8-4.

[0056] Step S8-2: Create a new logic cell c1 (not gate logic cell) of the logical NOT type. The input signal of c1 is sig_s, and the output signal is the inverted signal sr of the signal sig_s.

[0057] Step S8-3: Set the synchronous set input port signal of the trigger d to signal sr.

[0058] Step S8-4: Set the synchronous set input port signal of the trigger d to sig_s.

[0059] Step S8-5: Set the synchronization set value of the trigger unit d to the synchronization signal value sr_v.

[0060] Step S8 - 6 : If the synchronization signal value sr_v is a constant 1 signal and the type of the flip-flop unit d is DFF (D-type flip-flop), then update the type of d to DFFS (D flip-flop with synchronous set function).

[0061] Step S8-7: If the synchronization signal value sr_v is a constant 1 signal and the type of the flip-flop unit d = DFFE (D flip-flop with enable), then update the type of d = DFFSE (D flip-flop with synchronous set function).

[0062] Step S8-8: If the synchronization signal value sr_v is a non-constant signal and the type of the flip-flop unit d = DFF (D-type flip-flop), update the type of d = DFFSV (D-type flip-flop with synchronous set and reset functions, D Flip-Flop with Synchronous Set and Reset).

[0063] Step S8-9: If the synchronization signal value sr_v is a non-constant signal and the type of the flip-flop unit d = DFFE (D flip-flop with enable), then update the type of d to DFFSVE (D flip-flop with synchronous set, reset, and enable).

[0064] Example 2

[0065] The second embodiment provides a storage medium storing program code, which is called by a processor to execute the steps of the method for extracting a trigger synchronization control signal of an FPGA synthesis tool as described in the first embodiment.

[0066] Using a storage medium to store program code and using a processor to call and execute the program to implement the steps in the FPGA synthesis tool trigger synchronization control signal extraction method in Example 1 can improve the efficiency of trigger synchronization control signal extraction.

[0067] Example 3

[0068] Embodiment three provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the steps in the method for extracting a trigger synchronous control signal of an FPGA synthesis tool as described in embodiment one.

[0069] The above describes in detail the method, storage medium, and electronic device for extracting synchronous control signals from a trigger in an FPGA synthesis tool provided by the present invention. Specific examples are used herein to illustrate the structure and operating principles of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and core concept of the present invention. It should be noted that those skilled in the art may make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A method for extracting synchronous control signals from triggers of FPGA synthesis tools, characterized in that: Traversing the logic units in the circuit netlist, and storing the logic units of the trigger type into the trigger unit set; The mapping relationship between each output Y-terminal signal of the logic unit of the multiplexer type and the corresponding logic unit is stored in the multiplexer output mapping set; Traverse each trigger unit in the trigger unit set, and search the multiplexer output mapping set to see whether there is an input D-end signal of the trigger unit. If so, perform synchronization signal extraction; otherwise, exit the processing of the current trigger unit and process the next trigger unit; The synchronization signal extraction includes obtaining a multiplexer unit a whose output Y-end signal is the trigger input D-end signal in the multiplexer output mapping set, and obtaining an input A-end signal, an input B-end signal, and an input S-end signal of the multiplexer unit a; According to whether the input A-end signal and the input B-end signal of the multiplexer unit a are constant signals, setting the synchronization signal value and assigning 0 or 1 to the synchronization signal polarity value; And generate a trigger synchronization clear signal or a synchronization set signal according to the synchronization signal value and the synchronization signal polarity value.

2. A FPGA synthesis tool trigger synchronization control signal extraction method according to claim 1, characterized in that, If the input A-end signal of the multiplexer unit a is a constant signal, the synchronization signal value is the input A-end signal of the multiplexer unit a; If the input A-end signal of the multiplexer unit a is not a constant signal, confirm whether the input B-end signal of the multiplexer unit a is a constant signal; if the input B-end signal of the multiplexer unit a is a constant signal, set the synchronization signal value to the input B-end signal of the multiplexer unit a; If the input B-end signal of the multiplexer unit a is not a constant signal, the number of right-valued signals of the input A-end signal and the input B-end signal of the multiplexer unit a is compared, and the signal with the smaller right-valued signal is taken as the synchronization signal value.

3. A FPGA synthesis tool trigger synchronization control signal extraction method according to claim 2, characterized in that, If the synchronization signal value is set to the input A-end signal of the multiplexer unit a, the input D-end signal of the trigger unit is set to the input B-end signal of the multiplexer unit a; if the synchronization signal value is set to the input B-end signal of the multiplexer unit a, the input D-end signal of the trigger unit is set to the input A-end signal of the multiplexer unit a.

4. A FPGA synthesis tool trigger synchronization control signal extraction method according to claim 2, characterized in that, If the synchronization signal value is the input A-end signal of the multiplexer unit a, the synchronization signal polarity value is set to 0; if the synchronization signal value is the input B-end signal of the multiplexer unit a, the synchronization signal polarity value is set to 1.

5. A FPGA synthesis tool trigger synchronization control signal extraction method according to claim 1, characterized in that, When the synchronization signal value is a constant 0 signal, if the synchronization signal polarity value is 0, the inverted signal of the input S terminal signal of the newly created multiplexer unit a is used as the synchronization clear signal of the trigger unit; if the synchronization signal polarity value is 1, the input S terminal signal of the multiplexer unit a is used as the synchronization clear signal of the trigger unit; When the synchronization signal value is a constant 1 signal or a non-constant signal, if the synchronization signal polarity value is 0, then the inverted signal of the input S-end signal of the multiplexer unit a is newly created as the synchronization set signal of the trigger unit; if the synchronization signal polarity value is 1, then the input S-end signal of the multiplexer unit a is used as the synchronization set signal of the trigger unit.

6. A FPGA synthesis tool trigger synchronization control signal extraction method according to claim 5, characterized in that, When the synchronization signal value is a constant 0 signal, if the synchronization signal polarity value is 0, a new logic unit of a logical NOT type is created, the input signal of the logic NOT type logic unit is set to the input S-end signal of the multiplexer unit a, the output signal is the inverted signal of the input S-end signal of the multiplexer unit a, and the synchronization clear input end signal of the trigger unit is set to the inverted signal of the input S-end signal of the multiplexer unit a; If the polarity value of the synchronization signal is 1, the synchronization clear input terminal signal of the trigger unit is set to the input terminal S signal of the multiplexer unit a.

7. A method for extracting synchronous control signals from a trigger of an FPGA synthesis tool according to claim 6, characterized in that: If the trigger unit type is DFF, update the trigger unit type to DFFS; If the trigger unit type is DFFE, update the trigger unit type to DFFSE.

8. A method for extracting synchronous control signals from a trigger of an FPGA synthesis tool according to claim 5, characterized in that: When the synchronization signal value is a constant 1 signal or a non-constant signal, if the synchronization signal polarity value is 0, a new logic unit of a logical NOT type is created, the input signal of the logic NOT type logic unit is set to the input S-end signal of the multiplexer unit a, the output signal is the inverted signal of the input S-end signal of the multiplexer unit a, and the synchronization set input end signal of the trigger unit is set to the inverted signal of the input S-end signal of the multiplexer unit a; If the polarity value of the synchronization signal is 1, the synchronization set input terminal signal of the trigger unit is set to the input terminal S signal of the multiplexer unit a; At the same time, the synchronization setting value of the trigger unit is set to the synchronization signal value, and the trigger unit type is modified according to the synchronization signal value.

9. A method for extracting synchronous control signals from a trigger of an FPGA synthesis tool according to claim 8, characterized in that: If the synchronous set value of the trigger unit is a constant 1, and the type of the trigger unit is DFFE, then the type of the trigger unit is updated to DFFSE; If the synchronous set value of the trigger unit is a non-constant signal and the trigger unit type is DFF, then update the trigger unit type to DFFSV; If the synchronous set value of the trigger unit is a non-constant signal and the trigger unit type is DFFE, the trigger unit type is updated to DFFSVE.

10. The method for extracting synchronous control signals from a trigger of an FPGA synthesis tool according to claim 2, wherein: The method for counting the number of right-hand side signals of the input A-end signal of the multiplexer unit a includes: Step 1: Searching the multiplexer output mapping set for the input A-end signal of the multiplexer unit a; if so, searching the multiplexer output mapping set for a multiplexer unit b whose output signal is the input A-end signal of the multiplexer unit a, and obtaining the input A-end signal and the input B-end signal of the multiplexer unit b; If it does not exist, insert the input A terminal signal of the multiplexer unit a into the right value signal set; Step 2: Searching whether the input A-end signal of the multiplexer unit b exists in the multiplexer output mapping set; if so, recursively performing right-value signal statistical processing on the input A-end signal of the multiplexer unit b; if not, inserting the input A-end signal of the multiplexer unit b into the right-value signal set; Step 3: Searching the multiplexer output mapping set for the input B-end signal of the multiplexer unit b; if so, recursively performing right-value signal statistical processing on the input B-end signal of the multiplexer unit b; if not, inserting the input B-end signal of the multiplexer unit b into the right-value signal set; The number of signals in the right-value signal set is the number of right-value signals of the input A-end signal of the multiplexer unit a.

11. The method for extracting a synchronous control signal from a trigger of an FPGA synthesis tool according to claim 10, wherein: The method for counting the number of right-hand side signals of the input B-end signal of the multiplexer unit a is the same as the method for counting the number of right-hand side signals of the input A-end signal of the multiplexer unit a.

12. A storage medium, characterized in that: The storage medium stores program code, and the program code is called by a processor to execute the FPGA synthesis tool trigger synchronization control signal extraction method according to any one of claims 1 to 11.

13. An electronic device, characterized in that: including one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute the FPGA synthesis tool trigger synchronization control signal extraction method as described in any one of claims 1 to 11.

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