Storage device and data processing method

Abstract

The invention discloses a storage device and a data processing method. The storage device includes: a non-volatile storage device that stores or reads user data; and a controller controlling the non-volatile memory device, the non-volatile memory device including: a memory cell array including a plurality of memory cells, the plurality of memory cells storing data bits corresponding to user data; a compression circuit that compresses soft bit data sensed from the plurality of memory cells; and a control logic that controls the compression circuit through the plurality of compression stages and transmits a stage control signal to the compression circuit to control whether to perform compression on each of the plurality of compression stages.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0010481, filed with the Korean Intellectual Property Office on January 23, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present disclosure provides a storage device and a data processing method. Background Art

[0003] With the advancement of technologies such as artificial intelligence (AI), the amount of data being stored and processed is increasing. Accordingly, the storage capacity of data centers is continuously increasing. In data centers and cloud computing environments, the use of semiconductor device-based storage devices is increasing.

[0004] As the use of storage devices increases, continuous research is being conducted to improve the performance and lifespan of storage devices. A controller of a storage device controls an operation of storing data in a non-volatile memory device or an operation of reading data from the non-volatile memory device. Accordingly, a data transfer rate between the controller and the non-volatile memory device affects the performance of the storage device. Summary of the Invention

[0005] According to some embodiments of the present disclosure, there is provided a storage device having improved performance and a method of operating the same.

[0006] According to some embodiments of the present disclosure, there is provided a storage device having an improved lifespan and a method of operating the same.

[0007] According to some embodiments of the present disclosure, there is provided a storage device and a method of operating the same that increase a transfer speed of soft bit data between a controller and a memory device.

[0008] According to some embodiments of the present disclosure, a storage device includes: a non-volatile memory device that stores or reads user data; and a controller that controls the non-volatile memory device, and the non-volatile memory device includes: a memory cell array including a plurality of memory cells that store data bits corresponding to user data; a compression circuit that compresses soft bit data sensed from the plurality of memory cells; and control logic that controls the compression circuit through a plurality of compression stages and sends a stage control signal to the compression circuit to control whether to perform compression on each of the plurality of compression stages.

[0009] According to some embodiments of the present disclosure, a method of operating a storage device includes: sending, by a controller, a soft read command to a non-volatile memory device, the controller controlling the non-volatile memory device, generating, by the non-volatile memory device in response to the soft read command, soft bit data, providing, by a control logic circuit of the non-volatile memory device, a stage control signal to a compression circuit to control the compression circuit through a plurality of compression stages, generating, by the compression circuit, compressed soft bit data obtained by compressing the soft bit data based on the stage control signal, and sending, by the non-volatile memory device, the compressed soft bit data to the controller, and the stage control signal is a signal for controlling whether to perform compression on each of the plurality of compression stages.

[0010] According to some embodiments of the present disclosure, a storage device includes: a non-volatile memory device that stores or reads user data, and a controller that controls the non-volatile memory device, and the non-volatile memory device includes a memory cell array, and the memory cell array includes: a plurality of memory cells that store data bits corresponding to user data; a plurality of compression circuits that compress soft bit data sensed from the plurality of memory cells; and a control logic circuit that controls the compression circuits, and the plurality of compression circuits include: a conversion circuit that converts the soft bit data into input data composed of an index code and a dummy code based on a mapping table; a first compression circuit that compresses the input data at a first compression rate; and a second compression circuit that receives first output data from the first compression circuit and generates second output data by compressing the first output data at a second compression rate, and the control logic circuit controls the provision of the first output data for the second compression circuit based on the compression rate of the soft bit data. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become apparent by referring to the examples of the present disclosure described in detail with reference to the drawings.

[0012] Figure 1 is a block diagram showing an example of a computing system.

[0013] Figure 2 is a block diagram showing an example of a storage device.

[0014] Figure 3 is a block diagram showing an example of a storage device.

[0015] Figure 4 is a diagram showing an example of a non-volatile memory device of a storage device.

[0016] Figure 5A is a graph showing an example of the threshold voltage distribution of a triple-level cell (TLC).

[0017] Figure 5B is showingFigure 5A Graph of the change in the distribution

[0018] Figure 5C Is a diagram showing hard bits and soft bits when the threshold voltage distributions of memory cells overlap

[0019] Figure 6 Is a diagram showing an example of a memory block of a 3D V - NAND structure applicable to a storage device

[0020] Figure 7 Is a diagram showing an example of the operation of a soft - bit data conversion circuit

[0021] Figure 8 Is a diagram showing an example of input data

[0022] Figure 9 Is a diagram showing an example of the operation of a stage compression circuit

[0023] Figure 10 Is a diagram showing an example of the operation of multiple compression stages of a compression circuit

[0024] Figure 11 Is a diagram showing an example of compression by multiple - stage compression circuits of a compression circuit

[0025] Figure 12 Is a diagram showing an example of compression by multiple - stage compression circuits of a compression circuit

[0026] Figure 13 Is a diagram showing an example of the operation of a compression circuit

[0027] Figure 14 Is a diagram showing an example of the change in the compression ratio of a storage device

[0028] Figure 15 Is a diagram showing an example of the method by which a non - volatile memory device provides a compression - ratio change signal to a controller

[0029] Figure 16 and Figure 17 Is a diagram showing an example of the method by which a non - volatile memory device provides a compression - ratio change signal to a controller

[0030] Figure 18 Is a diagram showing an example of a method of operating a storage device Detailed Description

[0031] Figure 1 Is a block diagram showing a computing system 1 according to some embodiments of the present disclosure

[0032] The non-volatile memory device 200 of the storage device 20 can compress soft-bit data SBD, and can send the compressed soft-bit data to the controller 100 together with hard-bit data. The control logic circuit 210 of the non-volatile memory device 200 can control the compression circuit 260, and the compression circuit 260 includes a plurality of compression stages ST_1, ST_2,.... Each of the plurality of compression stages ST_1, ST_2,... can perform compression on the input data. The compression ratio of the soft-bit data SBD can be obtained by the compression of each of the plurality of compression stages ST_1, ST_2,.... The control logic circuit 210 can change the compression ratio of the soft-bit data SBD by controlling whether to perform compression on each of the plurality of compression stages ST_1, ST_2,..., by the compression of each of the plurality of compression stages ST_1, ST_2,..., and / or the compression in each of the plurality of compression stages ST_1, ST_2,....

[0033] The computing system 1 can include a host 10 and a storage device 20. The host 10 can communicate with a plurality of storage devices. Figure 1 Other storage devices not shown may have the same or similar configuration as the storage device 20.

[0034] The host 10 controls the overall operation of the storage device 20. The host 10 can send a request IO_REQ for input / output (I / O) of data to the storage device 20, and in response to the request IO_REQ, the host 10 can receive a response IO_RSP for input / output (I / O) of data from the storage device 20. In addition, the host 10 can send the data IO_DATA to be written to the non-volatile memory device 200 to the storage device 20 together with the request IO_REQ for data input, or can receive the data IO_DATA read from the non-volatile memory device 200 from the storage device 20 in response to the request IO_REQ for data output.

[0035] In this specification, the expression "write" means that data is "stored" or "programmed" in the non-volatile memory device 200.

[0036] The host 10 can include a processor 11 and a volatile memory device (or referred to as a memory) 12.

[0037] The host 10 can be one or more servers, personal computers, laptop computers, etc. of a data center or a cloud system. The host 10 can be a computing device having a processor 11 and a volatile memory device 12 configured to process data. The processor 11, the volatile memory device 12, the memory controller, the network port, the network interface, etc. can form the root complex 13 of the host 10.

[0038] The root complex 13 is a subsystem of the host 10 and may have interconnection functions and / or bridging functions with internal components and / or peripheral devices. In Figure 1 the example of Figure 1 , it is assumed that the processor 11 is implemented within the root complex 13. However, according to an embodiment, the root complex 13 and the processor 11 may be implemented separately.

[0039] The processor 11 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or any other type of processing device composed of software instructions, microcode, and / or firmware. The processor 11 may be composed of multiple processors.

[0040] The volatile memory device 12 may include static random access memory (SRAM) and dynamic random access memory (DRAM). The volatile memory device 12 may be composed of multiple memory modules. The volatile memory device 12 may store instructions executed by the processor 11.

[0041] The storage device 20 may be electrically connected to the host 10 and / or connected through a network, and may include a controller 100 and at least one non-volatile memory device 200.

[0042] The storage device 20 may be implemented in a state physically separated from the host 10, or may be implemented in a form factor installed in the same package as the host 10. For example, the storage device 20 may be implemented based on E1.S, E1.L, E3.S, E3.L, and PCIe AIC (CEM) form factors. In some embodiments, the storage device 20 is implemented based on the U.2 form factor, the M.2 form factor, or another type of PCIe form factor.

[0043] The storage device 20 may be combined to communicate with other components of the host 10 through a storage interface bus. In some embodiments, the storage device 20 is directly installed on a PCIe (Peripheral Component Interconnect Express)-based physical port of the host 10. The storage interface bus may be, for example, a PCIe bus. The host 10 may use a storage interface protocol to send data to or receive data from the storage device 20 through the storage interface bus. The data may include user data. The storage interface protocol may be, for example, Compute Express Link (CXL) and / or Non-Volatile Memory Host Controller Interface (NVMe).

[0044] The controller 100 may control the non-volatile memory device 200 to perform operations associated with an input / output request IO_REQ from the host 10. Operations associated with the input / output request IO_REQ may include: writing user data requested by the host 10 to the storage device 20, reading and / or erasing user data requested by the host 10.

[0045] The controller 100 can correct errors included in user data read from the non-volatile memory device 200. In some embodiments, the controller 100 corrects errors in the user data read using soft decision processing.

[0046] The non-volatile memory device 200 may include (e.g., in the memory cell array 220) flash memory of a 2D structure or a 3D structure. The flash memory may include, but is not limited to, any other type of non-volatile memory (such as NAND flash memory, V-NAND (vertical NAND) flash memory, NOR flash memory, magnetic RAM (MRAM), phase RAM (PRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), resistive RAM (RRAM), etc.).

[0047] The storage device 20 may include a volatile memory device. At least a part of the volatile memory device may be used as a working memory. The working memory may include a buffer memory that temporarily stores user data to be written to the non-volatile memory device 200 or user data read from the non-volatile memory device 200. The volatile memory device may include volatile memory cells. For example, the volatile memory device may include dynamic random access memory (DRAM) or static random access memory (SRAM).

[0048] In some embodiments, the storage device 20 includes a plurality of non-volatile memory devices 200. The non-volatile memory device 200 may include a memory cell array 220, a control logic circuit 210, and a compression circuit 260. The memory cell array 220 stores user data, the control logic circuit 210 controls the memory cell array 220, and the compression circuit 260 performs compression on soft bit data. The soft bit data SBD may be generated based on the data stored in the memory cell array 220.

[0049] The compression circuit 260 may perform compression on the soft bit data SBD through a plurality of compression stages ST_1 (stage 1), ST_2 (stage 2),.... At least some of the plurality of compression stages may compress the input data provided from the previous compression stage at a preset stage compression rate to generate output data, and the generated output data may be provided to the subsequent compression stage.

[0050] In some embodiments, in order to compress the soft bit data SBD at a preset first compression rate, among the plurality of compression stages ST_1, ST_2,...., one or more of the compression stages perform compression, and the remaining one or more compression stages do not perform compression. In some embodiments, in order to compress the soft bit data SBD at a preset second compression rate, all of the plurality of compression stages ST_1, ST_2,.... perform compression.

[0051] In some embodiments, the control logic circuit 210 sends a stage control signal SCS to the compression circuit 260, and the stage control signal SCS controls whether to perform compression on each of the plurality of compression stages ST_1, ST_2, …… based on the compression ratio.

[0052] The soft bit data compressed in the compression circuit 260 can be sent to the controller 100. The hard bit data can be sent to the controller 100 together with the compressed soft bit data.

[0053] Figure 2 is a block diagram showing the configuration of a storage device according to some embodiments of the present disclosure. Figure 2 The storage device 20 can be associated with Figure 1 the storage device 20 corresponding to.

[0054] The storage device 20 may include a controller 100 and at least one non-volatile memory device 200.

[0055] The controller 100 may include a host interface (I / F) circuit 110, a processor 120, a flash translation layer (FTL) 130, a packet manager 140, a command decoder 150, a working memory 160, an error correction code block 170, and a non-volatile memory interface circuit 180.

[0056] The controller 100 can communicate with the host 10 through the host interface circuit 110. The host interface circuit 110 can be implemented in various interface methods (such as, Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), IEEE 1394, Universal Serial Bus (USB), Non-Volatile Memory Express (NVMe), Compute Express Link (CXL), etc.).

[0057] The processor 120 can load the firmware of the storage device 20 into the working memory 160 and can control the overall operation of the controller 100.

[0058] The flash translation layer (FTL) 130 can perform several functions (such as, address mapping, wear-leveling, and garbage collection).

[0059] The flash translation layer (FTL) 130 can perform address mapping to convert the logical addresses received from the host 10 into physical addresses for actually programming data in the non-volatile memory device 200. To prevent excessive degradation of a specific block by ensuring that the blocks in the non-volatile memory device 200 are used evenly, the flash translation layer (FTL) 130 can perform wear leveling by, for example, balancing the erase counts of physical blocks. The flash translation layer (FTL) 130 copies the valid data of a block to a new block and then erases the existing block, thereby performing garbage collection to ensure the available capacity within the non-volatile memory device 200.

[0060] The packet manager 140 can generate packets according to the protocol of the interface agreed upon with the host 10, or can parse various information according to the packets received from the host 10.

[0061] The command decoder 150 can decode the commands parsed from the packets based on the protocol of the interface agreed upon with the host 10. For example, the command decoder 150 can distinguish between write commands, read commands, and / or flush commands by decoding the operation code (OPCODE) of the commands based on the NVMe protocol, and the processor 120 can perform operations associated with the requested input / output (IO_REQ) of the data requested from the host 10 based on the decoded commands.

[0062] The working memory 160 can include registers for storing variables within the controller 100. In some embodiments, a portion of the working memory 160 is used as a buffer memory. The buffer memory can temporarily store data to be written to the non-volatile memory device 200 or data read from the non-volatile memory device 200. Figure 2 It is shown that the working memory 160 is located inside the controller 100, but according to the embodiments, all or part of the working memory 160 can be provided inside and / or outside the controller 100. In some embodiments, when the host buffer memory is provided in the host 10, the working memory 160 does not operate as a buffer memory.

[0063] The ECC block 170 may perform error correction encoding on user data sent to the non-volatile memory device 200 using an error correction code (ECC). The ECC block 170 may perform error correction decoding on user data read from the non-volatile memory device 200 using an error correction code (ECC). In some embodiments, the ECC block 170 performs error correction decoding on the read user data using soft decision processing. Error correction decoding using soft decision processing may be referred to as soft decoding. The ECC block 170 may perform soft decoding using soft bit data. In some embodiments, the ECC block 170 performs soft decoding when error correction decoding using hard decision fails (e.g., based on and / or in response to). Error correction decoding using hard decision may be referred to as hard decoding. The ECC block 170 may perform hard decoding using hard bit data.

[0064] In some embodiments, the ECC block 170 uses at least one of a low density parity check (LDPC) code, a Reed-Solomon (RS) code, and a Bose-Chaudhuri-Hocquenghem (BCH) code to perform error correction decoding.

[0065] The ECC block 170 may include a soft bit decompressor 171 that decompresses the compressed soft bit data CSBD sent from the non-volatile memory device 200. The soft bit decompressor 171 may decompress the compressed soft bit data CSBD to generate soft bit data SBD, and the ECC block 170 may perform error correction decoding using the soft bit data SBD.

[0066] The soft bit decompressor 171 may determine the compression rate of the compressed soft bit data CSBD. In some embodiments, for example, as described below with reference to Figure 15 The soft bit decompressor 171 determines the compression rate of the compressed soft bit data CSBD based on a compression rate change signal sent from the non-volatile memory device 200. In some embodiments, for example, as described below regarding Figure 16 and Figure 17 The soft bit decompressor 171 determines the compression rate of the compressed soft bit data CSBD based on a partial bit sequence of the compressed soft bit data CSBD.

[0067] The soft bit decompressor 171 may decompress the compressed soft bit data CSBD based on the compression rate and generate soft bit data.

[0068] In some embodiments, the ECC block 170 requests the non-volatile memory device 200 to change the compression rate of the soft bit data SBD. For example, the ECC block 170 may send a command instructing the non-volatile memory device 200 to change the compression rate of the soft bit data SBD to the non-volatile memory device 200. In some embodiments, the ECC block 170 requests the non-volatile memory device 200 to change the compression rate of the soft bit data SBD based on the occurrence of wear, the failure rate of error correction decoding, the failure rate of hard decoding, the failure rate of soft decoding, and / or the ratio of error bits. For example, the ECC block 170 may request the non-volatile memory device 200 to change the compression rate of the soft bit data SBD when at least one of the failure rate of error correction decoding, the failure rate of hard decoding, the failure rate of soft decoding, and / or the ratio of error bits exceeds a preset standard / predetermined value.

[0069] In some embodiments, the ECC block 170 determines the life stage of the non-volatile memory device 200 based on at least one of the quantity of wear, the failure rate of error correction decoding, the failure rate of hard decoding, the failure rate of soft decoding, and / or the ratio of error bits. The ECC block 170 may request the non-volatile memory device 200 to change the compression rate of the soft bit data SBD to a preset value based on the determined life stage. Additionally or alternatively, the ECC block 170 may use various methods known in the art to determine the life stage of the non-volatile memory device 200.

[0070] Figure 3 is a block diagram showing a storage device according to some embodiments of the present disclosure. Figure 3 The storage device 20 of Figure 1 and Figure 2 corresponds to the storage device 20.

[0071] Referring to Figure 3 , the non-volatile memory device (or memory device) 200 may be connected to the controller 100 through a plurality of channels CH1... CHm.

[0072] The controller 100 may input data to / output data from / and / or erase data from / to the plurality of non-volatile memory devices NVM11 to NVMmn through the plurality of channels CH1... CHm (where m and n are natural numbers greater than or equal to 2).

[0073] The controller 100 can control each of the non-volatile memory devices NVM11 to NVMmn connected to one of the multiple channels CH1... CHm through a path (way). For example, the controller 100 can control the non-volatile memory devices NVM11, NVM12,... and NVM1n connected to the first channel CH1 through paths W11, W12,... and W1n.

[0074] The controller 100 can exchange signals with the non-volatile memory device 200 through the multiple channels CH1... CHm. For example, the controller 100 can send commands, addresses, and / or data to the non-volatile memory device 200 through the channels CH1... CHm, or can receive data from the non-volatile memory device 200.

[0075] The non-volatile memory device 200 can include a plurality of non-volatile memory devices NVM11 to NVMmn. Each of the non-volatile memory devices NVM11 to NVMmn can be a non-volatile memory package, a non-volatile memory die, a non-volatile memory plane, and / or a non-volatile memory block. In some embodiments, when the non-volatile memory devices NVM11 to NVMmn are non-volatile memory packages, each non-volatile memory package can include a plurality of memory dies, but the present disclosure is not limited thereto.

[0076] Figure 4 is a diagram showing the configuration of the non-volatile memory device of a storage device according to some embodiments of the present disclosure. Figure 4 The non-volatile memory device 200 of can be associated with Figure 1 , Figure 2 and Figure 3 the non-volatile memory device 200 corresponding.

[0077] Referring to Figure 4 , the non-volatile memory device 200 can include: a control logic circuit 210, a memory cell array 220, a page buffer circuit 230, a voltage generator 240, a row decoder 250, a compression circuit 260, and an input / output (I / O) circuit 270. Although not shown in Figure 4 , the non-volatile memory device 200 can include components of a conventional known solid-state drive memory device (such as column logic, a pre-decoder, a temperature sensor, a command decoder, and an address decoder).

[0078] The control logic circuit 210 can generally control various operations within the non-volatile memory device 200. The control logic circuit 210 can output various control signals in response to a command CMD and / or a physical address ADDR from the memory interface circuit. For example, the control signals can include: a voltage control signal CTRL_vol, a row address X_ADDR, and a column address Y_ADDR.

[0079] The memory cell array 220 can include a plurality of memory blocks BLK1 to BLKz (“z” is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz can include a plurality of memory cells. The memory cell array 220 can be connected to the page buffer circuit 230 through bit lines BL1 to BLn, and can be connected to the row decoder 250 through word lines WL, string selection lines SSL, and ground selection lines GSL.

[0080] The page buffer circuit 230 can include a plurality of page buffers PB1 to PBn (“n” is an integer of 3 or greater). The plurality of page buffers PB1 to PBn can be respectively connected to the memory cells within the plurality of memory blocks BLK1 to BLKz through a plurality of bit lines BL1 to BLn. The page buffer circuit 230 can select at least one of the bit lines BL1 to BLn in response to the column address Y_ADDR. The page buffer circuit 230 can operate as a write driver or a sense amplifier according to the operation mode. For example, during a programming operation, the page buffer circuit 230 can apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer circuit 230 can sense the data stored in the memory cell (e.g., the data bit corresponding to the user data) by sensing the current or voltage of the selected bit line. The page buffer circuit 230 can provide the data DATA_OUT sensed from the memory cell to the compression circuit 260.

[0081] The voltage generator 240 can generate various types of voltages for performing programming operations, read operations, and erase operations in response to the voltage control signal CTRL_vol.

[0082] The row decoder 250 can select one of the plurality of word lines WL and one of the plurality of string selection lines SSL in response to the row address X_ADDR.

[0083] The input / output circuit 270 can send the data DATA read from the memory cell array 220 to the controller 100. The data DATA sent to the controller 100 can include compressed soft bit data CSBD. The input / output circuit 270 can provide the input data DATA_IN provided by the controller 100 to the page buffer circuit 230. The input data DATA_IN can include user data to be programmed into the memory cell array 220.

[0084] The page buffer circuit 230 according to some embodiments of the present disclosure senses data stored in memory cells based on a soft read voltage and generates soft bit data SBD. The page buffer circuit 230 may provide the soft bit data SBD to the compression circuit 260 as part of the output data DATA_OUT.

[0085] The compression circuit 260 may compress the soft bit data SBD provided by the page buffer circuit 230 through a plurality of compression stages ST_1, ST_2,.... The control logic circuit 210 may control the compression circuit 260 through a plurality of compression stages ST_1, ST_2,... using stage control signals SCS. The control logic circuit 210 may send different stage control signals SCS to the compression circuit 260 based on the compression ratio of the soft bit data SBD. The stage control signal SCS may be a signal indicating whether to perform compression on each of the plurality of compression stages ST_1, ST_2,....

[0086] In some embodiments, each of the plurality of compression stages ST_1, ST_2,... is implemented as a separate stage compression circuit. In some embodiments, the plurality of compression stages ST_1, ST_2,... are implemented using the same one stage compression circuit. Each of the plurality of compression stages ST_1, ST_2,... may receive the output data of the previous compression stage as input data. Each of the plurality of compression stages ST_1, ST_2,... may compress the input data and may generate output data. Based on the stage control signal SCS, each of the plurality of compression stages ST_1, ST_2,... may perform compression or may not perform compression. When a particular compression stage does not perform compression, the output data of the compression stage before the particular compression stage may be sent to the controller 100 through the input / output circuit 270.

[0087] In some embodiments, the compression circuit 260 only performs compression on the soft bit data SBD and may not perform compression on the hard bit data. For example, the compression circuit 260 may only compress the soft bit data SBD in response to the stage control signal SCS. The data DATA_OUT other than the soft bit data SBD may be sent to the input / output circuit 270 without compression being performed. In some embodiments, the compression circuit 260 performs compression on the hard bit data. Compression of the hard bit data may use a conventionally known compression method (e.g., run length encoding (RLE)-based compression, etc.), rather than the plurality of compression stages ST_1, ST_2,....

[0088] The control logic circuit 210 can change the compression ratio of the soft bit data SBD. In some embodiments, the control logic circuit 210 changes the compression ratio of the soft bit data SBD in response to a command CMD sent from the controller 100 being a request for changing the compression ratio. In this case, the control logic circuit 210 can change the stage control signal SCS, and can provide the changed stage control signal SCS to the compression circuit 260. For example, the control logic circuit 210 can provide a first stage control signal SCS to the compression circuit 260 based on a first compression ratio, and the first stage control signal SCS controls compression to be performed in all of a plurality of compression stages ST_1, ST_2,.... In response to a request for changing the compression ratio from the controller 100, the control logic circuit 210 can provide a second stage control signal SCS to the compression circuit 260 based on a second compression ratio, and the second stage control signal SCS controls compression to be performed only in a part of a plurality of compression stages ST_1, ST_2,....

[0089] In some embodiments, the control logic circuit 210 determines a change in the compression ratio of the soft bit data SBD. For example, the control logic circuit 210 can determine a change in the compression ratio of the soft bit data SBD based on at least one of the ratio and / or the number of weak bits of the soft bit data SBD and the increasing trend of the weak bits of the soft bit data SBD. When the control logic circuit 210 determines to change the compression ratio of the soft bit data SBD, the control logic circuit 210 can change the stage control signal SCS for providing to the compression circuit 260, and can provide a compression ratio change signal CR_CHN to the controller 100 through the input / output circuit 270.

[0090] Figure 5A is a graph showing the distribution of the threshold voltage (Vth) of memory cells when the memory cells included in the memory cell array are triple level cells (TLC). Refer to Figures 5A to 5B The described memory cell array can correspond to Figures 1 to 4 the memory cell array 220.

[0091] Refer to Figure 5A , when each memory cell of the memory cell array 220 is a triple level cell programmed with 3 bits, the memory cell can have a threshold voltage distribution "E" corresponding to the erased state or one of the threshold voltage distributions P1 to P7 corresponding to the first to seventh programming states.

[0092] The first read voltage Vr1 has a voltage level between the threshold voltage distribution “E” of the memory cells in the erased state and the threshold voltage distribution P1 of the memory cells in the first programmed state. The second read voltage Vr2 to the seventh read voltage Vr7 have voltage levels between the threshold voltage distributions P1 to P7 of each adjacent respective programmed state. The non-volatile memory device 200 can apply at least one of the first read voltage Vr1 to the seventh read voltage Vr7, and can sense data stored in the memory cells based on the on-state or off-state of the memory cells.

[0093] Figure 5B is a graph showing Figure 5A the case where the distribution of the threshold voltage in the graph is changed. Referring to Figure 5B , the threshold voltage distributions P1 to P7 corresponding to the first programmed state to the seventh programmed state may overlap with each other. In this case, when reading data stored in the memory cells having overlapping distributions, an error may occur.

[0094] Figure 5C is a diagram showing hard bits and soft bits when the distributions of the threshold voltages of memory cells storing 1 bit overlap.

[0095] Figure 5C shows the case where the threshold voltage distribution “E” of the memory cells in the erased state overlaps with the threshold voltage distribution P1 in the first programmed state. When the threshold voltage of the memory cell is in the first region RG1, the hard bit can be read as bit “1” with respect to the applied hard read voltage Vread0. When the threshold voltage of the memory cell is in the third region RG3, the hard bit can be read as bit “0” with respect to the applied hard read voltage Vread0. Since the distributions of the respective threshold voltages in the first region RG1 and the third region RG3 do not overlap, the reliability of the read hard bit value is high. On the contrary, when the threshold voltage of the memory cell is located in the second region RG2, it is not clear whether the corresponding threshold voltage is due to the threshold voltage distribution “E” in the erased state or due to the threshold voltage distribution P1 in the first programmed state. Therefore, when the threshold voltage of the memory cell is in the second region RG2, the read hard bit value ( Figure 5C the bit “0” in) may have low reliability.

[0096] Figure 5CAn example of a non-volatile memory device can sense soft bits by applying soft read voltages Vread1 and Vread2 having a specific difference from a hard read voltage Vread0. The application of such voltages and the corresponding sensing can be referred to as soft decision processing. Memory cells having a threshold voltage lower than a first soft read voltage Vread1 can be identified as bit "1", and memory cells having a threshold voltage greater than the first soft read voltage Vread1 and less than a second soft read voltage Vread2 can be identified as bit "0". Memory cells having a threshold voltage greater than the second soft read voltage Vread2 can be identified as bit "1". A soft bit can be generated by performing an exclusive OR (XOR) of "a bit value depending on the on-off state of a memory cell according to the first soft read voltage Vread1" and "an inverted value of a bit value depending on the on-off state of a memory cell according to the second soft read voltage Vread2".

[0097] A soft bit can represent the reliability of a corresponding hard bit. Soft bits corresponding to hard bits read based on threshold voltages located in a first region RG1 and a third region RG3 can be referred to as strong bits. Soft bits corresponding to hard bits read based on threshold voltages located in a second region RG2 can be referred to as weak bits. Data composed of multiple soft bits can be referred to as soft bit data.

[0098] Figure 6 is a diagram showing in detail a memory block of a 3D V-NAND structure applicable to a storage device according to some embodiments of the present disclosure. According to Figure 6 An example of a memory block BLKi can correspond to Figure 4 any one of the memory blocks BLK_1, BLK_2,... of Figure 1 and Figure 2 When the non-volatile memory device 200 of the storage device 20 of Figure 6 is implemented as a 3D V-NAND type flash memory, each of the multiple memory blocks forming the non-volatile memory device 200 can be represented by an equivalent circuit as shown in

[0099] Figure 6 The memory block BLKi shown in

[0100] refers to Figure 6, the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1, BL2, and BL3 and the common source line CSL. Each of the plurality of NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1, MC2, …, and MC8, and a ground select transistor GST. In Figure 6 , each of the plurality of memory NAND strings NS11 to NS33 is shown as including eight memory cells MC1, MC2, …, and MC8, but the present disclosure is not limited thereto.

[0101] The string select transistor SST may be connected to the corresponding string select lines SSL1, SSL2, and SSL3. The plurality of memory cells MC1, MC2, …, and MC8 may be respectively connected to the corresponding gate lines GTL1, GTL2, …, and GTL8. The gate lines GTL1, GTL2, …, and GTL8 may be used as word lines, and some of the gate lines GTL1, GTL2, …, and GTL8 may be used as dummy word lines. The ground select transistor GST may be connected to the ground select lines GSL1, GSL2, and GSL3. The string select transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST may be connected to the common source line CSL.

[0102] Word lines of the same height (e.g., WL1) may be commonly connected, the ground select lines GSL1, GSL1, and GSL3 may be separated from each other, and the string select lines SSL1, SSL2, and SSL3 may be separated from each other. In Figure 6 , the memory block BLKi is shown as being connected to eight gate lines GTL1, GTL2, …, and GTL8 and three bit lines BL1, BL2, and BL3, but the present disclosure is not limited thereto.

[0103] The memory block BLKi may have different bit densities according to the number of bits stored by the memory cells included in the memory block BLKi.

[0104] Figure 7 is a diagram for describing the operation of the soft bit data conversion circuit 261 according to some embodiments of the present disclosure. The compression circuit may include the soft bit data conversion circuit 261. The compression circuit including Figure 7 the soft bit data conversion circuit 261 may correspond to Figure 1 and Figure 4 the compression circuit 260. For example, the compression circuit 260 may include the soft bit data conversion circuit 261. For illustrative purposes, Figure 7 it is described that each row of the input data IN_DATA has one cell data, but the data structure is not limited thereto.

[0105] The soft bit data conversion circuit 261 can convert the soft bit data SOFT_BIT_DATA into input data IN_DATA provided to Figure 1 and Figure 4 at multiple compression levels ST_1, ST_2, …….

[0106] The soft bit data SOFT_BIT_DATA can be composed of multiple soft bits sensed through soft decision. The soft bits can include strong bits and weak bits. According to an embodiment, the weak bit can be bit "0" or bit "1". In this specification, it is assumed that the weak bit is bit "1" and the strong bit is bit "0". The soft bit data SOFT_BIT_DATA can have any data size sent from the non-volatile memory device 200 to the controller 100. Figure 7 The soft bit data SOFT_BIT_DATA in

[0107] is shown as including four weak bits SBD1 to SBD4. Figure 7 In some embodiments, the soft bit data SOFT_BIT_DATA has a size that is a multiple of the number of data pins of the NAND flash memory of the non-volatile memory device 200. For example, Figure 7 the soft bit data SOFT_BIT_DATA in

[0108] can have a size that is 16 times the number of data pins DQ0 to DQ7. In this case, the soft bit data SOFT_BIT_DATA can be 128 bits.

[0108] The soft bit data conversion circuit 261 can convert the soft bit data SOFT_BIT_DATA into input data IN_DATA based on the mapping table MAP_TAB. In some embodiments, the number of index codes in the mapping table MAP_TAB is the same as the number of soft bits in the soft bit data SOFT_BIT_DATA. Each index code forming the mapping table MAP_TAB can be composed of the indexes of the corresponding soft bits in the soft bit data SOFT_BIT_DATA. For example, each index code forming the mapping table MAP_TAB can be a series of index codes of increasing sizes. In this case, the position and / or order of the soft bits in the soft bit data SOFT_BIT_DATA corresponding to the index code can be determined from the index code. For example, Figure 7 the index codes of the mapping table MAP_TAB in Figure 7The index codes MD1, MD2, MD3, and MD4 of the mapping table MAP_TAB in [[]] correspond to the weak bits SBD1, SBD2, SBD3, and SBD4 of the soft bit data SOFT_BIT_DATA, respectively. In this case, the weak bit SBD1 corresponding to the index code "0x0A" MD1 exists at the 11th position and / or order in the soft bit data SOFT_BIT_DATA.

[0109] The input data IN_DATA may include multiple unit data and may be composed of multiple rows.

[0110] In some embodiments, the soft bit data conversion circuit 261 converts the soft bits of each row of the soft bit data SOFT_BIT_DATA into the unit data of each row of the input data IN_DATA. The soft bit data conversion circuit 261 may select the number of soft bits corresponding to the unit data of each row of the input data IN_DATA from the soft bits of each row of the soft bit data SOFT_BIT_DATA, and may generate the input data IN_DATA by preferentially selecting weak bits.

[0111] In some embodiments, when there are no weak bits in a specific row of the soft bit data SOFT_BIT_DATA, the unit data of the corresponding row of the input data IN_DATA may be composed of dummy codes. The dummy codes may be codes not included in the mapping table MAP_TAB. In some embodiments, the number of bit digits of the dummy codes is the same as the number of bit digits of the index codes. Refer to Figure 7 , the rows of the soft bit data SOFT_BIT_DATA other than the 2nd, 7th, 10th, and 16th rows do not include weak bits. Therefore, the rows of the input data IN_DATA other than the 2nd, 7th, 10th, and 16th rows may be composed of dummy codes (0xFF). The unit data of the 2nd, 7th, 10th, and 16th rows of the input data IN_DATA may be composed of the index codes of the weak bits of the 2nd, 7th, 10th, and 16th rows of the soft bit data SOFT_BIT_DATA, respectively. For example, refer to Figure 7 , the unit data ID1, ID2, ID3, and ID4 of the 2nd, 7th, 10th, and 16th rows of the input data IN_DATA are each composed of the index codes MD1, MD2, MD3, and MD4 corresponding to the weak bits SBD1, SBD2, SBD3, and SBD4 of the soft bit data SOFT_BIT_DATA.

[0112] Figure 8 is a diagram for describing the input data IN_DATA according to some embodiments of the present disclosure. Refer to Figure 8 , each row of the input data IN_DATA may include multiple unit data. For example,Figure 7 In the example, each line of the first input data IN_DATA_1 consists of one unit of data, each line of the second input data IN_DATA_2 consists of two units of data, and each line of the third input data IN_DATA_3 consists of three units of data. When the number of weak bits in the corresponding line of the soft bit data SOFT_BIT_DATA is less than the number of units of data in the line of the input data IN_DATA, the remaining units of data other than the units of data corresponding to the weak bits may be composed of dummy codes. When the number of weak bits in the corresponding line of the soft bit data SOFT_BIT_DATA is greater than the number of units of data in the line of the input data IN_DATA, some of the index codes corresponding to the weak bits may be discarded (or lost). For example, when there are four weak bits in the 14th line of the soft bit data SOFT_BIT_DATA corresponding to the 14th line of the third input data IN_DATA_3, one weak bit may be discarded.

[0113] Figure 9 is a diagram showing a stage compression circuit SCC according to some embodiments of the present disclosure. Figure 9 The stage compression circuit SCC may include Figure 1 and Figure 4 at least one compression stage "stage i" among a plurality of compression stages ST_1, ST_2, ……

[0114] Referring to Figure 9 , the stage compression circuit SCC may generate output data OUT_DATA by compressing the input data IN_DATA. For example, the stage compression circuit SCC may compress the input data IN_DATA_1 and IN_DATA_2 to generate output data OUT_DATA_1 and OUT_DATA_2, respectively. The input data IN_DATA may correspond to Figure 7 the input data IN_DATA. The input data IN_DATA and the output data OUT_DATA include multiple units of data, and each of the units of data may be composed of one of an index code and a dummy code.

[0115] The stage compression circuit SCC may compress the input data IN_DATA based on a preset stage compression ratio. For example, Figure 9 the stage compression circuit SCC may compress the input data IN_DATA having eight units of data based on a stage compression ratio of 2:1 to generate output data OUT_DATA having four units of data.

[0116] The stage compression circuit SCC can generate the output data OUT_DATA by selecting at least one piece of cell data among multiple pieces of cell data of the input data IN_DATA. The stage compression circuit SCC can select the same number of pieces of cell data as the number of cell data of the output data OUT_DATA (the number corresponding to the stage compression ratio) among the multiple pieces of cell data of the input data IN_DATA. In some embodiments, the stage compression circuit SCC generates the output data OUT_DATA by preferentially selecting index codes from the cell data of the input data IN_DATA.

[0117] Referring to Figure 9 , among the cell data of the input data IN_DATA_1, the cell data including the index codes I1 and I2 are each selected as the cell data of the output data OUT_DATA_1. The remaining cell data of the output data OUT_DATA_1 are composed of dummy codes. In addition, among the cell data of the input data IN_DATA_2, the cell data including the index codes I3, I4, I5, and I7 are selected as the cell data of the output data OUT_DATA_2. The index code I6 that exceeds the number of cell data of the output data OUT_DATA_2 can be discarded. The following will refer to Figure 11 and Figure 12 to describe the method by which the stage compression circuit SCC selects at least one piece of cell data among multiple pieces of cell data of the input data IN_DATA.

[0118] The stage compression circuit SCC according to some embodiments generates the output data OUT_DATA by selecting at least one piece of cell data among multiple pieces of cell data of the input data IN_DATA. However, since the stage compression circuit SCC preferentially selects index codes, the input data IN_DATA and the output data OUT_DATA may include at least one identical index code. Even when multiple stage compression circuits are connected in series or the same stage compression circuit repeatedly performs compression, the same index code may be included. Therefore, the input data and the output data of the compression circuit 260 composed of multiple stages may include at least one identical index code. When at least one identical index code is represented as bit data, the input data and the output data of the compression circuit 260 may include at least a part in the same bit sequence. The number of bit digits of the same bit sequence may be a multiple (including a multiple of 1) of the number of bit digits of the index code.

[0119] Figure 10 is a diagram showing multiple compression stages of a compression circuit according to some embodiments of the present disclosure. Figure 10 The compression circuit 260 of Figure 1 and Figure 4 may correspond to the compression circuit 260 of Figure 10It is shown that the compression circuit 260 consists of three compression stages STAGE_1, STAGE_2, and STAGE_3, and includes three stage compression circuits 262, 263, and 264. However, the compression circuit 260 may consist of more or fewer compression stages, or may include more or fewer stage compression circuits.

[0120] Referring Figure 10 , in the compression circuit 260, each of the multiple compression stages STAGE_1, STAGE_2, and STAGE_3 may be executed by each of the multiple stage compression circuits 262, 263, and 264. For example, the first compression stage STAGE_1 may be executed by the first stage compression circuit 262, the second compression stage STAGE_2 may be executed by the second stage compression circuit 263, and the third compression stage STAGE_3 may be executed by the third stage compression circuit 264.

[0121] Each of the multiple stage compression circuits 262, 263, and 264 corresponding to each of the multiple compression stages STAGE_1, STAGE_2, and STAGE_3 may compress the input data based on the stage compression ratio. The stage compression ratio of each of the multiple compression stages STAGE_1, STAGE_2, and STAGE_3 may be the same as or different from each other. For example, each of the stage compression circuits 262, 263, and 264 may compress the input data based on the same or different stage compression ratios.

[0122] The compression ratio of the soft bit data SBD may be obtained through compression in each of the multiple compression stages STAGE_1, STAGE_2, and STAGE_3. For example, when all of the multiple compression stages STAGE_1, STAGE_2, and STAGE_3 perform compression based on the stage control signal SCS, the value given by the multiple of the stage compression ratio of each of the multiple compression stages STAGE_1, STAGE_2, and STAGE_3 may be the compression ratio of the compression circuit 260.

[0123] In some embodiments (for example, when the compression circuit 260 includes multiple stage compression circuits and when the multiple stage compression circuits are connected in series and have a structure in which the output data of one stage compression circuit is provided to another stage compression circuit), the input and output between the multiple stage compression circuits may be controlled by the stage control signal. For example, referring Figure 10 , based on the stage control signal SCS[1] provided by the Figure 1 and Figure 4 control logic circuit 210, the output data of the first stage compression circuit 262 may or may not be provided to the second stage compression circuit 263. Based on the stage control signal SCS[2], the output data of the second stage compression circuit 263 may or may not be provided to the third stage compression circuit 264.

[0124] In some embodiments, multiple compression stages STAGE_1, STAGE_2, and STAGE_3 perform compression sequentially. When a compression stage does not perform compression, the subsequent compression stages may also not perform compression. For example, when the stage control signal SCS[1] is a signal that does not provide the output data of the first-stage compression circuit 262 to the second-stage compression circuit 263, the stage control signal SCS[2] may also be a signal that does not provide the output data of the second-stage compression circuit 263 to the third-stage compression circuit 264. Therefore, the output data of the first-stage compression circuit 262 is output as the compressed soft-bit data CSBD1. As described above, when the stage control signals SCS[0] and SCS[1] are control signals that provide input data to the corresponding stage compression circuits 262 and 263, and when the stage control signal SCS[2] is a control signal that controls not to provide input data to the corresponding stage compression circuit 264, the output data of the second-stage compression circuit 263 is output as the compressed soft-bit data CSBD2. When the stage control signals SCS[0], SCS[1], and SCS[2] are control signals that provide input data to the corresponding stage compression circuits 262, 263, and 264, the output data of the third-stage compression circuit 264 is output as the compressed soft-bit data CSBD3.

[0125] In some embodiments, the hard-bit data HARD_BIT_DATA is not compressed (not provided to the stage compression circuits 262, 263, 264) in the multiple compression stages STAGE_1, STAGE_2, and STAGE_3 by the stage control signal SCS[0], and may be output as the output data OUT_DATA of the compression circuit 260.

[0126] Figure 11 is a diagram showing compression in the multiple stage compression circuits of a compression circuit according to some embodiments of the present disclosure. Figure 11 The stage compression circuits 262, 263, and 264 of Figure 9 may be associated with the stage compression circuit SCC of Figure 10 and the stage compression circuits 262, 263, and 264 of Figure 11 The compression circuit 260 of Figure 1 , Figure 4 and Figure 10corresponds to the compression circuit 260. A description will be given under the assumption that, based on the stage control signal, all the stage compression circuits 262, 263, and 264 of the compression circuit 260 perform compression based on the same stage compression ratio (SR1 = SR2 = SR3 = 2:1). However, in some embodiments, only some of the stage compression circuits 262, 263, and 264 perform compression based on the stage control signal, and the output data of any one of the stage compression circuits can be output as the output data OUT_DATA of the compression circuit 260. For example, the output data of any stage compression circuit can be output as the compressed soft bit data.

[0127] Referring to Figure 11 , the compression circuit 260 may include a plurality of stage compression circuits 262, 263, and 264. The first stage compression circuit 262 may receive the input data IN_DATA, which is obtained by converting the soft bit data SOFT_BIT_DATA using Figure 7 the soft bit data conversion circuit 261. As an example, Figure 11 the input data IN_DATA in

[0128] each of the first stage compression circuit 262, the second stage compression circuit 263, and the third stage compression circuit 264 may select one of the respective two unit data (referred to as shard input data) of the input data provided to each stage compression circuit based on each of the first stage compression ratio (SR1 = 2:1), the second stage compression ratio (SR2 = 2:1), and the third stage compression ratio (SR3 = 2:1) to generate one unit data of each of the first compressed soft bit data CSBD1, the second compressed soft bit data CSBD2, and the third compressed soft bit data CSBD3. The first stage compression circuit 262 may compress the input data IN_DATA to generate the first compressed soft bit data CSBD1, the second stage compression circuit 263 may compress the first compressed soft bit data CSBD1 to generate the second compressed soft bit data CSBD2, and the third stage compression circuit 264 may compress the second compressed soft bit data CSBD2 to generate the third compressed soft bit data CSBD3. Each of the first stage compression circuit 262, the second stage compression circuit 263, and the third stage compression circuit 264 may preferentially select the unit data composed of the index code among the unit data of the provided input data. In addition, in some embodiments, when there are multiple unit data composed of the index code, the unit data with a smaller index code may be selected first. In some embodiments, when there are multiple unit data composed of the index code, the unit data with a larger index code may be selected first.

[0129] Each of the first-stage compression circuit 262, the second-stage compression circuit 263, and the third-stage compression circuit 264 can select and compress the unit data of the provided input data based on each of the first-stage compression ratio (SR1 = 2:1), the second-stage compression ratio (SR2 = 2:1), and the third-stage compression ratio (SR3 = 2:1). As a result, the third-compressed soft bit data CSBD3 can be output as the output data OUT_DATA of the compression circuit 260. Therefore, the compression ratio of the compression circuit 260 with respect to the input data IN_DATA is 8:1 (= 12.5%), which is the product of the first-stage compression ratio (SR1 = 2:1), the second-stage compression ratio (SR2 = 2:1), and the third-stage compression ratio (SR3 = 2:1). When the first-compressed soft bit data CSBD1, which is the output data of the first-stage compression circuit 262, is output as the output data OUT_DATA of the compression circuit 260, the compression ratio of the compression circuit 260 is 2:1 (= 50%). In addition, when the second-compressed soft bit data CSBD2, which is the output data of the second-stage compression circuit 263, is output as the output data OUT_DATA of the compression circuit 260, the compression ratio of the compression circuit 260 is 4:1 (= 25%). Therefore, Figure 1 and Figure 4 the control logic circuit 210 of can obtain a target compression ratio (e.g., 50%, 25%, or 12.5%) by sending appropriate corresponding stage control signals that control whether to perform compression on each stage compression circuit. In one example, the control logic circuit 210 can control the number of stages utilized in the multiple compression stages based on the target compression ratio.

[0130] Figure 1 and Figure 4 the ECC block 170 of the controller 100 of can extract index codes from the compressed soft bit data. The ECC block 170 can generate soft bit data based on Figure 7 the mapping table MAP_TAB and the compression ratio. For example, when decompressing the third-compressed soft bit data CSBD3, soft bit data can be generated by extracting the index codes "0x0A" and "0x48" from the third-compressed soft bit data CSBD3 and by adding weak bits to the positions corresponding to the index codes "0x0A" and "0x48" in the soft bit data equal to the size of the mapping table MAP_TAB. In some embodiments, the number of 16 rows of soft bit data can be determined by multiplying the number of extracted index codes by the compression ratio (8:1), and the number of 8 columns of soft bit data can be determined based on the number of data pins DQ. The ECC block 170 can generate soft bit data by adding weak bits to the positions corresponding to the index codes "0x0A" and "0x48" in the soft bit data whose size is determined.

[0131] Figure 12It is a diagram showing another example of the compression of a multi-stage compression circuit by a compression circuit. Figure 12 The stage compression circuits 262a and 263a of Figure 9 can correspond to the stage compression circuit SCC of Figure 12 The compression circuit 260a of Figure 1 、 Figure 4 and Figure 10 can correspond to the compression circuit 260 of Figure 11 Unless otherwise emphasized or suggested by context, additional descriptions of elements or characteristics that are the same or similar to the corresponding elements or characteristics of Figure 12 will be omitted to avoid redundancy and can be similarly applied to

[0132] Referring to Figure 12 , the compression circuit 260a includes two stage compression circuits 262a and 263a, and each of the stage compression circuits 262a and 263a performs compression based on different stage compression ratios (SR1 = 4:1 and SR2 = 2:1) in response to a stage control signal.

[0133] The input data IN_DATA including 4 pieces of unit data composed of index codes of Figure 12 and 12 pieces of unit data composed of dummy codes is provided to the first stage compression circuit 262a. The first stage compression circuit 262a selects one of the respective four pieces of unit data of the input data IN_DATA based on the first stage compression ratio (SR1 = 4:1) to generate the unit data of the first compressed soft bit data CSBD1. The first stage compression circuit 262a can preferentially select the unit data composed of index codes among the unit data of the input data IN_DATA. For example, referring to Figure 12 , among the unit data of the first to fourth rows of the input data IN_DATA, the unit data of the second row composed of index codes is selected, and the unit data of the first row of the first compressed soft bit data CSBD1 is generated. The unit data of the first compressed soft bit data CSBD1 can be generated by selecting the unit data of the seventh row, the tenth row, and the sixteenth row in the same manner for the remaining unit data (the unit data of the fifth to sixteenth rows) of the input data IN_DATA.

[0134] As described above, the second-stage compression circuit 263a may also compress the first-compressed soft bit data CSBD1 to generate second-compressed soft bit data CSBD2. The second-stage compression circuit 263a selects one of every two unit data of the first-compressed soft bit data CSBD1 based on the second-stage compression ratio (SR2 = 2:1) to generate the unit data of the second-compressed soft bit data CSBD2. Among the unit data of the first to fourth rows of the input data IN_DATA, the unit data of the second row composed of index codes is selected and the unit data of the first row of the first-compressed soft bit data CSBD1 is generated. For example, referring to Figure 12 , any one of the unit data of the first to second rows of the first-compressed soft bit data CSBD1 is generated as the unit data of the first row of the second-compressed soft bit data CSBD2. In this case, in Figure 12 , all the unit data of the first to second rows of the first-compressed soft bit data CSBD1 are composed of index codes. Therefore, in this case, the second-stage compression circuit 263a may select the unit data of the first row with a small index code. Similarly, the unit data of the third row may be selected from among the unit data of the third to fourth rows all composed of index codes. As a result, the unit data of the second and fourth rows are not included in the second-compressed soft bit data CSBD2 and are lost. In this case, it will be understood that lossy compression is performed.

[0135] As in Figure 11 and Figure 12 confirmed in the examples, the index codes included in the input data IN_DATA and the output data OUT_DATA provided to the compression circuit may increase or decrease in the same manner as the mapping table MAP_TAB. Therefore, when the index code increases and when the index code of any unit data of the input data IN_DATA and the output data OUT_DATA is the last index code in the mapping table MAP_TAB, the unit data after the corresponding unit data does not include an index code. When the index code extracted from the compressed soft bit data CSBD is the last index code in the mapping table MAP_TAB, the ECC block 170 may stop extracting the index code from the compressed soft bit data CSBD.

[0136] In addition, since the compression circuit generates output data by selecting at least one unit data from among the unit data of the input data, compression can be performed independently of the bit configuration of the input data. Therefore, since the compression load of the compression circuit is low, compression can be effectively performed.

[0137] Figure 13 is a diagram showing multiple compression stages of a compression circuit according to some embodiments of the present disclosure. Figure 13 The compression circuit 260b ofFigure 1 or Figure 4 corresponds to the compression circuit 260. Figure 13 An example is shown in which the compression circuit 260b includes a single-stage compression circuit 265. Unless otherwise emphasized or suggested by context, additional descriptions of elements or features that are the same as or similar to those of the compression circuit described with respect to Figures 7 to 12 will be omitted to avoid redundancy and may equally apply to Figure 13 .

[0138] Referring to Figure 13 , in order for the compression circuit 260 to perform compression based on multiple stages, the output of the single-stage compression circuit 265 is stored in the memory element 266 and then can be provided again to the single-stage compression circuit 265 based on the stage control signals SCS[0] and SCS[1]. The stage control signals SCS[0] and SCS[1] can be based on the number of stages. Thus, compression of one stage or multiple stages can be performed.

[0139] Figure 14 is a diagram showing changes in the compression ratio of a storage device according to some embodiments of the present disclosure. Figure 14 The change in the compression ratio in Figures 1 to 13 can be performed in the storage device 20 of

[0140] Referring to Figure 14 , the storage device 20 can change the compression ratio of the soft bit data such that the compression circuits 260, 260a, and 260b compress the soft bit data at a first compression ratio CR1 in a first period Term1, compress the soft bit data at a second compression ratio CR2 in a second period Term2, and compress the soft bit data at a third compression ratio CR3 in a third period Term3. The second period Term2 can be a period after the first period Term1, the second compression ratio CR2 can be lower than the first compression ratio CR1, and the third compression ratio CR3 can be lower than the second compression ratio CR2. As time progresses from the first period Term1 to the third period Term3, it can be seen that the number of unit data of the compressed soft bit data CSBDa and CSBDb provided to the controller 100 increases. In one example, the index code CODE_LOSS is discarded. As time progresses from the first period Term1 to the third period Term3, the retention time of the storage device 20 can increase and / or the remaining life can decrease.

[0141] In some embodiments, the first compression ratio CR1, the second compression ratio CR2, and the third compression ratio CR3 may be preset. For example, whether to change the compression ratio and / or when to change the compression ratio may be determined by the controller 100 based on at least one of the retention time of the storage device 20, the remaining life of the non-volatile memory device 200, the occurrence of wear, the failure rate of error correction decoding, the failure rate of hard decoding, the failure rate of soft decoding, and the error bit rate. Optionally, or additionally, whether to change the compression ratio and / or when to change the compression ratio may be determined by the control logic circuit 210 based on at least one of the ratio and / or quantity of weak bits of the soft bit data SBD, the trend of increase in weak bits, etc.

[0142] Figure 15 FIG. is a diagram showing a method by which a non-volatile memory device according to some embodiments of the present disclosure provides a compression ratio change signal to a controller. Figure 15 The compression ratio change signal of may be provided by Figures 1 to 14 the non-volatile memory device 200 to the controller 100.

[0143] The non-volatile memory device 200 may compress the soft bit data at a first compression ratio CR1 in a first period Term1, and may compress the soft bit data at a second compression ratio CR2 in a second period Term2. The first compression ratio CR1 and the second compression ratio CR2 may be preset. The second compression ratio CR2 may be lower than the first compression ratio CR1, and the second period Term2 may be a period after the first period Term1.

[0144] After respectively or simultaneously transmitting the hard bit data HBD1, HBD2, and HBD3, the non-volatile memory device 200 may transmit the compressed soft bit data CSBD1, CSBD2, and CSBD3 corresponding to each of the hard bit data HBD1, HBD2, and HBD3. The compressed soft bit data CSBD1 and CSBD2 may be data compressed based on the first compression ratio CR1, and the compressed soft bit data CSBD3 may be data compressed based on the second compression ratio CR2.

[0145] The compression ratio of the soft bit data may be changed according to a request from the controller 100 or a determination of the non-volatile memory device 200. In this case, before transmitting the compressed soft bit data CSBD3 based on the changed compression ratio CR2, the non-volatile memory device 200 may send a compression ratio change signal CR_CHN composed of compression ratio change codes to the controller 100. The compression ratio change signal CR_CHN may include the same number of unit data as the soft bit data CSBD1 compressed at the first compression ratio CR1. The compression ratio change code may not be included in Figure 7a code in the mapping table MAP_TAB (e.g., not an index code), and can be a code that is not a dummy code. The compression rate change code can be a code having the same number of digit bits as the index code and the dummy code. The compression rate change code may or may not be preset according to the implementation.

[0146] When the compression rate change code is not preset, and when the same number of unit data as the compressed soft bit data CSBD1 is composed of codes not included in the mapping table MAP_TAB and is not a dummy code, the controller 100 may determine that the compression rate is reduced by one level. When the compression rate change code is preset, it may be determined that, corresponding to the reception of the compression rate change signal CR_CHN composed of the preset compression rate change code, the compression rate is reduced by one level.

[0147] In some embodiments, multiple different codes may be used as the compression rate change code. In this case, each time the compression rate is changed (i.e., each time the compression rate is reduced again), the compression rate change signal CR_CHN composed of the new compression rate change code may be sent to the controller 100.

[0148] Figure 16 and Figure 17 is a diagram showing a method by which a non-volatile memory device according to some embodiments of the present disclosure provides a compression rate change signal to a controller. Figure 16 and Figure 17 The compression rate change signal of Figures 1 to 14 may be provided to the controller 100 by the non-volatile memory device 200 of

[0149] The non-volatile memory device 200 may compress the soft bit data SBD at a first compression rate CR1 in a first period Term1, and may compress the soft bit data SBD at a second compression rate CR2 in a second period Term2. The first compression rate CR1 and the second compression rate CR2 may be preset. The second compression rate CR2 may be lower than the first compression rate CR1, and the second period Term2 may be a period after the first period Term1.

[0150] Referring to Figure 16 , the non-volatile memory device 200 may perform compression on the soft bit data SBD based on the first mapping table MAP_TAB_1 corresponding to the first compression rate CR1, and may perform compression on the soft bit data SBD based on the second mapping table MAP_TAB_2 corresponding to the second compression rate CR2. In the compression based on the first mapping table MAP_TAB_1, the last index code "0xFF" of the second mapping table MAP_TAB_2 may be used as a dummy code, and in the compression based on the second mapping table MAP_TAB_2, the last index code "0x7F" of the first mapping table MAP_TAB_1 may be used as a dummy code.

[0151] Referring to Figure 17 Figure 17 , after separately or simultaneously transmitting hard bit data HBD1, HBD2, and HBD3, the non-volatile memory device 200 may transmit compressed soft bit data CSBD1, CSBD2, and CSBD3 corresponding to each of the hard bit data HBD1, HBD2, and HBD3. The compressed soft bit data CSBD1 and CSBD2 may be data compressed based on a first compression ratio CR1, and the compressed soft bit data CSBD3 may be data compressed based on a second compression ratio CR2.

[0152] The controller 100 may determine a change from the first compression ratio CR1 to the second compression ratio CR2 based on a bit configuration of a first bit sequence of a size corresponding to the first compression ratio CR1 (e.g., Figure 17 4 unit data in

[0153] For example, the controller 100 may identify a code of 4 unit data corresponding to the first compression ratio CR1 in the third compressed soft bit data CSBD3, and the third compressed soft bit data CSBD3 is received at a specific time after the compressed soft bit data CSBD1 and CSBD2 based on the first compression ratio CR1. In a first case, when at least part of the codes of the 4 unit data are index codes 0x80 to 0xFE of the second mapping table MAP_TAB_2, it may be determined that the compression ratio is changed. In a second case, when the codes of the 4 unit data are "0xFF, 0x7F, 0x7F, and 0x7F", it may be determined that the compression ratio is changed. In this case, the code "0xFF" may be a dummy code used in the compression based on the first compression ratio CR1 or the last index code indicating a weak bit used in the compression based on the second compression ratio CR2. When the code "0xFF" is an index code used in the compression based on the second compression ratio CR2, the code "0xFF" is the last index code indicating a weak bit, so no index code may appear thereafter. In addition, when the code "0xFF" is a dummy code used in the compression based on the first compression ratio CR1, the next three codes different from "0xFF" should be dummy codes, so the same code may be repeated. Therefore, when the codes of the 4 unit data are "0xFF, 0x7F, 0x7F, and 0x7F", it may be determined that the compression ratio is changed.

[0154] As another example, the controller 100 may identify the codes of two unit data in the third compressed soft bit data CSBD3, and the third compressed soft bit data CSBD3 is received at a specific time after the compressed soft bit data CSBD1 and CSBD2 based on the first compression ratio CR1. In the first case, when the codes of the two unit data are different from each other and are the index codes 0x00 to 0x7F of the first mapping table MAP_TAB_1, it may be determined that the compression ratio is maintained. In the second case, when the codes of the two unit data are "0xFF and 0xFF" respectively, it may be determined that the compression ratio is maintained. When the compression ratio is changed and compression is performed based on the second mapping table MAP_TAB_2, the code "0xFF" is the index code of the second mapping table MAP_TAB_2, so the index codes may not be repeated. Therefore, the controller 100 may determine that the compression ratio is maintained.

[0155] Figure 18 is a diagram for illustrating an operation method of a storage device according to some embodiments of the present disclosure. The method may be performed, for example, by Figure 1 , Figure 2 and Figure 3 's storage device 20.

[0156] In operation S110, the controller 100 may send a soft read command to the non-volatile memory device 200. The soft read command may be a command instructing the non-volatile memory device 200 to perform a soft decision process on the memory cells using a soft read voltage.

[0157] In operation S120, the non-volatile memory device 200 may generate soft bit data in response to the soft read command. For example, the soft bit data may be the soft bit data SOFT_BIT_DATA described with reference to Figure 7 . The soft bit data may be composed of multiple soft bits sensed by soft decision. The soft bits may include strong bits and / or weak bits.

[0158] In operation S130, the control logic circuit 210 of the non-volatile memory device 200 may provide a stage control signal to the compression circuit 260 to control the compression circuit 260 through multiple compression stages. The multiple compression stages may correspond to the compression stages ST_1, ST_2,... of Figure 1 , Figure 10 's compression stages STAGE_1, STAGE_2, and STAGE_3, and Figure 13 's compression stage "stage K" (where K is a natural number greater than or equal to 1 but less than or equal to n, and n is a natural number greater than or equal to 2). Each of the multiple compression stages may be performed by each of the different multiple stage compression circuits as shown in Figure 10 , or may be repeatedly performed by the same stage compression circuit as shown in Figure 13 .

[0159] The compression circuit 260 may control whether to perform compression in each of a plurality of compression stages based on a stage control signal, and may generate compressed soft bit data obtained by compressing the soft bit data. The compression ratio of the soft bit data may be obtained by the stage compression ratio of each of the plurality of compression stages in which compression is performed.

[0160] At least some of the plurality of compression stages may generate output data by compressing the input data of the compression stage based on a stage control signal. The input data and the output data of the compression stage include a plurality of unit data, and each unit data may be composed of one of an index code and a dummy code. The index code may indicate the position and / or order of weak bits in the soft bit data SOFT_BIT_DATA. The index code of the input data input to the compression circuit 260 may be determined based on a mapping table.

[0161] At least some of the plurality of compression stages may generate output data by selecting at least one unit data among the plurality of unit data of the input data based on a stage control signal.

[0162] In operation S140, the non-volatile memory device 200 may send the compressed soft bit data to the controller 100. The controller 100 may decompress the compressed soft bit data, may extract the index code, and may generate the soft bit data by using the extracted index code based on the mapping table. The controller 100 may perform error correction decoding based on the generated soft bit data.

[0163] According to some embodiments, a storage device and an operation method thereof may improve the lifespan and / or performance of the storage device.

[0164] According to some embodiments, a storage device and an operation method thereof may improve the lifespan and / or performance of the storage device by compressing soft bit data in a non-volatile memory device and then sending the compressed soft bit data to a controller.

[0165] According to some embodiments, a storage device and an operation method thereof may effectively change the compression ratio of soft bit data.

[0166] Although this disclosure contains many specific implementation details, these should not be construed as limitations on the scope that can be claimed. Specific features described in the context of separate embodiments in this disclosure may also be combined in a single embodiment to be implemented. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. In addition, although the above features may be described as acting in a specific combination, in some cases one or more features from the combination may be deleted from the combination, and the combination may refer to a sub-combination or a variation of the sub-combination.

[0167] Although the present disclosure has been described with reference to various examples, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A storage device, comprising: A non-volatile memory device configured to store and read user data; And A controller configured to control the non-volatile memory device, Wherein, the non-volatile memory device includes: A memory cell array including a plurality of memory cells configured to store data bits corresponding to user data; A compression circuit configured to compress soft-bit data sensed from the plurality of memory cells at multiple compression levels; and Control logic configured to send a stage control signal to the compression circuit, Wherein, the stage control signal controls whether to perform compression in each of the multiple compression levels.

2. The storage device according to claim 1, wherein, The input data and output data of each of the multiple compression levels include at least one identical index code, and Wherein, the at least one identical index code corresponds to the position of weak bits in the soft-bit data.

3. The storage device according to claim 1, wherein, In at least one of the multiple compression levels, the output data generated by compressing the input data in a previous compression level is compressed at a preset compression rate.

4. The storage device according to claim 1, wherein, The control logic is configured to send different stage control signals to the compression circuit based on the compression rate for the soft-bit data.

5. The storage device according to claim 1, wherein Each of the multiple compression levels is executed by a corresponding stage compression circuit among a plurality of stage compression circuits included in the compression circuit, and Wherein, each of the plurality of stage compression circuits is configured to: Receive input data including multiple pieces of cell data; and Select at least a part of the multiple pieces of cell data as output data, Wherein, each of the multiple pieces of cell data is composed of one of a dummy code and an index code, and Wherein, the index code corresponds to the position of weak bits in the soft-bit data.

6. The storage device according to claim 5, wherein, The configuration of the input and output between the multiple stage compression circuits is controlled by the stage control signal.

7. The storage device according to claim 5, wherein, The compression circuit includes: a conversion circuit configured to convert weak bits of the soft-bit data into index codes based on a preset mapping table, and Wherein, the preset mapping table represents the mapping between the index code and the position or order of soft bits included in the soft-bit data.

8. The storage device according to claim 5, wherein, The multiple compression levels include: a first compression level and a second compression level, Wherein, the plurality of stage compression circuits includes: a first stage compression circuit configured to execute the first compression level; and a second stage compression circuit configured to execute the second compression level, and Wherein, each of the first stage compression circuit and the second stage compression circuit is configured to generate corresponding output data by selecting a part of the cell data from the corresponding input data based on the corresponding stage compression rate.

9. The storage device according to claim 8, wherein, The corresponding stage compression rates of the first stage compression circuit and the second stage compression circuit are different.

10. The storage device according to claim 5, wherein, Each of the plurality of stage compression circuits is configured to preferentially select index codes when selecting at least a part of the multiple pieces of cell data.

11. The storage device according to claim 1, wherein, The control logic is configured to control the number of levels utilized in the multiple compression levels based on the target compression rate.

12. The storage device according to claim 1, wherein, The compression circuit is configured to compress the soft-bit data at a first compression rate during a first time period and compress the soft-bit data at a second compression rate during a second time period, Wherein, the second time period is a time period after the first time period, and Wherein, the second compression rate is less than the first compression rate.

13. The storage device according to claim 12, wherein, The control logic is configured to provide a compression rate change signal to the controller in response to a change from a first compression rate to a second compression rate, wherein the compression circuit is configured to generate output data by compressing input data including an index code and a dummy code, wherein the compression circuit is configured to generate a compression rate change signal including a code not included in the mapping table, and wherein the index code includes a code converted from weak bits of soft bit data based on a mapping table, and the mapping table represents a mapping between the index code and the position or order of the soft bits included in the soft bit data.

14. The storage device according to claim 12, wherein, The compression circuit is configured to generate output data by compressing input data including an index code and a dummy code, wherein the compression circuit is configured to perform compression based on a first mapping table when using the first compression rate and perform compression based on a second mapping table when using the second compression rate, wherein the controller is configured to determine a change from the first compression rate to the second compression rate based on the bit configuration of a first bit sequence having a size corresponding to the first compression rate in the output data, and wherein the index code includes a code converted from weak bits of soft bit data based on one of a mapping table including the first mapping table and the second mapping table, and the mapping table represents a mapping between the index code and the position or order of the soft bits included in the soft bit data.

15. The storage device according to claim 14, wherein, The compression circuit is configured to use the last index code of the second mapping table as a dummy code when using the first compression rate and perform compression using the last index code of the first mapping table when using the second compression rate.

16. The storage device according to claim 1, wherein, The compression rate applied by the compression circuit is independent of the bit configuration of the input data.

17. The storage device according to claim 16, wherein, The compression rate applied by the compression circuit is changed based on the remaining life of the memory cell array.

18. A data processing method, comprising: sending, by the controller, a soft read command to a non-volatile memory device, the controller being configured to control the non-volatile memory device; generating, by the non-volatile memory device in response to the soft read command, soft bit data; providing, by a control logic circuit of the non-volatile memory device, a stage control signal to the compression circuit to control compression by the compression circuit in a plurality of compression stages; generating, by the compression circuit, compressed soft bit data by compressing the soft bit data based on the stage control signal; and sending, by the non-volatile memory device, the compressed soft bit data to the controller, wherein the stage control signal controls whether to perform compression in each of the plurality of compression stages.

19. The data processing method according to claim 18, further comprising: changing, by the control logic circuit, the compression rate applied by the compression circuit; and sending, by the control logic circuit, a signal corresponding to the change in the compression rate to the controller.

20. A storage device, comprising: a non-volatile memory device configured to store and read user data; and a controller configured to control the non-volatile memory device, wherein the non-volatile memory device includes: a memory cell array including a plurality of memory cells configured to store data bits corresponding to user data; a plurality of compression circuits configured to compress soft bit data sensed from the plurality of memory cells; and A control logic circuit configured to control the plurality of compression circuits, wherein the plurality of compression circuits includes: A conversion circuit configured to convert soft bit data into input data including an index code and a dummy code based on a mapping table; A first compression circuit configured to compress the input data at a first compression rate to obtain first output data; A second compression circuit configured to receive the first output data from the first compression circuit and generate second output data by compressing the first output data at a second compression rate, wherein the control logic circuit controls whether to provide the first output data to the second compression circuit based on a target compression rate for the soft bit data.

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