Preparation method of N-polar gallium nitride material

Abstract

The invention provides a preparation method of an N-polar gallium nitride material, which can be applied to the technical field of compound semiconductor materials. The method comprises the following steps: carrying out ion implantation on a Ga polar Si-based GaN wafer to a specified depth, bonding a GaN functional layer with a target wafer, and carrying out reinforcing annealing; stripping the GaN functional layer and the buffer layer from the Si substrate through stripping annealing; performing repair annealing on the stripped N-polarity GaN functional layer; and finally, removing the residual Si substrate and the buffer layer to obtain the N-polarity gallium nitride material on the target wafer. According to the method, mechanical polishing and chemical mechanical polishing processes are not needed, the GaN functional layer is prevented from being damaged, and therefore an alternative preparation scheme of the N-polarity gallium nitride material is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of compound semiconductor materials, and particularly relates to a method for preparing N-polar gallium nitride materials. Background Art

[0002] Compared with traditional gallium-polar gallium nitride materials, nitrogen (N)-polar gallium nitride has a natural back-barrier structure, a high two-dimensional electron gas concentration, and a lower contact resistance, and can realize high-performance W-band GaN HEMT power devices. However, the preparation of N-polar gallium nitride materials still faces many challenges. The main difficulty is that the surface of directly epitaxially grown N-polar gallium nitride materials has a large number of hexagonal mound-shaped protrusions, a large surface roughness, a high density of material dislocation defects, and serious oxygen impurity contamination at the same time. Summary of the Invention

[0003] In view of the above problems, the present disclosure provides a method for preparing N-polar gallium nitride materials. This method does not require mechanical polishing and chemical mechanical polishing processes, avoiding damage to the GaN functional layer, thereby realizing an alternative preparation scheme for N-polar gallium nitride materials.

[0004] According to an embodiment of the present disclosure, a method for preparing N-polar gallium nitride materials is provided, including the following steps: ion-implanting a Ga-polar Si-based GaN wafer to a specified depth. The Ga-polar Si-based GaN wafer includes a GaN functional layer, a buffer layer, and a Si substrate stacked in sequence. The GaN functional layer includes a GaN layer; ions are implanted from the GaN functional layer; the specified depth is greater than the total thickness of the GaN functional layer and the buffer layer; bonding the GaN functional layer to a target wafer and performing strengthening annealing; performing peeling annealing to peel the GaN functional layer and the buffer layer from the Si substrate; performing repair annealing on the GaN functional layer; removing the remaining Si substrate and buffer layer.

[0005] According to an embodiment of the present disclosure, the buffer layer includes a stack of one or more of an AlN layer, an aluminum gallium nitride layer, and a GaN layer.

[0006] According to an embodiment of the present disclosure, the GaN functional layer includes a stack of one or more of a GaN layer, an AlN layer, an aluminum gallium nitride layer, an aluminum indium nitride layer, an aluminum gallium indium nitride layer, a gallium indium nitride layer, and an InN layer.

[0007] According to an embodiment of the present disclosure, the total thickness of the buffer layer and the GaN functional layer is less than or equal to 2 μm.

[0008] According to an embodiment of the present disclosure, the Ga-polarity Si-based GaN wafer includes a protective layer; the protective layer is located on the surface of the GaN functional layer away from the buffer layer; the specified depth is greater than the total thickness of the protective layer, the GaN functional layer, and the buffer layer; after ion implantation, the method further includes a step of removing the protective layer. The protective layer includes a stacked structure of one or more of an AlN layer, an SiO2 layer, and a SiN mixed layer.

[0009] According to an embodiment of the present disclosure, the types of ions include one or more of H, He, B, and Ar ions; the energy E of ion implantation satisfies: 10 keV ≤ E ≤ 400 keV.

[0010] According to an embodiment of the present disclosure, the target wafer is one of SiC, diamond, AlN, BN, and Si.

[0011] According to an embodiment of the present disclosure, the bonding includes surface-activated bonding or hydrophilic bonding; the temperature T1 of the reinforcement annealing satisfies: 100 °C ≤ T1 ≤ 400 °C.

[0012] According to an embodiment of the present disclosure, the temperature T2 of the peeling annealing satisfies: 200 °C ≤ T2 ≤ 600 °C.

[0013] According to an embodiment of the present disclosure, the temperature T3 of the repair annealing satisfies: 500 °C ≤ T3 ≤ 1100 °C.

[0014] One or more of the above embodiments have the following beneficial effects:

[0015] The embodiments of the present disclosure use high-quality thin films obtained by a mature Ga-polarity GaN thin film preparation process, and then based on the Smart Cut and bonding technologies of Si, the polarity inversion is realized through the flipping of the bonded wafers. Thus, the Ga-polarity GaN functional layer is transformed into an N-polarity on the target wafer. Compared with the directly epitaxial N-polarity GaN functional layer, due to the use of a mature Ga-polarity GaN thin film preparation process, the transferred N-polarity GaN functional layer also has advantages in controlling the dislocation density and oxygen impurity concentration.

[0016] In the embodiments of the present disclosure, the ion implantation damage layer is located inside the Si substrate, and the separation interface is far from the GaN functional layer during the annealing process, reducing the risk of damage to the GaN functional layer during the film transfer process. After peeling, the remaining silicon thin film and buffer layer are removed. Since the corrosion / etching selectivity of silicon and gallium nitride is very good, by selecting a suitable etching method, optimizing etching process parameters, etc., it is easy to achieve good corrosion / etching selectivity between silicon and gallium nitride and protect the surface of the GaN functional layer. Therefore, this method can obtain a low-damage and smooth surface of the GaN functional layer without mechanical polishing and chemical mechanical polishing processes, effectively avoiding the problem of local over-polishing of the GaN functional layer. Description of the Drawings

[0017] Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above content and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0018] Figure 1 Schematically shows a flowchart of a method for preparing an N-polar gallium nitride material according to an embodiment of the present disclosure.

[0019] Figure 2 Schematically shows a structural diagram of a Ga-polar Si-based GaN wafer according to an embodiment of the present disclosure.

[0020] Figure 3 Schematically shows a flowchart of another method for preparing an N-polar gallium nitride material according to an embodiment of the present disclosure.

[0021] Figure 4 Schematically shows a structural diagram of an N-polar gallium nitride material obtained by the preparation method according to an embodiment of the present disclosure.

[0022] In the figure, 10 is a Si substrate, 20 is a buffer layer, 30 is a GaN functional layer, 11 is a hydrogen ion implantation layer, 12 is a Si thin film, 40 is a target wafer, and 111 is a peeling damage layer.

[0023] It should be noted that, for clarity, in the drawings used to describe the embodiments of the present disclosure, the size of the overall / local structure or the overall / local area may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. Detailed implementation manners

[0024] Hereinafter, the embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, the description of well-known structures and technologies is omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0025] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0026] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0027] In the case of using expressions such as "one or more of A, B, and C", generally, it should be interpreted according to the meaning that those skilled in the art usually understand this expression (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0028] In order to make the objectives, technical solutions, and advantages of the present invention more clearly understood, the following further elaborates on the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0029] As Figure 1 shown, embodiments of the present disclosure provide a method for preparing an N-polar gallium nitride material, including the following steps:

[0030] In step 1, ion implantation is performed on a Ga-polar Si-based GaN wafer to a specified depth.

[0031] In step 2, the GaN functional layer is bonded to the target wafer and annealed for strengthening.

[0032] In step 3, a lift-off annealing is performed to strip the GaN functional layer and the buffer layer from the Si substrate.

[0033] In step 4, a repair annealing is performed on the GaN functional layer.

[0034] In step 5, the residual Si substrate and buffer layer are removed. An N-polar gallium nitride material is obtained on the target wafer.

[0035] In the above step 1, the Ga-polar Si-based GaN wafer used can be pre-obtained, which includes a GaN functional layer, a buffer layer, and a Si substrate from top to bottom. The GaN functional layer contains a GaN layer. The GaN functional layer may include one GaN layer, or may include one GaN layer and other material layers for realizing different functions. The arrangement order of the GaN layer and other material layers is not limited, and is arranged according to the specific functions to be realized. The specified depth is greater than the thickness of the GaN functional layer and the buffer layer. By setting the specified depth to be greater than the thickness of the GaN functional layer and the buffer layer, ions can penetrate through the GaN functional layer and the buffer layer into the Si substrate during ion implantation.

[0036] In the above step 2, the Ga-polar Si-based GaN wafer implanted with ions is bonded to the target wafer and annealed for strengthening. The purpose is to perform wafer flipping, so that the polarity of the GaN functional layer changes from Ga polarity to N polarity. The bonding strength between the Ga-polar Si-based GaN wafer and the target wafer can be improved through the strengthening annealing operation.

[0037] In the above step 3, the GaN functional layer and the buffer layer are peeled off from the Si substrate by peel annealing. Since the depth of ion implantation in the embodiments of the present disclosure is greater than the thickness of the GaN functional layer and the buffer layer, the ion implantation damage layer is mainly located inside the Si substrate. During peel annealing, the separation interface is located inside the Si substrate and away from the GaN functional layer. Thus, the risk of damage to the GaN functional layer during the film transfer process is reduced.

[0038] In the above step 4, repair annealing is performed on the GaN functional layer. Although the ion implantation damage layer is mainly located inside the Si substrate, there are still more or less damages caused by implantation in the GaN functional layer. The damage to the GaN functional layer caused by ion implantation is repaired through the repair annealing operation.

[0039] In the above step 5, the method for removing the remaining Si film and the buffer layer includes one or a combination of wet etching and dry etching.

[0040] In the embodiments of the present disclosure, the buffer layer includes a stack of one or more of an AlN layer, an Al x Ga 1-x N layer, and a GaN layer, where 0 < x < 1. When forming a GaN layer on the Si substrate, an AlN layer is first formed as the buffer layer, mainly to overcome the lattice mismatch problem between the Si substrate and the GaN layer, reduce the influence of thermal mismatch, prevent Si atoms from reacting with Ga or N in the GaN layer, and improve the surface properties. The formation of the buffer layer can be to form an AlN layer, an Al x Ga 1-x N layer, and a GaN layer on the silicon substrate in sequence from bottom to top. The Al x Ga 1-x N layer is the aluminum gallium nitride transition layer. The value of x can gradually decrease from 1 to 0. For example, by adjusting the ratio of the input Al and Ga elements, the x value can gradually decrease from 1 to 0.9999, …, 0.999, …, 0.99, …, 0.01, …, 0.001, …, 0.0001, …, and gradually decrease to 0. When the x value is 1, Al x Ga 1-x N is AlN, and when the x value is 0, Al x Ga 1-x N is GaN. This adjustment of the element ratio to achieve the change of the non-stoichiometric compound chemical formula can be realized. Similarly, the ratio of the input Al and Ga elements can also be repeatedly adjusted to achieve other different stacked structures. For example, an AlN layer, an Al x Ga 1-x N layer, a GaN layer, an Al x Ga 1-x N layer, and a GaN layer stack are formed in sequence from bottom to top.

[0041] In the embodiments of the present disclosure, the GaN functional layer includes one or more stacks of a GaN layer, an AlN layer, an Al y Ga 1-y N layer, an Al z In 1-z N layer, an InN layer, an Al m Ga n In 1-m-n N layer, where 0 < y < 1, 0 < z < 1, 0 < m < 1, 0 < n < 1, 0 < p < 1, and 0 < m + n < 1. The Al y Ga 1-y N layer is an aluminum gallium nitride layer, and the Al z In 1-z N layer is an aluminum indium nitride layer, and the Al m Ga n In 1-m-n N layer is an aluminum gallium indium nitride layer, and the Ga p In 1-p N layer is a gallium indium nitride layer. By adjusting the proportions of the input Al, In, and Ga elements, the values of y, z, p, m, and n can be gradually reduced from 1 to 0, or the value of y can be gradually increased from 0 to 1. For example, the values of y, z, p, m, and n can be gradually reduced from 1 to 0.9999, …, 0.999, …, 0.99, …, 0.01, …, 0.001, …, 0.0001, …, and gradually reduced to 0; or the values of y, z, p, m, and n can be gradually reduced from 1 to 0.9999, …, 0.999, …, 0.99, …, 0.01, …, 0.001, …, 0.0001, …, and gradually reduced to 0. For example, a stacked structure of a GaN layer, an Al y Ga 1-y N layer, an AlN layer, an Al y Ga 1-y N layer, and a GaN layer can be formed; or a stacked structure of a GaN layer, an Al y Ga 1-y N layer, an AlN layer, an Al z In 1-z N layer, an Al m Ga n In 1-m-n N layer, a Ga p In 1-p N layer, and an InN layer can be formed; or other stacked structures with different numbers and orders can be formed.

[0042] In the embodiments of the present disclosure, the sum of the thicknesses of the buffer layer and the GaN functional layer is less than 2 μm. For example, the thickness of the buffer layer can be 200 nm and the thickness of the GaN functional layer can be 1 μm; or the thickness of the buffer layer can be 200 nm and the thickness of the GaN functional layer can be 1.8 μm.

[0043] In the embodiments of the present disclosure, the Ga-polarity Si-based GaN wafer may include a protective layer; the protective layer is located on the upper surface of the GaN functional layer. The Ga-polarity Si-based GaN wafer includes a protective layer, a GaN functional layer, a buffer layer, and a Si substrate from top to bottom. The Ga-polarity Si-based GaN wafer may pre-have a protective layer, or a protective layer may be grown on the upper surface of the GaN-polarity Si-based GaN wafer without a protective layer obtained before ion implantation. The protective layer includes a stacked structure of one or more of an AlN layer, an SiO2 layer, and a SiN mixed layer. The SiN mixed layer may be a mixture near the ratio of the stoichiometric compound Si3N4. For example, the atomic ratio of Si to N in the SiN mixed layer may be between 2.5:4 and 3.5:4. The protective layer may be a stacked layer of an AlN layer, an SiO2 layer, and a Si 2.5 N4 layer in sequence, or may be a stacked layer of an AlN layer, an SiO2 layer, and a Si 3.5 N4 layer in sequence, or may be a stacked layer of an AlN layer, an SiO2 layer, a Si3N4 layer, an SiO2 layer, and an AlN layer in sequence. The specified depth of ion implantation in this embodiment is greater than the total thickness of the protective layer, the GaN functional layer, and the buffer layer. During ion implantation, it can pass through the protective layer, the GaN functional layer, and the buffer layer in sequence into the Si substrate. The protective layer is used to reduce the impact of ions on the GaN functional layer during ion implantation. After the ion implantation in this embodiment is completed, it also includes the step of removing the protective layer. The protective layer can be removed by one or a combination of wet etching and dry etching.

[0044] In the embodiments of the present disclosure, the types of ion implantation include one or more of H, He, B, Ar, etc. ions, and the energy E of ion implantation can satisfy: 10 keV ≤ E ≤ 400 keV.

[0045] In the embodiments of the present disclosure, the target wafer is one of SiC, diamond, AlN, BN, and Si. The roughness Rq of the surface of the GaN functional layer and the surface of the target wafer can satisfy: 0.1 nm ≤ Rq ≤ 1 nm. At this roughness, it is beneficial for the Ga-polarity Si-based GaN wafer to bond with the target wafer.

[0046] In the embodiments of the present disclosure, the bonding includes surface activation bonding or hydrophilic bonding. The temperature T1 of the reinforcement annealing satisfies: 100 °C ≤ T1 ≤ 400 °C, and the heating rate from room temperature to the reinforcement annealing temperature is not greater than 20 °C / min. The polarity of the GaN functional layer is changed from Ga polarity to N polarity by flipping the Ga-polarity Si-based GaN wafer.

[0047] In the embodiments of the present disclosure, the temperature T2 of the stripping annealing satisfies: 200°C ≤ T2 ≤ 600°C, and the annealing atmosphere is N2, Ar or a mixed gas thereof. The heating rate from room temperature to the stripping annealing temperature is not greater than 20°C / min. The damage layer of the Ga-polar Si-based GaN wafer is stripped from the Si substrate within this temperature range.

[0048] In the embodiments of the present disclosure, the temperature T3 of the repair annealing satisfies: 500°C ≤ T3 ≤ 1100°C, and the annealing atmosphere is N2, Ar or a mixed gas thereof; the repair annealing is used to repair the damage of the GaN functional layer caused by ion implantation.

[0049] The present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0050] Embodiment 1

[0051] The Ga-polar Si-based GaN wafer structure of this embodiment is as Figure 2 shown, and includes: a Si substrate 10; a buffer layer 20: located on the Si substrate 1, which is a stack of a 100-nm AlN layer, a 50-nm Al x Ga 1-x N layer with x gradually decreasing from 1 to 0, and a 20-nm GaN layer from bottom to top; a GaN functional layer 30: located on the buffer layer 20, which is a 1-μm GaN layer. The target wafer 40 is a SiC wafer.

[0052] The method for preparing the N-polar gallium nitride material provided in this embodiment is as Figure 2 and Figure 3 shown, and includes the following steps:

[0053] Step 1: Grow a 20-nm AlN on the surface of the Ga-polar Si-based GaN wafer as a protective layer, and then inject H ions to a specified depth. The H ions pass through the protective layer, the GaN functional layer 30 and the buffer layer 20 into the Si substrate 1, and the specified depth is 2 μm, that is, the H ion implantation depth is 2 μm from the surface of the protective layer, forming a hydrogen ion implantation layer 11. After the ion implantation is completed, the protective layer is removed by wet etching;

[0054] Step 2: Flip the Ga-polar Si-based GaN wafer, so that the polarity of the GaN functional layer 30 changes from Ga polarity to N polarity, and the surface of the GaN functional layer 30 is surface-activated bonded to the target wafer 40, and the bonding strength is improved by reinforcement annealing. The reinforcement annealing temperature is 350°C, the time is 8 hours, and the heating rate is 5°C / min;

[0055] Step 3: Strip the GaN functional layer 30 and the buffer layer 20 from the Si substrate 10 by stripping annealing. The stripping annealing temperature is 500 °C, the annealing atmosphere is N2, the heating rate is 2 °C / min. After the temperature reaches 500 °C, it is maintained stable until the GaN functional layer 30 and the buffer layer 20 are stripped from the Si substrate 10; at this time, there is still a part of the Si film 12 and the stripping damage layer 111 on its surface on the surface of the buffer layer 20.

[0056] Step 4: Perform repair annealing on the stripped N-polar GaN functional layer 30 to repair the damage caused by ion implantation. The repair annealing temperature is 800 °C, the time is 20 mins, and the annealing atmosphere is N2;

[0057] Step 5: Remove the remaining Si film 12 by wet etching and remove the buffer layer 20 by dry etching, as Figure 4 shown, to obtain the N-polar gallium nitride material on the SiC wafer.

[0058] Example 2

[0059] The Ga-polar Si-based GaN structure of this example includes: Si substrate 10; buffer layer 20: located on the silicon substrate 10, from bottom to top is a 100-nm AlN layer, a 50-nm-thick Al x Ga 1-x N layer stack; GaN functional layer 30: located on the buffer layer 20, successively a 1-μm GaN layer and a 25-nm Al 0.25 Ga 0.75 N layer, and the target wafer 40 is a diamond wafer.

[0060] The method for preparing the N-polar gallium nitride material provided by this example, as Figure 2 and Figure 3 shown, includes the following steps:

[0061] Step 1: Perform H ion implantation on the Ga-polar Si-based GaN wafer to a specified depth. The ions pass through the GaN functional layer 30 and the buffer layer 20 into the silicon substrate interior. The specified depth is 2 μm, that is, the H ion implantation depth is 2 μm from the surface of the GaN functional layer 30.

[0062] Step 2: Flip the Ga-polar Si-based GaN wafer, so that the polarity of the GaN functional layer 30 changes from Ga polarity to N polarity. Bond the surface of the GaN functional layer 30 to the diamond wafer by surface activation bonding, and improve the bonding strength by reinforcement annealing. The reinforcement annealing temperature is 300 °C, the time is 12 hours, and the heating rate is 2 °C / min;

[0063] Step 3: The GaN functional layer 30 and the buffer layer 20 are peeled off from the Si substrate 10 by peel annealing. The peel annealing temperature is 500 °C, the annealing atmosphere is N2, the heating rate is 2 °C / min, and after the temperature reaches 500 °C, it is maintained stable until the GaN functional layer 30 and the buffer layer 20 are peeled off from the Si substrate;

[0064] Step 4: The peeled N-polar GaN functional layer 30 is subjected to repair annealing to repair the damage caused by ion implantation. The repair annealing temperature is 1100 °C, the time is 10 mins, and the annealing atmosphere is N2;

[0065] Step 5: The remaining Si film and the buffer layer 20 are removed by wet etching to obtain an N-polar GaN / AlGaN material on diamond.

[0066] Example 3

[0067] The difference between this example and Example 1 is that the thickness of the buffer layer 20 is 400 nm, and the GaN functional layer 30 includes a stack of a GaN layer, an AlN layer, an aluminum gallium nitride layer, an aluminum indium nitride layer, and an aluminum gallium indium nitride layer. The thickness of the GaN functional layer 30 is 1.6 μm. The surface of the Ga-polar Si-based GaN wafer has a protective layer with a total thickness of 50 nm of SiO2 layer and Si3N4 layer. The target wafer 40 is an AlN wafer.

[0068] Two kinds of ions, He and Ar, are co-implanted to a depth greater than 2.05 μm. The energy E of ion implantation is 400 keV.

[0069] The roughness Rq of the surface of the GaN functional layer 30 and the surface of the AlN wafer is 1 nm.

[0070] The surface of the GaN functional layer 30 and the surface of the AlN wafer are bonded by surface activation bonding, and reinforcement annealing is carried out at 100 °C for 18 hours, and the heating rate is 2 °C / min.

[0071] The temperature T2 of the peel annealing is 200 °C, the annealing atmosphere is N2, and the heating rate is 5 °C / min.

[0072] The temperature T3 of the repair annealing is 500 °C, the time is 60 mins, and the annealing atmosphere is N2. The heating rate is 5 °C / min.

[0073] The remaining Si film is removed by dry etching, and the buffer layer 20 is removed by wet etching.

[0074] Example 4

[0075] The difference between this embodiment and Embodiment 1 is that the thickness of the buffer layer 20 is 200 nm, and the GaN functional layer 30 includes a stack of a GaN layer, an InN layer, and a gallium indium nitride layer. The thickness of the GaN functional layer 30 is 1.2 μm. The surface of the Ga-polar Si-based GaN wafer has a protective layer of a total 50-nm-thick Si3N4 layer. The target wafer 40 is a BN wafer.

[0076] He and H ions are implanted to a depth greater than 2 μm. The energy E of the ion implantation is 100 keV.

[0077] The roughness Rq of the surface of the GaN functional layer 30 and the surface of the BN wafer is 0.1 nm.

[0078] The surface of the GaN functional layer 30 and the surface of the BN wafer are bonded by a hydrophilic bonding method and are annealed for reinforcement at 400 °C with a heating rate of 20 °C / min.

[0079] The temperature T2 of the stripping annealing is 400 °C, the annealing atmosphere is Ar gas, and the heating rate is 20 °C / min.

[0080] The temperature T3 of the repair annealing is 600 °C, and the annealing atmosphere is Ar gas.

[0081] The remaining Si film is removed by dry etching, and the buffer layer is removed by wet etching.

[0082] Embodiment 5

[0083] The difference between this embodiment and Embodiment 2 is that the buffer layer 20 is a GaN layer. The GaN functional layer 30 includes: a 1-μm GaN layer and a 25-nm Al 0.5 Ga 0.5 N layer. The target wafer 40 is a Si wafer.

[0084] He ions are implanted to a depth greater than 2 μm. The energy E of the ion implantation is 10 keV.

[0085] The temperature for the reinforcement annealing is 400 °C, the time is 12 hours, the annealing atmosphere is a mixed gas of N2 and Ar, and the heating rate is 20 °C / min;

[0086] The temperature T2 of the stripping annealing is 600 °C, the annealing atmosphere is a mixed gas of N2 and Ar, and the heating rate is 20 °C / min.

[0087] The temperature T3 of the repair annealing is 1100 °C, the time is 10 mins, the annealing atmosphere is a mixed gas of N2 and Ar. The heating rate is 20 °C / min.

[0088] The remaining Si film and the GaN buffer layer 20 are removed by dry etching.

[0089] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0090] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in the respective embodiments cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A method for preparing N-polar gallium nitride material, characterized in that, It includes the following steps: Ion implant the Ga-polarity Si-based GaN wafer to a specified depth. The Ga-polarity Si-based GaN wafer includes a GaN functional layer, a buffer layer, and a Si substrate stacked in sequence. The GaN functional layer includes a GaN layer. The ions are implanted from the GaN functional layer. The specified depth is greater than the total thickness of the GaN functional layer and the buffer layer. Bond the GaN functional layer to a target wafer and perform strengthening annealing. Perform peeling annealing to peel the GaN functional layer and the buffer layer from the Si substrate. Perform repair annealing on the GaN functional layer. Remove the residual Si substrate and the buffer layer.

2. The method for preparing N-polar gallium nitride material according to claim 1, wherein The buffer layer includes a stack of one or more of an AlN layer, an aluminum gallium nitride layer, and a GaN layer.

3. The method for preparing an N-polar gallium nitride material according to claim 1, wherein The GaN functional layer includes a stack of one or more of a GaN layer, an AlN layer, an aluminum gallium nitride layer, an aluminum indium nitride layer, an aluminum gallium indium nitride layer, a gallium indium nitride layer, and an InN layer.

4. The method for preparing an N-polar gallium nitride material according to claim 1, wherein The total thickness of the buffer layer and the GaN functional layer is less than or equal to 2 μm.

5. The method for preparing an N-polar gallium nitride material according to claim 1, characterized in that, The Ga-polarity Si-based GaN wafer includes a protective layer. The protective layer is located on the surface of the GaN functional layer away from the buffer layer. The specified depth is greater than the total thickness of the protective layer, the GaN functional layer, and the buffer layer. After ion implantation, the method includes the step of removing the protective layer. The protective layer includes a stack of one or more of an AlN layer, an SiO2 layer, and a SiN mixed layer.

6. The method for preparing an N-polar gallium nitride material according to claim 1, wherein The types of the ions include one or more of H, He, B, and Ar ions. The energy E of the ion implantation satisfies: 10 keV ≤ E ≤ 400 keV.

7. The method for preparing N-polar gallium nitride material according to claim 1, wherein The target wafer is one of SiC, diamond, AlN, BN, and Si.

8. The method for preparing an N-polar gallium nitride material according to claim 1, wherein, The bonding includes surface activation bonding or hydrophilic bonding. The temperature T1 of the strengthening annealing satisfies: 100°C ≤ T1 ≤ 400°C.

9. The method for preparing N-polar gallium nitride material according to claim 1, characterized in that, The temperature T2 of the peeling annealing satisfies: 200°C ≤ T2 ≤ 600°C.

10. The method for preparing N-polar gallium nitride material according to claim 1, wherein The temperature T3 of the repair annealing satisfies: 500°C ≤ T3 ≤ 1100°C.

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