Semiconductor packaging method with high wiring density

Abstract

The invention relates to the technical field of chip packaging, in particular to a semiconductor packaging method with high wiring density. Comprising the following steps that S1, a substrate is provided, and an oxide layer is arranged on the surface of one side of the substrate; s2, forming a graphical PI layer; s3, forming a metal seed layer on the surface of the PI layer, forming a metal circuit layer on the surface of the metal seed layer, and grinding and polishing until the surface of the metal circuit embedded in the pit is exposed; s4, repeating the steps S2 to S3 to form a plurality of PI layers and metal circuit layers; s5, carrying out counterpoint bonding, mounting a chip, and carrying out plastic packaging; s6, the substrate is ground and etched, the substrate is removed, and etching stays on the oxide layer; s7, performing graphical windowing on the surface of the oxide layer to expose the metal circuit layer; s8, forming a conductive layer; s9, salient points are formed; and S10, scribing is carried out. Compared with the prior art, the PI layer is adopted to replace an existing inorganic dielectric layer, and the CMP grinding step is changed in a matched mode, so that the internal stress resistance is high, the process steps are simple, and the cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and more specifically to a semiconductor packaging method with high wiring density. Background Art

[0002] In the current packaging field, as the integration level continues to increase, that is, the line width and line pitch are getting smaller and smaller. For the simple RDL process, namely the process of electroplating lines after lithographic resist exposure and development on a metal seed layer, and finally removing the lithographic resist and wet etching the metal seed layer, due to the side etching effect of the wet etching of the metal seed layer on the lines, it is very difficult to make the line width and line pitch of RDL small. Generally, the limit is 2um / 2um line width and line pitch.

[0003] In order to increase the line width and line pitch, the damascene process is generally introduced. The full name is "damascene inlay process". First, a pattern film for etching metal wires is etched on a dielectric layer, then metal is filled into these structures, and finally the excess metal is polished flat by chemical mechanical polishing (CMP) to form a flat surface. The line width and line pitch of this process can reach the sub-micron level. However, the processing objects of CMP are generally metal lines and inorganic dielectric layers, and the dielectric layer has a high hardness, which easily causes stress concentration and cracking. In addition, the patterning process of the inorganic dielectric layer is relatively complex and its cost is relatively high. Summary of the Invention

[0004] The present invention aims to overcome the deficiencies of the prior art and provides a semiconductor packaging method with high wiring density.

[0005] To achieve the above object, a semiconductor packaging method with high wiring density is designed, including the following steps: S1, provide a substrate, and an oxide layer is provided on one surface of the substrate; S2, form a patterned PI layer; S3, on the surface of the PI layer, form a metal seed layer in the pits of the PI layer through physical vapor deposition process, form a metal line layer on the surface of the metal seed layer through electroplating process, and then polish by CMP process until the surface of the metal lines embedded in the pits is exposed; S4, repeat steps S2 to S3 to form several layers of PI layers and metal line layers; S5, perform alignment bonding, mount the chip, and perform plastic encapsulation; S6, grind and etch the substrate, remove the substrate, and the etching stops on the oxide layer; S7, perform patterning and window opening on the surface of the oxide layer to expose the metal line layer; S8, form a conductive layer at the exposed metal line layer through the UBM process; S9, form bumps at the conductive layer; S10, dicing.

[0006] In the step S1, a substrate with a self - contained oxide layer is selected, or an oxide layer is formed on the surface of the substrate through a chemical vapor deposition process.

[0007] In the step S2, a patterned PI layer is formed on the surface of the oxide layer through coating, exposure, development, and baking.

[0008] In the step S5, the connection between the chip and the metal wiring layer is filled with a molding compound through an underfill process, or the whole chip is encapsulated with a molding compound.

[0009] The material of the PI layer is selected as a PI material with a relative dielectric constant of 2.7 to 3.2 and a glass transition temperature ≥ 400 °C.

[0010] In the step S2, the thickness of the PI layer is 3 ± 2 mm.

[0011] In the CMP process of the step S3, the polishing slurry contains 0.5 - 1 wt% of alumina particles, 3 - 4 wt% of silica particles, 2 - 3 wt% of cerium oxide particles, the pH value is controlled to be 12 - 13, the polishing rate is 3000 ± 500 Å / min, and the surface roughness is 200 ± 20 Å.

[0012] In the step S2, pits of the patterned PI layer are formed through photolithography and curing.

[0013] Compared with the prior art, the present invention uses a PI layer to replace the existing inorganic dielectric layer, and in combination with changing the CMP polishing step, it has strong internal stress resistance, simple process steps, and reduced costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a flow schematic diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] The present invention will be further described below with reference to the drawings.

[0016] As Figure 1 shown, the semiconductor packaging method with high wiring density in this embodiment includes the following steps: S1, provide a substrate 1, and an oxide layer 2 is provided on one side surface of the substrate 1; S2, form a patterned PI layer 3; S3, form a metal seed layer in the pits 3 - 1 of the PI layer 3 on the surface of the PI layer 3 through a physical vapor deposition process, form a metal wiring layer 4 on the surface of the metal seed layer through an electroplating process, and then polish by a CMP process until the surface of the metal wiring embedded in the pits 3 - 1 is exposed; S4. Repeat steps S2 to S3 to form multiple layers of PI layer 3 and metal wiring layer 4; S5. Perform alignment bonding, mount chip 5, and encapsulate; S6. Grind and etch substrate 1, remove substrate 1, and stop etching on oxide layer 2. Oxide layer 2 serves as a cutoff and can well protect the RDL circuit from etching attack; S7. Pattern and open windows on the surface of oxide layer 2 to expose metal wiring layer 4; S8. Form conductive layer 6 at the exposed metal wiring layer 4 through UBM process; S9. Form bumps 7 at conductive layer 6; S10. Dicing.

[0017] In step S1, select a substrate with a self - contained oxide layer 2 or form an oxide layer on the surface of substrate 1 through chemical vapor deposition process.

[0018] In step S5, fill the encapsulant 8 at the connection between chip 5 and metal wiring layer 4 or wrap chip 5 with encapsulant 8 through underfill process.

[0019] Since PI layer 3 is used as an insulating layer in high - density wiring, a lower relative dielectric constant is required to reduce its parasitic capacitance. Select a PI material with a relative dielectric constant of 2.7 to 3.2, which is significantly lower than the relative dielectric constant of silicon oxide, 3.9. In addition, PI is also required to have a relatively high glass transition temperature of ≥400 °C to enable it to have good mechanical properties and insulation properties. In step S2, the thickness of PI layer 3 is 3 ± 2 mm.

[0020] In the CMP process of step S3, since PI layer 3 will be polished by grinding, in this embodiment, the grinding fluid contains 0.5 wt% of alumina particles, 3 wt% of silica particles, 2 wt% of cerium oxide particles, the pH value is controlled at 12 - 13, the grinding rate is 3000 Å / min, and the surface roughness is 200 Å.

[0021] In step S2, form a patterned PI layer 3 on the surface of oxide layer 2 through coating, exposure, development, and baking. Form pits of the patterned PI layer 3 through photolithography and curing. In step S7, it is specifically completed through coating PR, exposure and development, dry etching, and removing the glue and cleaning. In step S8, form conductive layer 6 through PVD metal seed layer, PR patterning, electroplating the circuit, removing the PR glue, and wet etching to remove the metal seed layer. In step S9, prepare bumps through electroplating bumps or ball mounting.

[0022] In the present invention, a multi-layer RDL is fabricated by forming a PI of an organic material with a metal circuit. The PI layer replaces the existing inorganic dielectric layer, featuring a simple process flow, low cost, and strong internal stress resistance. Moreover, the damascene process is adopted, and the CMP step in the damascene process is improved according to the application characteristics of the present invention, enabling the line width and line pitch to be further reduced to the sub-micron level, while enhancing the internal stress resistance and preventing cracking. Using the oxide layer as an etching stop layer can effectively remove the substrate without damaging the RDL, while replacing the temporary bonding scheme, simplifying the operation, and reducing the cost.

Claims

1. A semiconductor packaging method with high wiring density, characterized in that: It includes the following steps: S1. Provide a substrate (1), and an oxide layer (2) is provided on one surface of the substrate (1); S2. Form a patterned PI layer (3); S3. On the surface of the PI layer (3), a metal seed layer is formed in the pits (3-1) of the PI layer (3) through physical vapor deposition process, a metal circuit layer (4) is formed on the surface of the metal seed layer through electroplating process, and then polished by CMP process until the surface of the metal circuit embedded in the pits (3-1) is exposed; S4. Repeat steps S2 to S3 to form several layers of PI layers (3) and metal circuit layers (4); S5. Perform alignment bonding, mount the chip (5), and perform encapsulation; S6. Grind and etch the substrate (1) to remove the substrate (1), and the etching stops on the oxide layer (2); S7. Pattern and open a window on the surface of the oxide layer (2) to expose the metal circuit layer (4); S8. Form a conductive layer (6) at the exposed metal circuit layer (4) through UBM process; S9. Form bumps (7) at the conductive layer (6); S10. Perform dicing.

2. The semiconductor packaging method with high wiring density according to claim 1, wherein: In the step S1, a substrate with a self-provided oxide layer (2) is selected, or an oxide layer is formed on the surface of the substrate (1) through chemical vapor deposition process.

3. A semiconductor packaging method with high wiring density according to claim 1, characterized in that: In the step S2, a patterned PI layer (3) is formed on the surface of the oxide layer (2) through coating, exposure, development and baking.

4. A semiconductor packaging method with high wiring density according to claim 1, characterized in that: In the step S5, the connection between the chip (5) and the metal circuit layer (4) is filled with an encapsulant (8) through underfill process or the chip (5) is integrally wrapped with the encapsulant (8).

5. A semiconductor packaging method with high wiring density according to claim 1, characterized in that: The material of the PI layer (3) is selected as a PI material with a relative dielectric constant of 2.7 to 3.2 and a glass transition temperature ≥400°C.

6. A semiconductor packaging method with high wiring density according to claim 1, characterized in that: In the step S2, the thickness of the PI layer (3) is 3±2mm.

7. A semiconductor packaging method with high wiring density according to claim 1, characterized in that: In the CMP process of the step S3, the grinding fluid contains 0.5-1wt% of alumina particles, 3-4wt% of silica particles, 2-3wt% of cerium oxide particles, the pH value is controlled to be 12-13, the grinding rate is 3000±500A / min, and the surface roughness is 200±20A.

8. A semiconductor packaging method with high wiring density according to claim 1, characterized in that: In the step S2, the pits (3-1) of the patterned PI layer (3) are formed through photolithography and curing.

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