Control method and system for ultra-small high-precision servo drive rotary table

Abstract

The invention provides a control method and system for an ultra-small high-precision servo drive rotary table, and relates to the technical field of servo drive rotary tables, and the method comprises the steps: determining a picture of each segmented chip and information of each segmented chip based on a picture of a wafer to be detected; determining a plurality of first risk chips based on each piece of segmented chip information; based on the multiple pieces of first risk chip information, using a clustering algorithm to perform clustering to obtain K clusters and representative chips of each cluster; obtaining X-ray inspection information of the representative chip from each cluster; determining a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of pieces of first risk chip information and the X-ray inspection information of the representative chips of each cluster; determining a final detection path based on the plurality of second risk chip pictures in each risk cluster; and based on the final detection path, controlling the ultra-small high-precision servo driving turntable to carry out electrical performance detection. The method can quickly and accurately determine the optimal wafer detection path.

Description

Technical Field

[0001] The present invention relates to the technical field of servo-driven turntables, and in particular to a control method and system for an ultra-small and high-precision servo-driven turntable. Background Art

[0002] With the continuous progress of semiconductor manufacturing processes, the number of chips integrated on a wafer has accelerated, and at the same time, the requirements for chip quality inspection have become increasingly high. Traditional wafer inspection methods mainly rely on manual quality inspection or automated inspection equipment with fixed paths, which have problems such as low inspection efficiency, high missed inspection rate, and poor adaptability. Especially in high-density integrated circuits, the chip size is getting smaller and the defect features are more subtle, and traditional inspection methods are difficult to meet the quality control requirements of modern semiconductor manufacturing. Existing technologies usually adopt a full-inspection mode, that is, all chips on the wafer are inspected one by one. Although this method can ensure the inspection coverage rate, the inspection time is long and the resource consumption is large. However, defects in semiconductor manufacturing often have the characteristic of regional aggregation. If a random sampling inspection method is used, it is easy to miss high-risk areas, resulting in quality hazards. In addition, most existing automated inspection equipment adopts a preset fixed inspection path and cannot dynamically adjust according to the actual defect distribution. When encountering a new defect mode, the defect recognition accuracy of fixed-path inspection will decrease significantly.

[0003] Therefore, how to quickly and accurately determine the optimal wafer inspection path is an urgent problem to be solved at present. Summary of the Invention

[0004] The main technical problem to be solved by the present invention is how to quickly and accurately determine the optimal wafer inspection path.

[0005] According to a first aspect, the present invention provides a control method for an ultra-small and high-precision servo-driven turntable, including: obtaining a picture of a wafer to be inspected; determining each segmented chip picture and each segmented chip information based on the picture of the wafer to be inspected; determining a plurality of first risk chips based on each segmented chip information; using a clustering algorithm to cluster based on the information of the plurality of first risk chips to obtain K clusters and representative chips of each cluster; controlling the ultra-small and high-precision servo-driven turntable to move to the representative chips of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chips of each cluster; determining a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the information of the plurality of first risk chips and the X-ray inspection information of the representative chips of each cluster; determining a final inspection path based on the pictures of the plurality of second risk chips in each risk cluster; controlling the ultra-small and high-precision servo-driven turntable to perform electrical performance inspection based on the final inspection path.

[0006] In a possible implementation, determining the final detection path based on multiple second risk chip images in each risk cluster includes: determining necessary detection components, secondary detection components, and optional detection components in the second risk chips based on the multiple second risk chip images in each risk cluster and each second risk chip information; generating multiple alternative detection paths, the detection information of each alternative detection path, and the difference degree of the detection information of each alternative detection path based on the positions of each second risk chip, the necessary detection components, secondary detection components, and optional detection components in the second risk chips; constructing a detection graph, where the detection graph includes multiple detection path nodes and multiple edges between the multiple detection path nodes, and the node feature of each detection path node includes an alternative detection path and the detection information of each alternative detection path, and the edge between the detection path nodes is the difference degree of the detection information of each alternative detection path; and determining the final detection path by processing the detection graph based on a graph neural network.

[0007] In a possible implementation, the representative chip of each cluster is the chip closest to the centroid of each cluster.

[0008] In a possible implementation, the clustering algorithm is the K-means clustering algorithm.

[0009] According to a second aspect, the present invention provides a control system for a ultra-small high-precision servo-driven turntable, including: an acquisition module for acquiring images of a wafer to be detected; an information segmentation module for determining each segmented chip image and each segmented chip information based on the images of the wafer to be detected; a first determination module for determining multiple first risk chips based on each segmented chip information; a clustering module for clustering using a clustering algorithm based on the multiple first risk chip information to obtain K clusters and the representative chip of each cluster; a ray inspection module for controlling the ultra-small high-precision servo-driven turntable to move to the representative chip of each cluster and performing X-ray inspection to obtain the X-ray inspection information of the representative chip of each cluster; a second determination module for determining multiple risk clusters and multiple second risk chips in each risk cluster based on the multiple first risk chip information and the X-ray inspection information of the representative chip of each cluster; a path planning module for determining the final detection path based on the multiple second risk chip images in each risk cluster; and an electrical detection module for controlling the ultra-small high-precision servo-driven turntable to perform electrical performance detection based on the final detection path.

[0010] In a possible implementation, the path planning module is further configured to: determine necessary detection components, secondary detection components, and optional detection components in the second-risk chips based on multiple second-risk chip images in each risk cluster and each second-risk chip information; generate multiple alternative detection paths, detection information for each alternative detection path, and the difference degree of the detection information for each alternative detection path based on the positions of each second-risk chip, the necessary detection components, secondary detection components, and optional detection components in the second-risk chips; construct a detection map, where the detection map includes multiple detection path nodes and multiple edges between the multiple detection path nodes, and the node feature of each detection path node includes an alternative detection path and the detection information for each alternative detection path, and the edge between the detection path nodes is the difference degree of the detection information for each alternative detection path; and determine the final detection path by processing the detection map based on a graph neural network.

[0011] In a possible implementation, the representative chip of each cluster is the chip closest to the centroid of each cluster.

[0012] In a possible implementation, the clustering algorithm is the K-means clustering algorithm.

[0013] According to a third aspect, an embodiment of the present invention provides an electronic device, including: a processor; a memory; and a computer program; wherein, the computer program is stored in the memory and is configured to be executed by the processor to implement the method as described above, and the method includes: obtaining an image of a wafer to be detected; determining each segmented chip image and each segmented chip information based on the image of the wafer to be detected; determining multiple first-risk chips based on each segmented chip information; clustering the multiple first-risk chip information using a clustering algorithm to obtain K clusters and the representative chip of each cluster; controlling a ultra-small high-precision servo drive turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain the X-ray inspection information of the representative chip of each cluster; determining multiple risk clusters and multiple second-risk chips in each risk cluster based on the multiple first-risk chip information and the X-ray inspection information of the representative chip of each cluster; determining the final detection path based on multiple second-risk chip images in each risk cluster; and controlling the ultra-small high-precision servo drive turntable to perform electrical performance detection based on the final detection path.

[0014] According to a fourth aspect, the present embodiment provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, it implements the control method of the ultra-small and high-precision servo-driven turntable provided above. The method includes: acquiring a picture of a wafer to be detected; determining each segmented chip picture and each segmented chip information based on the picture of the wafer to be detected; determining a plurality of first risk chips based on each segmented chip information; using a clustering algorithm to cluster based on the plurality of first risk chip information to obtain K clusters and representative chips of each cluster; controlling the ultra-small and high-precision servo-driven turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster; determining a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster; determining a final detection path based on the plurality of second risk chip pictures in each risk cluster; and controlling the ultra-small and high-precision servo-driven turntable to perform electrical performance detection based on the final detection path.

[0015] A control method and system for an ultra-small and high-precision servo-driven turntable provided by the present invention. The method includes acquiring a picture of a wafer to be detected; determining each segmented chip picture and each segmented chip information based on the picture of the wafer to be detected; determining a plurality of first risk chips based on each segmented chip information; using a clustering algorithm to cluster based on the plurality of first risk chip information to obtain K clusters and representative chips of each cluster; controlling the ultra-small and high-precision servo-driven turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chip of each cluster; determining a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster; determining a final detection path based on the plurality of second risk chip pictures in each risk cluster; and controlling the ultra-small and high-precision servo-driven turntable to perform electrical performance detection based on the final detection path. This method can quickly and accurately determine the optimal wafer detection path. Description of the Drawings

[0016] Figure 1 It is a flowchart of a control method for an ultra-small and high-precision servo-driven turntable provided by an embodiment of the present invention;

[0017] Figure 2 It is a schematic diagram of a wafer provided by an embodiment of the present invention;

[0018] Figure 3 It is a schematic diagram of a K-means clustering provided by an embodiment of the present invention;

[0019] Figure 4 It is a flowchart of a method for determining a final detection path provided by an embodiment of the present invention;

[0020] Figure 5 Schematic diagram of constructing a detection map provided by an embodiment of the present invention;

[0021] Figure 6 Schematic diagram of a control system of an ultra-small and high-precision servo-driven turntable provided by an embodiment of the present invention. Specific embodiments

[0022] The present invention will be further described in detail below in conjunction with the accompanying drawings through specific embodiments. Similar elements in different embodiments are labeled with related similar element numbers. In the following embodiments, many details are described to enable a better understanding of the present invention. However, those skilled in the art can easily recognize that some of the features can be omitted in different situations, or can be replaced by other elements, materials, and methods. In some cases, some operations related to the present invention are not shown or described in the specification to avoid the core part of the present invention being overwhelmed by excessive description. For those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0023] In an embodiment of the present invention, there is provided a control method of an ultra-small and high-precision servo-driven turntable as shown in Figure 1 The control method of the ultra-small and high-precision servo-driven turntable includes steps S1 to S8:

[0024] Step S1, obtaining a picture of the wafer to be detected.

[0025] The wafer to be detected is a silicon wafer that has completed the main process processing in the semiconductor manufacturing process. Figure 2 Schematic diagram of a wafer provided by an embodiment of the present invention. The surface of the wafer to be detected contains a large number of repeating integrated circuit chips such as CPUs and memories. For example, a 12-inch wafer can contain hundreds of identical chips on its surface.

[0026] The picture of the wafer to be detected is a surface image of the wafer captured by a high-resolution industrial camera for the wafer to be detected.

[0027] Step S2, determining each segmented chip picture and each segmented chip information based on the picture of the wafer to be detected.

[0028] In some embodiments, an information segmentation model may be used to determine each segmented chip image and each segmented chip information based on the image of the wafer to be detected. The information segmentation model is a convolutional neural network model. The input of the information segmentation model is the image of the wafer to be detected, and the output of the information segmentation model is each segmented chip image and each segmented chip information.

[0029] A convolutional neural network (CNN) model is a deep learning model. The convolutional neural network model can process data with a grid structure such as images. The convolutional neural network model can automatically extract data features through components such as convolutional layers, pooling layers, and fully connected layers.

[0030] Each segmented chip image is the image corresponding to each individual chip segmented from the image of the entire wafer to be detected output by the information segmentation model. The segmented chip image contains all the detailed features of the chip.

[0031] Each segmented chip information is the structured information extracted from the image of the wafer to be detected by the information segmentation model and corresponding to each segmented chip image. The segmented chip information can characterize the physical attributes, position features, and preliminary detection features of the segmented chip. The segmented chip information includes information such as the physical attribute information and preliminary detection features of the segmented chip.

[0032] The physical attribute information includes information such as the geometric dimensions of the segmented chip, the row and column positions of the segmented chip in the wafer, the pixel coordinate range of the segmented chip, and the surface texture features.

[0033] The preliminary detection features are the preliminary defect information such as the positions and morphologies of scratches, particle attachments, and abnormal metal layers on the surface of the segmented chip extracted based on the segmented chip image, as well as process identification information such as the batch number and process version mark of the segmented chip.

[0034] The convolutional neural network model can analyze the image of the wafer to be detected through its unique hierarchical feature extraction mechanism. The convolutional neural network can identify basic image features such as the edges and textures of the image of the wafer to be detected through the convolutional layer, and then construct the complete chip contour features through the deep network. During the feature extraction process, the pooling layer can reduce the computational complexity while retaining the key spatial information. Finally, the convolutional neural network can output the exact boundary mask of each segmented chip image and extract the segmented chip information corresponding to each segmented chip image.

[0035] Step S3, determine multiple first risk chips based on each of the segmented chip information.

[0036] In some embodiments, a first risk determination model can be used to determine multiple first risk chips based on each piece of segmented chip information. The first risk determination model is a Transformer model. The input of the first risk determination model is each piece of segmented chip information, and the output of the first risk determination model is multiple first risk chips.

[0037] The Transformer model is a deep learning model based on the self-attention mechanism. The Transformer model can effectively capture the long-range dependencies between elements in the input sequence through components such as the multi-head self-attention mechanism, positional encoding, feed-forward neural network, residual connection, and layer normalization, so as to complete deep feature extraction and semantic understanding of the data.

[0038] The first risk chips are the chips with potential quality risks screened out by the first risk determination model.

[0039] The potential quality risks can include particle contamination, scratches, bridging, open circuits, and short circuit signs, etc.

[0040] The segmented chip information covers the physical attribute information and preliminary detection feature information of the chips, and there are complex non-linear relationships between these information. The multi-head self-attention mechanism of the Transformer model can automatically learn and capture the weights and associations between information in each dimension. For example, when features such as the size deviation, surface roughness, and texture complexity of key areas of the chip appear abnormal at the same time, the Transformer model can keenly identify and assign higher risk weights. In addition, there is also a spatial dependence relationship between the position of the chip and the risk. For example, the chips at the edge of the wafer are more likely to have defects due to factors such as stress. The positional encoding technology of the Transformer model can effectively retain the spatial coordinate information of the chips and deeply mine the spatial features in combination with the self-attention mechanism, so as to accurately identify the chips with potential risks.

[0041] Step S4: Use a clustering algorithm to cluster based on the multiple first risk chip information to obtain K clusters and the representative chips of each cluster.

[0042] The first risk chip information is the information corresponding to the first risk chips extracted from all the segmented chip information.

[0043] The clustering algorithm is the K-means clustering algorithm. The K-means clustering algorithm is an unsupervised machine learning algorithm. The K-means clustering algorithm can divide a given data set into K different clusters, so that the data points in the same cluster have high similarity, while the data points between different clusters are obviously different. The K-means clustering algorithm can achieve effective data grouping by continuously iteratively adjusting the cluster center and then minimizing the sum of the squares of the distances from each data point to the center of the cluster to which it belongs.

[0044] In some embodiments, the K value in the K-means clustering algorithm can be obtained by artificially setting in advance.

[0045] In some embodiments, the specific execution process of clustering based on multiple first risk chip information using the K-means clustering algorithm is as follows: first, K chips are randomly selected from the first risk chip information data set as initial clustering centers, and then the Euclidean distance is used to calculate the distance between each first risk chip information and the K initial clustering centers and the chips are divided into corresponding clusters according to the principle of the closest distance. After all first risk chips are divided, the average value of each feature of the chip in each cluster is recalculated to update the clustering center of each cluster. The above division and update steps are repeated until the change in the cluster center is less than a preset threshold. At this time, the clustering process converges, and finally K clusters are obtained, thereby completing K-means clustering.

[0046] Each cluster may represent a set of first risk chips with similar risk characteristics. Figure 3 FIG. 4 is a schematic diagram of a K-means clustering in an embodiment of the present invention. Figure 3 As shown, Figure 3 Including cluster 1, cluster 2, cluster 3, cluster 4, cluster 5, each cluster corresponds to a cluster of data points with similar distances in the feature space, and the commonality of each cluster can be quantitatively characterized by the average characteristics, distribution range or key indicators of the data within the cluster. These similarities can be reflected in multiple dimensions such as the physical defect type of the chip, electrical performance parameters, and position distribution rules.

[0047] For example, one cluster may contain chips with tiny cracks in the edge area of the wafer, while another cluster may be mainly composed of chips with unstable performance in the central area due to material impurities. Some clusters are significantly concentrated in the high stress area at the edge of the wafer, while others are concentrated in the low defect density area in the center.

[0048] The representative chip of each cluster is the chip closest to the centroid of each cluster. The representative chip of each cluster is a typical sample of the risk chip of this type, and the representative chip can reflect the common characteristics of the corresponding cluster.

[0049] Clustering the first risk chips can improve the detection efficiency and analysis accuracy. By dividing a large number of discrete risk chips into a finite number of clusters, the data structure can be simplified, thus avoiding the cumbersome process of analyzing each chip one by one, and enabling the detection resources to focus on key areas. The representative chip of each cluster can be used as the priority object for subsequent in-depth detection. Therefore, only by detecting the representative chip can the potential risks of other chips in the cluster be inferred.

[0050] Step S5, control the ultra-small high-precision servo-driven turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain the X-ray inspection information of the representative chip of each cluster.

[0051] The ultra-small high-precision servo-driven turntable is a mechanical device with high-precision motion control capabilities. The ultra-small high-precision servo-driven turntable can achieve micron-level precision positioning and motion control through servo motor drive, and thus can perform precise movement, rotation, etc. in three-dimensional space.

[0052] The X-ray inspection information of the representative chip of each cluster is the detection information obtained by accurately positioning the X-ray detection device to the representative chip of each cluster by the ultra-small high-precision servo-driven turntable and scanning its internal structure. The X-ray inspection information includes quantitative data of physical characteristics such as the connection state of the metal interconnection layer inside the representative chip, the structural integrity inside the silicon substrate, and the morphology of solder balls or bonding points in the wafer-level packaging process, as well as structured information such as the defect type, the three-dimensional position coordinates of the defect in the chip coordinate system, and the defect size obtained based on X-ray image analysis.

[0053] Step S6, determine a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster.

[0054] In some embodiments, a second risk determination model can be used to determine a plurality of risk clusters and a plurality of second risk chips in each risk cluster based on the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster. The second risk determination model is a deep neural network model. The input of the second risk determination model is the plurality of first risk chip information and the X-ray inspection information of the representative chip of each cluster, and the output of the second risk determination model is a plurality of risk clusters and a plurality of second risk chips in each risk cluster.

[0055] The deep neural network model includes a Deep Neural Network (DNN), which is a machine learning model developed based on the architecture of artificial neural networks. The deep neural network can automatically learn complex feature representations and patterns from massive amounts of data. The components of the deep neural network include an input layer, multiple hidden layers, and an output layer, and the neurons between layers are interconnected by learnable weights.

[0056] The risk cluster is a chip cluster with more significant risk features screened out from each of all clusters output by the second risk determination model. The risk cluster focuses on a set of chips with a more severe degree of defects and a higher probability of functional failure.

[0057] Multiple second-risk chips in the risk cluster are chips further determined to be high-risk in the risk cluster output by the second risk determination model.

[0058] Multiple first-risk chip information includes external risk features such as chip surface defects and physical properties, and the X-ray inspection information of the representative chip of each cluster can reveal internal structural defects of the chip. The multiple first-risk chip information and the X-ray inspection information of the representative chip of each cluster complement each other from the aspects of macroscopic risk performance and microscopic defect essence. The model can automatically explore the correlation law between surface risks and internal defects by fusing the two types of information, and cluster chips with similar high-risk features, such as chips with surface scratches accompanied by internal solder joint voids, into a risk cluster. At the same time, the model can further screen out second-risk chips with higher risks within the cluster based on the severity of the defects.

[0059] The deep neural network can explore the complex hidden correlations between data from the first-risk chip information such as the geometric dimensions and appearance defect probability of the chip, as well as information such as the internal structure and defect features in the X-ray inspection information. Through training with a large amount of labeled data, the deep neural network can learn the mapping relationship between different risk features and the chip risk level, so as to accurately divide the chips into different risk clusters and identify the second-risk chips in each cluster.

[0060] Step S7, determine the final detection path based on the pictures of multiple second-risk chips in each risk cluster.

[0061] In some embodiments, Figure 4 As shown in the flowchart of a process for determining the final detection path provided by an embodiment of the present invention, the determination of the final detection path includes steps S71 to S74:

[0062] Step S71, determine the necessary detection components, secondary detection components, and optional detection components in the second-risk chips based on the pictures of multiple second-risk chips in each risk cluster and each second-risk chip information.

[0063] The multiple second-risk chip pictures in the risk cluster are images corresponding to the second-risk chips extracted from all the segmented chip pictures, and all the detailed features of the second-risk chips are included in the second-risk chip pictures.

[0064] The second-risk chip information is the structured information corresponding to the second-risk chips extracted from all the segmented chip information.

[0065] In some embodiments, based on the multiple second-risk chip pictures in each risk cluster and each second-risk chip information, a component analysis model can be used to determine the necessary detection components, secondary detection components, and optional detection components in the second-risk chips. The component analysis model is a convolutional neural network model. The input of the component analysis model is the multiple second-risk chip pictures in each risk cluster and each second-risk chip information, and the output of the component analysis model is the necessary detection components, secondary detection components, and optional detection components in the second-risk chips.

[0066] The necessary detection components are the components in the second-risk chips output by the component analysis model that are determined to have a relatively high probability of functional failure risk.

[0067] The secondary detection components are the components output by the component analysis model that have a certain risk but a lower probability than the necessary detection components.

[0068] The optional detection components are the components output by the component analysis model with an extremely low risk probability, and the risk probability of the optional detection components is lower than that of the necessary detection components and the secondary detection components.

[0069] The convolutional neural network can achieve component-level risk assessment through a multi-scale feature fusion mechanism. First, the convolutional neural network extracts component-level microscopic features from the second-risk chip pictures through the convolutional layer, and at the same time constructs a multi-dimensional feature vector space in combination with the second-risk chip information. Finally, the fully connected layer learns the mapping relationship between the feature combinations and the risk levels in the historical defect samples.

[0070] In some embodiments, the component analysis model includes a component parsing layer, an information association layer, and a priority division layer. The input of the component parsing layer is multiple second risk chip pictures in each risk cluster, and the output of the component parsing layer is the distribution position, size and shape of each component, and the interconnection relationship between components. The input of the information association layer is the distribution position, size and shape of each component, and the interconnection relationship between components. The output of the information association layer is component function positioning information, position sensitivity coefficient, risk probability, failure propagation coefficient, and detectability score. The input of the priority division layer is component function positioning information, position sensitivity coefficient, risk probability, failure propagation coefficient, and detectability score. The output of the priority division layer is the necessary detection components, secondary detection components, and optional detection components in the second risk chip.

[0071] The interconnection relationship between components is the electrical connection path formed by metal wiring among components in the chip. For example, pin 1 of resistor R1 is connected to pin 3 of capacitor C2.

[0072] The function positioning information is the information used to describe the specific function of each component.

[0073] The position sensitivity coefficient is used to quantify the impact value of the physical position of the component on its reliability.

[0074] The failure propagation coefficient is the value used to evaluate the degree of chain effect of a single component failure on the surrounding circuit.

[0075] The detectability score is the score based on the physical characteristics of the component to evaluate its detection difficulty. The larger the detectability score, the smaller the detection difficulty of the component.

[0076] Different layers can be responsible for information abstraction and processing at different levels. The component parsing layer is responsible for extracting the distribution position, size and shape, and interconnection relationship of components from the chip picture. The information association layer is responsible for generating evaluation indicators such as risk probability and position sensitivity coefficient. The priority division layer is responsible for determining the detection priority classification of components based on risk indicators. Through such hierarchical processing, complex chip detection information can be processed more effectively. By constructing multiple layers, the modularity of the system can be improved, and information can be processed more effectively, thereby improving the accuracy and efficiency of the system.

[0077] Step S72, generate multiple alternative detection paths, the detection information of each alternative detection path, and the difference degree of the detection information of each alternative detection path based on the position of each second risk chip, the necessary detection components, secondary detection components, and optional detection components in the second risk chip.

[0078] The position of the second risk chip is to extract the row, column and coordinate positions of the second risk chip in the wafer from the second risk chip information.

[0079] In some embodiments, multiple alternative detection paths, the detection information of each alternative detection path, and the difference degree of the detection information of each alternative detection path can be generated by a generative adversarial network based on the position of each second risk chip, the necessary detection components, secondary detection components, and optional detection components in the second risk chip. The input of the generative adversarial network is the position of each second risk chip, the necessary detection components, secondary detection components, and optional detection components in the second risk chip, and the output of the generative adversarial network is multiple alternative detection paths, the detection information of each alternative detection path, and the difference degree of the detection information of each alternative detection path.

[0080] Generative Adversarial Networks (GANs) is a deep learning model that realizes data generation through a game learning mechanism. The generative adversarial network consists of two neural networks, a generator and a discriminator. The generator is responsible for learning the distribution law of real data to generate simulated data that approximates real samples, and the discriminator can identify the authenticity of the input data and distinguish real data from the samples output by the generator. The generator and the discriminator confront each other in iterative training and finally reach a Nash equilibrium state, so that the data output by the generator is highly similar to the real data in terms of distribution and features.

[0081] Multiple alternative detection paths are a combination of multiple detection strategy paths generated by a generative adversarial network for the second risk chip. Each alternative detection path passes through all the necessary detection components, as well as some secondary detection components and optional detection components.

[0082] The detection information of each alternative detection path is information that can describe the execution details and quantization indicators of each detection path. The detection information of the alternative detection path includes information such as component coverage strategy, detection execution order, estimated resource consumption, efficiency indicators, and path reliability score.

[0083] The component coverage strategy is a detection coverage rule formulated for the necessary detection components, secondary detection components, and optional detection components in the second risk chip.

[0084] As an example, 100% full-scale detection is required for necessary detection components to ensure no omission in high-risk areas. Secondary detection components can be sampled and detected at a ratio of 50% to 80% to balance risk and detection efficiency at the same time. Optional detection components are sampled at a rate of no more than 30% to optimize resource allocation.

[0085] The detection execution order is the sequence of detecting various components on the chip in the alternative detection paths. The detection execution order covers the detection sequence arrangements of the necessary detection components, secondary detection components, and optional detection components by the detection instrument, as well as the connection sequence of different detection steps.

[0086] The expected resource consumption is the quantitative value of the resource inputs such as the expected device running duration and energy loss during the detection process when executing an alternative detection path.

[0087] The efficiency index is a quantitative index for measuring the detection quantity per unit time or the detection time per single sample of the alternative detection path.

[0088] The path reliability score is an index used to quantitatively evaluate the stability and accuracy of the alternative detection path during execution.

[0089] The difference degree of the detection information of each alternative detection path is a value output by the generative adversarial network for quantifying the difference degree of the detection information between alternative detection paths. The difference degree can be represented by a value between 0 and 1, and the higher the value, the greater the difference degree of the detection information of the alternative detection path.

[0090] The generator of the generative adversarial network can learn the characteristic patterns of the detection paths based on data such as the location and component distribution of the second-risk chip, so as to generate multiple alternative detection paths and corresponding detection information. The discriminator can continuously distinguish between real path data and generated path data to reversely optimize the generator, so that the output of the generator is more in line with actual requirements. In addition, the discriminator of the generative adversarial network can also convert the information of different detection paths into feature vectors, and then calculate the difference degree between alternative detection paths by measuring the distribution difference between vectors.

[0091] Step S73, construct a detection map, where the detection map includes multiple detection path nodes and multiple edges between the detection path nodes. The node feature of each detection path node includes an alternative detection path and the detection information of each alternative detection path, and the edge between the detection path nodes is the difference degree of the detection information of each alternative detection path.

[0092] The detection map is a visual data structure composed of detection path nodes and the edges connecting these nodes. The detection path nodes store the specific alternative detection paths and their detailed detection information, such as component coverage strategies and detection execution orders, as basic units. The edges between the nodes quantitatively represent the difference degree of the detection information of two corresponding alternative detection paths. Figure 5 It is a schematic diagram of constructing a detection map provided by an embodiment of the present invention. As Figure 5 shown, Figure 5It includes detection path node A, detection path node B, detection path node C, and detection path node D. The edge between two detection path nodes represents the difference degree of the detection information of the paths included by these two detection path nodes.

[0093] By constructing the detection graph, which is a form of data organization, complex multiple alternative detection paths and their mutual relationships can be presented in an intuitive and clear manner.

[0094] Step S74: Process the detection graph based on the graph neural network to determine the final detection path.

[0095] The graph neural network (Graph Neural Network, GNN) is a machine learning model that can process non-Euclidean structured data. The graph neural network can learn the topological structure data with nodes and edges in the detection graph and effectively extract the structural features and semantic information in the data. The input of the graph neural network is the detection graph, and the output of the graph neural network is the final detection path.

[0096] The final detection path is the detection path that the graph neural network selects from multiple alternative detection paths and best meets the detection objectives and requirements. The final detection path is the specific path adopted when actually performing the detection task.

[0097] The final detection path can achieve the optimal allocation of detection resources while ensuring the detection quality.

[0098] Each node in the detection graph corresponds to an alternative detection path. The node is the basic unit for analysis and can provide data support for the determination of the final detection path. Through the node, multiple alternative detection paths can be stored and represented in the form of discrete units. The node enables the graph neural network to independently process each path and efficiently extract features, and then comprehensively consider all alternative paths.

[0099] The node features include the detection information of each alternative detection path, such as component coverage strategy, detection execution order, expected resource consumption, etc. These information can provide a decision-making basis for the graph neural network. The graph neural network can learn the advantages and disadvantages of different paths in meeting the detection objectives based on the node features, so as to judge the value of each path for determining the final detection path.

[0100] The edge between the detection path nodes can numerically represent the difference degree of the detection information of each alternative detection path. Through the quantitative information of the edge, the graph neural network can analyze the association and difference between each path and identify redundant paths or complementary path combinations. The edge can assist the graph neural network in weighing the relationship between paths from a global perspective, so as to more accurately determine the final detection path with the optimal comprehensive performance.

[0101] The information contained in the nodes and edges in the detection graph can match the processing mode of the graph neural network. The graph neural network can utilize the detailed information of the alternative detection paths in the node features and combine the path difference represented by the edges, and then learn the importance and relevance of different detection paths in the entire graph through layer-by-layer information transmission and aggregation. In this way, the graph neural network can comprehensively evaluate all alternative detection paths from a global perspective and weigh various detection indicators to output the final detection path that best meets the detection target.

[0102] Step S8, controlling the ultra-small high-precision servo-driven turntable to perform electrical performance detection based on the final detection path.

[0103] When the final detection path is determined, the information such as the coordinates of the detection chips and the detection order included in the final detection path is converted into control instructions for the ultra-small high-precision servo-driven turntable through a motion control algorithm, such as parameters like rotation angle, displacement distance, and motion speed. The ultra-small high-precision servo-driven turntable can accurately adjust the probe position of the probe station according to these instructions, so that the probes of the probe station can accurately align with the chip pads on the wafer to be detected in sequence according to the planned order, and then complete the electrical performance detection of the chips on the wafer to be detected.

[0104] Based on the same inventive concept, Figure 6 The figure is a schematic diagram of a control system for an ultra-small high-precision servo-driven turntable provided by an embodiment of the present invention. The control system of the ultra-small high-precision servo-driven turntable includes:

[0105] An acquisition module 61, configured to acquire a picture of the wafer to be detected;

[0106] An information segmentation module 62, configured to determine each segmented chip picture and each segmented chip information based on the picture of the wafer to be detected;

[0107] A first determination module 63, configured to determine a plurality of first-risk chips based on each segmented chip information;

[0108] A clustering module 64, configured to perform clustering on the basis of the information of a plurality of first-risk chips using a clustering algorithm to obtain K clusters and representative chips of each cluster;

[0109] A ray inspection module 65, configured to control the ultra-small high-precision servo-driven turntable to move to the representative chips of each cluster and perform X-ray inspection to obtain X-ray inspection information of the representative chips of each cluster;

[0110] A second determination module 66, configured to determine a plurality of risk clusters and a plurality of second-risk chips in each risk cluster based on the information of the plurality of first-risk chips and the X-ray inspection information of the representative chips of each cluster;

[0111] A path planning module 67, configured to determine a final detection path based on multiple second risk chip images in each risk cluster;

[0112] An electrical detection module 68, configured to control an ultra-small high-precision servo drive turntable to perform electrical performance detection based on the final detection path.

[0113] It should be noted that, in order to simplify the expression disclosed in this specification and thus help the understanding of one or more embodiments of the invention, in the foregoing description of the embodiments of this specification, sometimes multiple features are merged into one embodiment, drawing, or description thereof. However, this disclosure method does not mean that the features required by the subject of this specification are more than those mentioned in the claims. In fact, the features of the embodiment are less than all the features of the single embodiment disclosed above.

[0114] Finally, it should be understood that the embodiments described in this specification are only used to illustrate the principles of the embodiments of this specification. Other deformations may also fall within the scope of this specification. Therefore, by way of example rather than limitation, alternative configurations of the embodiments of this specification can be regarded as consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to the embodiments clearly introduced and described in this specification.

Claims

1. A control method for a super-small and high-precision servo-driven turntable, characterized in that, Including: Obtain a picture of the wafer to be detected; Determine each segmented chip picture and each segmented chip information based on the picture of the wafer to be detected; Determine multiple first-risk chips based on each of the segmented chip information; Use a clustering algorithm to cluster based on the information of multiple first-risk chips to obtain K clusters and the representative chips of each cluster; Control the ultra-small high-precision servo drive turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain the X-ray inspection information of the representative chip of each cluster; Determine multiple risk clusters and multiple second-risk chips in each risk cluster based on the information of the multiple first-risk chips and the X-ray inspection information of the representative chip of each cluster; Determine the final detection path based on the pictures of multiple second-risk chips in each risk cluster; Control the ultra-small high-precision servo drive turntable to perform electrical performance detection based on the final detection path.

2. The control method of the ultra-small and high-precision servo-driven turntable according to claim 1, wherein, The determining the final detection path based on the pictures of multiple second-risk chips in each risk cluster includes: Determine the necessary detection components, secondary detection components, and optional detection components in the second-risk chips based on the pictures of multiple second-risk chips in each risk cluster and each second-risk chip information; Generate multiple alternative detection paths, the detection information of each alternative detection path, and the difference degree of the detection information of each alternative detection path based on the position of each second-risk chip, the necessary detection components, secondary detection components, and optional detection components in the second-risk chip; Construct a detection graph, where the detection graph includes multiple detection path nodes and multiple edges between the multiple detection path nodes. The node feature of each detection path node includes an alternative detection path and the detection information of each alternative detection path, and the edge between the detection path nodes is the difference degree of the detection information of each alternative detection path; Process the detection graph based on a graph neural network to determine the final detection path.

3. The control method of the ultra-small and high-precision servo-driven turntable according to claim 1, characterized in that, The representative chip of each cluster is the chip closest to the centroid of each cluster.

4. The control method of the ultra-small high-precision servo-driven turntable according to claim 1, characterized in that, The clustering algorithm is the K-means clustering algorithm.

5. A control system for an ultra-small high-precision servo-driven turntable, characterized in that, Including: An acquisition module for obtaining a picture of the wafer to be detected; An information segmentation module for determining each segmented chip picture and each segmented chip information based on the picture of the wafer to be detected; A first determination module for determining multiple first-risk chips based on each of the segmented chip information; A clustering module for using a clustering algorithm to cluster based on the information of multiple first-risk chips to obtain K clusters and the representative chips of each cluster; A ray inspection module for controlling the ultra-small high-precision servo drive turntable to move to the representative chip of each cluster and perform X-ray inspection to obtain the X-ray inspection information of the representative chip of each cluster; A second determination module for determining multiple risk clusters and multiple second-risk chips in each risk cluster based on the information of the multiple first-risk chips and the X-ray inspection information of the representative chip of each cluster; A path planning module for determining the final detection path based on the pictures of multiple second-risk chips in each risk cluster; An electrical detection module for controlling the ultra-small high-precision servo drive turntable to perform electrical performance detection based on the final detection path.

6. The control system of the ultra-small and high-precision servo-driven turntable according to claim 5, characterized in that, The path planning module is further configured to: Determine the necessary detection components, secondary detection components, and optional detection components in the second-risk chips based on multiple second-risk chip images and each second-risk chip information in each risk cluster; Generate multiple alternative detection paths, the detection information of each alternative detection path, and the difference degree of the detection information of each alternative detection path based on the position of each second-risk chip, the necessary detection components, secondary detection components, and optional detection components in the second-risk chip; Construct a detection graph, which includes multiple detection path nodes and multiple edges between the multiple detection path nodes. The node feature of each detection path node includes an alternative detection path and the detection information of each alternative detection path, and the edge between the detection path nodes is the difference degree of the detection information of each alternative detection path; Determine the final detection path based on processing the detection graph by a graph neural network.

7. The control system of the ultra-small and high-precision servo-driven turntable according to claim 5, characterized in that, The representative chip of each cluster is the chip closest to the centroid of each cluster.

8. The control system of the ultra-small and high-precision servo-driven turntable according to claim 5, characterized in that, The clustering algorithm is the K-means clustering algorithm.

9. An electronic device, characterized in that, Including: A processor; A memory; And a computer program; wherein, the computer program is stored in the memory and configured to be executed by the processor to implement the control method of the ultra-small high-precision servo drive turntable according to any one of claims 1 to 4.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the control method of the ultra-small high-precision servo drive turntable according to any one of claims 1 to 4.

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