Chip packaging structure, circuit board assembly, transceiver and base station

Abstract

The invention provides a chip packaging structure, a circuit board assembly, a transceiver and a base station. The chip packaging structure comprises a bottom plate, the bottom plate is provided with a first surface and a second surface, and the first surface and the second surface are located on the same side of the bottom plate; the chip is arranged on the first surface; at least part of the packaging body is arranged on the second surface, a cavity is defined by the packaging body and the bottom plate, and the chip is located in the cavity; the electric connecting piece is arranged on the packaging body in a penetrating mode, the electric connecting piece comprises a first pin and a second pin which are connected, at least part of the first pin is located in the cavity and electrically connected with the chip, at least part of the second pin is located on the outer side of the packaging body, and the distance between the first pin and the first surface is larger than the distance between the second surface and the first surface in the stacking direction of the bottom plate and the chip. The distance is smaller than the distance between the second pin and the second surface. According to the invention, the parasitic inductance can be reduced, and meanwhile, the generation of plate-level dendritic crystals can be reduced.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and particularly to a chip packaging structure, a circuit board assembly, a transceiver, and a base station. Background Art

[0002] An amplifier is an essential component in the transceiver of a base station, and an amplifier is usually a chip packaging structure. The chip packaging structure includes a bottom plate, a chip, a package body, and electrical connectors. The chip can be connected to the electrical connectors through bonding wires, and the electrical connectors can be electrically connected to the circuit board, thereby realizing the electrical connection between the chip and the circuit board.

[0003] Parasitic inductance will be generated inside the chip packaging structure. Moreover, through testing the chip packaging structure, it can be known that the smaller the thickness of the package body between the electrical connector and the bottom plate, the smaller the parasitic inductance. Therefore, in a related technology, by reducing the mounting height of the electrical connector on the package body, the thickness of the package body between the electrical connector and the bottom plate is reduced, thereby reducing the parasitic inductance.

[0004] The electrical connector needs to be soldered to the circuit board, and the bottom plate also needs to be soldered to the circuit board. When the mounting height of the electrical connector on the package body is reduced, the distance between the electrical connector and the bottom plate will also be reduced, resulting in the phenomenon of board-level dendrites, thereby causing the electrical connector and the bottom plate to be electrically connected, and further causing a short circuit. Summary of the Invention

[0005] To solve the above technical problems, this application provides a chip packaging structure, a circuit board assembly, a transceiver, and a base station, which can reduce the generation of board-level dendrites while reducing parasitic inductance.

[0006] In the first aspect of this application, a chip packaging structure is provided, including: a bottom plate, a chip, a package body, and electrical connectors. The bottom plate has a first surface and a second surface, and the first surface and the second surface are on the same side of the bottom plate. The chip is disposed on the first surface. At least part of the package body is disposed on the second surface. Exemplarily, the package body is disposed on the second surface, or a part of the package body is disposed on the first surface and the remaining part of the package body is disposed on the second surface. The package body and the bottom plate enclose a cavity, and the chip is located inside the cavity. The electrical connector penetrates through the package body, and the electrical connector includes a connected first pin and a second pin. At least part of the first pin is located inside the cavity and is electrically connected to the chip, and at least part of the second pin is located outside the package body. The chip can be connected to the first pin through a bonding wire, and the second pin can be electrically connected to the circuit board, thereby realizing the electrical connection between the chip and the circuit board.

[0007] In the stacking direction of the base plate and the chip, the distance between the first pin and the first surface is less than the distance between the second pin and the second surface. The distance between the first pin and the first surface may refer to the distance between the surface of the first pin facing the base plate and the first surface, and the distance between the second pin and the second surface may refer to the distance between the surface of the second pin facing the base plate and the second surface. Based on the related art, the present application can keep the distance between the second pin and the second surface unchanged and reduce the distance between the first pin and the first surface. Since at least part of the package is fixed on the second surface, part of the package is located between the first pin and the second surface. When part of the package is also provided on the first surface, part of the package is also located between the first pin and the first surface. By reducing the distance between the first pin and the first surface, the thickness of the package between the first pin and the first surface can be reduced, thereby reducing the parasitic inductance. Moreover, in the related art, the first pin is higher than the chip. In the present application, by reducing the distance between the first pin and the first surface, the length of the bonding wire between the chip and the electrical connector can also be reduced, thereby also reducing the parasitic inductance. In addition, since the present application keeps the distance between the second pin and the second surface unchanged based on the related art, the dendrite problem caused by the reduction of the distance between the second pin and the second surface can be reduced, thereby avoiding the electrical connection between the electrical connector and the base plate and further causing a short circuit. That is to say, the present application can reduce the generation of board-level dendrites while reducing the parasitic inductance.

[0008] To achieve that the distance between the first pin and the first surface is less than the distance between the second pin and the second surface, in a possible implementation manner, the first surface and the second surface are coplanar, that is to say, the top surface of the base plate is a plane. Moreover, in the stacking direction, there is a spacing between the first pin and the second pin. That is to say, there is a height difference between the first pin and the second pin.

[0009] Moreover, the electrical connector further includes a connecting portion connected between the first pin and the second pin, that is to say, the electrical connector includes the first pin, the connecting portion, and the second pin connected in sequence. There is a first included angle between the extending direction of the connecting portion and the extending direction of the first pin, and there is a second included angle between the extending direction of the connecting portion and the extending direction of the second pin. The material of the electrical connector can be a conductive material, specifically a metal. Therefore, the electrical connector can be a sheet metal part, and the electrical connector can be obtained by bending a flat plate during manufacturing. This solution has a simple structure and is easy to implement. In addition, the electrical connector can form a 3D structure after being bent.

[0010] Furthermore, the first angle and the second angle may be the same, so that the first pin and the second pin are parallel to each other. In one example, the first angle is a right angle, and the second angle is a right angle. In another example, the first angle is an obtuse angle, and the second angle is also an obtuse angle. Thus, when manufacturing the electrical connector, it is convenient to bend the flat plate, and the larger the first angle and the second angle are, the less likely the electrical connector will crack at the bend during the bending process.

[0011] In some embodiments, the package body is provided with a through hole, and the through hole penetrates from the outer wall to the inner wall of the package body, that is, one end of the through hole is connected to the outside of the package body, and the other end is connected to the cavity.

[0012] Regarding the positional relationship between the first pin, the connecting portion, the cavity and the through hole, in a possible implementation, the first pin and a portion of the connecting portion are both located in the cavity, and the rest of the connecting portion is located in the through hole. In other words, the bend between the first pin and the connecting portion is located in the cavity.

[0013] In another possible implementation, part of the first pin is located in the cavity, and the rest of the first pin and the connecting portion are located in the through hole. In other words, the bend between the first pin and the connecting portion is located in the through hole. In this way, the length of the first pin can be increased, thereby reducing the situation where a large deformation is generated when the first pin is bent due to the first pin being too short.

[0014] A portion of the second pin is located in the through hole, and the rest of the second pin extends out of the package body. That is, the bend between the second pin and the connecting portion is located in the through hole. In this way, the distance between the portion of the second pin extending out of the package body and the second surface is the same and large, thereby reducing the generation of board-level dendrites caused by the small distance between part of the second pin and the second surface.

[0015] In order to achieve that the distance between the first pin and the first surface is smaller than the distance between the second pin and the second surface, in another possible embodiment, there is a height difference between the first surface and the second surface. Specifically, the base plate also has a third surface, and the third surface is located on the side away from the first surface and the second surface, and the distance between the first surface and the third surface is greater than the distance between the second surface and the third surface. In other words, the side of the base plate facing the chip is a step surface. When the electrical connector is a flat structure or the electrical connector is a 3D structure and the second pin is higher than the first pin, it is also possible to achieve that the distance between the first pin and the first surface is smaller than the distance between the second pin and the second surface. Moreover, on the basis of the relevant technology, the present application can raise the middle area on the top of the base plate to form the first surface, thereby reducing the distance between the first pin and the first surface without reducing the distance between the second pin and the third surface.

[0016] The encapsulation body and the bottom plate enclose a cavity, and the first pin is located inside the cavity. Regarding the positional relationship between the projection of the first pin on the bottom plate and the first surface and the second surface, in a possible implementation, the projection of the first pin on the bottom plate is located within the first surface, and a part of the encapsulation body is located between the first pin and the first surface. In this way, the thickness of the encapsulation body between the first pin and the bottom plate is small, thereby further reducing the parasitic inductance.

[0017] In another possible implementation, the projection of the first pin on the bottom plate is located within the second surface, and a part of the encapsulation body is located between the first pin and the second surface. In this way, the distance between the first pin and the first surface can also be reduced, thereby reducing the thickness of the encapsulation body between the first pin and the first surface, and thus reducing the parasitic inductance.

[0018] In still another possible implementation, the projection of the first pin on the bottom plate overlaps with the first surface, the projection of the first pin on the bottom plate overlaps with the second surface, a part of the encapsulation body is located between the first pin and the first surface, and a part of the encapsulation body is located between the first pin and the second surface.

[0019] In some implementations, the chip packaging structure includes a plurality of electrical connectors arranged in sequence along the width direction. There is a notch on the second pin, and at least two adjacent notches of the electrical connectors are provided on the side close to each other and are in corresponding positions. Here, the width direction can be the direction perpendicular to both the stacking direction and the connection direction, and the connection direction can be the direction in which the first pin and the second pin are connected. There is a spacing between the notch and the encapsulation body, that is, there is a spacing between the end face of the notch facing the encapsulation body and the encapsulation body. The maximum width of the second pin is greater than or equal to the width of the chip. Since there is a notch on the second pin, and there is a spacing between the notch and the encapsulation body, the part of the second pin close to the encapsulation body is not provided with a notch, and the width of this part is greater than the width of the part provided with the notch. Then, the maximum width of the second pin can refer to the width of the part not provided with a notch. When the chip packaging structure is applied to a circuit board assembly, the second pin needs to be soldered to the circuit board. During soldering, a soldering area can be provided between the second pin and the circuit board. In this way, since the maximum width of the second pin is greater than or equal to the width of the chip, the width of the entire soldering area will not be reduced due to the provision of the notch, thereby being able to remain the same as or greater than the width of the chip, and further being able to reduce the situation of chip performance degradation.

[0020] In addition, since the circuit board assembly also includes a capacitor, the capacitor has a certain width. In the present application, the notches of two adjacent electrical connectors are arranged on the side close to each other and the positions are corresponding. In this way, the notch is arranged so that the distance between the parts with notches between the two adjacent electrical connectors is larger, so that the capacitor can be arranged between the two adjacent electrical connectors, so that there is no need to open a separate installation position for the capacitor on the circuit board, thereby improving the utilization rate of the circuit board. In other words, the present application can improve the utilization rate of the circuit board while ensuring sufficient welding width to reduce the performance degradation of the chip.

[0021] In a possible implementation, the notch is extended inward from an end of the second pin away from the package body, thereby increasing the size of the notch along the connection direction between the first pin and the second pin, thereby providing sufficient installation space for the capacitor close to the package chip structure.

[0022] In another possible implementation, the notch is disposed at a middle position of the second pin along the connection direction between the first pin and the second pin, that is, there is a distance between the notch and an end of the second pin away from the package body.

[0023] Based on this, at least two notches are provided on the second pin, and the at least two notches are respectively provided on two opposite surfaces of the second pin. In this way, when there are a large number of capacitors in the circuit board assembly, a capacitor can be fixed between every two adjacent electrical connectors, thereby further improving the utilization rate of the circuit board.

[0024] Further, with respect to the shape of the notch, in a possible implementation, the notch is a right-angled notch, that is, the notch is a notch with a right angle. The second pin has two connected and perpendicular surfaces, and the two surfaces together form the notch. In another possible implementation, the notch is an oblique angle notch. That is, the second pin has an inclined surface.

[0025] In the second aspect of the present application, there is also provided a chip packaging structure, including a bottom plate, a chip, a package body, and a plurality of connectors. The chip is disposed on the bottom plate. The package body is disposed on the bottom plate and wraps the chip. The plurality of electrical connectors are arranged in sequence along the width direction. The electrical connector includes a connected first pin and a second pin. The first pin is located inside the package body, and at least a part of the second pin is located outside the package body. There is a notch on the second pin. At least two adjacent electrical connectors have notches disposed on one side close to each other and corresponding in position, and there is a spacing between the notch and the package body. The maximum width of the second pin is greater than or equal to the width of the chip. Since there is a notch on the second pin, and there is a spacing between the notch and the package body, the part of the second pin close to the package body is not provided with a notch, and the width of this part is greater than the width of the part provided with the notch. Then, the maximum width of the second pin can refer to the width of the part not provided with the notch. When the chip packaging structure is applied to a circuit board assembly, the second pin needs to be soldered to the circuit board. During soldering, a soldering area can be provided between the second pin and the circuit board. In this way, since the maximum width of the second pin is greater than or equal to the width of the chip, the width of the entire soldering area will not be reduced due to the setting of the notch, so that it can remain the same as or greater than the width of the chip, thereby reducing the situation of chip performance degradation.

[0026] In addition, since the circuit board assembly further includes a capacitor, the capacitor has a certain width. In the present application, the notches of two adjacent electrical connectors are disposed on one side close to each other and corresponding in position. In this way, the setting of the notches makes the distance between the parts provided with notches between two adjacent electrical connectors relatively large. Thus, the capacitor can be disposed between two adjacent electrical connectors, so that there is no need to set up a separate installation position for the capacitor on the circuit board, thereby improving the utilization rate of the circuit board. That is to say, the present application can improve the utilization rate of the circuit board while ensuring a sufficient soldering width to reduce the situation of chip performance degradation.

[0027] In the second aspect of the present application, there is also provided a circuit board assembly, including a circuit board, an electronic device, and the chip packaging structure according to any one of the above embodiments. The electronic device and the chip packaging structure are both electrically connected to the circuit board, and the electronic device is located between the second pins of two adjacent electrical connectors. The circuit board assembly can achieve all the effects of the chip packaging structure.

[0028] In the third aspect of the present application, there is also provided a transceiver, including a housing and the above circuit board assembly, and the circuit board assembly is fixed inside the housing. The transceiver can achieve all the effects of the circuit board assembly.

[0029] In the fourth aspect of the present application, there is also provided a base station, including an antenna and the above transceiver, and the antenna is electrically connected to the transceiver. The base station can achieve all the effects of the transceiver. Description of the Drawings

[0030] To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1 It is a schematic structural diagram of a circuit board assembly in a related technology;

[0032] Figure 2 It is a schematic structural diagram of a circuit board assembly in another related technology;

[0033] Figure 3 It is Figure 1 a cross-sectional view at A-A in

[0034] Figure 4 It is Figure 1 another cross-sectional view at A-A in

[0035] Figure 5 It is a schematic structural diagram of a circuit board assembly in the first embodiment of the present application;

[0036] Figure 6 It is Figure 5 a partial enlarged schematic view at B in

[0037] Figure 7 It is a schematic structural diagram of a circuit board assembly in the second embodiment of the present application;

[0038] Figure 8 It is a partial enlarged schematic view of a circuit board assembly in the third embodiment of the present application;

[0039] Figure 9 It is Figure 5 a cross-sectional view at C-C in

[0040] Figure 10 It is Figure 5 another cross-sectional view at C-C in

[0041] Figure 11 It is Figure 5 yet another cross-sectional view at C-C in

[0042] Figure 12 It is a schematic structural diagram of a circuit board assembly in the fourth embodiment of the present application;

[0043] Figure 13 It is a schematic structural diagram of a circuit board assembly in the fifth embodiment of the present application;

[0044] Figure 14It is a schematic structural diagram of a circuit board assembly in the sixth embodiment of the present application;

[0045] Figure 15 It is a schematic structural diagram of a circuit board assembly in the seventh embodiment of the present application;

[0046] Figure 16 is Figure 15 a cross-sectional view taken along line D-D in

[0047] Reference numerals: 1 - circuit board assembly; 200 - circuit board; 201 - recess; 300 - capacitor; 100 - chip package structure; 10 - chip; 20 - base plate; 21 - first surface; 22 - second surface; 23 - third surface; 30 - package body; 31 - cavity; 32 - dielectric layer; 33 - cover plate; 34 - third connection layer; 35 - through hole; 36 - fourth connection layer; 40 - electrical connector; 41 - first pin; 42 - connection part; 43 - second pin; 431 - notch; 432 - inclined surface; 50 - bonding wire; 61 - first connection layer; 62 - second connection layer; 63 - adhesive layer. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without making creative efforts shall fall within the protection scope of the present application.

[0049] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. Among them, A and B can be singular or plural. The character " / " generally represents that the associated objects before and after are in an "or" relationship. "At least one (item)" means one or more, and "multiple" means two or more. "At least one (individual) of the following" or its similar expression means any combination of these items, including any combination of single (individual) or plural items (individuals). For example, at least one (individual) of a, b or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0050] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, rather than to describe a specific order of the target objects.

[0051] Terms such as "connected" and "linked" are used to express the interconnection or interaction between different components, which may include direct connection or indirect connection through other components. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a method, system, product, or device that comprises a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices. Terms such as "upper", "lower", "left", and "right" are only used with respect to the orientation of components in the drawings. These directional terms are relative concepts used for description and clarification, and they can change accordingly with the change in the orientation of the components placed in the drawings.

[0052] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0053] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" refers to two or more. For example, a plurality of processing units refers to two or more processing units; a plurality of systems refers to two or more systems.

[0054] A base station generally includes a transceiver and an antenna, and the transceiver is electrically connected to the antenna. The transceiver may include a housing and a circuit board assembly fixed within the housing, and the circuit board assembly may be referred to as a main board. The circuit board assembly includes a circuit board, electronic devices, and amplifiers, etc. The electronic devices may be capacitors. The amplifier may specifically be a power amplifier (air cavity package, PA). The amplifier generally integrates multiple different chips, and each chip may have different functions. Therefore, the amplifier may be referred to as a chip package structure.

[0055] Generally, a cavity packaging method is adopted to package multiple different chips to form a chip package structure. Exemplarily, such as Figure 1As shown, the chip package structure 100 includes a chip 10, a bottom plate 20, a package body 30, and an electrical connector 40. The package body 30 is disposed on the bottom plate 20 and encloses a cavity 31 with the bottom plate 20. The chip 10 is fixed on the bottom plate 20 and located within the cavity 31. The electrical connector 40 is fixed on the package body 30, with a part located within the cavity 31 and a part extending outside the package body 30. The chip 10 is connected to the part of the electrical connector 40 within the cavity 31 by wire bonding (WB), that is, the chip 10 and the electrical connector 40 are connected by a bonding wire 50.

[0056] As Figure 1 shown, a recess 201 is provided on the circuit board 200. The bottom plate 20 is located within the recess 201 and is connected to the recess 201 by welding to form a welding area b1. The part of the electrical connector 40 extending outside the package body 30 is attached to and welded to the circuit board 200 to form a welding area b2. Thus, electrical connection between the chip 10 and the circuit board 200 can be achieved through the bonding wire 50 and the electrical connector 40.

[0057] When the chip package structure 100 is in use, parasitic inductance Ld will be generated inside. Next, the relationship between the thickness L1 of the package body 30 between the electrical connector 40 and the bottom plate 20 and the parasitic inductance Ld is tested, and the test results shown in Table 1 are obtained.

[0058] Table 1 Relationship table between the thickness L1 of the package body 30 between the electrical connector 40 and the bottom plate 20 and the parasitic inductance Ld

[0059]

[0060]

[0061] It can be seen from Table 1 that the smaller the thickness L1 of the package body 30 between the electrical connector 40 and the bottom plate 20, the smaller the generated parasitic inductance Ld. Therefore, in order to reduce the parasitic inductance Ld, it is necessary to reduce the thickness L1 of the package body 30 between the electrical connector 40 and the bottom plate 20.

[0062] The relationship between the length d of the bonding wire 50 between the chip 10 and the electrical connector 40 and the parasitic inductance Ld is tested, and the test results shown in Table 2 are obtained.

[0063] Table 2 Relationship table between the length d of the bonding wire 50 and the parasitic inductance Ld

[0064] Number d Ld 1 600um 387pH 2 300um 257pH

[0065] As can be seen from Table 2, the shorter the length d of the bonding wire 50, the smaller the parasitic inductance Ld generated. Therefore, in order to reduce the parasitic inductance Ld, it is necessary to reduce the length d of the bonding wire 50 between the chip 10 and the electrical connector 40.

[0066] As can be seen from Table 1 and Table 2, in order to reduce the parasitic inductance Ld, it can be achieved by reducing the thickness L1 of the package 30 between the electrical connector 40 and the bottom plate 20, and / or reducing the length d of the bonding wire 50. Since Figure 1 in the related art shown, the top surface of the electrical connector 40 is higher than the top surface of the chip 10. Therefore, in another related art, as Figure 2 shown, by reducing the mounting height of the electrical connector 40 on the package 30, thereby reducing the thickness L1 of the package 30 between the electrical connector 40 and the bottom plate 20 and reducing the length d of the bonding wire 50, and further reducing the parasitic inductance Ld.

[0067] However, as Figure 2 shown, the distance between the welding area b1 and the welding area b2 is the same as the thickness L1 of the package 30 between the electrical connector 40 and the bottom plate 20. When the thickness L1 of the package 30 between the electrical connector 40 and the bottom plate 20 is reduced, the distance between the welding area b1 and the welding area b2 is also reduced. As a result, during the long-term use of the chip package structure 100, the solder at the welding area b1 will grow dendrites and condensation in the direction of the welding area b2, and the solder at the welding area b2 will also grow dendrites and condensation in the direction of the welding area b1, thereby causing the electrical connector 40 to be electrically connected to the bottom plate 20, and further causing a short circuit.

[0068] Based on this, as Figure 5 shown, the present embodiment provides a chip package structure 100, and the chip package structure 100 can be packaged by a plastic cavity sandwich (ACS) method. The chip package structure 100 may include a bottom plate 20, a chip 10, a package 30, and an electrical connector 40.

[0069] For ease of description, three directions can be defined here, namely the X direction, the Y direction, and the Z direction. The X direction is the length direction of the chip package structure 100, the Y direction is the width direction of the chip package structure 100, and the Z direction is the thickness direction of the chip package structure 100. Moreover, the X direction, the Y direction, and the Z direction are perpendicular to each other in pairs.

[0070] As Figure 5 shown, the bottom plate 20 may include a first surface 21, a second surface 22, and a third surface 23. The first surface 21 and the second surface 22 are located on the same side of the bottom plate 20 and are opposite to the third surface 23. In the present embodiment, the first surface 21 and the second surface 22 are coplanar, that is to say, the top surface of the bottom plate 20 is a plane.

[0071] The material of the bottom plate 20 can be a conductive material. Exemplarily, the material of the bottom plate 20 can be a metal. Specifically, in one example, the material of the bottom plate 20 can be entirely copper or diamond copper. In another example, the bottom plate 20 can include three metal layers. The material of the bottommost metal layer can be copper or diamond copper, the material of the middle metal layer can be molybdenum copper alloy, and the material of the topmost metal layer can be copper or diamond copper. Diamond copper can be a composite material of diamond powder and copper alloy.

[0072] The chip 10 can be a bare chip (die), that is, an unencapsulated chip. In this embodiment, the number of chips 10 can be multiple, and the functions of each chip 10 may be different. Exemplarily, the chip 10 can be a transistor, a capacitor, or a resistor, etc.

[0073] As Figure 5 shown, the chip 10 can be fixed to the first surface 21 of the bottom plate 20 through the first connection layer 61. Here, the first connection layer 61 can be a sintered silver layer. Of course, in other embodiments, the first connection layer 61 can also be a soldering layer, etc.

[0074] As Figure 5 shown, the package 30 can include a dielectric layer 32, a cover plate 33, and a third connection layer 34 located between the dielectric layer 32 and the cover plate 33. The dielectric layer 32 is fixed to the second surface 22 of the bottom plate 20 through the second connection layer 62. A cavity 31 can be formed between the dielectric layer 32, the third connection layer 34, the cover plate 33 and the bottom plate 20. The chip 10 is located in the cavity 31, that is, the package 30 can wrap the chip 10. Specifically, the package 30 can wrap the top surface and the side surface of the chip 10.

[0075] As Figure 6 shown, the dielectric layer 32 is provided with a through hole 35. The through hole 35 penetrates from the outer wall of the dielectric layer 32 to the inner wall, that is, one end of the through hole 35 communicates with the outside of the dielectric layer 32, and the other end communicates with the cavity 31.

[0076] The materials of both the dielectric layer 32 and the cover plate 33 can be plastics. Specifically, the materials of the dielectric layer 32 and the cover plate 33 can be epoxy resin.

[0077] As Figure 6 shown, the electrical connector 40 is fixed to the dielectric layer 32. The electrical connector 40 includes a first pin 41, a second pin 43, and a connecting portion 42 connected between the first pin 41 and the second pin 43. That is to say, the electrical connector 40 includes the first pin 41, the connecting portion 42, and the second pin 43 connected in sequence.

[0078] As Figure 5As shown, along the stacking direction of the base plate 20 and the chip 10, the distance L1 between the first pin 41 and the first surface 21 is less than the distance L2 between the second pin 43 and the second surface 22. That is, along the Z direction, the distance L1 between the first pin 41 and the first surface 21 is less than the distance L2 between the second pin 43 and the second surface 22. The distance L1 between the first pin 41 and the first surface 21 may refer to the distance L1 between the surface of the first pin 41 facing the base plate 20 and the first surface 21, and the distance L2 between the second pin 43 and the second surface 22 may refer to the distance L2 between the surface of the second pin 43 facing the base plate 20 and the second surface 22. Based on the related art, in this embodiment, the distance L2 between the second pin 43 and the second surface 22 is kept unchanged, and the distance L1 between the first pin 41 and the first surface 21 is reduced. Since at least part of the package 30 is fixed on the second surface 22, part of the package 30 is located between the first pin 41 and the second surface 22. When part of the package 30 is also provided on the first surface 21, part of the package 30 is also located between the first pin 41 and the first surface 21. By reducing the distance L1 between the first pin 41 and the first surface 21, the thickness of the package 30 between the first pin 41 and the first surface 21 can be reduced, thereby reducing the parasitic inductance. Moreover, in the related art, the first pin 41 is higher than the chip 10. In this embodiment, by reducing the distance L1 between the first pin 41 and the first surface 21, the length of the bonding wire 50 between the chip 10 and the electrical connector 40 can also be reduced, thus also reducing the parasitic inductance. In addition, since in this embodiment, based on the related art, the distance L2 between the second pin 43 and the second surface 22 is kept unchanged, the dendrite problem caused by the reduction of the distance L2 between the second pin 43 and the second surface 22 can be reduced, thereby avoiding the electrical connection between the electrical connector 40 and the base plate 20, which may lead to a short circuit. That is to say, while reducing the parasitic inductance, this embodiment can also reduce the generation of board-level dendrites.

[0079] Moreover, along the Z direction, there is a spacing between the first pin 41 and the second pin 43. That is to say, there is a height difference between the first pin 41 and the second pin 43.

[0080] Moreover, as Figure 6 shown, there is a first included angle a1 between the extending direction of the connecting portion 42 and the extending direction of the first pin 41, and there is a second included angle a2 between the extending direction of the connecting portion 42 and the extending direction of the second pin 43. The material of the electrical connector 40 can be a conductive material, specifically a metal. Therefore, the electrical connector 40 can be a sheet metal part, and in production, the electrical connector 40 can be obtained by bending a flat plate. This solution has a simple structure and is easy to implement. In addition, the electrical connector 40 can form a 3D structure after being bent.

[0081] Further, the first included angle a1 and the second included angle a2 may be the same. In this way, the first pin 41 and the second pin 43 are parallel to each other. In one example, as Figure 6 shown, the first included angle a1 is an obtuse angle, and the second included angle a2 is also an obtuse angle. Thus, when manufacturing the electrical connector 40, it is convenient to bend the flat plate. Moreover, the larger the first included angle a1 and the second included angle a2 are, the less likely the electrical connector 40 is to crack at the bending position during the bending process.

[0082] In another example, as Figure 7 shown, the first included angle a1 between the first pin 41 and the connecting portion 42 is a right angle, and the second included angle a2 between the second pin 43 and the connecting portion 42 is also a right angle.

[0083] Regarding the positional relationship among the first pin 41, the connecting portion 42, the cavity 31, and the through hole 35, in one possible implementation, as Figure 6 and Figure 7 shown, a part of the first pin 41 is located inside the cavity 31, and the remaining part of the first pin 41 and the connecting portion 42 are located inside the through hole 35. That is to say, the bending position between the first pin 41 and the connecting portion 42 is located inside the through hole 35. In this way, the length of the first pin 41 can be increased, thereby reducing the situation of large deformation during bending due to the too short length of the first pin 41.

[0084] Moreover, as Figure 6 and Figure 8 shown, the top surface of the part of the first pin 41 located inside the cavity 31 is exposed. One end of the bonding wire 50 is fixed to the chip 10, and the other end is fixed to the top surface of the first pin 41. In this way, the chip 10 can be electrically connected to the first pin 41 through the bonding wire 50, and the second pin 43 can be electrically connected to the circuit board 200, thereby realizing the electrical connection between the chip 10 and the circuit board 200.

[0085] In another possible implementation, as Figure 8 shown, a part of both the first pin 41 and the connecting portion 42 are located inside the cavity 31, and the remaining part of the connecting portion 42 is located inside the through hole 35. That is to say, the bending position between the first pin 41 and the connecting portion 42 is located inside the cavity 31.

[0086] As Figure 6 and Figure 8As shown, a part of the second pin 43 is located within the through hole 35, and the remaining part of the second pin 43 extends outside the dielectric layer 32. That is to say, the bending portion between the second pin 43 and the connecting portion 42 is located within the through hole 35. In this way, the distances between the portions of the second pin 43 extending outside the dielectric layer 32 and the second surface 22 are the same and large, thereby reducing the generation of board-level dendrites due to the too small distance between some of the second pins 43 and the second surface 22.

[0087] In addition, in Figure 1 the related art shown, the chip packaging structure 100 usually includes multiple chips 10. Exemplarily, Figure 3 for Figure 1 the cross-sectional view at A-A of Figure 3 as shown, in this related art, the chip packaging structure 100 includes two chips 10. It can be understood that here only the chip packaging structure 100 is illustrated by way of example. In actual products, the number of chips 10 is usually greater than two. As Figure 3 shown, the width W1 of the portion of the electrical connector 40 extending outside the package 30 is less than the width W2 of the chip 10, which will cause the performance of the chip 10 to decline. Therefore, based on this, as Figure 4 shown, by increasing the width W1 of the portion of the electrical connector 40 extending outside the package 30 so that the width W1 is greater than or equal to the width W2 of the chip 10, the performance decline of the chip 10 is reduced.

[0088] However, as Figure 3 shown, the capacitor 300 is provided on the circuit board 200 and electrically connected to the circuit board 200. In order to improve the utilization rate of the circuit board 200, the capacitor 300 can be located between two adjacent electrical connectors 40. And as Figure 4 shown, when the width W1 of the portion of the electrical connector 40 extending outside the package 30 is widened to be greater than or equal to the width W2 of the chip 10, the distance between the portions of two adjacent electrical connectors 40 extending outside the package 30 is reduced and is less than the width of the capacitor 300. As a result, the capacitor 300 needs to be installed on the side of the electrical connector 40 located at the edge among multiple electrical connectors 40, thereby reducing the utilization rate of the circuit board 200.

[0089] Based on this, in this embodiment, as Figure 9As shown, the chip package structure 100 includes a plurality of electrical connectors 40 arranged in sequence along the Y direction, and the structures of the plurality of electrical connectors 40 are the same. A notch 431 is provided on the second pin 43, and at least two adjacent electrical connectors 40 have the notches 431 provided on the side close to each other and corresponding in position. There is a spacing between the notch 431 and the dielectric layer 32, that is, there is a spacing between the end face of the notch 431 facing the dielectric layer 32 and the dielectric layer 32. The maximum width W1 of the second pin 43 is greater than or equal to the width W2 of the chip 10. Since the notch 431 is provided on the second pin 43 and there is a spacing between the notch 431 and the dielectric layer 32, the part of the second pin 43 close to the dielectric layer 32 is not provided with the notch 431, and the width of this part is greater than the width of the part provided with the notch 431. The maximum width W1 of the second pin 43 may refer to the width of the part not provided with the notch 431. When the chip package structure 100 is applied to the circuit board assembly 1, the second pin 43 needs to be soldered to the circuit board 200. During soldering, a soldering area b3 can be provided between the second pin 43 and the circuit board 200. In this way, since the maximum width W1 of the second pin 43 is greater than or equal to the width W2 of the chip 10, the maximum width of the entire soldering area b3 will not be reduced due to the provision of the notch 431, so that it can remain the same as or greater than the width W2 of the chip 10, and thus the situation of performance degradation of the chip 10 can be reduced.

[0090] In addition, as Figure 9 shown, since the circuit board assembly 1 further includes a capacitor 300, the capacitor 300 has a certain width. In this embodiment, the notches 431 of two adjacent electrical connectors 40 are provided on the side close to each other and corresponding in position. In this way, the provision of the notches 431 makes the distance between the parts provided with the notches 431 between two adjacent electrical connectors 40 relatively large. Thus, the capacitor 300 can be arranged between two adjacent electrical connectors 40, so that there is no need to set a separate installation position for the capacitor 300 on the circuit board 200, and thus the utilization rate of the circuit board 200 can be improved. That is to say, this embodiment can, while ensuring a sufficient soldering width to reduce the performance degradation of the chip 10, also improve the utilization rate of the circuit board 200.

[0091] Regarding the setting position of the notch 431, in this embodiment, as Figure 9 shown, the notch 431 extends inward from the end of the second pin 43 facing away from the dielectric layer 321. Thus, the size of the notch 431 along the X direction can be increased, so as to provide sufficient installation space for the capacitor 300 close to the chip package structure 100.

[0092] In other embodiments, the notch 431 is provided at the middle position of the second pin 43 along the X direction, that is, there is a spacing between the notch 431 and the end of the second pin 43 facing away from the dielectric layer 32.

[0093] Regarding the number of notches 431 provided on the second pin 43, in one possible implementation, at least two notches 431 are provided on the second pin 43. Exemplarily, as Figure 9 shown, two notches 431 are provided on the second pin 43, and the two notches 431 are respectively provided on two opposite surfaces of the second pin 43. In this way, when the number of capacitors 300 in the circuit board assembly 1 is relatively large, one capacitor 300 can be fixed between every two adjacent electrical connectors 40, thereby further improving the utilization rate of the circuit board 200.

[0094] In another possible implementation, as Figure 10 shown, one notch 431 is provided on the second pin 43. Moreover, the notches 431 on the second pins 43 of two adjacent electrical connectors 40 are located on the sides close to each other, so that the capacitor 300 can be located between the two electrical connectors 40.

[0095] Regarding the shape of the notch 431, in one possible implementation, as Figure 9 and Figure 10 shown, the notch 431 is a right-angle notch, that is to say, the notch 431 is a notch with a right angle. The second pin 43 has two connected and perpendicular surfaces, and these two surfaces can jointly form the notch 431. Exemplarily, Figure 9 in, the second pin 43 as a whole can be in a "T" shape. Figure 10 in, the second pin 43 as a whole can be in an "L" shape.

[0096] In another possible implementation, as Figure 11 shown, the notch 431 is an oblique-angle notch. That is to say, the second pin 43 has an inclined surface 432. Exemplarily, the second pin 43 as a whole can be in a trapezoidal shape.

[0097] In other embodiments of the present application, the difference from the Figure 5 shown embodiment lies in the packaging method of the chip packaging structure 100, the top surface structure of the bottom plate 20, the structure of the electrical connector 40, the structure and material of the package body 30, and the positional relationship between the electrical connector 40 and the dielectric layer 32.

[0098] Specifically, as Figure 12 shown, in this embodiment, the packaging method of the chip packaging structure 100 can be a ceramic cavity packaging (ceramic flat package, CPF) method. Then, the materials of the dielectric layer 32 and the cover plate 33 can both be ceramics. The second connection layer 62 and the third connection layer 34 can both be solder layers, and the fourth connection layer 36 can be an adhesive layer.

[0099] As Figure 12As shown, there is a height difference between the first surface 21 and the second surface 22. Specifically, the bottom plate 20 further has a third surface 23, and the third surface 23 is located on the side away from the first surface 21 and the second surface 22. The distance between the first surface 21 and the third surface 23 is greater than the distance between the second surface 22 and the third surface 23. That is to say, the top surface of the bottom plate 20 is a stepped surface.

[0100] As Figure 12 shown, the electrical connector 40 is a flat plate structure, that is, the top surfaces of the first pin 41, the connecting portion 42, and the second pin 43 are coplanar, and the bottom surfaces of the first pin 41, the connecting portion 42, and the second pin 43 are coplanar. In this way, the distance L1 between the first pin 41 and the first surface 21 can be made smaller than the distance L2 between the second pin 43 and the second surface 22. Moreover, in this embodiment, on the basis of the related art, the middle area at the top of the bottom plate 20 can be heightened to form the first surface 21, so that without reducing the distance between the second pin 43 and the third surface 23, the distance L1 between the first pin 41 and the first surface 21 can be reduced.

[0101] As Figure 12 shown, the package 30 is disposed on the second surface 22. The package 30 Figure 5 On the basis of the embodiment shown, a fourth connection layer 36 is further added. The dielectric layer 32 can be fixed to the second surface 22 through the second connection layer 62, the electrical connector 40 can be fixed to the dielectric layer 32 through the fourth connection layer 36, and the cover plate 33 is fixed to the electrical connector 40 through the third connection layer 34.

[0102] Regarding the positional relationship between the projection of the first pin 41 on the bottom plate 20 and the first surface 21 and the second surface 22, in a possible implementation manner, as Figure 12 shown, the projection of the first pin 41 on the bottom plate 20 is located within the second surface 22, and the package 30 is disposed on the second surface 22. In this way, the distance L1 between the first pin 41 and the first surface 21 can be reduced, and thus the thickness of the package 30 between the first pin 41 and the first surface 21 can be reduced, thereby reducing the parasitic inductance.

[0103] In another possible implementation manner, as Figure 13As shown, the projection of the first pin 41 on the bottom plate 20 overlaps with the first surface 21, and the projection of the first pin 41 on the bottom plate 20 overlaps with the second surface 22. A part of the package body 30 is located between the first pin 41 and the first surface 21, and a part of the package body 30 is located between the first pin 41 and the second surface 22. In another possible implementation, the projection of the first pin 41 on the bottom plate 20 is located within the first surface 21. A part of the package body 30 is provided on the first surface 21, and a part of the package body 30 is provided on the second surface 22. In this way, the thickness of the package body 30 between the first pin 41 and the bottom plate 20 is smaller, thereby further reducing the parasitic inductance.

[0104] In other embodiments of the present application, as Figure 14 shown, the difference from the embodiment shown in Figure 12 is the positional relationship between the electrical connector 40 and the dielectric layer 32, and in this embodiment, the third connection layer 34 is removed based on the embodiment shown in Figure 12 Specifically, in this embodiment, the dielectric layer 32 is provided with a through hole 35 along the X direction, and a part of the electrical connector 40 is provided in the through hole 35.

[0105] In other embodiments of the present application, the difference from the embodiment shown in Figure 12 is the structure and material of the package body 30. As Figure 15 shown, in this embodiment, the packaging method of the chip packaging structure 100 is a small outline package (SOP) method. The material of the package body 30 can be a plastic encapsulant. The package body 30 can be attached to the surface of the chip 10. A glue layer 63 is provided on the top of the chip 10. The package body 30 covers the top surface of the glue layer 63, and covers the side surfaces of the glue layer 63, the chip 10, and the first connection layer 61. Moreover, the package body 30 also covers the area on the top surface of the bottom plate 20 where the first connection layer 61 is not provided and the side surfaces.

[0106] As Figure 16 shown, two notches 431 can be provided on the second pin 43, and the two notches 431 are respectively provided on two opposite surfaces of the second pin 43. In this way, when the number of capacitors 300 in the circuit board assembly 1 is large, a capacitor 300 can be fixed between every two adjacent electrical connectors 40, thereby further improving the utilization rate of the circuit board 200.

[0107] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all belong to the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that, Comprising: A bottom plate having a first surface and a second surface, the first surface and the second surface being on the same side of the bottom plate; A chip disposed on the first surface; A package, at least a part of the package being disposed on the second surface, the package and the bottom plate enclosing a cavity, and the chip being located in the cavity; An electrical connector passing through the package, the electrical connector including a first pin and a second pin connected to each other, at least a part of the first pin being located in the cavity and electrically connected to the chip, at least a part of the second pin being located outside the package, and along the stacking direction of the bottom plate and the chip, the distance between the first pin and the first surface is less than the distance between the second pin and the second surface.

2. The chip packaging structure according to claim 1, wherein, Along the stacking direction, there is a spacing between the first pin and the second pin.

3. The chip packaging structure according to claim 1 or 2, wherein The electrical connector further includes a connecting portion connected between the first pin and the second pin, and there is a first included angle between the connecting portion and the extending direction of the first pin, and a second included angle between the connecting portion and the extending direction of the second pin.

4. The chip packaging structure according to claim 3, wherein, The first included angle is an obtuse angle or a right angle, and the second included angle is an obtuse angle or a right angle.

5. The chip packaging structure according to claim 3 or 4, characterized in that, The package is provided with a through hole; At least a part of the first pin and a part of the connecting portion are both located in the cavity, and the remaining part of the connecting portion is located in the through hole; or, a part of the first pin is located in the cavity, and the remaining part of the first pin and the connecting portion are located in the through hole.

6. The chip packaging structure according to any one of claims 3-5, characterized in that, The package is provided with a through hole, a part of the second pin is located in the through hole, and the remaining part of the second pin extends outside the package.

7. The chip packaging structure according to any one of claims 1-5, characterized in that, The bottom plate further has a third surface on a side opposite to the first surface and the second surface, and the distance between the first surface and the third surface is greater than the distance between the second surface and the third surface.

8. The chip packaging structure according to claim 7, characterized in that, The projection of the first pin on the bottom plate satisfies any one of the following conditions: The projection of the first pin on the bottom plate is located within the first surface, and a part of the package is located between the first pin and the first surface; The projection of the first pin on the bottom plate is located within the second surface, and a part of the package is located between the first pin and the second surface; The projection of the first pin on the bottom plate overlaps with the first surface, the projection of the first pin on the bottom plate overlaps with the second surface, a part of the package is located between the first pin and the first surface, and a part of the package is located between the first pin and the second surface.

9. The chip packaging structure according to any one of claims 1-8, characterized in that, The chip packaging structure includes a plurality of the electrical connectors arranged in sequence along the width direction, a notch is provided on the second pin, and the maximum width of the second pin is greater than or equal to the width of the chip; At least two adjacent ones of the notches of the electrical connectors are disposed on one side close to each other and are in corresponding positions, and there is a spacing between the notches and the encapsulation body. The width direction is the direction perpendicular to both the stacking direction and the connection direction, and the connection direction is the direction in which the first pin is connected to the second pin.

10. The chip package structure according to claim 9, characterized in that, The notch extends inward from one end of the second pin away from the encapsulation body.

11. The chip packaging structure according to claim 10, wherein, At least two notches are provided on the second pin, and the at least two notches are respectively disposed on two opposite surfaces of the second pin.

12. The chip packaging structure according to claim 10 or 11, characterized in that, The notch is a right-angle notch or an oblique-angle notch.

13. A chip packaging structure, characterized in that, Comprising: A bottom plate; A chip, which is disposed on the bottom plate; An encapsulation body, which is disposed on the bottom plate and wraps the chip; A plurality of electrical connectors arranged in sequence along the width direction. The electrical connectors include a connected first pin and a second pin. The first pin is located inside the encapsulation body and is electrically connected to the chip. At least a part of the second pin is located outside the encapsulation body. A notch is provided on the second pin. At least two adjacent ones of the notches of the electrical connectors are disposed on one side close to each other and are in corresponding positions. The width direction is the direction perpendicular to both the stacking direction and the connection direction. The stacking direction is the direction in which the bottom plate and the chip are stacked, and the connection direction is the direction in which the first pin is connected to the second pin.

14. A circuit board assembly, characterized in that, Comprising a circuit board, an electronic device, and the chip packaging structure according to any one of claims 1-13. The electronic device and the chip packaging structure are both electrically connected to the circuit board, and the electronic device is located between the second pins of two adjacent electrical connectors.

15. A transceiver, characterized in that, Comprising a housing and the circuit board assembly according to claim 14. The circuit board assembly is fixed inside the housing.

16. A base station, characterized in that, Comprising an antenna and the transceiver according to claim 15. The antenna is electrically connected to the transceiver.

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