Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, the semiconductor device being capable of suppressing the occurrence of a three-phase point comprising a plating layer, a resin layer, and a solder layer in an electrode layer, and being capable of preventing the occurrence of cracks in the electrode layer. This semiconductor device is sealed by a sealing resin, and is provided with: a semiconductor substrate; an electrode layer provided on the upper surface side of the semiconductor substrate; a plating layer provided on the upper surface of the electrode layer and having a first region and a second region outside the first region in plan view; a solder layer disposed on the first region of the plating layer; and a solder blocking part which is formed on the plating layer and blocks the solder from flowing from the first region to the second region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. Background Art

[0002] In Patent Document 1, there is disclosed a semiconductor module including a semiconductor chip having a semiconductor substrate and an electrode layer formed on the semiconductor substrate, a plating layer formed on the electrode layer, a solder layer formed on the plating layer, and a sealing resin for sealing the semiconductor chip. Further, a structure in which the entire side surface of the plating layer is covered with the solder layer is shown. Prior Art Documents Patent Documents

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-178755 Summary of the Invention Technical Problem to be Solved by the Invention

[0004] In the semiconductor device described in Patent Document 1, there is a triple point where a plating layer, a resin layer, and a solder layer are aggregated with each other on the electrode layer. Therefore, due to the stress difference between the three layers, strain is concentrated in the triple point portion, and there is a problem that cracks are generated in the electrode layer.

[0005] The present invention is proposed to solve the above technical problem, and an object thereof is to provide a semiconductor device and a method for manufacturing a semiconductor device, which can suppress the generation of a triple point composed of a plating layer, a resin layer, and a solder layer on an electrode layer and prevent cracks from being generated in the electrode layer. Technical Means for Solving the Technical Problem

[0006] The semiconductor device according to the present disclosure is a semiconductor device sealed with a sealing resin, and includes: a semiconductor substrate; an electrode layer provided on the upper surface side of the semiconductor substrate; a plating layer provided on the upper surface of the electrode layer and having a first region and a second region outside the first region in a plan view; and a solder blocking portion formed on the plating layer to block solder so that the solder does not flow from the first region to the second region.

[0007] The method for manufacturing a semiconductor device according to the present disclosure is a method for manufacturing a semiconductor device sealed with a sealing resin, and includes: an electrode layer forming step of forming an electrode layer on the upper surface side of a semiconductor substrate; a plating layer forming step of forming a plating layer having a first region and a second region outside the first region in a plan view on the upper surface of the electrode layer; a solder blocking portion forming step of forming a solder blocking portion on the plating layer to block solder so that the solder does not flow from the first region to the second region; and a solder layer forming step of providing solder on the first region to form a solder layer. Advantages of the Invention

[0008] According to the semiconductor device and the method of manufacturing the semiconductor device according to the present disclosure, it is possible to suppress the generation of the triple point of the plating layer, the resin layer, and the solder layer on the electrode layer, and it is possible to prevent the electrode layer from cracking. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic top view of the semiconductor device according to Embodiment 1. Figure 2 It is the Figure 1 schematic cross-sectional view taken along line X-X in the semiconductor device according to Embodiment 1. Figure 3 It is the Figure 2 schematic top view taken along line Y-Y in the semiconductor device according to Embodiment 1. Figure 4 It is a schematic top view of the semiconductor device according to Modification 1 of Embodiment 1. Figure 5 It is the Figure 4 schematic cross-sectional view taken along line X-X in the semiconductor device according to Modification 1 of Embodiment 1. Figure 6 It is a schematic cross-sectional view of the semiconductor device according to Modification 2 of Embodiment 1. Figure 7 It is a schematic top view of the semiconductor device according to Modification 3 of Embodiment 1. Figure 8 It is a schematic top view of the semiconductor device according to Modification 3 of Embodiment 1. Figure 9 It is a schematic top view of the semiconductor device according to Modification 4 of Embodiment 1. Figure 10 It is the Figure 9 schematic cross-sectional view taken along line X-X in the semiconductor device according to Modification 4 of Embodiment 1. Figure 11 It is a schematic top view of the semiconductor device according to the modification of Embodiment 1. Figure 12 It is a schematic top view of the semiconductor device according to the modification of Embodiment 1. Figure 13 It is a schematic top view of the semiconductor device according to Embodiment 2. Figure 14 It is the Figure 13 schematic cross-sectional view taken along line X-X in the semiconductor device according to Embodiment 2. Figure 15 It is a schematic top view of the semiconductor device according to Modification 1 of Embodiment 2. Figure 16This is a schematic cross-sectional view taken along line X-X of the semiconductor device according to Modification Example 1 of Embodiment 2. Figure 15 in the Figure 17 This is a schematic cross-sectional view of the semiconductor device according to Modification Example 2 of Embodiment 2. Figure 18 This is a schematic top view of the semiconductor device according to Modification Example 3 of Embodiment 2. Figure 19 This is a schematic top view of the semiconductor device according to Modification Example 3 of Embodiment 2. Detailed Embodiments

[0010] <Introduction> In this specification, one side in the direction parallel to the depth direction of the semiconductor device is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of the substrate, layer, or other member is referred to as the upper surface, and the other is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is mounted.

[0011] In addition, for the sake of convenience in explanation, hereinafter, the width direction of the semiconductor device is defined as the x direction, the depth direction of the semiconductor device intersecting the x direction is defined as the y direction, and the thickness direction or depth direction of the semiconductor device, that is, the normal direction with respect to the xy plane, is defined as the z direction for explanation.

[0012] In addition, the drawings are schematically shown, and the mutual relationships of the sizes and positions of the images respectively shown in different drawings are not necessarily accurately recorded and can be appropriately changed. In addition, in the following description, the same reference numerals are assigned to the same structural elements for illustration, and their names and functions are also assumed to be the same. Thus, the detailed description thereof may sometimes be omitted.

[0013] Embodiment 1. The following describes Embodiment 1 with reference to the drawings. Figure 1 This is a schematic top view of the semiconductor device 100 according to Embodiment 1. Figure 2 This is a schematic cross-sectional view of the semiconductor device 100 according to Embodiment 1. Figure 2 Indicates Figure 1 the cross-section along the single dotted line X-X shown.

[0014] In the following description, semiconductor devices sealed with a sealing resin and semiconductor devices that are assumed to be sealed with a sealing resin in the future are described.

[0015] Using Figures 1 to 3 to explain the structure of the semiconductor device 100. As Figure 2 shown, the semiconductor device 100 includes a semiconductor substrate 1, an electrode layer 2, a plating layer 3, a solder layer 4, and a solder blocking portion 5.

[0016] The semiconductor substrate 1 is made of various semiconductor materials such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

[0017] As Figure 2 shown, the electrode layer 2 is provided on the upper surface side of the semiconductor substrate 1. An interlayer insulating film described later may also be provided between the electrode layer 2 and the semiconductor substrate 1. The electrode layer 2 may also be made of aluminum alloy. For example, the electrode layer 2 is formed of an aluminum-silicon alloy (Al-Si-based alloy).

[0018] As Figure 2 shown, the plating layer 3 is provided on the upper surface of the electrode layer 2. Next, Figure 3 is used to describe the plating layer 3 in more detail. Figure 3 is a horizontal cross-sectional view with the dash-dot line Y-Y shown in Figure 2 as the cross-section. That is, it is a horizontal cross-sectional view with the upper surface of the plating layer 3 as the cross-section, and is a view showing the solder layer 4 omitted. The above horizontal cross-sectional view is called a top view. In the following description of the present invention, the "top view" is Figure 3 similarly a horizontal cross-sectional view with the upper surface of the plating layer 3 of the semiconductor device as the cross-section. As Figure 3 shown, the plating layer 3 is composed of a first region 3a located at the center of the plating layer 3 and a second region 3b located outside the first region 3a when viewed from above. Here, the so-called "viewed from above" means observing from the viewpoint shown in Figure 3 . In the following description of the present invention, as Figure 3 shown, the "top view" is a viewpoint that takes the upper surface of the plating layer 3 of the semiconductor device as the cross-section and observes the cross-section from above. In addition, the plating layer 3 may be made of Au, for example, or may be made of nickel or a nickel alloy. In addition, the plating layer 3 may have a laminated structure including two or more metal layers, for example. This laminated structure is composed of a NiP layer and an Au layer, for example. By providing the plating layer 3, the wettability between the electrode layer 2 and the bonding member, that is, the solder layer 4, can be improved. For example, the bonding property with the lead frame can be enhanced.

[0019] As Figures 1 to 3 shown, the solder layer 4 is provided on the first region 3a of the plating layer 3. In the present embodiment, the solder layer 4 is provided over the entire upper surface of the first region 3a, but may also be provided on a part of the upper surface of the first region 3a.

[0020] As Figure 2 , Figure 3 shown, the solder blocking portion 5 is formed on the plating layer 3. In the present embodiment, the solder blocking portion 5 is a gap between the first region 3a and the second region 3b of the plating layer 3. As Figure 3As shown, a gap may also be formed so as to surround the outer periphery of the first region 3a of the plating layer 3. Additionally, Figure 2 , Figure 3 The width of the gap is shown more emphasizedly in [reference] than the actual width of the gap. However, as described later, the width of the gap may also be the width of the degree of cracking that divides the first region 3a and the second region 3b. Additionally, as Figure 2 shown, among the side surfaces of the first region 3a and the second region 3b where the gap is formed, it is preferable that the side surface of the first region 3a is perpendicular to the upper surface of the electrode layer 2. The reason will be described later. Additionally, as Figure 2 shown, the gap may also be provided from the upper surface of the plating layer 3 to the lower surface of the plating layer 3. The gap only needs to be formed on the upper surface of the plating layer 3, and it may not reach the lower surface of the plating layer 3.

[0021] As Figure 3 shown, it is preferable to form the gap so that the center of the first region 3a coincides with the center of the entire plating layer 3. In Figure 3 , the gap is provided symmetrically with respect to the center of the entire plating layer 3, but it is not necessary to be provided symmetrically. As long as a gap is formed between the first region 3a and the second region 3b, the formation position and shape of the gap are arbitrary.

[0022] As described above, the semiconductor device 100 of the present embodiment is configured. By providing the solder blocking portion 5, i.e., the gap, on the plating layer 3, it is possible to suppress the generation of a triple point composed of the three layers of the plating layer 3, the resin layer, and the solder layer 4 on the electrode layer 2, and to prevent the electrode layer 2 from cracking. The reason will be described below.

[0023] By providing the gap, it is possible to block the solder supplied to the upper surface of the first region 3a so that it does not flow from the upper surface of the first region 3a to the upper surface of the second region 3b. It is possible to make the solder stay on the upper surface of the first region 3a by the surface tension of the solder, and to prevent the solder from flowing over the second region 3b and the electrode layer 2. Additionally, by adjusting the width of the gap in consideration of the viscosity of the solder, etc., it is possible to prevent the solder from entering the gap. Therefore, even when the semiconductor device 100 is sealed with a sealing resin, it is possible to suppress the generation of a triple point composed of the three layers of the plating layer 3, the resin layer formed of the sealing resin, and the solder layer 4 on the electrode layer 2. Thereby, it is possible to prevent the electrode layer 2 from cracking. Additionally, when the crack generated in the electrode layer 2 reaches the interlayer insulating film 7, the insulating film function cannot be exerted, resulting in element failure. By applying the present invention, it is possible to prevent the triple point on the electrode layer 2 from cracking and to prevent element failure.

[0024] The width of the gap serving as the solder blocking portion 5 is preferably narrow. By forming the width of the gap to be narrow, it is possible to further suppress the inflow of solder into the gap and its flow on the electrode layer 2. In addition, among the side surfaces of the first region 3a and the second region 3b where the gap is formed, it is preferable that the side surface of the first region 3a is perpendicular to the upper surface of the electrode layer 2. Usually when forming the plating layer 3 on the electrode layer 2, the end portion of the plating layer 3 becomes a gentle shape with respect to the electrode layer 2. In the case of a gentle shape, solder easily flows on the electrode layer 2. Therefore, by forming the side surface of the first region 3a where the gap is formed to be perpendicular to the upper surface of the electrode layer 2, it is possible to further suppress the case where solder flows into the gap and on the electrode layer 2.

[0025] In addition, when the semiconductor substrate 1 is made of SiC, since the breakdown voltage is higher than that of Si, a higher voltage is applied when using the semiconductor device. Therefore, in the SiC substrate, cracks in the electrode layer 2 are more likely to occur. By applying the present invention, it is possible to prevent cracks from occurring at the triple points on the electrode layer 2 and suppress the occurrence of cracks in the electrode layer 2.

[0026] In addition, when the electrode layer 2 is made of an aluminum alloy, such as an Al - Si alloy, the strength is lower compared to the case where the electrode layer 2 is made of other materials, so cracks in the electrode layer 2 are more likely to occur. By applying the present invention, in the case where the electrode layer 2 is made of an aluminum alloy that is prone to cracking, it is possible to prevent cracks from occurring in the three - phase electricity on the electrode layer 2.

[0027] Next, a method for manufacturing the semiconductor device 100 of the present embodiment will be described. The method for manufacturing the semiconductor device 100 of the present embodiment is basically the same as the manufacturing method of a conventional semiconductor device except for the solder blocking portion forming process, so a part of it will be omitted for description.

[0028] The manufacturing method of the semiconductor device 100 includes an electrode layer forming process, a plating layer forming process, a solder blocking portion forming process, and a solder layer forming process.

[0029] First, the electrode layer forming process will be described. The semiconductor substrate 1 is formed, and the electrode layer 2 is formed on the upper surface side of the semiconductor substrate 1. The electrode layer 2 can also be formed by a PVD method such as sputtering or evaporation.

[0030] Next, the plating layer forming process will be described. A plating layer 3 having a first region 3a and a second region 3b outside the first region 3a in a top view is formed on the upper surface of the electrode layer 2. The plating layer 3 can be formed by a non - electrolytic plating method or an electrolytic plating method.

[0031] Next, the solder blocking portion forming process will be described. In the present embodiment, a method of forming a gap between the first region 3a and the second region 3b of the plating layer 3 with the solder blocking portion 5 as the gap will be described.

[0032] As an example of the method for forming the gap, it is preferable to pass an electric current and form the gap by dividing the plating layer 3 into a first region 3a and a second region 3b. For example, the main current flowing between the upper electrode and the lower electrode provided in the semiconductor device may also be used, and the plating layer 3 is separated by passing a main current larger than the normal case. If the gap is formed by the above method, the width of the gap can be set to the width of the crack that divides the first region 3a and the second region 3b, and the side surface of the first region 3a where the gap is formed can be formed perpendicular to the upper surface of the electrode layer 2.

[0033] Therefore, if the plating layer 3 is divided into the first region 3a and the second region 3b to form the gap, the width of the gap can be reduced, and the side surface of the first region 3a where the gap is formed can be formed perpendicular to the upper surface of the electrode layer 2. The method for forming the gap is not limited to the method using the above electric current. For example, a groove may be provided on the plating layer 3 by grinding or etching to form the gap.

[0034] Next, the plating layer forming process will be described. Solder is provided on the first region 3a of the plating layer 3 to form a solder layer 4.

[0035] Through the above process, the semiconductor device 100 is manufactured. As described above, the manufacturing method of the semiconductor device 100 according to the present embodiment further includes a solder blocking portion forming process, and the solder blocking portion 5 is a gap. By forming the gap, in the solder layer forming process, the solder provided on the first region 3a can be blocked so that it does not flow from the first region 3a to the second region 3b. The surface tension of the solder can be used to keep the solder staying on the first region 3a, and the solder can be prevented from flowing over the second region 3b and the electrode layer 2. In addition, by adjusting the width of the gap in consideration of the viscosity of the solder, etc., the solder can be prevented from entering the gap. Therefore, even when the semiconductor device 100 is sealed with a sealing resin, it is possible to suppress the generation of a triple point composed of the plating layer 3, the resin layer made of the sealing resin, and the solder layer 4 on the electrode layer 2. As a result, cracking of the electrode layer 2 can be prevented.

[0036] In addition, by forming the width of the gap to be narrow, the situation where the solder flows into the gap and flows on the electrode layer 2 can be further suppressed. In addition, by forming the side surface of the first region 3a where the gap is formed perpendicular to the upper surface of the electrode layer 2, the situation where the solder flows into the gap and flows on the electrode layer 2 can be further suppressed.

[0037] Next, use Figures 4 to 12 to describe a modification of Embodiment 1. In Figures 4 to 12 , the width of the gap is shown more emphatically than the actual width of the gap. First, use Figure 4 , Figure 5Description of Modification Example 1 Figure 4 It is a schematic top view of the semiconductor device according to Modification Example 1 Figure 5 It is a schematic cross-sectional view of the semiconductor device according to Modification Example 1 Figure 5 Indicates Figure 4 The cross-section of the single dotted line X-X shown

[0038] As Figure 4 、 Figure 5 As shown, a protective film 8 surrounding the outer periphery of the plating layer 3 can be further formed on the upper surface side of the electrode layer 2. As Figure 5 As shown, the protective film 8 can be in contact with the upper surface of the electrode layer 2. In addition, as Figure 4 As shown, the protective film 8 can be formed so as to surround the outer periphery of the second region 3b of the plating layer 3. The protective film 8 can be formed of, for example, polyimide

[0039] Next, use Figure 6 To describe Modification Example 2 Figure 6 It is a schematic cross-sectional view of the semiconductor device according to Modification Example 2. In Modification Example 2, it is assumed that the semiconductor device is sealed with a sealing resin. As Figure 6 As shown, a sealing resin 9 that seals at least the electrode layer 2 can be formed. In addition, as Figure 6 As shown, the sealing resin 9 may not be filled into the gap. As described above, the width of the gap is emphasized, and the actual width of the gap is narrow. By making the width of the gap narrow, like the solder, the sealing resin 9 can be prevented from entering the gap. A void can also be formed in the gap. By preventing the solder and the sealing resin 9 from entering the gap, a void can be formed in the gap. By forming the void, since the solder on the first region 3a does not enter the gap, the generation of the triple point on the electrode layer 2 can be further suppressed. By optimizing the viscosity, material, or sealing process of the sealing resin, etc., the sealing resin 9 can be prevented from entering the gap. The sealing resin 9 can also be filled in the gap. By filling the sealing resin 9 into the gap, the solder on the first region 3a does not enter the gap, so the generation of the triple point on the electrode layer 2 can be further suppressed

[0040] Next, use Figure 7 、 Figure 8 To describe Modification Example 3 Figure 7 、 Figure 8 It is a schematic top view of the semiconductor device according to Modification Example 3 Figure 7 The cross-sectional view of the single dotted line X-X shown is the same as the cross-sectional view shown in Figure 2 As shown Figure 8 The cross-sectional view of the single dotted line X-X shown is the same as the cross-sectional view shown in Figure 5 As shown. The semiconductor chip 10 includes a semiconductor substrate 1 and an electrode layer 2. As Figure 7As shown, when the semiconductor chip 10 is rectangular in plan view, gaps can also be formed only in the region of the plating layer 3 on the short side of the semiconductor chip 10. It is known that when the semiconductor chip 10 is rectangular, cracks are more likely to occur in the electrode layer 2 when flowing on the short side of the semiconductor chip 10 than on the long side. Therefore, by adopting a structure in which gaps are formed only in the region of the plating layer 3 on the short side of the semiconductor chip 10, generation of triple points on the electrode layer 2 can be suppressed on the short side of the semiconductor chip 10 where cracks are likely to occur, and cracks in the electrode layer 2 can be prevented. In addition, according to the structure of Modification 3, the area of the first region 3a is larger than that of the structure of Embodiment 1. Therefore, the region carrying the solder can be enlarged, and the bonding strength can be improved.

[0041] In addition, as Figure 8 shown, in addition to the structure of Modification 3, the protective film 8 can also be formed in the same manner as in Modification 1. In addition, as Figure 8 shown, the protective film 8 can also be formed so as to surround the outer periphery of the entire plating layer 3 including the gaps.

[0042] In addition, in addition to the structure of Modification 3, the sealing resin 9 can also be formed in the same manner as in Modification 2.

[0043] Next, Figure 9 and Figure 10 are used to describe Modification 4. Figure 9 is a schematic plan view of the semiconductor device according to Modification 4. Figure 10 is a schematic cross-sectional view of the semiconductor device according to Modification 4. Figure 10 represents Figure 9 the cross-section along the dash-dotted line X-X shown in Figure 9 and Figure 10 shown, the width and depth of the first region 3a of the plating layer 3 and the width of one side of the second region 3b can be equal to or greater than the thickness of the protective film 8. As Figure 9 shown, let the width of the first region 3a be B1 and the depth be B2. In addition, let the width of one side of the second region 3b be C1, C2, let the width of one side of the second region 3b adjacent to B1 be C1, and let the width of one side of the second region 3b adjacent to B2 be C2. As Figure 9 and Figure 10 shown, when the thickness of the protective film 8 is A, it can be set as A ≤ B1, B2, C1, C2. In addition, as Figure 9 and Figure 10 shown, the width and depth of the first region 3a of the plating layer 3 are preferably wider than the width of one side of the adjacent second region 3b. By adopting a structure in which C1 ≤ B1 and C2 ≤ B2, the size of the first region 3a carrying the solder can be ensured. The thickness of the protective film 8 is, for example, about 10 μm.

[0044] In addition, as Figure 11 described, a gap can also be formed. As Figure 11 shown, the shape of the second region 3b can vary according to the shape of the gap.

[0045] In addition, a gate electrode 6 can also be provided on the upper surface of the semiconductor substrate 1. As Figure 12 shown, it is preferable to provide the gate electrode 6 directly below the first region 3a on the upper surface of the semiconductor substrate 1, and not to provide the gate electrode 6 directly below the second region 3b. By not providing the gate electrode 6 directly below the second region 3b, a main current can flow only directly below the first region 3a where the solder is carried. In addition, Figure 12 shows a trench-structured gate electrode 6, but it can also be a planar-structured gate electrode. In addition, as Figure 12 shown, an interlayer insulating film 7 can be provided on the upper surface of the gate electrode 6.

[0046] Embodiment 2. Use Figure 13 , Figure 14 to describe the semiconductor device 200 in Embodiment 2. Figure 13 is a simplified top view of the semiconductor device 200 according to Embodiment 2. Figure 14 is a simplified cross-sectional view of the semiconductor device 200 according to Embodiment 2. Figure 14 Represents Figure 13 the cross-section along the single-dot chain line X-X shown in Figure 13 is a diagram showing, for the sake of easy explanation, a solder blocking portion 5 added in a horizontal cross-sectional view taken along the single-dot chain line Y-Y shown in Figure 14 , and is a diagram showing the solder layer 4 omitted.

[0047] In the semiconductor device 200 of Embodiment 2, the solder blocking portion 5 is an oxide film. As Figure 13 , Figure 14 shown, the oxide film is formed on the second region 3b of the plating layer 3. Setting the solder blocking portion 5 as an oxide film and the position where the solder blocking portion 5 is provided on the second region 3b is different from Embodiment 1. In Embodiment 2, as Figure 13 , Figure 14 shown, the oxide film is provided over the entire second region 3b, but it can also be provided only in the region of the second region 3b close to the first region 3a. For example, the oxide film can be provided only in the region of the second region 3b close to the first region 3a so as to surround the first region 3a.

[0048] As Figure 13 shown, it is preferable to form the oxide film such that the center of the first region 3a coincides with the center of the entire plating layer 3. InFigure 13 In this case, the oxide film is provided symmetrically with respect to the center of the entire plating layer 3, but it is not necessarily provided symmetrically. As long as the oxide film is formed on the second region 3b, the formation position and shape of the oxide film are arbitrary. In addition, the width of the oxide film can be changed on each side.

[0049] As described above, the semiconductor device 200 according to the second embodiment is configured. By providing a structure for the gap of the solder blocking portion 5 on the plating layer 3, it is possible to suppress the generation of a triple point of the three layers of the plating layer 3, the resin layer, and the solder layer 4 on the electrode layer 2, and it is possible to prevent the electrode layer 2 from cracking. The reason therefor will be described below.

[0050] By providing the oxide film, it is possible to block the solder supplied to the first region 3a so that it does not flow from the first region 3a to the second region 3b. Since the solder does not wet the oxide film, the solder does not flow onto the second region 3b and stays on the first region 3a. As a result, it does not flow on the electrode layer 2. Therefore, even in a state where the semiconductor device 200 is sealed with a sealing resin, it is possible to suppress the generation of a triple point of the three layers of the plating layer 3, the resin layer formed of the sealing resin, and the solder layer 4 on the electrode layer 2. Thereby, it is possible to prevent the electrode layer 2 from cracking.

[0051] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. The method for manufacturing the semiconductor device 200 according to the second embodiment is different from that of the first embodiment in the solder blocking portion forming step. Hereinafter, the solder blocking portion forming step will be described, and the other steps are the same as those of the first embodiment.

[0052] In the second embodiment, an example of a method for forming the solder blocking portion 5 as an oxide film on the second region 3b of the plating layer 3 has been described.

[0053] An example of a method for forming the oxide film will be described. First, a metal having a higher ionization tendency than the metal constituting the plating layer 3 is coated on the second region 3b. Here, the metal constituting the plating layer 3 is defined as the first metal, and the metal having a higher ionization tendency than the metal constituting the plating layer 3 is defined as the second metal. When the first metal is gold (Au), it is preferable to use lithium (Li), copper (Cu), etc. that are oxidized in air as the second metal. For example, the second metal is made of aluminum (Al).

[0054] Next, the second metal is oxidized to form an oxide film. For example, the second metal can also be oxidized by bringing the second metal into contact with air.

[0055] In addition, when the second metal is coated on the second region 3b, it is preferable that the second metal does not flow on the electrode layer 2 but stays on the second region 3b. When the second metal flows onto the electrode layer 2, a triple point is generated on the electrode layer 2 by the three layers of the oxide film formed by oxidizing the second metal, the plating layer 3, and the sealing resin. By coating the second metal on the second region 3b so that it does not flow on the electrode layer 2, it is possible to prevent the generation of a triple point composed of the three layers of the oxide film, the plating layer 3, and the sealing resin on the electrode layer 2.

[0056] Through the above process, the semiconductor device 200 is manufactured. As described above, the manufacturing method of the semiconductor device 200 according to the second embodiment includes a solder blocking portion forming process, and the solder blocking portion 5 is an oxide film. By forming an oxide film on the plating layer 3, in the solder layer forming process, similarly to the first embodiment, it is possible to block the solder supplied to the first region 3a so that it does not flow from the first region 3a to the second region 3b. Since the solder does not wet on the oxide film, the solder does not flow onto the second region 3b and stays on the first region 3a. As a result, it does not flow on the electrode layer 2. Therefore, even in a state where the semiconductor device 200 is sealed with a sealing resin, it is possible to suppress the generation of a triple point composed of the three layers of the plating layer 3, the resin layer composed of the sealing resin, and the solder layer 4 on the electrode layer 2. Thereby, it is possible to prevent the electrode layer 2 from cracking.

[0057] In addition, when the solder blocking portion 5 is an oxide film, compared with the first embodiment in which the solder blocking portion 5 is a gap, the solder blocking portion 5 can be formed more easily.

[0058] Next, use Figures 15 to 19 to describe a modification of the second embodiment. First, use Figure 15 , Figure 16 to describe Modification 1. Figure 15 is a schematic top view of the semiconductor device according to Modification 1. Figure 16 is a schematic cross-sectional view of the semiconductor device according to Modification 1. Figure 16 is Figure 15 the X-X cross-sectional view shown by the dash-dot line in Figure 15 , 18 , 19 is the same as Figure 13 in the horizontal cross-sectional view taken along the dash-dot line Y-Y in the cross-sectional view corresponding to each top view, and is a view showing the addition of the solder blocking portion 5.

[0059] As Figure 15 , Figure 16 shown, a protective film 8 surrounding the outer periphery of the plating layer 3 can be further formed on the upper surface side of the electrode layer 2. In addition, as Figure 15As shown, the protective film 8 can be formed so as to surround the outer periphery of the second region 3b of the plating layer 3.

[0060] Next, use Figure 17 to describe Modification 2. Figure 17 is a schematic cross-sectional view of the semiconductor device according to Modification 2. In Modification 2, it is assumed that the semiconductor device is sealed with a sealing resin. Similar to Modification 2 of Embodiment 1, as Figure 17 shown, the semiconductor device can also be sealed with a sealing resin 9.

[0061] Next, use Figure 18 , Figure 19 to describe Modification 3. Figure 18 , Figure 19 is a schematic top view of the semiconductor device according to Modification 3. Figure 18 The cross-sectional view along the single-dot chain line X-X shown is the same as the Figure 14 shown cross-sectional view. Figure 19 The cross-sectional view along the single-dot chain line X-X shown is the same as the Figure 16 shown cross-sectional view. As Figure 18 shown, when the semiconductor chip 10 is rectangular in top view, an oxide film can be formed only in the region of the plating layer 3 on the short side of the semiconductor chip 10. It is known that when the semiconductor chip 10 is rectangular, compared with the long side of the semiconductor chip 10, when solder flows on the short side of the semiconductor chip 10, cracks are more likely to occur on the electrode layer 2. Therefore, by adopting a structure in which an oxide film is formed only in the region of the plating layer 3 on the short side of the semiconductor chip 10, the generation of triple points on the electrode layer 2 can be suppressed on the short side of the semiconductor chip 10 where cracks are likely to occur, and the electrode layer 2 can be prevented from cracking. In addition, according to the structure of Modification 3, compared with the structure of Embodiment 2, the area of the first region 3a becomes larger. Therefore, the area carrying the solder can be expanded, and the bonding strength can be improved.

[0062] In addition, as Figure 19 shown, in addition to the structure of Modification 3, the protective film 8 can be formed in the same manner as in Modification 1. In addition, as Figure 19 shown, the protective film 8 can also be formed so as to surround the entire outer periphery of the plating layer 3 including the oxide film.

[0063] In addition, in addition to the structure of Modification 3, the sealing resin 9 can be formed in the same manner as in Modification 2.

[0064] In addition, similar to the fourth modification of Embodiment 1, the width and depth of the first region 3a of the plating layer 3 and the width of one side of the second region 3b may be equal to or greater than the thickness of the protective film 8. In addition, the width and depth of the first region 3a of the plating layer 3 are preferably wider than the width of one side of the adjacent second region 3b. Thereby, the size of the first region 3a carrying the solder can be ensured.

[0065] The structures shown in the above embodiments are examples of the content of the present disclosure and may be combined with other known techniques. In addition, the embodiments and the modifications may be combined with each other. In addition, within the scope not departing from the gist of the present disclosure, a part of the structure may be omitted or changed. Reference Signs Explanation

[0066] 1 Semiconductor substrate, 2 Electrode layer, 3 Plating layer, 4 Solder layer, 5 Solder blocking portion, 6 Gate electrode, 8 Protective film, 9 Sealing resin, 10 Semiconductor chip, 100, 200 Semiconductor device.

Claims

1. A semiconductor device sealed with a sealing resin, wherein the semiconductor device has: A semiconductor substrate; An electrode layer provided on the upper surface side of the semiconductor substrate; A plating layer provided on the upper surface of the electrode layer, having a first region and a second region outside the first region in a plan view; A solder layer provided on the first region of the plating layer; And A solder blocking portion formed in the plating layer for blocking the solder so that it does not flow from the first region onto the second region.

2. The semiconductor device according to claim 1, wherein The solder blocking portion is a gap between the first region and the second region.

3. The semiconductor device according to claim 1, wherein The solder blocking portion is an oxide film formed on the second region of the plating layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, In a plan view, the semiconductor chip is rectangular, The solder blocking portion is formed only in the region of the plating layer on the short side of the semiconductor chip.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, On the upper surface side of the electrode layer, a protective film surrounding the outer periphery of the plating layer is further formed.

6. The semiconductor device according to claim 5, wherein In a plan view, the width and depth of the first region of the plating layer and the width of one side of the second region are greater than or equal to the thickness of the protective film.

7. The semiconductor device according to claim 2, wherein The gap is a crack that divides the first region and the second region.

8. The semiconductor device according to claim 2 or 7, wherein Among the side surfaces of the first region and the second region where the gap is formed, the side surface of the first region is perpendicular to the upper surface of the electrode layer.

9. The semiconductor device according to claim 2 or 7, wherein The sealing resin is not filled in the gap.

10. The semiconductor device according to any one of claims 1 to 3, wherein A gate electrode is provided directly below the first region on the upper surface of the semiconductor substrate, and the gate electrode is not provided directly below the second region.

11. The semiconductor device according to any one of claims 1 to 3, characterized in that, The electrode layer is formed of aluminum alloy.

12. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor substrate is made of SiC.

13. A method for manufacturing a semiconductor device sealed with a sealing resin, wherein the method for manufacturing the semiconductor device includes: An electrode layer forming step of forming an electrode layer on the upper surface side of a semiconductor substrate; A plating layer forming step of forming a plating layer having a first region and a second region outside the first region in a plan view on the upper surface of the electrode layer; A solder blocking portion forming step of forming a solder blocking portion on the plating layer for blocking the solder so that it does not flow from the first region onto the second region; And A solder layer forming step of providing solder on the first region to form a solder layer.

14. The manufacturing method of the semiconductor device according to claim 13, characterized in that, The solder blocking portion is a gap, The solder blocking portion forming step forms the gap between the first region and the second region.

15. The method for manufacturing a semiconductor device according to claim 14, wherein The solder blocking part forming process forms the gap by dividing the plating layer into the first region and the second region.

16. The method for manufacturing a semiconductor device according to claim 13, wherein, The solder blocking part is an oxide film. The solder blocking part forming process forms the oxide film on the second region.

17. The method of manufacturing a semiconductor device according to claim 16, wherein in the solder blocking part forming process, a metal having a higher ionization tendency than the metal constituting the plating layer is coated on the second region, and the metal having the higher ionization tendency is oxidized to form the oxide film.

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