A bidirectional isolated SRC-LLC topology overcurrent protection circuit

Abstract

The application discloses a kind of overcurrent protection circuits of bidirectional isolation SRC-LLC topology, it is related to power electronic converter protection technical field, including: DSP control chip, first or gate, second or gate, third or gate, fourth or gate, latching module and overcurrent signal detection circuit;Latch module includes logic gate circuit, its first input end connects the output end of overcurrent signal detection circuit, second input end connects the reset signal output end of DSP control chip;Wherein, DSP control chip is used to detect the zero-crossing point of resonant cavity current, and when detecting zero-crossing point, TZ_PWM1 and TZ_PWM2 signals of each or gate logic output are used to cut off EPWM1A, EPWM1B, EPWM2A and EPWM2B drive signal, to shut off MOS tube at zero-crossing point, avoid current impact caused by non-zero-crossing point shutdown.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronic converter protection, in particular to a kind of overcurrent protection circuit of bidirectional isolation SRC-LLC topology. BACKGROUND

[0002] At present, in bidirectional isolation SRC-LLC topology circuit, the traditional overcurrent protection scheme usually directly monitors current, immediately forces to cut off driving signal once overcurrent is detected.However, this direct shutdown scheme has obvious disadvantages, since the current of MOS tube in SRC-LLC topology is sinusoidal variation by inductance capacitor resonance, if directly cutting off driving signal at non-zero point, it will make the voltage and current phase of MOS tube mismatch, lead to great current pulse, this excessive current pulse can possibly exceed the current limit specified by MOS tube, cause overcurrent damage, even lead to tube explosion, seriously affect the reliability and stability of circuit. SUMMARY

[0003] The purpose of the present application is to provide a kind of overcurrent protection circuit of bidirectional isolation SRC-LLC topology, with the advantages of shutting down MOS tube at resonance cavity current zero point, effectively avoid the current impact caused by non-zero point shutdown, protect the safety of power device.

[0004] The present application provides an overcurrent protection circuit of bidirectional isolation SRC-LLC topology, comprising: DSP control chip, first or gate, second or gate, third or gate, fourth or gate, latch module and overcurrent signal detection circuit;Latch module includes logic gate circuit, its first input end is connected with the output end of overcurrent signal detection circuit, second input end is connected with the reset signal output end of DSP control chip;The signal output end of EPWM1A and EPWM1B of DSP control chip is connected with the two input ends of first or gate respectively, and the signal output end of EPWM2A and EPWM2B is connected with the two input ends of second or gate respectively;The output end of first or gate is connected with the output end of latch module and is commonly connected to the two input ends of third or gate, and the output end of second or gate is connected with the output end of latch module and is commonly connected to the two input ends of fourth or gate;The output end of third or gate is connected with the TZ_PWM1 drive protection port of DSP control chip, and the output end of fourth or gate is connected with the TZ_PWM2 drive protection port of DSP control chip;Wherein, DSP control chip is used to detect the zero point of resonance cavity current, and when detecting zero point, EPWM1A, EPWM1B, EPWM2A and EPWM2B driving signal are cut off by TZ_PWM1 and TZ_PWM2 signal, to shut down MOS tube at zero point, avoid the current impact caused by non-zero point shutdown.

[0005] In some embodiments, EPWM1A and EPWM1B are a set of complementary symmetrical pulse width modulation signals, and EPWM2A and EPWM2B are another set of complementary symmetrical pulse width modulation signals, and the phase difference between the two sets of signals is 180°, used to drive the alternating conduction of MOS transistors in the bidirectional isolation SRC-LLC topology.

[0006] In some embodiments, the DSP control chip has a built-in zero-crossing detection module, which detects the instantaneous amplitude and phase angle of the resonant cavity current waveform in real time, and determines that a zero-crossing point is reached when the following conditions are met: the instantaneous current amplitude is less than 5% of the rated current; the phase angle change rate exceeds 50° / μs.

[0007] In some embodiments, the latch module includes a combination of AND gate and OR gate logic circuits, which outputs a low-level latch control signal when the overcurrent signal is high and the reset signal is low, triggering the third OR gate and the fourth OR gate to output low-level TZ_PWM1 and TZ_PWM2 signals.

[0008] In some embodiments, the overcurrent signal detection circuit includes a Hall current sensor and a voltage comparator, which compares the collected current signal with the threshold value of 420A and outputs a high-level overcurrent trigger signal to the latch module.

[0009] In some embodiments, the current sampling frequency of the zero-crossing detection module is not less than 200kHz to ensure real-time performance.

[0010] In some embodiments, the latch module further includes an inverter for converting the high level of the reset signal to a low level to match the input requirements of the AND gate logic.

[0011] In some embodiments, TZ_PWM1 and TZ_PWM2 signals are low-level active signals, and when the latch module outputs a low level, the drive protection port of the DSP control chip immediately disables the output of EPWM1A, EPWM1B, EPWM2A, and EPWM2B signals.

[0012] In some embodiments, an RC delay circuit is further included to delay for 10ms to 100ms after the overcurrent signal is triggered to confirm the persistence of the overcurrent state before performing the shutdown operation.

[0013] In some embodiments, the circuit is suitable for a bidirectional isolation power supply system with a working current range of 300A to 600A and a resonant frequency of 100kHz.

[0014] From the above, the over-current protection circuit of the bidirectional isolation SRC-LLC topology provided by the application accurately detects the zero-crossing point of the resonant cavity current and triggers a protection signal through a DSP control chip, and the latch module and the logic gate circuit are combined to realize the rapid and reliable cutting-off of the driving signal, so that the MOS tube is turned off at the zero-crossing point of the resonant cavity current, and the current impact caused by the non-zero-crossing point turn-off is effectively avoided, and the safety of the power device is protected. BRIEF DESCRIPTION OF DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification, and are used to explain the technical solutions of the present application together with the embodiments of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0016] The present application will be further described below in combination with the accompanying drawings and embodiments.

[0017] Figure 1 A schematic diagram of the over-current protection circuit of the bidirectional isolation SRC-LLC topology provided by the embodiment of the present application is shown in the figure.

[0018] Figure 2 In the over-current protection circuit of the bidirectional isolation SRC-LLC topology provided by the embodiment of the present application, the timing diagram of each signal is shown in the figure. DETAILED DESCRIPTION

[0019] The technical solutions in the present application will be described clearly and completely below in combination with the accompanying drawings in the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. The components of the present application described and shown in the accompanying drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. It should be noted that: similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0020] In the prior art, in a bidirectional isolated SRC-LLC topology circuit, a traditional overcurrent protection scheme directly monitors the current and forcibly cuts off the driving signal when overcurrent is detected. Since the resonant cavity current presents a sine wave characteristic, non-zero-crossing-off can cause the voltage across the MOS tube to be out of phase with the current, resulting in a transient large current pulse that may exceed the device tolerance limit and cause device damage. Such problems are particularly prominent in application scenarios that require fast response and frequent current fluctuations, such as when a high-power-density power supply system is running, sudden load changes can easily trigger false shutdown or non-ideal shutdown actions.

[0021] Therefore, the present application proposes an overcurrent protection scheme comprising a DSP control chip, four OR gates, a latch module and an overcurrent signal detection circuit. The EPWM1A and EPWM1B signals of the DSP control chip are connected to the input terminals of the first OR gate, and the EPWM2A and EPWM2B signals are connected to the input terminals of the second OR gate. The output terminal of the first OR gate is connected to the output terminal of the latch module, and the output terminal of the second OR gate is connected to the output terminal of the latch module. The output of the third OR gate is connected to the TZ_PWM1 drive protection port, and the output of the fourth OR gate is connected to the TZ_PWM2 drive protection port. The latch module receives the overcurrent signal and the reset signal and controls the output of the protection signal through logic combination.

[0022] The scheme of the present application will be described below with reference to the accompanying drawings.

[0023] Reference Figure 1 , Figure 1 The schematic diagram of the overcurrent protection circuit of the bidirectional isolated SRC-LLC topology provided by the embodiment of the present application; wherein the DSP control chip is located on the left side of the figure, marked as "DSP", used to generate pulse width modulation (PWM) signals (EPWM1A, EPWM1B, EPWM2A, EPWM2B) and reset signals (RESET), also used to detect the zero-crossing point of the resonant cavity current, and when the zero-crossing point is detected, the driving signal is cut off through the TZ_PWM1 and TZ_PWM2 signals.

[0024] First OR gate (OR1): receives EPWM1A and EPWM1B signals from the DSP, and outputs to the third OR gate (OR3).

[0025] Second OR gate (OR2): receives EPWM2A and EPWM2B signals from the DSP, and outputs to the fourth OR gate (OR4).

[0026] Third OR gate (OR3): receives signals from the first OR gate (OR1) and the latch module (LOCK), and outputs the TZ_PWM1 signal to the drive protection port of the DSP.

[0027] Fourth OR gate (OR4): receives signals from the second OR gate (OR2) and the latch module (LOCK), and outputs the TZ_PWM2 signal to the drive protection port of the DSP.

[0028] Latch module (LOCK): includes a logic gate circuit for processing the overcurrent signal and the reset signal.

[0029] The first input end is connected to the overcurrent signal detection circuit (LLC_OCP), the second input end is connected to the RESET signal of the DSP, and the output signal LOCK_OCP is connected to the third OR gate (OR3) and the fourth OR gate (OR4).

[0030] Overcurrent signal detection circuit: used for detecting overcurrent in the SRC-LLC topology, and outputting an overcurrent signal (LLC_OCP) to the latch module (LOCK) when the current exceeds a set threshold.

[0031] It can be understood that, in normal operation, the EPWM signal output by the DSP is transmitted through the OR gates (OR1 and OR2) to the third OR gate (OR3) and the fourth OR gate (OR4), and then output to the drive protection port (TZ_PWM1 and TZ_PWM2) of the DSP to control the normal switching action of the MOS tube; when the overcurrent signal detection circuit detects overcurrent, the LLC_OCP signal is output to the latch module (LOCK), and the latch module (LOCK) performs logic processing according to the LLC_OCP signal and the RESET signal, and outputs the signal to the third OR gate (OR3) and the fourth OR gate (OR4). According to the received signals, the third OR gate (OR3) and the fourth OR gate (OR4) forcibly turn off the TZ_PWM1 and TZ_PWM2 signals to cut off the drive signal and protect the MOS tube. When the DSP control chip detects the zero-crossing point, the EPWM signal is cut off through the TZ_PWM1 and TZ_PWM2 signals to ensure that the MOS tube is turned off at the zero-crossing point, avoiding current impact caused by non-zero-crossing point turn-off.

[0032] In some embodiments, the DSP control chip refers to a microcontroller with digital signal processing capability, which acquires current signals in real time and calculates phase information through the built-in ADC module. The first OR gate and the second OR gate constitute a drive signal preprocessing unit, which can be implemented by an integrated circuit, for merging complementary PWM signals into a single control signal. The latch module is composed of AND gates and OR gates, for example, realized by combining SN74HC08 and SN74HC32, for maintaining the protection state during the overcurrent signal is valid until the reset signal triggers. The overcurrent signal detection circuit includes a current sensing element and a comparison circuit, which can be implemented by combining a Hall sensor and an LM393 voltage comparator, for converting an analog current signal into a digital trigger signal.

[0033] Specifically, the DSP control chip continuously monitors the phase change of the resonant cavity current, and sends a turn-off instruction to the TZ_PWM1 and TZ_PWM2 ports when the current zero-crossing point is detected. At this time, the high-level signal output by the overcurrent signal detection circuit and the reset signal state of the latch module jointly determine the output of the or gate. When an overcurrent event occurs, the latch module will maintain a low-level output state, forcing the third and fourth or gates to output low levels, thereby triggering the drive protection port to close the EPWM signal output. This logic design ensures that the MOS tube turn-off operation will only be performed under the double conditions of valid overcurrent signal and DSP detection of zero-crossing point, thereby avoiding the current impact caused by non-zero-crossing turn-off.

[0034] It can be understood that the traditional scheme only relies on current amplitude comparison to trigger turn-off, and cannot consider the phase characteristics of resonant current. The present scheme introduces a zero-crossing detection mechanism to synchronize the turn-off action with the natural zero-crossing time of the current, eliminating the problem of voltage and current phase mismatch. At the same time, the logic gate combination is used to realize signal latching and conditional triggering, which not only ensures the real-time performance of overcurrent protection, but also avoids the risk of misoperation. Compared with the extensive protection of directly cutting off the drive, the present scheme realizes precise matching of protection action and circuit dynamic characteristics.

[0035] In some embodiments, in the overcurrent protection circuit of the bidirectional isolation SRC-LLC topology, EPWM1A and EPWM1B are a set of complementary and symmetric pulse width modulation signals, EPWM2A and EPWM2B are another set of complementary and symmetric pulse width modulation signals, and the phase difference between the two sets of signals is 180°, used to drive the alternating conduction of MOS tubes in the bidirectional isolation SRC-LLC topology.

[0036] Among them, the complementary and symmetric pulse width modulation signals refer to two sets of driving signals whose waveforms do not overlap in time axis and have opposite polarities, which can be realized by using the built-in PWM generation module of the DSP control chip, and the conduction and turn-off states of the upper and lower MOS tubes on the same bridge arm are controlled through a logic circuit. The phase difference of 180° means that the rising edge and the falling edge of the two sets of driving signals are separated by half a period in time axis, which can be realized by adjusting the PWM phase register parameters of the DSP control chip, so that the two sets of MOS tubes are alternately conducted in different periods.

[0037] Specifically, the complementary and symmetric pulse width modulation signals are configured to allow only one MOS tube in the same bridge arm to be conducted at the same time, avoiding the risk of short circuit caused by overlapping driving signals. The setting of the phase difference of 180° makes the conduction time of the two sets of bridge arms staggered with each other, for example, when the first set of signals drives the primary side bridge arm to conduct, the second set of signals remains in the off state, and only after the primary side is turned off, the secondary side bridge arm is driven to conduct. This alternating driving mechanism makes the resonant cavity current provided by different bridge arms in the positive and negative half cycles, respectively, thereby maintaining the continuity of the current waveform.

[0038] It can be understood that the single PWM signal or phase-synchronous driving mode in the traditional scheme can cause the simultaneous conduction of the upper and lower tubes on the same bridge arm, resulting in a through current. The combination of the complementary symmetrical signal and the phase difference design eliminates the risk of bridge arm through, and maintains the resonant characteristics of the current through alternating conduction, ensuring that the voltage stress borne by the MOS tube when switching at zero crossing point is minimized.

[0039] In some embodiments, the DSP control chip has a zero-crossing detection module built-in. The zero-crossing detection module acquires the instantaneous amplitude and phase angle of the resonant cavity current waveform in real time, and determines that the current is at zero crossing when the following conditions are met: the instantaneous current amplitude is less than 5% of the rated current; the phase angle change rate exceeds 50° / μs.

[0040] The zero-crossing detection module refers to a circuit unit integrated in the DSP chip for identifying the zero-crossing state of the resonant current. It can be implemented using high-speed ADC sampling and digital filtering algorithms to track the current waveform changes in real time. The instantaneous current amplitude less than 5% of the rated current means comparing the current value at the current sampling point with the system nominal current value, which can be realized by a proportional coefficient calculation to determine whether the current is in the low-amplitude range close to zero. The phase angle change rate exceeding 50° / μs means calculating the phase angle difference between adjacent sampling points and converting it into a time change rate, which can be realized by differential operation or difference algorithm to capture the rapid phase flip feature at the moment of current direction switching.

[0041] Specifically, the zero-crossing detection module acquires the resonant cavity current signal through the current sensor, converts it to digital quantity through ADC, and then calculates the instantaneous current amplitude and phase angle synchronously by the DSP internal algorithm. When the current amplitude is detected to be below 5% of the rated value and the phase angle change rate exceeds 50° / μs, it is determined that the current is at zero crossing. At this time, the DSP immediately triggers a protection signal to turn off the MOS tube drive signal at zero crossing, avoiding the impact caused by sudden current change.

[0042] It can be understood that the traditional scheme only relies on a single condition of current amplitude to determine zero crossing, which is prone to false positives due to noise interference or transient fluctuations. This scheme uses the unique amplitude minimum value and rapid phase flip characteristics of current zero crossing to significantly improve the accuracy of determination by superimposing amplitude and phase change rate double condition detection.

[0043] Through the above technical solutions, the problem of current impact caused by non-zero-crossing turn-off is effectively solved. By accurately identifying the current zero-crossing moment and implementing protection actions, the MOS tube is turned off when the current is close to zero, avoiding voltage spikes caused by sudden current changes, thereby improving system reliability and reducing the risk of device damage.

[0044] In some embodiments, the latch module includes a combination logic circuit of an AND gate and an OR gate, and outputs a low-level latch control signal when the overcurrent signal is high and the reset signal is low, triggering the third and fourth OR gates to output low-level TZ_PWM1 and TZ_PWM2 signals.

[0045] The combination logic circuit of the AND gate and the OR gate refers to a signal processing unit composed of standard logic gates, which can be implemented by combining AND gates and OR gates in the 74 series integrated circuit, and is used to generate a latch control signal according to the input signal state. The high-level overcurrent signal refers to the overcurrent trigger state signal output by the voltage comparator, which can be realized by comparing the current signal collected by the Hall sensor with the set threshold, and is used to indicate that the system is in an overload working condition. The low-level reset signal refers to the reset control signal output by the control chip, which can be realized by outputting a low-level pulse through the GPIO port, and is used to release the latch state. The low-level latch control signal refers to the trigger signal for driving the protection port, which can be realized by outputting a low-level logic value through the logic gate circuit, and is used to immediately disable the output of the pulse width modulation signal.

[0046] Specifically, when the overcurrent detection circuit detects an overcurrent state, the voltage comparator outputs a high-level signal to the first input end of the AND gate. At this time, if the reset signal remains at a low level, the AND gate outputs a low-level trigger to the OR gate combination circuit, so that the third and fourth OR gates output low-level signals to the driving protection port. This logic control method can ensure that the driving signal cutoff function is triggered only when the overcurrent state is continuous and the reset operation is not performed.

[0047] It can be understood that the conventional scheme usually uses a simple latch to realize signal retention, which has the problems of reset response lag and false triggering risk. The present scheme builds a dynamic latch mechanism by combining logic gate circuits, so that the overcurrent trigger signal and the reset signal form a mutual locking relationship, effectively avoiding the false action problem caused by the delay of the reset signal.

[0048] In some embodiments, the overcurrent signal detection circuit includes a Hall current sensor and a voltage comparator, and the voltage comparator compares the collected current signal with the threshold of 420A and outputs a high-level overcurrent trigger signal to the latch module.

[0049] The Hall current sensor refers to a non-contact sensor that realizes current measurement through the magnetoelectric effect, which can be realized by using a closed-loop Hall element. It generates a proportional voltage signal by sensing the magnetic field strength generated by the measured current. The voltage comparator refers to a circuit module for judging whether the input voltage exceeds the preset threshold, which can be realized by combining a high-speed differential amplifier with a reference voltage source. It compares the voltage signal output by the Hall sensor with the reference voltage corresponding to the 420A current in real time.

[0050] Specifically, the Hall current sensor is configured in the power loop to collect the resonant cavity current flowing through the MOS tube in real time and convert it into a voltage signal. The voltage signal is input to the non-inverting terminal of the voltage comparator, and the inverting terminal is connected to a reference level set to 420A corresponding voltage value. When the current exceeds the threshold value, the voltage comparator outputs a logic high level to trigger the latch module, and the use of a hysteresis comparator can prevent false triggering caused by noise. The comparison process of the current detection signal and the reference threshold value is completed within microseconds, ensuring that the overcurrent state is captured in time.

[0051] It can be understood that the traditional scheme uses resistance sampling combined with a fixed threshold comparator, which is susceptible to temperature drift and has limited response speed. The Hall current sensor does not require a series sampling resistor, which can avoid power loss and improve detection accuracy, and its wideband characteristics can accurately track high-frequency resonant current waveforms. The voltage comparator uses a preset threshold value rather than a dynamic adjustment mode, which simplifies the circuit structure and enhances the anti-interference ability.

[0052] In some embodiments, the current sampling frequency of the zero-crossing detection module is not less than 200 kHz to ensure real-time performance.

[0053] Among them, the current sampling frequency refers to the number of current signal acquisitions per unit time, which can be realized by using a high-speed ADC module, such as a 12-bit analog-to-digital conversion unit integrated in a DSP chip, which controls the data capture rate by setting its sampling period register value. Real-time performance refers to the degree of synchronization between system response speed and physical process changes, which is achieved by shortening the sampling interval to less than 5 microseconds, so that the detection lag time of current waveform changes is compressed within the allowable range of the resonant period.

[0054] Specifically, the zero-crossing detection module digitally samples the resonant cavity current at fixed time intervals, and when the sampling frequency reaches 200 kHz, more than 400 data points can be obtained within each power frequency period. This high-density sampling allows the zero-crossing mutation of the current waveform to be quickly captured, and the system can complete the judgment logic operation within three sampling periods before the current amplitude drops below the threshold value, ensuring that the deviation between the current zero-crossing point and the generation time of the off command does not exceed 1.5 degrees of phase angle.

[0055] It can be understood that the traditional overcurrent protection scheme usually uses a sampling frequency below 100 kHz, resulting in a delay of more than 10 microseconds in detecting the current zero-crossing point. This scheme improves the sampling rate, doubling the speed of acquiring phase information of current changes, effectively eliminating the problem of over-zero point misjudgment or omission caused by too long sampling interval, and avoiding the forced shutdown of the MOS tube in a non-zero-current state.

[0056] In some embodiments, the latch module includes an inverter for converting the high level of the reset signal to a low level to match the input requirements of the AND gate logic.

[0057] Wherein, the inverter refers to a circuit unit that logically negates the input signal, which can be implemented by a transistor-built NOT gate circuit or an integrated logic chip. Its function is to convert a high-level signal into a low-level signal to ensure that the logic gate input level matches. The input requirements of the AND gate logic refer to the voltage threshold conditions that the logic gate needs to meet when receiving different level signals, which can be implemented by standard TTL or CMOS level specifications. Its function is to avoid logic misjudgment through level matching.

[0058] Specifically, when the reset signal is high, the inverter converts it to a low-level signal input to the AND gate. At this time, if the overcurrent signal is also high, the AND gate will output a low-level latch control signal, which will trigger the drive protection port to cut off the pulse width modulation signal output. When the reset signal is low, the inverter outputs a high level, so that the AND gate logic judges according to the overcurrent signal state, thereby realizing the logical synchronization processing of the reset signal and the overcurrent signal.

[0059] It can be understood that the traditional overcurrent protection circuit does not consider the compatibility problem of the reset signal of the control chip and the level specification of the logic gate. When the reset signal level does not match the input requirements of the logic gate, the latch module may not respond correctly. By adding an inverter, the contradiction between the high level of the reset signal and the low level trigger condition of the logic gate can be eliminated, ensuring the effectiveness of the overcurrent protection mechanism.

[0060] In some embodiments, an RC delay circuit is also included for delaying 10ms to 100ms after the overcurrent signal is triggered to confirm the persistence of the overcurrent state before performing the shutdown operation.

[0061] Wherein, the RC delay circuit refers to a delay circuit composed of a resistor and a capacitor, which can be implemented by connecting a fixed resistor and a variable capacitor in parallel, and the delay time can be changed by adjusting the capacitance or resistance value. This circuit forms a time window in the overcurrent signal transmission path to filter transient interference signals. Wherein, the delay after the overcurrent signal is triggered refers to the waiting time between detecting the overcurrent signal and performing the shutdown operation, which can be implemented by setting the RC time constant, for example, setting the resistance to 10kΩ and the capacitance to 1μF to form a delay of about 10ms. This delay is used to distinguish between transient overcurrent and persistent overcurrent to avoid false triggering of the protection action.

[0062] Specifically, when the overcurrent signal detection circuit outputs a high level trigger signal, the RC delay circuit starts to work. The state of the overcurrent signal is continuously monitored within a preset delay time, for example, in the range of 10 ms to 100 ms. If the overcurrent signal disappears during this period, it is determined to be a transient disturbance, and the shutdown operation is not triggered. If the overcurrent signal persists, it is confirmed that the overcurrent state is valid, and then a low level signal is output through the latch module to trigger the drive protection port to cut off the MOS tube drive signal.

[0063] It can be understood that the traditional scheme immediately cuts off the drive signal after detecting overcurrent, and cannot distinguish between transient disturbance and real failure, which is prone to frequent shutdown due to misjudgment. However, the present scheme introduces a delay confirmation mechanism, which effectively avoids the misoperation caused by transient disturbance while maintaining real-time protection capability, and avoids the risk of protection failure due to excessive delay.

[0064] In some embodiments, an RC delay circuit is further included for delaying 10 ms to 100 ms after the overcurrent signal is triggered to confirm the persistence of the overcurrent state before performing the shutdown operation.

[0065] The RC delay circuit refers to a delay trigger circuit composed of a resistor and a capacitor, which can be implemented by a series-connected metal film resistor and electrolytic capacitor. Different delay times can be set by adjusting the resistance value and capacitance value. The persistence of the overcurrent state refers to determining whether the current continuously exceeds the threshold value within a preset time window, which can be implemented by a timer module and a comparator to distinguish between transient disturbance and real failure.

[0066] Specifically, when the Hall current sensor detects that the current exceeds 420 A, the overcurrent signal detection circuit outputs a high level trigger signal to the RC delay circuit. At this time, the RC circuit starts to charge and start the delay, for example, the resistance can be selected from 1 kΩ to 10 kΩ, and the capacitance can be selected from 10 μF to 100 μF, so that the delay time reaches the range of 10 ms to 100 ms. If the overcurrent signal persists during the delay period, it is determined to be a real overcurrent failure, and the latch module outputs a low level to trigger the drive protection port to cut off the MOS tube drive signal. If the overcurrent signal disappears during the delay period, it is determined to be a transient disturbance, and the RC circuit is automatically reset.

[0067] In some specific embodiments, the resistor and the capacitor are connected in parallel at the input end of the latch module, and the delay parameters can be fine-tuned by changing the wire length of the RC elements in the PCB layout.

[0068] It can be understood that the traditional overcurrent protection scheme immediately cuts off the drive signal after detecting that the current exceeds the threshold, and cannot distinguish between transient current spikes and continuous overload. However, by introducing a delay judgment mechanism, the mistriggering caused by transient fluctuations of resonant current can be effectively avoided, while ensuring accurate protection action when real overcurrent occurs.

[0069] In some embodiments, the circuit is suitable for a bidirectional isolated power supply system with a working current range of 300A to 600A and a resonant frequency of 100 kHz.

[0070] Wherein, the working current range of 300A to 600A refers to the current interval that the circuit can carry in the bidirectional energy transmission scenario, which can be realized by using MOS tubes with current resistance exceeding 600A and low-loss magnetic elements. This parameter range enables the circuit to meet the demand of high-power density power supply system. The resonant frequency of 100 kHz refers to the inherent oscillation frequency formed by the inductance and capacitance in the resonant cavity, which can be realized by adjusting the parameter combination of the resonant elements with inductance of 3μH and capacitance of 0.25μF. This frequency setting is conducive to achieving a balance between the switching loss of silicon-based devices and system efficiency.

[0071] Specifically, when the circuit operates in the current range of 300A to 600A, the Hall sensor in the overcurrent signal detection circuit will collect current signals in real time. For example, the CASR series sensor of LEM Company can meet the linear detection demand of 600A range. When an overcurrent event is detected, the latch module and the DSP control chip work together to ensure that the MOS tube drive signal is cut off at the zero-crossing point of the current sinusoidal wave, combined with the zero-crossing detection mechanism under the resonant frequency of 100 kHz. The resonant period under this frequency is 10μs, which requires the zero-crossing detection module to complete signal sampling, processing and response actions within 5μs. For example, the 16-bit ADC of AD7606 type can realize a sampling rate of 200kSPS, meeting the real-time requirement.

[0072] It can be understood that the traditional overcurrent protection scheme is designed only for low-voltage and small-power scenarios below 200A, and its current detection accuracy and response speed cannot adapt to large-current working conditions above 300A. Moreover, there is a risk of misjudgment of zero-crossing point in the resonant system above 50kHz. This scheme can accurately capture the zero-crossing point of 100kHz high-frequency resonant current by optimizing the bandwidth of the detection circuit and the logic control timing, thereby avoiding voltage spikes caused by large-current shutdown.

[0073] Reference Figure 2 , Figure 2 In the overcurrent protection circuit of the bidirectional isolated SRC-LLC topology provided by the embodiments of the present application, the timing diagram of each signal is shown. Wherein, EPWM1A and EPWM1B are complementary to each other when working normally, one is high and the other is low. For example, at the initial moment, EPWM1A is high and EPWM1B is low. After a period of time, the levels of the two are reversed, EPWM1A becomes low and EPWM1B becomes high, and the change is alternating. When shutting down, when an overcurrent signal appears, both of them may be forced to be low to stop outputting the drive signal.

[0074] EPWM2A and EPWM2B, in normal operation, are also complementary, alternating with each other, cooperating with EPWM1A and EPWM1B to realize the control of the bidirectional isolated SRC-LLC topology; when off, the two can also be forced to be low when the overcurrent signal appears.

[0075] LLC_OCP is normally low, and becomes high and remains when the current exceeds the set threshold, as an overcurrent signal to trigger subsequent protection actions; LOCK_OCP is normally low, and becomes high and remains after a certain delay after LLC_OCP becomes high, realizing the locking of the overcurrent signal, ensuring that the protection mechanism can continue to act, preventing the overcurrent signal from disappearing temporarily and causing the protection to be interrupted.

[0076] TZ_PWM2 and TZ_PWM1, in normal operation, are controlled by EPWM signals and change with the EPWM signals, for example, when EPWM1A and EPWM1B output normal complementary signals, TZ_PWM1 changes accordingly, used to drive MOS tubes and other devices; when overcurrent off, after LOCK_OCP becomes high, TZ_PWM1 and TZ_PWM2 signals are forced to be low, cutting off the driving signal to the MOS tube, realizing the off protection; in addition, after the overcurrent signal is eliminated and certain conditions are met, TZ_PWM1 and TZ_PWM2 can only restore the output of normal signals.

[0077] The above is only an embodiment of the present application and does not limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and variations. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An overcurrent protection circuit with bidirectional isolation SRC-LLC topology, characterized in that, include: The system comprises a DSP control chip, a first OR gate, a second OR gate, a third OR gate, a fourth OR gate, a latch module, and an overcurrent signal detection circuit. The latch module includes logic gate circuits, with its first input connected to the output of the overcurrent signal detection circuit and its second input connected to the reset signal output of the DSP control chip. The EPWM1A and EPWM1B signal outputs of the DSP control chip are respectively connected to the two inputs of the first OR gate, and the EPWM2A and EPWM2B signal outputs are respectively connected to the two inputs of the second OR gate. The outputs of the first OR gate and the latch module are connected together to the two inputs of the third OR gate, and the outputs of the second OR gate and the latch module are connected together to the two inputs of the fourth OR gate. The output of the third OR gate is connected to the TZ_PWM1 drive protection port of the DSP control chip, and the output of the fourth OR gate is connected to the TZ_PWM2 drive protection port of the DSP control chip. The DSP control chip is used to detect the zero-crossing point of the resonant cavity current. When the zero-crossing point is detected, the drive signals of EPWM1A, EPWM1B, EPWM2A and EPWM2B are cut off through the TZ_PWM1 and TZ_PWM2 signals to turn off the MOSFET at the zero-crossing point and avoid current surge caused by non-zero-crossing point turn-off.

2. The overcurrent protection circuit of the bidirectional isolated SRC-LLC topology according to claim 1, characterized in that, EPWM1A and EPWM1B are a set of complementary symmetrical pulse width modulation signals, and EPWM2A and EPWM2B are another set of complementary symmetrical pulse width modulation signals. The two sets of signals have a phase difference of 180° and are used to drive the alternating conduction of MOS transistors in the bidirectional isolated SRC-LLC topology.

3. The overcurrent protection circuit of the bidirectional isolated SRC-LLC topology according to claim 1, characterized in that, The DSP control chip has a built-in zero-crossing detection module. The zero-crossing detection module collects the instantaneous amplitude and phase angle of the resonant cavity current waveform in real time. It determines the zero-crossing point when the following conditions are met: the instantaneous current amplitude is less than 5% of the rated current; and the phase angle change rate exceeds 50° / μs.

4. The overcurrent protection circuit of the bidirectional isolated SRC-LLC topology according to claim 1, characterized in that, The latch module includes AND and OR gate combinational logic circuits. When the overcurrent signal is high and the reset signal is low, it outputs a low-level latch control signal, triggering the third OR gate and the fourth OR gate to output low-level TZ_PWM1 and TZ_PWM2 signals.

5. The overcurrent protection circuit of the bidirectional isolated SRC-LLC topology according to claim 1, characterized in that, The overcurrent signal detection circuit includes a Hall current sensor and a voltage comparator. The voltage comparator compares the acquired current signal with a threshold of 420A and outputs a high-level overcurrent trigger signal to the latch module.

6. The overcurrent protection circuit of the bidirectional isolated SRC-LLC topology according to claim 3, characterized in that, The current sampling frequency of the zero-crossing detection module is not less than 200kHz to ensure real-time performance.

7. The overcurrent protection circuit of the bidirectional isolated SRC-LLC topology according to claim 4, characterized in that, The latch module also includes an inverter for converting the high level of the reset signal to a low level to match the input requirements of the AND gate logic.

8. The overcurrent protection circuit of the bidirectional isolated SRC-LLC topology according to claim 1, characterized in that, The TZ_PWM1 and TZ_PWM2 signals are active low-level signals. When the latch module outputs a low level, the drive protection port of the DSP control chip immediately disables the output of EPWM1A, EPWM1B, EPWM2A and EPWM2B signals.

9. The overcurrent protection circuit of the bidirectional isolated SRC-LLC topology according to claim 1, characterized in that, It also includes an RC delay circuit, which delays the overcurrent signal by 10ms to 100ms after it is triggered, in order to confirm the persistence of the overcurrent state before performing the shutdown operation.

10. The overcurrent protection circuit of the bidirectional isolated SRC-LLC topology according to claim 1, characterized in that, The circuit is suitable for bidirectional isolated power supply systems with an operating current range of 300A to 600A and a resonant frequency of 100kHz.

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