Thermal power generating unit primary frequency modulation control method under deep peak regulation working condition

Abstract

The invention provides a primary frequency modulation control method for a thermal power generating unit under a deep peak regulation working condition, belongs to the technical field of power grid thermal power generating unit frequency modulation, solves the problems that the primary frequency modulation capacity is reduced and the contribution rate is low under the deep peak regulation working condition of the thermal power generating unit, and improves the primary frequency modulation capacity under the deep peak regulation working condition. According to the scheme, the primary frequency modulation control method for the thermal power generating unit under the deep peak regulation working condition, the electronic equipment and the computer readable storage medium are provided, and the method comprises the following steps that S1, DEH side primary frequency modulation quantity generation logic is carried out; s2, performing primary frequency modulation time correction logic; s3, performing primary frequency modulation speed correction logic; and S4, performing primary frequency modulation pressure correction logic. According to the technical scheme, the defects that the thermal power generating unit is poor in DEH valve flow characteristic and low in unit parameter and weak in frequency modulation capacity under the deep peak regulation working condition are overcome, the thermal power generating unit meets the primary frequency modulation requirement of a power grid on the thermal power generating unit under the deep peak regulation working condition, and the safety of the power grid is guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency regulation of thermal power units in power grids, and particularly relates to a primary frequency regulation control method for thermal power units under deep peak shaving conditions. Background Art

[0002] This section aims to provide background or context for the embodiments of the present invention described in the claims. The descriptions herein may include concepts that can be explored, but not necessarily concepts that have been previously thought of or explored. Therefore, unless otherwise indicated herein, the content described in this section is not prior art for the specification and claims of this application, and is not admitted to be prior art merely by virtue of being included in this section.

[0003] With the in-depth promotion of the national strategic goals of "carbon peak and carbon neutrality", the installed capacity of renewable energy power generation has increased rapidly. The large-scale access of renewable energy to the grid has enabled more and more thermal power units to participate in deep peak shaving operation. The operation practice of deep peak shaving thermal power units shows that deep peak shaving leads to a reduction in the primary frequency regulation ability of thermal power units and a low contribution rate, increasing the difficulty of coordinated dispatching of regional power grids and threatening the safe and stable operation of the power grid. Therefore, studying the primary frequency regulation control method for thermal power units under deep peak shaving conditions is of great significance for maintaining the stability of the power system and ensuring the safety of the power grid. Summary of the Invention

[0004] To solve the problems in the prior art that deep peak shaving leads to a reduction in the primary frequency regulation ability of thermal power units and a low contribution rate, the purpose of the present invention is to provide a primary frequency regulation control method, an electronic device, and a computer-readable storage medium for thermal power units under deep peak shaving conditions.

[0005] To solve the above technical problems, in a first aspect, according to some embodiments, the present invention provides a primary frequency regulation control method for thermal power units under deep peak shaving conditions, including the following steps:

[0006] S1: The primary frequency regulation quantity generation logic on the DEH side, specifically including:

[0007] Obtain the actual speed signal 1 and the rated speed signal 2 of the thermal power unit, and generate a slip signal 11 through the subtraction module 3; input the slip signal 11 into the function module 4 to generate an initial primary frequency regulation action quantity signal based on the preset relationship between slip and primary frequency regulation function (Table 1); input the initial primary frequency regulation action quantity signal into the first limiting module 6 for limiting based on the upper and lower limits of primary frequency regulation specified by the national standard to generate a primary frequency regulation action quantity signal 12; the slip signal 11 passes through the absolute value module 5 to generate a slip absolute value signal, and the slip absolute value signal is used by the first high limit module 7 and the first low limit module 8 to respectively determine whether the slip absolute value exceeds the preset action threshold or reset threshold. Input the output signal of the first high limit module 7 into the RS flip-flop module 10, and input the output signal of the low limit module 8 into the RS flip-flop module 10 through the delay module 9 to generate a primary frequency regulation action signal 13;

[0008] S2: Primary frequency regulation time correction logic, specifically including:

[0009] Obtain the slip signal 11 and input it into the second low limit module 14 to generate a slip less than signal. The output signal of the slip less than signal after passing through the first anti-delay module 15 is used as the switching condition of the first switching module (16), specifically including: when the slip is less than 1.8 r / min, output 0.3, otherwise delay for 1 s and output -0.3; use the output signal of the primary frequency regulation action signal 13 after passing through the pulse module 17 as the switching condition of the second switching module 21. The pulse time of the pulse module 17 is 2 s, and the second switching module 21 alternately outputs the output signal of the first switching module 16 and 0; the output of the second switching module 21 and the primary frequency regulation action quantity signal 12 pass through the first adder module 23 to generate a primary frequency regulation action quantity correction signal; the primary frequency regulation action signal 13 generates a cascade correction coefficient through the multi-stage delay module and the switching module. The primary frequency regulation action quantity correction signal and the cascade correction coefficient pass through the first multiplication module 26 to generate a primary frequency regulation time correction signal 27;

[0010] Among them, the primary frequency regulation action signal 13 generates a cascade correction coefficient through a multi-stage delay module and a switching module, specifically including: the primary frequency regulation action signal 13 enters the third switching module 22 after passing through the first delay module 18. The time of the first delay module 18 is 13 s, and the correction coefficient of the third switching module 22 is switched between 1.2 and 1.0. After the primary frequency regulation action signal 13 passes through the second delay module 19, it enters the fourth switching module 24 together with the output of the third switching module 22. The time of the second delay module 19 is 28 s, and the output of the fourth switching module 24 is the alternating output of 1.3 and the third switching module 22. The primary frequency regulation action signal 13 enters the fifth switching module 25 after passing through the third delay module 20. The time of the third delay module 20 is 43 s, and the output of the fifth switching module 25 is the alternating output of 1.1 and the fourth switching module 24, serving as the cascade correction coefficient.

[0011] S3: Primary frequency regulation speed correction logic, specifically including:

[0012] Perform positive and negative value separation processing on the primary frequency regulation time correction signal 27 and input them into the first maximum selection module 28 and the first minimum selection module 29 respectively to generate an acceleration rate and a deceleration rate control signal, specifically including: the output of the first maximum selection module 28 serves as the input of the first inertia module 30 and the second maximum selection module 32, and the output of the first inertia module 30 also serves as the input of the second maximum selection module 32. After the second maximum selection module 32 performs maximum selection, it outputs to the first rate limiting module 34. The output of the first minimum selection module 29 serves as the input of the second inertia module 31 and the second minimum selection module 33, and the output of the second inertia module 31 also serves as the input of the second minimum selection module 33. After the second minimum selection module 33 performs minimum selection, it outputs to the second rate limiting module 39. Dynamically adjust the rate limiting parameters based on the real-time value of the slip signal 11, specifically including: the slip signal 11 passes through the second high limit module 35 to generate a slip greater than signal, serving as the input of the sixth switching module 37. When the slip is greater than 2.1 r / m, the sixth switching module 37 outputs 0.01; otherwise, the sixth switching module 37 outputs 20. The output of the sixth switching module 37 serves as the input of the second rate limiting module 34. The slip signal 11 passes through the third low limit module 36 to generate a slip less than signal, serving as the input of the seventh switching module 38. When the slip is less than 2.1 r / m, the seventh switching module 38 outputs 0.01; otherwise, the seventh switching module 38 outputs 20. The output of the seventh switching module 38 serves as the input of the second rate limiting module 39. Use the second rate limiting module 39 and the first rate limiting module 34 as the input of the second adder module 40, and obtain the output of the second adder module 40 as the correction of the primary frequency regulation speed.

[0013] S4: Primary frequency regulation pressure correction logic, specifically including:

[0014] The main steam pressure signal 42, the output of the second anti-delay module 49, and the output of the eighth switching module 43 are used as the inputs of the eighth switching module 43. The output signal of the eighth switching module 43 is divided by the main steam pressure signal 42 through the first division module 50 to generate a pressure correction signal, which is used as the input of the ninth switching module 52; the main steam pressure signal 42 is divided by the output of the eighth switching module 43 through the second division module 51 to generate a pressure correction signal, which is used as the input of the ninth switching module 52; the primary frequency regulation speed correction signal 41 is obtained, passed through the third high limit module 44 to generate a primary frequency regulation speed correction greater than signal, and the output of the fifth delay module 45 is used as the input of the ninth switching module 52; when the switching condition of the ninth switching module 52 is set to 1, the ninth switching module 52 outputs the output of the first division module 50, and when the switching condition of the ninth switching module 52 is set to 0, the ninth switching module 52 outputs the output of the second division module 51. The output signal of the ninth switching module 52 is used as the input of the second limit module 53, and the primary frequency regulation speed correction signal 41 is multiplied by the output of the second limit module 53 through the second multiplication module 54 to generate a primary frequency regulation pressure correction signal 55.

[0015] Optionally, in some embodiments, the output method of the second anti-delay module 49 specifically includes:

[0016] The primary frequency regulation speed correction signal 41 is obtained, passed through the third high limit module 44 to generate a primary frequency regulation speed correction greater than signal, and the output of the fifth delay module 45 is used as the input of the OR module 48;

[0017] The primary frequency regulation speed correction signal 41 is passed through the fourth low limit module 46 to generate a primary frequency regulation speed correction less than signal, and the output of the sixth delay module 47 is used as the input of the OR module 48. The output signal of the OR module 48 is used as the input of the second anti-delay module 49 to obtain the output of the second anti-delay module 49.

[0018] Optionally, in some embodiments, the slip absolute value signal respectively determines whether the slip absolute value exceeds a preset action threshold or a reset threshold through the first high limit module 7 and the first low limit module 8, and inputs the output signal of the first high limit module 7 to the RS flip-flop module 10, specifically including:

[0019] The absolute value of the slip passes through the first high limit module 7 to generate a signal indicating that the absolute value of the slip is greater, which is output when the absolute value of the slip is greater than 2.05; the absolute value of the slip passes through the first low limit module 8 to generate a signal indicating that the absolute value of the slip is less, and the fourth delay module 9 has a delay time of 0.2 seconds. When the absolute value of the slip is less than 2.01, it is output after a delay of 0.2 seconds.

[0020] Optionally, in some embodiments, generating the primary frequency regulation action signal 13 specifically includes: triggering an action when the absolute value of the slip exceeds 2.05 r / min, and resetting the fourth delay module 9 after 0.2 seconds when the absolute value of the slip is lower than 2.01 r / min.

[0021] Optionally, in some embodiments, the lower limit value of the second low limit module 14 is 1.8, and the delay time of the first inverse delay module 15 is 1 second.

[0022] Optionally, in some embodiments, generating the primary frequency regulation time correction signal 27 specifically includes: within 2 seconds, if the slip signal is less than 1.8, adding 0.3 to the primary frequency regulation action quantity signal; otherwise, delaying for 1 second and subtracting 0.3 from the primary frequency regulation action quantity signal, and outputting the original primary frequency regulation action quantity after 2 seconds.

[0023] Optionally, in some embodiments, the ramp rate limit value of the rate limit module 34 for increasing is 20 MW / s, and the ramp rate limit value for decreasing is the output of the sixth switching module 37. When the output of the second major selection module 32 increases, the output of the rate limit module 34 increases at a rate of 20 MW / s. When the output of the second major selection module 32 decreases, if the slip is greater than 2.1 r / m, the output of the rate limit module 34 decreases at a rate of 0.01 MW / s; otherwise, the output of the rate limit module 34 decreases at a rate of 20 MW / s.

[0024] Optionally, in some embodiments, the ramp rate limit value for decreasing of the second rate limit module 39 is 20 MW / s, and the ramp rate limit value for increasing is the output of the seventh switching module 38. Specifically, when the output of the second minor selection module 33 decreases, the output of the second rate limit module 39 decreases at a rate of 20 MW / s. When the output of the second minor selection module 33 increases, if the slip is less than 2.1 r / m, the output of the second rate limit module 39 increases at a rate of 0.01 MW / s; otherwise, the output of the second rate limit module 39 increases at a rate of 20 MW / s.

[0025] In a second aspect, an embodiment of the present invention further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the steps of the method according to any one of the above first aspects are implemented.

[0026] In a third aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method according to any one of the above first aspects are implemented.

[0027] The above technical solutions of the present invention have at least the following beneficial technical effects:

[0028] The traditional primary frequency regulation control strategy of thermal power units does not fully consider the characteristics of the deep peak shaving working conditions of thermal power units and cannot meet the requirements of national standards. A primary frequency regulation control method for thermal power units under deep peak shaving working conditions according to the present invention performs three-stage corrections of time correction, speed correction, and pressure correction on the feedforward frequency regulation amount in the DEH, and sends the final pressure correction to the DEH valve as a dynamic feedforward for compensation. Among them, the time correction acts in advance at 2s, 15s, 30s, and 45s required by the national standard, ensuring the action amplitude and rapidity of primary frequency regulation at each time node; for the speed correction, based on the time correction, a fast-acting and slow-return logic is adopted. When primary frequency regulation increases, the rapidity of primary frequency regulation is ensured, and the load increase rate is fast. When primary frequency regulation decreases, the rate changes slowly, ensuring the maximum amplitude of primary frequency regulation and increasing the integral power of primary frequency regulation; for the pressure correction, when the requirement for the amplitude of primary frequency regulation is large, after the primary frequency regulation action, it will inevitably cause changes in the main steam pressure of the thermal power unit, resulting in a weakening of the subsequent primary frequency regulation ability. The present invention determines whether to perform pressure correction based on the magnitude of the primary frequency regulation speed correction. When the pressure correction condition is met, the current main steam pressure is maintained. When primary frequency regulation increases the load, a pressure correction coefficient is generated by dividing the maintained main steam pressure by the current main steam pressure to correct the time correction amount of primary frequency regulation. When primary frequency regulation decreases the load, a pressure correction coefficient is generated by dividing the current main steam pressure by the maintained main steam pressure to correct the time correction amount of primary frequency regulation. To ensure that the primary frequency regulation action does not overshoot, the pressure correction coefficient is limited between -2 and 2. After the pressure correction, the action intensity of primary frequency regulation is ensured. The present invention corrects the primary frequency regulation feedforward on the DEH side by using three-stage corrections, ensuring the primary frequency regulation ability of thermal power units under deep peak shaving working conditions, overcoming the characteristics of poor flow characteristics of DEH valves of thermal power units and low unit parameters and weak frequency regulation ability under deep peak shaving working conditions, enabling thermal power units to meet the primary frequency regulation requirements of the power grid for thermal power units under deep peak shaving working conditions, ensuring the safety of the power grid, and improving the primary frequency regulation ability under deep peak shaving working conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or in the prior art, the following will briefly introduce the accompanying drawings required for the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0030] Figure 1 is the primary frequency modulation quantity generation logic provided by the embodiments of the present invention on the DEH side.

[0031] Figure 2 is the primary frequency modulation time correction logic provided by the embodiments of the present invention.

[0032] Figure 3 is the primary frequency modulation speed correction logic provided by the embodiments of the present invention.

[0033] Figure 4 is the primary frequency modulation pressure correction logic provided by the embodiments of the present invention.

[0034] Among them, Figures 1 to 4 the corresponding relationship between the reference numerals in the

[0035] 1 - Actual rotational speed signal, 2 - Rated rotational speed signal, 3 - Subtraction module, 4 - Function module, 5 - Absolute value module, 6 - First limiting module, 7 - First high limit module, 8 - First low limit module, 9 - Fourth delay module, 10 - RS flip - flop module, 11 - Slip signal, 12 - Primary frequency regulation action quantity signal, 13 - Primary frequency regulation action signal, 14 - Second low limit module, 15 - First inverse delay module, 16 - First switching module, 17 - Pulse module, 18 - First delay module, 19 - Second delay module, 20 - Third delay module, 21 - Second switching module, 22 - Third switching module, 23 - First adder module, 24 - Fourth switching module, 25 - Fifth switching module, 26 - First multiplication module, 27 - Primary frequency regulation time correction signal, 28 - First maximum selection module, 29 - First minimum selection module, 30 - First inertia module, 31 - Second inertia module, 32 - Second maximum selection module, 33 - Second minimum selection module, 34 - First rate limiting module, 35 - Second high limit module, 36 - Third low limit module, 37 - Sixth switching module, 38 - Seventh switching module, 39 - Second rate limiting module, 40 - Second adder module, 41 - Primary frequency regulation speed correction signal, 42 - Main steam pressure signal, 43 - Eighth switching module, 44 - Third high limit module, 45 - Fifth delay module, 46 - Fourth low limit module, 47 - Sixth delay module, 48 - OR module, 49 - Second inverse delay module, 50 - First division module, 51 - Second division module, 52 - Ninth switching module, 53 - Second limiting module, 54 - Second multiplication module, 55 - Primary frequency regulation pressure correction signal. Detailed implementation manners

[0036] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0037] In addition, in the following description, the descriptions of well - known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0038] If the descriptions such as "first" and "second" are involved in the embodiments of the present application, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features; the technical solutions between various embodiments may be combined with each other based on what can be achieved by those of ordinary skill in the art.

[0039] In the embodiments of the present application, when referring to A and / or B, it means three cases: A, B, and A and B.

[0040] It should be noted that the serial numbers of the sequence mentioned in the present application do not necessarily represent strict execution in the actual specific implementation process. The serial numbers are used to distinguish each step for easy explanation and to prevent confusion.

[0041] The schematic diagram of the layer structure according to the embodiments of the present invention is shown in the drawings. These figures are not drawn to scale. For the purpose of clarity, some details are enlarged and some details may be omitted. The various regions, shapes of the layers, and their relative sizes and positional relationships shown in the figures are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations. Those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0042] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0043] According to the latest national standard, there are mainly 4 indicators for the primary frequency regulation dynamic performance of thermal power units under the deep peak shaving condition: ① The response time of the primary frequency regulation active power should be less than 2 s; ② The time for the primary frequency regulation active power to reach 75% should be less than 15 s; ③ The time for the primary frequency regulation active power to reach 90% should be less than 30 s; ④ The regulation time of the active power should be less than 45 s.

[0044] Based on the requirements of the latest standard, the present application formulates a primary frequency regulation control method for thermal power units under the deep peak shaving condition. That is, the primary frequency regulation quantity instruction on the DEH side is corrected in a cascade manner, and the final pressure correction instruction is sent to the DEH valve as dynamic feedforward compensation to ensure that the primary frequency regulation dynamic performance meets the index requirements under the deep peak shaving condition.

[0045] The present invention is mainly divided into 4 parts:

[0046] (1) The primary frequency regulation quantity generation logic on the DEH side, as Figure 1 shown.

[0047] (2) The primary frequency regulation time correction logic, as Figure 2 shown.

[0048] (3) The primary frequency regulation speed correction logic, as Figure 3 shown.

[0049] (4) The primary frequency regulation pressure correction logic, as Figure 4 shown.

[0050] The following describes in detail the detailed steps of each correction logic through specific embodiments.

[0051] Embodiment 1: The primary frequency modulation quantity generation logic on the DEH side is as Figure 1 shown.

[0052] Specifically, the actual speed and the rated speed of the thermal power unit pass through the subtraction module 3 to generate a slip signal 11. The slip signal passes through the function module 4 to generate a primary frequency modulation quantity signal. The function generation module 4 is specifically set as shown in Table 1:

[0053] Table 1: Setting table of the conversion function between slip and primary frequency modulation load

[0054]

[0055] In Table 1, Pn is the rated power of the thermal power unit. The initial primary frequency modulation action quantity signal passes through the first limiter module 6 to generate a primary frequency modulation action quantity signal 12. The main function of the first limiter module 6 is to limit the magnitude of the primary frequency modulation action quantity according to the national standard requirements; the slip signal passes through the absolute value module 5 to generate an absolute value signal of the slip. The absolute value of the slip passes through the first high limit module 7 to generate a signal that the absolute value of the slip is greater than. The high limit value of the first high limit module 7 is 2.05, that is, it outputs when the absolute value of the slip is greater than 2.05. The absolute value of the slip passes through the first low limit module 8 to generate a signal that the absolute value of the slip is less than, and then passes through the fourth delay module 9 to generate a delayed output signal. The low limit value of the first low limit module 8 is 2.01, and the delay time of the fourth delay module 9 is 0.2 s, that is, when the absolute value of the slip is less than 2.01, it outputs after a delay of 0.2 s. The two output signals pass through the RS flip-flop module 10 to form a primary frequency modulation action signal 13. That is, the primary frequency modulation action occurs when the absolute value of the slip is greater than 2.05, and when the slip is less than 2.01, the primary frequency modulation action is reset after a delay of 0.2 s.

[0056] Embodiment 2: The primary frequency modulation time correction logic is as Figure 2 shown.

[0057] Specifically, the slip signal 11 passes through the second lower limit module 14 to generate a slip less than signal. The output signal of the slip less than signal after passing through the first inverse delay module 15 is used as the switching condition of the first switching module 16. The lower limit value of the second lower limit module 14 is 1.8, the delay time of the first inverse delay module 15 is 1 s, and the first switching module 16 has two values, which are 0.3 and -0.3 respectively. That is, when the slip is less than 1.8 r / m, the first switching module 16 outputs 0.3; otherwise, after a 1 s delay, the first switching module 16 outputs -0.3. The output signal of the primary frequency regulation action signal 13 after passing through the pulse module 17 is used as the switching condition of the second switching module 21. The pulse time of the pulse module 17 is 2 s. That is, when the primary frequency regulation acts for 2 s, the switching module 21 outputs the output of the first switching module 16; after 2 s, the switching module 21 outputs 0. The primary frequency regulation action quantity signal 12 and the second switching module 21 pass through the first adder module 23 to generate a primary frequency regulation action quantity correction signal. The main function of this part of the logic is that within 2 s based on the primary frequency regulation action quantity signal, if the slip signal is less than 1.8, the primary frequency regulation action quantity signal is added with 0.3; otherwise, after a 1 s delay, the primary frequency regulation action quantity signal is subtracted by 0.3. The purpose is to meet the requirement in the national standard that the active power response time of the primary frequency regulation should be less than 2 s. After 2 s, the original primary frequency regulation action quantity is output. The output signal of the primary frequency regulation action signal 13 after passing through the first delay module 18 is used as the switching condition of the third switching module 22. The time of the first delay module 18 is 13 s, and the third switching module 22 has two values, which are 1.2 and 1 respectively. That is, when the primary frequency regulation acts, the third switching module 22 outputs 1; after 13 s, the third switching module 22 outputs 1.2. The output signal of the primary frequency regulation action signal 13 after passing through the second delay module 19 is used as the switching condition of the fourth switching module 24. The time of the second delay module 19 is 28 s, and the fourth switching module 24 has two values, which are 1.3 and the output of the switching module 22 respectively. That is, when the primary frequency regulation acts, the fourth switching module 24 outputs the output of the third switching module 22; after 28 s, the fourth switching module 24 outputs 1.3. The output signal of the primary frequency regulation action signal 13 after passing through the third delay module 20 is used as the switching condition of the fifth switching module 25. The time of the third delay module 20 is 43 s, and the fifth switching module 25 has two values, which are 1.1 and the output of the fourth switching module 24 respectively. That is, when the primary frequency regulation acts, the fifth switching module 25 outputs the output of the fourth switching module 24; after 43 s, the fifth switching module 25 outputs 1.1. The output of the first adder module 23 and the output of the fifth switching module 25 pass through the first multiplication module 26 to generate a primary frequency regulation time correction signal 27.The main function of this part of the logic is to generate a correction coefficient for the primary frequency regulation action amount. After the primary frequency regulation action for 13 s, the correction coefficient is 1.2; after the primary frequency regulation action for 28 s, the correction coefficient is 1.3; after the primary frequency regulation action for 43 s, the correction coefficient is 1.1. All correction coefficients are 2 s ahead of the time required by the national standard and are amplified on the basis of the primary frequency regulation action amount. The purpose is to meet the requirements of the national standard that the time for the primary frequency regulation active power to reach 75% should be less than 15 s; the time for the primary frequency regulation active power to reach 90% should be less than 30 s; and the regulation time of the active power should be less than 45 s.

[0058] Embodiment 3: Primary frequency regulation speed correction logic, as Figure 3 shown.

[0059] Specifically, after the primary frequency regulation time correction signal 27 is selected through the first major selection module 28 and compared with 0, it is simultaneously output to the first inertia module 30 and the second major selection module 32. The time constant of the first inertia module 30 is 2 s. After being selected through the second major selection module 32, the output is sent to the first rate limiting module 34. After the primary frequency regulation time correction 27 is selected through the first minor selection module 29 and compared with 0, it is simultaneously output to the second inertia module 31 and the second minor selection module 33. The time constant of the first inertia module 31 is 2 s. After being selected through the second minor selection module 33, the output is sent to the second rate limiting module 39. The slip signal 11 passes through the second high limit module 35 to generate a slip greater than signal and is output as the switching condition of the sixth switching module 37. The sixth switching module 37 has two values, 0.01 and 20 respectively. That is, when the slip is greater than 2.1 r / m, the sixth switching module 37 outputs 0.01; otherwise, the sixth module 37 outputs 20. The rising rate limit value of the first rate limiting module 34 is 20 MW / s, and the falling rate limit value is the output of the seventh switching module 37. That is, when the output of the second major selection module 32 increases, the output of the first rate limiting module 34 increases at a rate of 20 MW / s. When the output of the second major selection module 32 decreases, if the slip is greater than 2.1 r / m, the output of the first rate limiting module 34 decreases at a rate of 0.01 MW / s; otherwise, the output of the first rate limiting module 34 decreases at a rate of 20 MW / s. The slip signal 11 passes through the third low limit module 36 to generate a slip less than signal and is output as the switching condition of the seventh switching module 38. The seventh switching module 38 has two values, 0.01 and 20 respectively. That is, when the slip is less than 2.1 r / m, the seventh switching module 38 outputs 0.01; otherwise, the seventh switching module 38 outputs 20. The falling rate limit value of the second rate limiting module 39 is 20 MW / s, and the rising rate limit value is the output of the seventh switching module 38. That is, when the output of the second minor selection module 33 decreases, the output of the second rate limiting module 39 decreases at a rate of 20 MW / s. When the output of the second minor selection module 33 increases, if the slip is less than 2.1 r / m, the output of the second rate limiting module 39 increases at a rate of 0.01 MW / s; otherwise, the output of the second rate limiting module 39 increases at a rate of 20 MW / s. The main function of the primary frequency regulation speed correction logic is that, on the basis of time correction, if the primary frequency regulation increases the load, it increases at a speed of 20 MW / s. If the primary frequency regulation decreases during the actual load increase process, first, due to the action of the major selection module and the inertia module, the decreasing effect will slow down. Second, it decreases at a speed of 0.01 MW / s. By adopting the fast-acting and slow-return logic, the rising effect is strong and the falling effect is weak, which is equivalent to increasing the frequency regulation effect during the primary frequency regulation load increase process, increasing the integral power of the primary frequency regulation, and strengthening the primary frequency regulation effect.Similarly, if the primary frequency regulation reduces the load, it decreases at a rate of 20 MW / s. If the primary frequency regulation increases during the actual load reduction process, first, due to the action of the small selection module and the inertia module, the increasing effect will slow down. Second, it increases at a rate of 0.01 MW / s. By adopting the fast-acting and slow-return logic, the decreasing effect is strong and the increasing effect is weak, which is equivalent to increasing the frequency regulation effect during the primary frequency regulation load reduction process, increasing the integral power of the primary frequency regulation, and strengthening the primary frequency regulation effect.

[0060] Embodiment 4: The primary frequency regulation pressure correction logic is as Figure 4 shown.

[0061] Specifically, the primary frequency regulation speed correction signal 41 passes through the third high limit module 44 to generate a primary frequency regulation speed correction greater than signal, and then passes through the fifth delay module 45 and is output as the switching condition of the ninth switching module 52. The high limit value of the third high limit module 44 is 3, and the delay time of the fifth delay module 45 is 10 s, that is, when the primary frequency regulation speed correction signal 41 is greater than 3, it is delayed for 10 s as the switching condition for switching the ninth switching module 52. The primary frequency regulation speed correction signal 41 passes through the fourth low limit module 46 to generate a primary frequency regulation speed correction less than signal, and then passes through the sixth delay module 47. The outputs of the fifth delay module 45 and the sixth delay module 47 are used as the inputs of the OR module 48. The output signal of the OR module 48 is connected to the second anti-delay module 49 and then output as the switching condition of the eighth switching module 43. The low limit value of the fourth low limit module 46 is -3, the delay time of the sixth delay module 47 is 10 s, and the delay time of the second anti-delay module 49 is 2 s. The main steam pressure signal 42 is connected to the eighth switching module 43, that is, when the primary frequency regulation speed correction signal 41 is greater than 3 and is delayed for 10 s, or when the primary frequency regulation speed correction signal 41 is less than -3 and is delayed for 10 s, the main steam pressure signal 42 maintains the current value as the output of the eighth switching module 43. Otherwise, it is delayed for 2 s, and the main steam pressure signal 42 is used as the output of the eighth switching module 43. The output signal of the eighth switching module 43 passes through the first division module 50 and is divided by the main steam pressure signal 42 to generate a pressure correction signal, which is used as the input of the ninth switching module 52; the main steam pressure signal 42 passes through the second division module 51 and is divided by the output signal of the eighth switching module 43 to generate a pressure correction signal, which is used as the input of the ninth switching module 52. When the switching condition of the ninth switching module 52 is set to 1, the ninth switching module 52 outputs the output of the first division module 50. When the switching condition of the ninth switching module 52 is set to 0, the ninth switching module 52 outputs the output of the second division module 51. The output signal of the ninth switching module 52 is connected to the second limiting module 53. The function of the second limiting module 53 is to limit the main steam pressure correction signal between -2 and 2. The primary frequency regulation speed correction signal 41 passes through the second multiplication module 54 and multiplies with the output of the second limiting module 53 to generate a primary frequency regulation pressure correction.

[0062] An embodiment of the present invention further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the steps of the method according to any one of the above embodiments are implemented.

[0063] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method according to any one of the above embodiments are implemented.

[0064] An embodiment of the present invention further provides a computer program product, including a computer program stored in a computer-readable storage medium. When a processor of an electronic device reads the computer program from the computer-readable storage medium, the processor executes the computer program, so that the electronic device executes the steps of the method according to any one of the above embodiments.

[0065] Obviously, the described embodiments are part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0066] It should be understood that the above specific embodiments of the present invention are only used for exemplary illustration or explanation of the principle of the present invention, and do not constitute a limitation to the present invention. Therefore, any modifications, equivalent replacements, improvements, etc. made without departing from the spirit and scope of the present invention shall be included in the protection scope of the present invention. In addition, the appended claims of the present invention are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

Claims

1. A primary frequency regulation control method for thermal power units under deep peak shaving conditions, characterized in that It includes the following steps: S1: The primary frequency regulation quantity generation logic on the DEH side, specifically including: Obtain the actual speed signal (1) and the rated speed signal (2) of the thermal power unit, and generate a slip signal (11) through a subtraction module (3); input the slip signal (11) into a function module (4) to generate an initial primary frequency regulation action quantity signal based on a preset function relationship between slip and primary frequency regulation; input the initial primary frequency regulation action quantity signal into a first limiting module (6) to perform limiting based on the upper and lower limits of primary frequency regulation specified by national standards, and generate a primary frequency regulation action quantity signal (12); the slip signal (11) passes through an absolute value module (5) to generate a slip absolute value signal, and the slip absolute value signal respectively determines whether the slip absolute value exceeds a preset action threshold or a reset threshold through a first high limit module (7) and a first low limit module (8), input the output signal of the first high limit module (7) into an RS flip-flop module (10), and input the output signal of the first low limit module (8) into the RS flip-flop module (10) through a fourth delay module (9) to generate a primary frequency regulation action signal (13); S2: The primary frequency regulation time correction logic, specifically including: Obtain the slip signal (11) and input it into a second low limit module (14) to generate a slip less than signal, and the output signal of the slip less than signal after passing through a first anti-delay module (15) is used as the switching condition of a first switching module (16), specifically including: output 0.3 when the slip is less than 1.8 r / min, otherwise output -0.3 after a 1 s delay; based on the output signal of the primary frequency regulation action signal (13) after passing through a pulse module (17) as the switching condition of a second switching module (21), the pulse time of the pulse module (17) is 2 s, and the second switching module (21) alternately outputs the output signal of the first switching module (16) and 0; the output of the second switching module (21) and the primary frequency regulation action quantity signal (12) pass through a first adder module (23) to generate a primary frequency regulation action quantity correction signal; the primary frequency regulation action signal (13) generates a step correction coefficient through a multi-stage delay module and a switching module, and the primary frequency regulation action quantity correction signal and the step correction coefficient pass through a first multiplication module (26) to generate a primary frequency regulation time correction signal (27); Among them, the primary frequency regulation action signal (13) generates a cascade correction coefficient through a multi-stage delay module and a switching module, specifically including: the primary frequency regulation action signal (13) enters the third switching module (22) after passing through the first delay module (18). The time of the first delay module (18) is 13 s, and the correction coefficient of the third switching module (22) is switched between 1.2 and 1.0; after the primary frequency regulation action signal (13) passes through the second delay module (19), it enters the fourth switching module (24) together with the output of the third switching module (22). The time of the second delay module (19) is 28 s, and the output of the fourth switching module (24) is the alternating output of 1.3 and the third switching module (22); after the primary frequency regulation action signal (13) passes through the third delay module (20), it enters the fifth switching module (25). The time of the third delay module (20) is 43 s, and the output of the fifth switching module (25) is the alternating output of 1.1 and the fourth switching module (24), which serves as the cascade correction coefficient; S3: Primary frequency regulation speed correction logic, specifically including: Perform positive and negative value separation processing on the primary frequency modulation time correction signal (27), and input it into the first maximum selection module (28) and the first minimum selection module (29) respectively to generate the acceleration rate and deceleration rate control signals, which specifically include: the output of the first maximum selection module (28) serves as the input of the first inertia module (30) and the second maximum selection module (32), the output of the first inertia module (30) also serves as the input of the second maximum selection module (32), and the second maximum selection module (32) outputs to the first rate limiting module (34) after maximum selection; the output of the first minimum selection module (29) serves as the input of the second inertia module (31) and the second minimum selection module (33), the output of the second inertia module (31) also serves as the input of the second minimum selection module (33), and the second minimum selection module (33) outputs to the second rate limiting module (39) after minimum selection; dynamically adjust the rate limiting parameters based on the real-time value of the slip signal (11), which specifically includes: the slip signal (11) passes through the second high limit module (35) to generate a slip greater than signal, which serves as the input of the sixth switching module (37). When the slip is greater than 2.1 r / m, the sixth switching module (37) outputs 0.01, otherwise the sixth switching module (37) outputs 20. The output of the sixth switching module (37) serves as the input of the second rate limiting module (34); the slip signal (11) passes through the third low limit module (36) to generate a slip less than signal, which serves as the input of the seventh switching module (38). When the slip is less than 2.1 r / m, the seventh switching module (38) outputs 0.01, otherwise the seventh switching module (38) outputs 20. The output of the seventh switching module (38) serves as the input of the second rate limiting module (39); use the second rate limiting module (39) and the first rate limiting module (34) as the input of the second adder module (40) to obtain the output of the second adder module (40) as the primary frequency modulation speed correction; S4: Primary frequency modulation pressure correction logic, which specifically includes: The main steam pressure signal (42), the output of the second anti-delay module (49), and the output of the eighth switching module (43) serve as the input of the eighth switching module (43). The output signal of the eighth switching module (43) is divided by the main steam pressure signal (42) through the first division module (50) to generate a pressure correction signal, which serves as the input of the ninth switching module (52). The main steam pressure signal (42) is divided by the output of the eighth switching module (43) through the second division module (51) to generate a pressure correction signal, which serves as the input of the ninth switching module (52). The primary frequency regulation speed correction signal (41) is obtained, passed through the third high limit module (44) to generate a primary frequency regulation speed correction greater than signal, and the output of the fifth delay module (45) serves as the input of the ninth switching module (52). When the switching condition of the ninth switching module (52) is set to 1, the ninth switching module (52) outputs the output of the first division module (50). When the switching condition of the ninth switching module (52) is set to 0, the ninth switching module (52) outputs the output of the second division module (51). The output signal of the ninth switching module (52) serves as the input of the second limiting module (53). The primary frequency regulation speed correction signal (41) is multiplied by the output of the second limiting module (53) through the second multiplication module (54) to generate a primary frequency regulation pressure correction signal (55).

2. The method according to claim 1, characterized in that, The output method of the second anti-delay module (49) specifically includes: Obtain the primary frequency regulation speed correction signal (41), pass it through the third high limit module (44) to generate a primary frequency regulation speed correction greater than signal, and the output of the fifth delay module (45) serves as the input of the OR module (48). The primary frequency regulation speed correction signal (41) passes through the fourth low limit module (46) to generate a primary frequency regulation speed correction less than signal, and the output of the sixth delay module (47) serves as the input of the OR module (48). The output signal of the OR module (48) serves as the input of the second anti-delay module (49), and the output of the second anti-delay module (49) is obtained.

3. The method according to claim 1, characterized in that The slip absolute value signal respectively determines whether the slip absolute value exceeds a preset action threshold or a reset threshold through the first high limit module (7) and the first low limit module (8). The output signal of the first high limit module (7) is input to the RS flip-flop module (10), and specifically includes: The slip absolute value passes through the first high limit module (7) to generate a slip absolute value greater than signal, which is output when the slip absolute value is greater than 2.

05. The slip absolute value passes through the first low limit module (8) to generate a slip absolute value less than signal. The delay time of the fourth delay module (9) is 0.2 seconds, and when the absolute value of the slip is less than 2.01, it is output after a 0.2-second delay.

4. The method according to claim 1, wherein The generation of the primary frequency regulation action signal (13) specifically includes: triggering an action when the slip absolute value exceeds 2.05 r / min, and resetting through the fourth delay module (9) after 0.2 seconds when the slip absolute value is lower than 2.01 r / min.

5. The method according to claim 1, wherein The lower limit value of the second lower limit module (14) is 1.8, and the delay time of the first anti-delay module (15) is 1 second.

6. The method according to claim 1, wherein The generation of the primary frequency regulation time correction signal (27) specifically includes: within 2 seconds, if the slip signal is less than 1.8, add 0.3 to the primary frequency regulation action amount signal; otherwise, delay for 1 second and subtract 0.3 from the primary frequency regulation action amount signal, and output the original primary frequency regulation action amount after 2 seconds.

7. The method according to claim 1, wherein The rising rate limit value of the rate limit module (34) is 20 MW / s, and the falling rate limit value is the output of the sixth switching module (37). When the output of the second largest selection module (32) increases, the output of the rate limit module (34) increases at a rate of 20 MW / s. When the output of the second largest selection module (32) decreases, if the slip is greater than 2.1 r / m, the output of the rate limit module (34) decreases at a rate of 0.01 MW / s; otherwise, the output of the rate limit module (34) decreases at a rate of 20 MW / s.

8. The method according to claim 1, wherein The falling rate limit value of the second rate limit module (39) is 20 MW / s, and the rising rate limit value is the output of the seventh switching module (38). Specifically, when the output of the second smallest selection module (33) decreases, the output of the second rate limit module (39) decreases at a rate of 20 MW / s. When the output of the second smallest selection module (33) increases, if the slip is less than 2.1 r / m, the output of the second rate limit module (39) increases at a rate of 0.01 MW / s; otherwise, the output of the second rate limit module (39) increases at a rate of 20 MW / s.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1-8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the method according to any one of claims 1-8.

Images