Transient response of VCSEL driver

Abstract

The invention relates to a transient response of a VCSEL driver. According to an embodiment, a feedback circuit for a power converter system is presented. The feedback circuit comprises an outer loop circuit and an inner loop circuit. The outer loop circuit includes a current estimator and a feedback controller. The current estimator is configured to generate a first voltage based on a difference between an output current of the power converter system and an average current at an inductor of the power converter system. The feedback controller is configured to generate an error signal as a difference between the first voltage and a desired setpoint voltage. The inner loop circuit is configured to generate a pulse width modulation (PWM) signal based on the error signal to operate a switching element of the power converter system.

Description

Technical Field

[0001] The present disclosure generally relates to optical laser transmitters and, in particular embodiments, to improving the transient response time of a vertical cavity surface emitting laser (VCSEL) driver to regulate the operation of an optical laser transmitter. Background Art

[0002] Optical laser transmitters are used in various technical applications due to their ability to deliver large amounts of power in extremely short durations. However, this ability places stringent demands on the accuracy and performance of the feedback mechanisms involved in their operation. A well-designed feedback loop is crucial for ensuring the accuracy and responsiveness of power delivery, especially considering the fast time scales at which laser transmitters are expected to operate.

[0003] Traditionally, feedback loops (such as those for conventional feedback (FB) systems) rely on monitoring the vertical cavity surface emitting laser (VCSEL) current or coil current to achieve regulation of the laser output current. When the VCSEL current is regulated, the output poles generated by the VCSEL and the output capacitor introduce significant delays in the time response, hindering the response speed to levels slower than, for example, 4 microseconds. This pole makes it difficult to implement a fast feedback loop. The resulting speed reduction is detrimental to applications that require fast laser intensity modulation.

[0004] Conversely, when an inductor current regulation feedback loop is employed, during transient events, a large amount of power is directed to the output capacitor (C OUT ). This causes the current within the VCSEL to rise undesirably slowly. The increase in current takes longer to reach the expected level within the VCSEL because the output capacitor absorbs the current. This reduces the overall efficiency and effectiveness of the laser transmitter in fast response scenarios. It is desirable to address these deficiencies in conventional solutions. Summary of the Invention

[0005] Technical advantages are generally achieved by embodiments of the present disclosure that describe solutions for improving the transient response time of a vertical cavity surface emitting laser (VCSEL) driver to regulate the operation of an optical laser transmitter.

[0006] A first aspect relates to a feedback circuit for a power converter system. The feedback circuit includes an outer loop circuit and an inner loop circuit. The outer loop circuit includes a current estimator and a feedback controller. The current estimator is configured to generate a first voltage based on the difference between the output current of the power converter system and the average current at the inductor of the power converter system. The feedback controller is configured to generate an error signal as the difference between the first voltage and a desired setpoint voltage. The inner loop circuit is configured to generate a pulse width modulation (PWM) signal based on the error signal to operate a switching element of the power converter system.

[0007] The second aspect relates to a feedback circuit for a power converter system. The feedback circuit includes an outer loop circuit and an inner loop circuit. The outer loop circuit includes a current estimator and a feedback controller. The current estimator is configured to generate a first voltage based on a difference between an output current of the power converter system and a desired setpoint voltage. The feedback controller is configured to generate an error signal as a difference between the first voltage and an average current at an inductor of the power converter system. The inner loop circuit is configured to generate a pulse width modulation (PWM) signal based on the error signal to operate a switching element of the power converter system.

[0008] The third aspect relates to a power converter system. The power converter system includes a DC-DC power stage and a feedback circuit. The DC-DC power stage includes a switching element and an inductor. The switching element includes a high-side switch and a low-side switch. A shared terminal of the high-side switch and the low-side switch is coupled to a first terminal of the inductor. A second terminal of the inductor is coupled to a load of the power converter system. The feedback circuit is configured to regulate an output current of the DC-DC power stage for the load. The feedback circuit includes an outer loop circuit and an inner loop circuit. The outer loop circuit includes a current estimator and a feedback controller. The current estimator is configured to generate a first voltage based on a difference between the output current and an average current at the inductor or based on a difference between the output and a desired setpoint voltage. The feedback controller is configured to generate an error signal as a difference between the first voltage and the desired setpoint voltage or a difference between the first voltage and the average current at the inductor. The inner loop circuit is configured to generate a pulse width modulation (PWM) signal based on the error signal to operate a switching element of the power converter system.

[0009] Embodiments may be implemented in hardware, software, or a combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of a circuit configured as a constant output current converter in, for example, a switched mode power supply (SMPS);

[0012] Figure 2 is a schematic diagram of a feedback circuit based on peak current mode control;

[0013] Figure 3 is a schematic diagram of a proportional integral (PI) regulator;

[0014] Figure 4 is a block diagram of an embodiment control system;

[0015] Figures 5A to 5B and 6A to 6B are Bode plots;

[0016] Figure 7 is a block diagram of an exemplary power converter system;

[0017] Figure 8 is a block diagram of an exemplary control system;

[0018] Figure 9 is a block diagram of an exemplary feedback outer loop (F OL );

[0019] Figure 10 is a block diagram of an exemplary feedback outer loop (F OL );

[0020] Figure 11 is a schematic diagram showing an exemplary current estimator circuit;

[0021] Figure 12 is a schematic diagram of an exemplary current estimator circuit;

[0022] Figure 13 is a block diagram of a feedback outer loop (F OL );

[0023] Figure 14 is a block diagram of a feedback outer loop (F OL ); and

[0024] Figure 15 is a schematic diagram of an exemplary symmetric feedback controller. DETAILED DESCRIPTION

[0025] The present disclosure provides many applicable inventive concepts that can be implemented in various specific contexts. The specific embodiments merely illustrate specific configurations and do not limit the scope of the claimed embodiments. Features from different embodiments can be combined to form other embodiments, unless otherwise mentioned. Various embodiments are illustrated in the drawings, where the same reference numerals identify the same components and elements, and repeated descriptions are omitted for brevity.

[0026] The variations or modifications described in one embodiment in the examples can also apply to other embodiments. Further, various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0027] Although aspects of the present invention are mainly described in the context of buck converters, it should also be understood that these aspects of the invention can also apply to any general type of DC-DC converter.

[0028] Figure 1is a block diagram of a circuit 100 configured as a constant output current converter in, for example, a switched mode power supply (SMPS). Circuit 100 includes a DC-DC converter 102, a power supply 104, an output capacitor (C OUT ) 106, and a load 108, which may (or may not) be arranged as shown. Circuit 100 may include additional components not shown, such as inductive elements at the output of the DC-DC converter 102 and before the output capacitor (C OUT ) 106 to store energy, for example, in a buck converter or a boost converter.

[0029] The DC-DC converter 102 converts a direct current (DC) source from one voltage level to another. They are used in various applications where the voltage level must be boosted (boost converter), bucked (buck converter), or even inverted. These converters are crucial in providing the correct voltage and current to an electronic device and ensuring its safe and efficient operation. In an embodiment, the DC-DC converter 102 is a buck peak current mode DC-DC type converter.

[0030] The DC-DC converter 102 is coupled to a power supply 104 that supplies voltage to the DC-DC converter 102. As shown, the DC-DC converter 102 has a reference input that receives a reference signal (i.e., V REF or I REF ) that drives the DC-DC converter 102. The output of the DC-DC converter 102 is coupled to the output capacitor (C OUT ) 106 and the load 108. Thus, the DC-DC converter 102 delivers a regulated output current to the output capacitor (C OUT ) 106 and the load 108 based on the reference signal at the reference input.

[0031] The output capacitor (C OUT ) 106 provides an energy reserve that can be called upon when the demand of the load 108 transiently increases. It stores energy when the power consumption is less than the power consumption output by the DC-DC converter 102 and releases the energy quickly when the demand briefly exceeds the supplied current.

[0032] The output capacitor (C OUT ) 106 smooths out any voltage ripple generated by the switching action of the DC-DC converter 102. Ripple is inherent in switched converters due to the periodic energy accumulation and release of inductive elements (usually inductors or transformers). While the constant current regulation mode aims to regulate the load current, the output capacitor ensures that the voltage remains relatively stable throughout all switching phases of the DC-DC converter.

[0033] Further, the output capacitor (C OUT ) 106 provides a buffer to prevent load transients - sudden changes in the load 108 that cause rapid changes in current and voltage. The output capacitor (C OUT ) 106 can respond to these sudden transitions and prevent immediate output interruptions.

[0034] Moreover, the output capacitor (C OUT ) 106 can stabilize the feedback control loop used in the constant current converter. The value and characteristics of the output capacitor (C OUT ) 106 affect how quickly and smoothly the DC - DC converter 102 can respond to changes in the load 108 and the input reference voltage, thus affecting system stability and preventing oscillations or other instabilities.

[0035] In an embodiment, the load 108 is a vertical - cavity surface - emitting laser (VCSEL) coupled to a VCSEL driver. The DC - DC converter 102 provides a constant - current output to drive the VCSEL. Generally, a VCSEL requires a stable current source to maintain a consistent optical output and preserve the life of the laser diode. Ensuring a constant current is crucial because variations can cause light intensity fluctuations and may damage the laser diode.

[0036] Adjusting the coil current (I COIL ) of the DC - DC converter 102 to be equal to the output current (I VCSEL ) provided to the VCSEL is desirable and is typically determined and set using a feedback circuit. It allows for the use of only one current - sensing element in the output current path.

[0037] In a conventional feedback circuit, the current - sensing element at the VCSEL introduces additional poles into the feedback path of the circuit 100, which originate from the VCSEL resistance and the output capacitor (C OUT ) 106, resulting in a low - pass filtering effect. This filtering effect is typically represented by a "pole" in the frequency domain. The presence of the additional poles generated by the VCSEL and the output capacitor (C OUT ) 106 causes a delay that is difficult for even a fast feedback controller to overcome. Adversely, it slows down the current rise of the output current (I VCSEL ) (i.e., slows down the response time) to more than a few microseconds.

[0038] Further, as another method in a conventional feedback circuit, when a pulsed reference signal is applied to drive the DC - DC converter 102, it initiates the process of regulating the current flowing through its output inductor, which in turn raises the output voltage. This rise in the output voltage is due to driving the desired current through the load 108. However, a significant drawback of this second method is in the output capacitor (COUT ) concurrently drive an uncontrolled parasitic current in 106.

[0039] The regulation mechanism of the feedback circuit within the DC-DC converter 102 is designed to maintain the coil current (I COIL ) in agreement with the load current. However, since it is typically not feasible to directly measure the load current at the optical laser emitter, as discussed above, with regard to additional poles and increased lag time as well as the need for an additional current sensor, the current charging and discharging the output capacitor (C OUT ) 106 introduces ambiguity. Considering that the unmeasured portion of the total current is being diverted into the output capacitor (C OUT ) 106, this additional current flow results in uncertainty regarding the actual amount of current delivered to the load 108. Therefore, ensuring precise control of the current supplied to the VCSEL during the current rise and fall intervals becomes complex and may affect the performance and reliability of the laser operation.

[0040] Furthermore, the VCSEL driver typically requires a fast response time to modulate the laser output. Therefore, the DC-DC converter 102 must be able to provide high-frequency pulse power to ensure rise and fall times within 1 to a few microseconds. The output capacitor (C OUT ) 106 substantially affects the performance characteristics of the current supplied to the VCSEL. For example, when the capacitance of the output capacitor (C OUT ) 106 increases, the ripple of the output current (I VCSEL ) is beneficially reduced, and I VCSEL is the current feeding the VCSEL. This reduction in ripple is beneficial for the stable operation of the VCSEL because excessive ripple may cause unwanted noise and instability in the laser output.

[0041] However, increasing the capacitance of the output capacitor (C OUT ) 106 incurs a trade-off. Specifically, this has an indirect impact on the dynamic response of the output current (I VCSEL ). As the capacitance value rises, the output current (I VCSEL ) takes longer to increase to its desired value (i.e., the rise time of the output current is slower (I VCSEL )) because the output capacitor (C OUT ) 106 absorbs a relatively high current. This increased capacitance introduces a larger time constant into the circuit 100, resulting in a more sluggish response to changes in the requirements of the converter's control system.

[0042] Conversely, reducing the capacitance of the output capacitor (C OUT ) 106 results in a faster response time, allowing the output current (I VCSEL) reaches its desired value more quickly, thereby providing a faster rise time. However, the smaller capacitance of the output capacitor (C OUT ) 106 results in a poorer suppression effect of the switching ripple of the DC-DC converter 102 in the output current (I VCSEL ). The increased ripple level may impair the operational stability of the VCSEL by introducing undesirable noise and fluctuations in the laser output.

[0043] Therefore, since the output capacitor (C OUT ) 106 is beneficially used to reduce the ripple at the output current (I VCSEL ) supplied to the VCSEL, the ambiguity of the parasitic current added to and generated in the output capacitor (C OUT ) 106 increases the complexity of the fast rise time of the load current supplied to the DC-DC converter 102.

[0044] In an embodiment, a solution to the limitations in a conventional feedback circuit is proposed, which employs a feedback technique based on the estimation and appropriate weighting of the output capacitor current (I COIL ) when only sensing the coil current (I COUT ). By adding a variable gain stage to compensate for introducing additional poles into the system, the variable gain stage introduces adjacent zeros into the transfer function, thereby providing sufficient compensation for the poles. Therefore, the proposed method significantly improves the rise time performance of the output current (I VCSEL ) supplied to the VCSEL, achieving a rise time as fast as 1 microsecond. These and additional features will be further detailed below.

[0045] Figure 2 FIG. illustrates a schematic diagram of a feedback circuit 200 based on peak current mode control, which can be combined with the circuit 100. As shown, the feedback circuit 200 includes a sense resistor 202, a first differential amplifier 204, a low-pass filter 208, a capacitive current estimator 210, an adder 212, a digital-to-analog converter (DAC) 216 that provides a reference value, a linear feedback controller 218, a ramp compensator circuit 220, a PWM comparator 222, and a flip-flop 224, which may (or may not) be arranged as shown. The feedback circuit 200 may include additional components not shown.

[0046] The feedback circuit 200 is configured to monitor the coil current (I COIL ) to maintain a set point of the current, regardless of changes in the input voltage or changes in the load 108, to achieve a constant output current operation.

[0047] In an embodiment, the coil current (I COIL) It is regulated by a carefully designed control loop that senses peak and average current values. Initially, a sense resistor 202 is introduced into the current path of the coil current (I COIL ). The voltage across the sense resistor 202 indicates the instantaneous current flowing through it. Then, this voltage is fed to a first differential amplifier 204 responsible for sensing the peak current. By amplifying the voltage across the sense resistor 202, the first differential amplifier 204 provides a signal proportional to the peak current of the coil current (I COIL ).

[0048] A low-pass filter 208 coupled to the output of the first differential amplifier 204 transforms the peak current into an average current. The voltage on the output of the low-pass filter 208 is proportional to the current flowing through it but represents the average value, rather than the true inductor current with inductor ripple current at the switching frequency. The resulting voltage on the output of the low-pass filter 208 reflects the average current through the time-averaging characteristic.

[0049] The capacitance of the output capacitor (C OUT ) 106 shapes the response of the output current regulation. The output voltage (V OUT ) on the output capacitor (C OUT ) 106 is shaped by the transfer function of a capacitive current estimator 210 and fed into an adder 212. The adder 212 has two inputs; the positive input receives the average current from the low-pass filter 208, and the negative input is connected to the amplified signal from the capacitive current estimator 210. The adder 212 effectively combines these signals to produce a signal corresponding to any deviation from the desired output current.

[0050] Then the summing signal is provided to a linear feedback controller 218 as its first input. Additionally, a reference current (I VCSEL(REF) ) 214 is converted to an analog signal by a DAC 216. The output of the DAC 216 represents the reference current signal, which constitutes the second input of the linear feedback controller 218. This controller represents the so-called outer loop known in the peak current mode control topology. In this system, the linear feedback controller 218 evaluates the two inputs according to a predefined transfer function and performs adjustments to regulate the average output current. The control algorithm includes an expression outlining the determination of the duty cycle of the PWM of the buck converter based on the peak coil current (I COIL ).

[0051] In parallel with these processes, another branch of the first differential amplifier 204 is fed into a ramp compensator circuit 220. This signal helps to further stabilize the internal control loop by ensuring the convergence of the inner loop for higher duty cycle values.

[0052] The subsequent stage involves a PWM comparator 222, whose first input is coupled to the output of the ramp compensator circuit 220 and whose second input receives information from the linear feedback controller 218. When a difference occurs between these signals, indicating a deviation from the favorable operating conditions, the output of the PWM comparator 222 is switched, which affects the downstream timing circuitry.

[0053] The output of the PWM comparator 222 is fed into the data input (D) of a flip-flop 224, which also receives a clock signal (CLK) as an input, ensuring synchronous operation with the system timing.

[0054] The output (Q) of the flip-flop 224 provides a switching PWM signal to the DC-DC converter 102. In a buck converter, it is related to the on-time (T ON ) duration. This duty cycle management ensures that the output current regulation meets the transient response requirements and steady-state accuracy, maintaining the desired performance level under various operating conditions.

[0055] An advantage provided by embodiments of the present disclosure is a single current sensing element that can concurrently measure peak and average current and provide average and peak current information.

[0056] Further, since the current (I VCSEL ) supplied to the VCSEL is no longer monitored, the additional circuitry of the capacitive current estimator 210 is used to establish an image of the output current (I VCSEL ) in the adder 212. This summing block implements the function of the ideal equation I COIL = I’ COUT + I VCSEL . Thus, the input to the linear feedback controller is: I’ VCSEL = I COIL - I’ COUT , where I’ COUT is an estimate of I COUT , and I’ VCSEL is an estimate of the VCSEL current for regulation.

[0057] Figure 3 Illustrated is a schematic diagram of a proportional-integral (PI) regulator 300, which can be combined with the circuit 100. As shown, the PI regulator 300 includes a first resistor (R1) 302, a second resistor (R2) 304, a capacitor (C INT ) 306, and an operational amplifier 308, which may (or may not) be arranged as shown. The PI regulator 300 may include additional components not shown.

[0058] In an embodiment, the PI regulator 300 is configured to regulate the estimated coil current (I’ COIL ) or the output current (I VCSEL ) supplied to the VCSEL. The first resistor (R1) 302 is responsible for determining the amount of feedback signal directly related to the instantaneous error in the system. This error is the difference between the desired output current and the sensed actual output current. By adjusting the resistance value of the first resistor (R1) 302, the response rate to the error can be controlled.

[0059] The second resistor (R2) 304 and the capacitor (C INT ) 306 arranged in series form part of the control scheme. The capacitor (C INT ) 306, in combination with the second resistor (R2) 304, performs the task of accumulating the error over time. It integrates the error signal, ensuring that even small and persistent errors that may not be corrected immediately will eventually be zeroed out. The combination of the second resistor (R2) 304 and the capacitor (C INT ) 306 defines the time response of the integral action. It balances the speed at which the controller reacts to the accumulated error signal.

[0060] The operational amplifier 308 includes a non-inverting input (+) and an inverting input (-). The inverting input (-) of the operational amplifier 308 is coupled to the shared node between the first terminal of the first resistor (R1) 302 and the first terminal of the second resistor (R2) 304. Depending on the desired operating conditions of the operational amplifier 308 and the control loop, the non-inverting input (+) is coupled to a reference ground or a reference voltage. The output of the operational amplifier 308 is coupled to the second terminal of the capacitor (C INT ) 306.

[0061] The operational amplifier 308 amplifies the small error signal to a level sufficient to effect a practical adjustment to the output of the DC-DC converter 102. The shared node between the first resistor (R1) 302 and the second resistor (R2) 304 provides a path for the error signal to reach the inverting input (-). The output voltage or current (after being scaled and optionally inverted by additional circuit elements not shown) is combined with some reference to generate the error signal.

[0062] The operational amplifier 308 generates a correction signal, which is then fed back into the control circuitry of the DC-DC converter 102, thereby influencing its behavior to correct any deviation found in the output current. The proportional element of the signal ensures a rapid response to changes, preventing rapid fluctuations in the current. In contrast, the integral element systematically addresses the gradual drift or long-term difference between the desired current and the actual current.

[0063] The cooperation of these actions of the resistor-capacitor network and the amplifier ultimately forms a finely tuned feedback system. The PI regulator 300 adjusts and maintains the output current of the DC-DC converter 102, thereby generating a stable and reliable power supply, which is crucial for the optimal performance and lifespan of the VCSEL.

[0064] Figure 4 The block diagram of an embodiment control system 400 is illustrated. The control system 400 illustrates a proposed arrangement that allows for indirectly measuring the output current (I COUT ) 418 provided to the VCSEL by subtracting the coil current (I COIL ) 404 from the capacitor current (I VCSEL ) 418.

[0065] The control system 400 is described with reference to the symmetric feedback controller 1500 combined with the circuit 100. The various components illustrate different transfer functions that provide the relationships between the various inputs and outputs in the circuit 100.

[0066] It should be understood that the relationship between the capacitor current (I OUT ) 418 of the output capacitor (C COUT ) 106, the coil current (I COIL ) 404, and the output current (I VCSEL ) 412 provided to the VCSEL can be expressed by the equation: I COIL = I VCSEL + I COUT . Alternatively, this relationship can be expressed as the equation: I VCSEL = I COIL - I COUT . The control system 400 effectively subtracts the coil current (I COUT ) from the capacitor current (I COIL ) to indirectly measure the output current (I VCSEL ) provided to the VCSEL. This subtraction is further controlled by the programmable k-factor 420. The switching frequency ripple is attenuated by a first filter (represented as the transfer function 428) and a second filter (represented as the transfer function 430) to provide an average value of the inductor current similar to that of the low-pass filter 208 in the control system 400.

[0067] In the frequency domain, the power stage and pulse-width modulation (PWM) of the DC-DC converter 102 are represented as a transfer function 402. The power stage converts the DC input voltage into a desired DC output voltage. It typically consists of switches (such as transistors like MOSFETs), diodes, inductors, and capacitors. The configuration of these components can vary depending on the type of converter (e.g., buck, boost, buck-boost, etc.). The switches turn on and off at a high frequency, thereby shaping the voltage and current to achieve the desired output.

[0068] The PWM controller specifies the operation of the power stage by controlling the timing of the switches in the power stage. The PWM controller generates a PWM signal, typically a square wave that toggles between an on (high voltage) and off (low voltage) state. The duty cycle of the PWM signal (the ratio of the time the signal is high to low within each period) determines the average output voltage of the DC-DC converter 102 relative to its input.

[0069] In an embodiment, the PWM controller operates such that the power stage has a transfer function 402 approximately equal to 1 (e.g., for a buck converter); this means it is configured to produce an output voltage very close to the input voltage multiplied by the duty cycle.

[0070] The transfer function 406 encapsulates how the load 108 and the output capacitor (C OUT ) 106 transform the average inductor current into the output voltage V OUT 408 under different operating conditions. The transfer function 406 of the circuit 100 in the frequency domain can be represented as Equation (4.1): where's' is the complex frequency variable in the Laplace transform, R LOAD is the equivalent resistance value of the load 108, and the output capacitor (C OUT ) 106 is the capacitance value of the output capacitor (C OUT ) 106. The transfer function 406 represents the impedance of the output of the DC-DC converter 102 (i.e., the parallel connection of the output capacitor (C OUT ) 106 and the load 108).

[0071] The denominator in Equation (4.1) introduces poles into the control system 400. It represents a first-order low-pass filter with a cut-off frequency of This cut-off frequency determines how quickly the voltage across R LOAD can respond to changes. A higher cut-off frequency allows for a faster response, while a lower cut-off frequency results in a slower response.

[0072] At low frequencies (i.e., s close to zero), the output behaves like a simple resistor, and its output voltage is proportional to any given current based on Ohm's law (V = IR). This means that, under steady-state conditions, the output impedance of the DC-DC converter 102 (as seen by the load 108) is essentially R LOAD .

[0073] As the frequency increases, the capacitive reactance of the output capacitor (C OUT ) 106 plays a more significant role. The term sR LOAD C OUT grows, and thus the overall value of the impedance decreases. This effectively smooths or filters out high-frequency variations due to the capacitive effect, which cancels out rapid changes in the voltage across the load 108.

[0074] The transfer function 406 describes how fluctuations in the coil current (I COIL ) due to changes in the PWM controller commands or changes in the input voltage or the load 108 are converted into changes in the output voltage (V OUT ) by considering the electrical characteristics of the power stage components, including the dynamic interaction between the inductor and the capacitor during energy transfer. The behavior of the output voltage (V OUT ) 408 can be predicted by the transfer function 406, which takes into account the effects of R LOAD and the output capacitor (C OUT ) 106.

[0075] In the frequency domain, by providing the coil current (I COIL ) 404 as the input to the transfer function 406, the output voltage (V OUT ) 408 can be expressed as

[0076] The output current (I VCSEL ) 412 is proportional to the output voltage (V OUT ) 408 and inversely proportional to the resistance (R LOAD ) of the load 108, expressed as Here, the conductance 410 indicates how the current in the circuit 100 increases as the resistance decreases, and vice versa.

[0077] In the frequency domain, the transfer function 416 that describes how the capacitor current (I COUT ) 418 is related to its output voltage (V OUT ) 408 is expressed as sC OUT , which corresponds to the definition of the capacitor current as . By providing the output voltage (V OUT)408 serves as the input to transfer function 416, and the capacitor current (I COUT )418 can be expressed as

[0078] The capacitor current (I COUT )418 is provided as the input to the programmable k-factor 420. In future embodiments, the programmable k-factor 420 is implemented as a variable sensing capacitor (C SNS ). It will be shown that this capacitor implements the transfer function 416. The variable sensing capacitor (C SNS ) allows the feedback loop to adjust its behavior based on the capacitance value, effectively becoming a tuning parameter or programmable k-factor within the control system 400.

[0079] The variable sensing capacitor (C SNS ) affects the impedance and thus controls the dynamics of the feedback loop. The impedance of the capacitor is inversely proportional to its capacitance and the frequency of the signal passing through it, as given by the expression Z = 1 / (jωC), where ω is the angular frequency and C is the capacitance. By electronically adjusting the capacitance of the variable sensing capacitor (C SNS ), for example, by discretely programming the capacitance value using switches, the effective gain k in the feedback loop can be changed.

[0080] The programmable k-factor 420 scales the image of the capacitor current (I’ COUT )418 by the k-factor. Thus, the output of the programmable k-factor 420 is expressed as: kI COUT (s) or

[0081] In an embodiment, due to the ripple in the coil current (I COIL ) at 404, a first filter with a gain of G SNS is introduced into the system to provide an average current image of the output current. The transfer function 428 of the first filter represents how the output of the first filter responds to its input, taking into account the gain (G SNS ) and the time constant (τ). The transfer function 428 of the first filter is expressed as The time constant (τ) is characteristic of the response rate of a first-order system to a change in its input. The transfer function 428 of the first filter adds a pole, where the denominator (1 + sτ) represents a first-order lag. Thus, the transfer function 428 scales the coil current (I COIL )404 such that the output of the transfer function 428 is expressed as: In an embodiment, the gain of the first filter is between 0.01 and 2; in a particular embodiment, the first filter has a unity gain (G SNS = 1).

[0082] In an embodiment, due to the capacitor current (ICOUT ) The ripple at 418, with a gain of G SNS of the second filter is introduced into the system. The transfer function 430 represents how the output of the second filter responds to its input. The transfer function 430 is represented as Thus, the transfer function 430 scales the output of the programmable k-factor 420 such that the output of the transfer function 430 is represented as: In an embodiment, the second filter has a unity gain (G SNS = 1).

[0083] Adding a second pole through the second filter introduces a further phase lag in the transfer function of the system. This additional phase lag can become significant, moving the system closer to its stability margin. Due to the possibility of increased phase delay and reduced phase margin, the cumulative effect of multiple poles complicates the stability of the system. Advantageously, the programmable k-factor 420 introduces an additional zero into the system, and compensates for the additional pole from the output node impedance (1 + sR LOAD C OUT ) (i.e., reduces the phase shift to 90° or less).

[0084] In an embodiment having a first filter and a second filter, the first adder 422 subtracts (i) the output of the transfer function 430 from (ii) the output of the transfer function 428 of the first filter, which provides a feedback current (I FB ) at its output. In the frequency domain, the feedback current (I FB ) is represented as: This transfer function represents an estimated image of the VCSEL current (I’ VCSEL ).

[0085] In an embodiment without a first filter and a second filter, the first adder 422 subtracts (i) the output of the programmable k-factor 420 from (ii) the output of the transfer function 402, which provides a feedback current (I FB ) at its output. In the frequency domain, the feedback current (I FB ) is represented as:

[0086] Thus, when k is equal to zero (i.e., k = 0), there is no zero in the transfer function, and the feedback current (I FB ) is represented as: Or I without a first filter and a second filter FB (s) = I COIL (s). This represents that the estimation of the capacitor current is disabled. When k is equal to 1 (i.e., k = 1), the zero cancels out C in the denominator OUT R OUTThe introduced pole, and the feedback current (I FB ) is represented by the bipolar transfer function as: Or in the absence of the first filter and the second filter, it is a first-order transfer function.

[0087] Therefore, it is recommended to set the variable factor k in the range of 0 to 1 to achieve optimal performance in the feedback regulation loop. This adjustment ensures that the transfer function associated with the feedback current (I FB ) closely reflects the output current (I VCSEL ) provided to the VCSEL, while compensating for the slow pole (1 + sC OUT R OUT ). The presence of the pole can be harmful because it not only slows down the rise time of the output current (I VCSEL ), but also causes additional phase shift. This phase shift complicates the compensation process within the feedback loop and may affect system stability and response.

[0088] The feedback current (I FB ) is fed to the second adder 424. Another input to the second adder 424 is a scaled version of the reference voltage (V REF ). The reference voltage (V REF ) is set based on the desired average current of the output current (I VCSEL ). The gain factor of G SNS scales the reference voltage (V REF ). The second adder 424 subtracts the feedback current (I REF ) from the scaled version of the reference voltage (V FB ). In an embodiment, the second adder 424 and the transfer function 426 implemented by the symmetric feedback controller 1500.

[0089] The transfer function 426 of the PI regulator 300 in the frequency domain can be represented by the equation: where R1 is the resistance value of the first resistor (R1) 302, R2 is the resistance value of the second resistor (R2) 304. And C INT is the capacitance value of the capacitor (C INT ) 306. The transfer function 426 characterizes its behavior according to how the PI regulator 300 responds to different frequency components of the signal.

[0090] Therefore, in the presence of the first filter and the second filter, the open-loop feedback (FB OL ) at the output of the transfer function 426 is: In the absence of the first filter and the second filter, the open-loop feedback (FB OL ) at the output of the transfer function 426 is:

[0091] Figures 5A to 5B Illustrates the Bode plot (Bode magnitude and phase plot) of the feedback current (I FB ) in the control system 400, where there is no first filter (represented by the transfer function 428) and second filter (represented by the transfer function 430). As Figure 4 discussed, in the absence of the first and second filters, the feedback current (I FB ) in the frequency domain is represented as: Advantageously, by using the programmable k-factor 420 and adjusting the variable k-factor to have a zero transfer function, a zero is introduced to compensate for the first-order lag from the pole introduced by C FB in the denominator of the feedback current (I OUT R OUT .

[0092] In Figure 5A , the Bode magnitude plot illustrates the magnitude (in dB) of the frequency response of the first feedback current (I FB ) 502 (k-factor equal to '0'), the second feedback current (I FB ) 504 (k-factor between '0' and '1'; for example, approximately equal to 0.5) and the third feedback current (I FB ) 506 (k-factor equal to '1').

[0093] In Figure 5B , the Bode phase plot illustrates the phase shift (in degrees) of the frequency response of the first feedback current (I FB ) 552 (k-factor equal to '0'), the second feedback current (I FB ) 554 (k-factor between '0' and '1'; for example, approximately equal to 0.5) and the third feedback current (I FB ) 556 (k-factor equal to '1').

[0094] For the first feedback current (I FB ) 502, the k-factor is equal to '0', I FB (s) = I COIL (s), and the frequency response remains at 0 dB over the entire frequency range. For the third feedback current (I FB ) 506, the k-factor is equal to '1', and the frequency response illustrates a -20 dB / dec magnitude roll-off due to the pole, which actually corresponds to directly measuring the output current (I VCSEL ).

[0095] For the first feedback current (I FB)552, the k factor equals '0', I FB (s) = I COIL (s), and the frequency response remains at 0 degrees over the entire frequency range. For the third feedback current (I FB )556, the k factor equals '1', and the frequency response plot shows a 90-degree phase shift due to the pole, corresponding to the directly measured output current (I VCSEL ). As previously discussed, with the additional phase shift in the system, this phase shift complicates the compensation process within the feedback loop and may affect system stability and response.

[0096] Therefore, by setting the k factor to a value between '0' and '1', a zero is introduced to compensate for the first-order lag from the pole in the denominator of the feedback current (I FB ) due to C OUT R OUT introduced.

[0097] It can be observed through the second feedback current (I FB )504 that by setting the k factor to a value between '0' and '1', although the magnitude initially decreases, it becomes stable as the frequency increases. Also, by setting the k factor to a value between '0' and '1', the phase shift of the second feedback current (I FB )554 returns to zero, which is desirable.

[0098] Figures 6A to 6B The Bode plot (Bode magnitude and phase plot) of the feedback current (I FB ) in the control system 400 is illustrated, which includes a first filter (represented as transfer function 428) and a second filter (represented as transfer function 430). As Figure 4 discussed, in the case of having a first filter and a second filter, the feedback current (I FB ) in the frequency domain is represented as: Advantageously, by using the programmable k factor 420 and adjusting the variable k factor to have a zero transfer function, a zero is introduced to compensate for the second-order lag from the pole in the denominator of the feedback current (I FB ) due to C OUT R OUT introduced.

[0099] In Figure 6A , the Bode magnitude plot illustrates the first feedback current (I FB )602 (k factor equals '0'), the second feedback current (I FB )604 (k factor between '0' and '1'), and the third feedback current (I FB)Magnitude (in dB) of the frequency response for 606 (k-factor equal to '1').

[0100] In Figure 6B , the Bode phase plot illustrates the phase shift (in degrees) of the frequency response for the first feedback current (I FB ) 652 (k-factor equal to '0'), the second feedback current (I FB ) 654 (k-factor between '0' and '1'), and the third feedback current (I FB ) 656 (k-factor equal to '1').

[0101] For the first feedback current (I FB ) 602, the k-factor is equal to '0', and the frequency response has a first-order lag over the entire frequency range. Since the k-factor is equal to zero, there is no information about the output capacitor current. For the third feedback current (I FB ) 606, the k-factor is equal to '1', and the frequency response has a second-order lag over the entire frequency range. This transfer function represents the output current (I VCSEL ), but although it contains two poles, it is difficult to stabilize.

[0102] For the first feedback current (I FB ) 652, the k-factor is equal to '0', and the frequency response has a first-order lag over the entire frequency range. For the third feedback current (I FB ) 656, the k-factor is equal to '1', and the frequency response illustrates a 180-degree phase shift due to the two poles in the transfer function.

[0103] Therefore, by setting the k-factor to a value between '0' and '1', a zero is introduced to compensate for the first-order lag from one of the poles in the denominator of the feedback current (I FB ).

[0104] It can be observed through the second feedback current (I FB ) 604 that by setting the k-factor to a value between '0' and '1', as the frequency increases, the magnitude drops by approximately -20 dB / dec. Also, by setting the k-factor to a value between '0' and '1', the phase shift of the second feedback current (I FB ) 654 returns to 90 degrees, which is more desirable than compensating for the 180-degree phase shift in the feedback loop.

[0105] Figure 7 Illustrates the use of the sense capacitor (C SNS)Block diagram of an example power converter system 700 of a peak current mode feedback loop as a current estimator. The power converter system 700 includes a DC-DC power stage 702, a feedback outer loop (F OL )704, a feedback inner loop (F IL )706, a slope compensator 708, an adder 710, an output capacitor (C OUT )106, and a load 108, which may or may not be arranged as shown. The power converter system 700 may include additional components not shown. The power converter system 700 is configured to regulate the current of the load 108, which may include an optical laser emitter, such as a VCSEL.

[0106] In an embodiment, the DC-DC power stage 702 includes a switch circuit (e.g., high-side switch, low-side switch) 703 coupled to an inductor 705, as known in the art.

[0107] In an embodiment, the feedback outer loop (F OL )704 includes a current estimator 712 coupled to a feedback controller 714, which may or may not be arranged as shown. In an embodiment, the feedback outer loop (F OL )704 may include components not shown.

[0108] In an embodiment, the feedback outer loop (F OL )704 is configured to receive an image of the average coil current (V(I COIL_AVG )) and the output voltage (V COUT ).

[0109] In an embodiment, the image of the average coil current (V(I COIL_AVG )) represents a voltage signal proportional to the average current flowing through the inductor 705 of the DC-DC power stage 702.

[0110] In an embodiment, the capacitor current (I COUT )418 represents a voltage signal proportional to the current associated with the output capacitor (C OUT )106. This signal indicates the energy transferred to or from the output capacitor (C OUT )106. In the power converter system 700, the image of the capacitor current (I’ COUT ) is generated by a sense capacitor in the current estimator 712.

[0111] The feedback controller 714 of the feedback outer loop (F OL )704 is configured to generate a voltage error (V ERR ) based on these input signals, representing the difference from a reference voltage (V REF)(i.e., the desired set point). The feedback controller (714) receives the average coil current (V(I COIL_AVG )) image minus the estimated image of the capacitor current (I’ COUT )418 to determine the state of the system relative to the reference voltage (V REF ). The voltage error (V ERR ) indicates whether the voltage at the load 108 is higher or lower than the desired target.

[0112] In an embodiment, the adder 710 has a first input coupled to the output of the feedback outer loop (F OL )704. The second input of the adder 710 is coupled to the slope compensator 708. Thus, the output of the adder 710 is the algebraic sum of these two signals. Then, the adder 710 adds or subtracts them depending on the polarities of the two signals. It generates an output to the feedback inner loop (F IL )706, which combines the instantaneous error voltage and the rate-of-change compensation (slope compensation).

[0113] The slope compensator 708 is configured to stabilize the internal control loop in the power converter system 700, which may exhibit subharmonic transient response or become unstable. The slope compensator 708 can adjust the duty cycle reference (control effort) based on a function of the output system variable or the switching frequency, preventing subharmonic oscillations that may occur in a pulse width modulation (PWM) system.

[0114] In an embodiment, the feedback inner loop (F IL )706 includes a comparator 716 and a latch 718, which may or may not be arranged as shown. In an embodiment, the feedback inner loop (F IL )706 may include components not shown. In an embodiment, the feedback inner loop (F IL )706 is configured to receive a clock signal (T CLK ), the image of the peak coil current (V(I COIL_PEAK )) and the output signal from the adder 710.

[0115] The clock signal (T CLK ) provides timing information and synchronizes the operation of the feedback inner loop (F IL )706 with the overall frequency of the power converter system 700. This ensures that the control actions taken by the feedback inner loop (F IL )706 are timely and consistent with other processes within the power converter system 700.

[0116] The image of the peak coil current (V(I COIL_PEAK )) provides real-time data of the current through the inductor 705. The peak coil current (V(I COIL_PEAK)) The Feedback Inner Loop (FIL) 706 is allowed to rapidly adjust the inductor current to the peak value given by the output of the adder 710.

[0117] The Feedback Inner Loop (F IL ) 706 also receives the output signal from the adder 710, which is used to coordinate the regulation of the Feedback Inner Loop (F IL ) 706 and the Feedback Outer Loop (F OL ) 704.

[0118] The Feedback Inner Loop (F IL ) 706 is configured to generate a Pulse Width Modulation (PWM) signal based on these input signals, and this PWM signal is provided as an input signal to the DC-DC power stage 702 within the power converter system 700. The Feedback Inner Loop (F IL ) 706's PWM output directly controls the switching circuit 703 in the DC-DC power stage 702, modulating its operation to convert the input DC power into an output DC power at the desired voltage and current levels.

[0119] Figure 8 The block diagram of an embodiment control system 800 is illustrated, which can be implemented as the power converter system 700. The control system 800 illustrates a proposed arrangement that allows for indirectly measuring the output current (I COIL ) 412 provided to the VCSEL by subtracting the capacitor current (I COUT) ) 418 from the coil current (I VCSEL ) 404. In an embodiment, the output capacitor current observer is implemented by a sensing capacitor (C SNS ) and a sensing resistor (R SNS ), represented as the transfer function 802.

[0120] For the sake of brevity of this disclosure, items with similar reference numerals in Figure 8 will not be repeated in the Figure 4 description.

[0121] In the control system 800, the transfer function 416 in the control system 400 is replaced by the transfer function 802 (the output capacitor current observer transfer function). In the frequency domain, the transfer function 802 describes how the capacitor current (I COUT ) 418 is related to the representation of the sensed voltage (V CSNS ) 804. The transfer function 802 is represented as sC SNS R SNS , where C SNS is the capacitance of the variable sensing capacitor (C SNS ), and R SNS is the resistance of the sensing resistor (R SNS ).

[0122] In an embodiment, a variable sensing capacitor (C SNS ) is arranged between the output voltage (V OUT ) 408 and virtual ground, implemented by, for example, an operational amplifier. In the time domain, the variable sensing capacitor (C SNS ) generates a sensing current (I OUT ) from the output voltage (V CSNS ), which can be expressed as:

[0123] In an embodiment, a sensing resistor (R SNS ) transforms the sensing current (I CSNS ) and generates a sensing voltage (V CSNS ) 804 in the time domain, which can be expressed as

[0124] Thus, the variable sensing capacitor (C SNS ) is used in combination with the sensing resistor (R SNS ) in a feedback loop to sense the coil current (I COIL ) 404 flowing through the inductor 705 and convert it into a proportional sensing voltage (V CSNS ) 804. The sensing voltage (V CSNS ) 804 is used for control and regulation purposes as the input to the unity factor 806. The variable sensing capacitor (C SNS ) can smooth the input signal, similar to the function of a second filter in the control system 400. In an embodiment, it is desired that C SNS R SNS be equal to kC SNS C OUT . The variable sensing capacitor (C SNS ) provides a variable k factor, which can be programmable.

[0125] In an embodiment, the gain (G SN ) of the combination of the sense variable sensing capacitor (C SNS ) S and the sensing resistor (R SNS ) is approximately equal to 0.5.

[0126] The combination of the variable sensing capacitor (C SNS ) and the sensing resistor (R SNS ) eliminates the need for a dedicated capacitor current sensor (such as a resistive current sensor or a current transformer).

[0127] The programmable k factor 420 in the control system 400 is replaced by the unity factor 806 in the control system 800 because the function of the programmable k factor 420 is performed by the variable sensing capacitor (CSNS ) and the transfer function 802 to satisfy.

[0128] The second filter in control system 400 (represented as transfer function 430) is replaced by a different second filter in control system 800. Different from the second filter in control system 400, the second filter in control system 800 does not include a gain (G SNS ), because the gain function is satisfied by the variable sensing capacitor (C SNS ) and the transfer function 802. Therefore, the transfer function 808 is represented as In some embodiments, the poles of the second filter (1 + sτ) (represented as transfer function 808) may not be required because the capacitor ripple current is typically low.

[0129] Therefore, the open - loop feedback (FB OL ) at the output of the transfer function 808 is:

[0130] Figure 9 Illustrates a block diagram of an embodiment feedback outer loop (F OL ) 900, which can be implemented as the feedback outer loop (F OL ) 704 in the power converter system 700. As shown, the feedback outer loop (F OL ) 900 includes a programmable k - factor 904, an adder 906, and a feedback controller 714, which may or may not be arranged as shown. In an embodiment, the feedback outer loop (F OL ) 900 may include components not shown.

[0131] The adder 906 receives the average coil current (I COIL_AVG ) and the capacitor current (I COUT ) multiplied by the variable k - factor, and provides the difference between these signals at its output.

[0132] In the frequency domain, the transfer function 902 receives a reference current (I REF ) and the output of the adder 906, and generates a voltage error (V ERR ) based on these input signals.

[0133] In an embodiment, the capacitor current (I COUT ) is measured by the variable sensing capacitor (C SNS ) in combination with a sensing resistor (R SNS ). In other embodiments, the capacitor current (I COUT ) is measured by a dedicated capacitor current sensor, such as a resistive shunt sensor or a current transformer.

[0134] Figure 10 FIG. illustrates a block diagram of an embodiment feedback outer loop (F OL ) 1000, which can be implemented as a feedback outer loop (F OL ) 704 in a power converter system 700. As shown, the feedback outer loop (F OL ) 1000 includes a programmable k-factor 1004, an adder 1006, and a feedback controller 714, which may or may not be arranged as shown. In an embodiment, the feedback outer loop (F OL ) 1000 may include components not shown.

[0135] The adder 1006 receives the average current (I REF ) and the capacitor current (I COUT ) multiplied by the variable k-factor, and provides the sum of these signals at its output.

[0136] In the frequency domain, the transfer function 1002 receives the average coil current (I COIL_AVG ) and the output of the adder 1006, and generates a voltage error (V ERR ) based on these input signals.

[0137] In an embodiment, the capacitor current (I COUT ) is measured by a variable sensing capacitor (C SNS ) in combination with a sensing resistor (R SNS ). In other embodiments, the capacitor current (I COUT ) is measured by a dedicated capacitor current sensor, such as a shunt resistance sensor or a current transformer.

[0138] Compared with the feedback outer loop (F OL ) 900, in the feedback outer loop (F OL ) 1000, the output of the current estimator is not subtracted from the average coil current (I COIL_AVG ), but added to the reference signal (i.e., I’ REF = I’ COUT + V REF , where I’ REF is the image of the reference current (I REF ), and I’ COUT is the estimated image of the capacitor current (I COUT ). From the perspective of the transfer function, this is the same as Figure 9 . However, advantageously, the current estimator is not inserted into the feedback in the feedback outer loop (F OL ) 1000, which does not reduce the phase stability margin.

[0139] Figure 11FIG. illustrates a schematic diagram showing an embodiment of a current estimator circuit 1100, which can be implemented as current estimator 712 in power converter system 700 or as a current estimator (represented as transfer function 802) in control system 800. As shown, current estimator circuit 1100 includes a voltage source (V a ) 1102, a first resistor (R1) 1104, a second resistor (R2) 1106, a third resistor (R3) 1108, a fourth resistor (R4) 1110, a variable sense capacitor (C SNS ) 1112, a first operational amplifier 1114, and a second operational amplifier 1116, which may (or may not) be arranged as shown. Current estimator circuit 1100 may include additional components not shown.

[0140] The voltage source (V a ) 1102 provides a common-mode voltage (V a ) to the non-inverting (+) inputs of the first operational amplifier 1114 and the second operational amplifier 1116. In an embodiment, the value of the voltage source (V a ) 1102 is set to approximately half of the supply voltage (V DD ) from power supply 104.

[0141] In an embodiment, the variable sense capacitor (C SNS ) 1112 is coupled between the output node of the DC-DC converter 102 (i.e., coupled to load 108) and the virtual ground terminal (-) of the first operational amplifier 1214 (i.e., equal to V a ). The sense current (I SNS ) from the variable sense capacitor (C CSNS ) 1112 is provided to the inverting (-) input of the second operational amplifier 1116, which is coupled to its output via the fourth resistor (R4) 111O. The inverting (-) input of the second operational amplifier 1116 represents a virtual ground equal to the voltage V a . The connection to the virtual ground allows for the implementation of where I CSNS (t) is transformed into a sense voltage (V CSNS ) across the fourth resistor (R4) 111O.

[0142] The average coil current (I COIL_AVG) The image of () is provided by the first inverting amplifier 1107, which is implemented by the first operational amplifier 1214, the first resistor (R1) 1204, and the second resistor (R2) 1206. The output of the first operational amplifier 1114 is coupled to the second inverting amplifier 1109 composed of the second operational amplifier 1116, the third resistor (R3) 1108, and the fourth resistor (R4) 111O.

[0143] The current estimator circuit 11OO is arranged in an in-loop implementation, where the average coil current (I COIL_AVG ) is subtracted from the estimated output capacitor current (I SNS ) represented by the sense current (I CSNS ) from the variable sense capacitor (C COUT ). The output voltage (V OUT ) is represented as V OUT = V(I COIL_AVG ) - V CSNS (t) or

[0144] Advantageously, the feedback amplifier implemented as the transfer function 426 of the current estimator circuit 11OO operates within a well-defined common-mode voltage.

[0145] Figure 12 The schematic diagram of the exemplary current estimator circuit 1200 is illustrated, which can be implemented as the current estimator in the power converter system 700. As shown, the current estimator circuit 1200 includes a voltage source (V a ) 1202, the first resistor (R1) 11204, the second resistor (R2) 1206, the third resistor (R3) 1208, the fourth resistor (R4) 121O, the variable sense capacitor (C SNS ) 1212, the first operational amplifier 1214, and the second operational amplifier 1216, which may (or may not) be arranged as shown. The current estimator circuit 1200 may include additional components not shown.

[0146] The voltage source (V a ) 1202 provides a reference voltage (V a ) to the non-inverting (+) inputs of the first operational amplifier 1214 and the second operational amplifier 1216.

[0147] In an embodiment, the variable sense capacitor (C SNS ) 1212 is coupled between the output node of the DC-DC converter 102 (i.e., coupled to the load 108) and the virtual ground terminal (-) of the first operational amplifier 1214 (i.e., equal to V a ). From the variable sense capacitor (CSNS ) The sense current (I CSNS ) of 1112 is provided to the inverting (-) input of the first operational amplifier 1114, which is coupled to its output via the second resistor (R2) 1206. The connection to virtual ground allows for where I CSNS (t) to be transformed into the negative value (-V CSNS ) of the sense voltage across the second resistor (R2) 1206.

[0148] The reference voltage (V REF ) is provided to the input of the first inverting amplifier 1207, which is implemented by the first operational amplifier 1214, the first resistor (R1) 1204, and the second resistor (R2) 1206. The output of the first operational amplifier 1214 is coupled to the input of the second inverting amplifier 1209, which consists of the second operational amplifier 1216, the third resistor (R3) 1208, and the fourth resistor (R4) 1210.

[0149] This second solution of the current estimator circuit 1200 is arranged in the path of the reference voltage (V REF ) such that the estimated image of the output capacitor current (I SNS ) represented by the sense current (I CSNS ) from the variable sense capacitor (C COUT ) 1212 is added to the reference voltage (V REF ). The output voltage (V OUT ) is represented as V OUT(CSNS) = V REF + V CSNS (t) or

[0150] Advantageously, the parasitic phase lag from the current estimator circuit 1200 does not affect the stability of the system because it is outside the feedback loop.

[0151] Figure 13 Illustrated is a block diagram of the feedback outer loop (F OL ) 1300, which can be implemented as the feedback outer loop (F OL ) 704 in the power converter system 700. The feedback outer loop (F OL ) 1300 includes a current estimator 1302 and a feedback controller 1304, which may (or may not) be arranged as shown. The feedback outer loop (F OL ) 1300 may include additional components not shown.

[0152] In an embodiment, the current estimator 1302 is in the feedback outer loop (F OL)It is implemented as current estimator 712 in 704 and is implemented within the feedback loop. In an embodiment, current estimator 1302 is implemented as Figure 11 the current estimator circuit 11OO in

[0153] As Figure 7 shown, the input signal of the feedback outer loop (F OL ) 1300 is the image of the average coil current (V(I COIL_AVG ))), the image of the capacitor current (I COUT ), and the reference voltage (V REF ).

[0154] Current estimator 1302 receives the images of the average coil current (V(I COIL_AVG )) and the output voltage (VOUT). Current estimator 1302 generates an output voltage (V OUT ), expressed as

[0155] In an embodiment, feedback controller 1404 is implemented as feedback controller 714 in power converter system 700. The feedback controller 1404 of the feedback outer loop (F OL ) 1400 is configured to generate a voltage error (V REF ) based on the reference voltage (V CSNS(OUT) ) and the output voltage (V ERR ) from current estimator 1402. The voltage error (V ERR ) indicates whether the voltage at load 108 is higher or lower than the desired target. The voltage error (V ERR ) is the input signal of the feedback inner loop (F IL ) 706 of power converter system 700.

[0156] Figure 14 Illustrates a block diagram of the feedback outer loop (F OL ) 1400, which can be implemented as the feedback outer loop (F OL ) 704 in power converter system 700. The feedback outer loop (F OL ) 1400 includes current estimator 1402 and feedback controller 1404, which may (or may not) be arranged as shown. The feedback outer loop (F OL ) 1400 may include additional components not shown.

[0157] In an embodiment, current estimator 1402 is implemented as part of the feedback outer loop (F OL ) 704, as current estimator 712, and is implemented outside the feedback loop. In an embodiment, current estimator 1402 is implemented as Figure 12 the current estimator circuit 1200 in

[0158] As Figure 7 shown, the input signals of the feedback outer loop (F OL ) 1400 are the image of the average coil current (V(I COIL_AVG ))), the output voltage (V OUT ) and the reference voltage (V REF ).

[0159] The current estimator 1402 receives the image of the reference voltage (V REF ) and the image of the capacitor current (I COUT ). The current estimator 1302 generates the output voltage (V OUT ), expressed as

[0160] In an embodiment, the feedback controller 1404 is implemented as the feedback controller 714 in the power converter system 700. The feedback controller 1404 of the feedback outer loop (F OL ) 1400 is configured to generate a voltage error (V COIL_AVG )) based on the average coil current (V(I OUT(CSNS) )) and the output voltage (V ERR ) from the current estimator 1402. The voltage error (V ERR ) indicates whether the voltage at the load 108 is higher or lower than the desired target. The voltage error (V ERR ) is the input signal of the feedback inner loop (F IL ) 706 of the power converter system 700.

[0161] In other words, although the feedback outer loop (F OL ) 1300 is implemented by applying the image of the capacitor current (I’ COUT ) to the sensed average inductor current, the feedback outer loop (F OL ) 1400 applies the image of the capacitor current (I’ COUT ) to the reference voltage (V REF ).

[0162] Figure 15A schematic diagram of an embodiment symmetrical feedback controller 1500 is illustrated, which can be implemented as a feedback controller 1304, 1404, 714, or a PI regulator 300. The symmetrical feedback controller 1500 includes a first resistor (R1) 1502, a second resistor (R2) 1504, a third resistor (R3) 1506, a fourth resistor (R4) 1508, a first capacitor (C1) 1510, a second capacitor (C2) 1512, and an operational amplifier 1514, which may (or may not) be arranged as shown. The symmetrical feedback controller 1500 may include additional components not shown. In an embodiment, the resistance of the first resistor (R1) 1502 is approximately equal to the resistance of the second resistor (R2) 1504. In an embodiment, the resistance of the third resistor (R3) 1506 is approximately equal to the resistance of the fourth resistor (R4) 1508. In an embodiment, the capacitance of the first capacitor ( C1 ) 1510 is approximately equal to the capacitance of the second capacitor ( C2 ) 1512 .

[0163] Compared to the PI regulator 300, the symmetric feedback controller 1500 implements a symmetric (ie, identical) transfer function V ERR / V REF =-V ERR / V OUT .

[0164] The feedback from the outer loop (F OL )1300 or feedback outer loop (F OL )1400 The output voltage of the current estimator (V OUT ) is provided to the first resistor (R1) 1502. The output of the operational amplifier 1514 is coupled to its inverting (-) input via the second resistor (R2) 1504 and the first capacitor (C1) 1510.

[0165] Reference voltage (V REF ) or average coil current (V(I COIL_AVG )) is provided to a third resistor (R3) 1506. The non-inverting (+) input of the operational amplifier 1514 is coupled to a reference ground via a fourth resistor (R4) 1508 and a second capacitor (C2) 1512. The fourth resistor (R4) 1508 and the second capacitor (C2) 1512 allow for symmetry in the frequency domain (i.e., equal transfer functions with different polarities) from both inputs.

[0166] In an embodiment, the operational amplifier 1514 is based on (i) the feedback from the outer loop (F OL )1300 output voltage (V OUT ) and (ii) reference voltage (V REF ) to generate the voltage error (V ERR ).

[0167] In an embodiment, the operational amplifier 1514 generates a voltage error (V OL ) based on the difference between (i) the output voltage (V OUT ) from the feedback outer loop (F COIL_AVG ) 1400 and (ii) the average coil current (V(I ERR )).

[0168] Advantageously, embodiments of the present disclosure provide better control of the rise time of a DC-DC power converter while minimizing the risk of overshoot.

[0169] A first aspect relates to a feedback circuit for a power converter system. The feedback circuit includes an outer loop circuit and an inner loop circuit. The outer loop circuit includes a current estimator and a feedback controller. The current estimator is configured to generate a first voltage based on the difference between the output current of the power converter system and the average current at the inductor of the power converter system. The feedback controller is configured to generate an error signal as the difference between the first voltage and a desired setpoint voltage. The inner loop circuit is configured to generate a pulse width modulation (PWM) signal based on the error signal to operate a switching element of the power converter system.

[0170] In a first implementation form of the feedback circuit according to the first aspect as such, the power converter system is configured to provide a regulated current to a vertical cavity surface emitting laser (VCSEL) driver, which is configured to drive a VCSEL.

[0171] In a second implementation form of the feedback circuit according to the first aspect as such or any previous implementation form of the first aspect, the power converter system includes: a variable sensing capacitor arranged in parallel with the load of the power converter system; and a sensing resistor having a first terminal coupled to the variable sensing capacitor, and a second terminal of the sensing resistor being coupled to the load.

[0172] In a third implementation form of the feedback circuit according to the first aspect as such or any previous implementation form of the first aspect, the power converter system includes a DC-DC power stage, which includes a switching element. The switching element includes a high-side switch and a low-side switch. A shared terminal of the high-side switch and the low-side switch is coupled to a first terminal of the inductor. A second terminal of the inductor is coupled to the load of the power converter system.

[0173] In a fourth implementation form of the feedback circuit according to the first aspect as such or any previous implementation form of the first aspect, the feedback circuit further includes a slope compensator and an adder. The adder is coupled between the outer loop circuit and the inner loop circuit. The adder is configured to generate an algebraic sum of a signal from the slope compensator and the error signal to the inner loop circuit.

[0174] In a fifth implementation of the feedback circuit according to the first aspect itself or any previous implementation of the first aspect, the load of the power converter system is a vertical cavity surface emitting laser (VCSEL).

[0175] In a sixth implementation of the feedback circuit according to the first aspect itself or any previous implementation of the first aspect, the power converter system is configured to provide a regulated current to operate a vertical cavity surface emitting laser (VCSEL).

[0176] A second aspect relates to a feedback circuit for a power converter system. The feedback circuit includes an outer loop circuit and an inner loop circuit. The outer loop circuit includes a current estimator and a feedback controller. The current estimator is configured to generate a first voltage based on a difference between an output current of the power converter system and a desired setpoint voltage. The feedback controller is configured to generate an error signal as a difference between the first voltage and an average current at an inductor of the power converter system. The inner loop circuit is configured to generate a pulse width modulation (PWM) signal based on the error signal to operate a switching element of the power converter system.

[0177] In a first implementation of the feedback circuit according to the second aspect itself, the power converter system is configured to provide a regulated current to a vertical cavity surface emitting laser (VCSEL) driver, which is configured to drive the VCSEL.

[0178] In a second implementation of the feedback circuit according to the second aspect itself or any previous implementation of the second aspect, the power converter system includes: a variable sensing capacitor arranged in parallel with the load of the power converter system; and a sensing resistor having a first terminal coupled to the variable sensing capacitor, and a second terminal of the sensing resistor is coupled to the load.

[0179] In a third implementation of the feedback circuit according to the second aspect itself or any previous implementation of the second aspect, the power converter system includes a DC-DC power stage, which includes a switching element. The switching element includes a high-side switch and a low-side switch. A shared terminal of the high-side switch and the low-side switch is coupled to a first terminal of an inductor. A second terminal of the inductor is coupled to the load of the power converter system.

[0180] In a fourth implementation of the feedback circuit according to the second aspect itself or any previous implementation of the second aspect, the feedback circuit further includes a slope compensator and an adder. The adder is coupled between the outer loop circuit and the inner loop circuit. The adder is configured to generate an algebraic sum of a signal from the slope compensator and the error signal to the inner loop circuit.

[0181] In a fifth implementation of the feedback circuit according to the second aspect itself or any previous implementation of the second aspect, the load of the power converter system is a vertical-cavity surface-emitting laser (VCSEL).

[0182] In a sixth implementation of the feedback circuit according to the second aspect itself or any previous implementation of the second aspect, the power converter system is configured to provide a regulated current to operate a vertical-cavity surface-emitting laser (VCSEL).

[0183] A third aspect relates to a power converter system. The power converter system includes a DC-DC power stage and a feedback circuit. The DC-DC power stage includes a switching element and an inductor. The switching element includes a high-side switch and a low-side switch. A shared terminal of the high-side switch and the low-side switch is coupled to a first terminal of the inductor. A second terminal of the inductor is coupled to the load of the power converter system. The feedback circuit is configured to regulate the output current of the DC-DC power stage for the load. The feedback circuit includes an outer loop circuit and an inner loop circuit. The outer loop circuit includes a current estimator and a feedback controller. The current estimator is configured to generate a first voltage based on a difference between the output current and the average current at the inductor or based on a difference between the output and a desired setpoint voltage. The feedback controller is configured to generate an error signal as a difference between the first voltage and the desired setpoint voltage or a difference between the first voltage and the average current at the inductor. The inner loop circuit is configured to generate a pulse-width modulation (PWM) signal based on the error signal to operate the switching element of the power converter system.

[0184] In a first implementation of the power converter system according to the third aspect itself, the power converter system is configured to provide a regulated current to a vertical-cavity surface-emitting laser (VCSEL) driver, which is configured to drive the VCSEL.

[0185] In a second implementation of the power converter system according to the third aspect itself or any previous implementation of the third aspect, the power converter system further includes: a variable sensing capacitor arranged in parallel with the load; and a sensing resistor having a first terminal coupled to the variable sensing capacitor, and a second terminal of the sensing resistor is coupled to the load.

[0186] In a fourth implementation of the power converter system according to the third aspect itself or any previous implementation of the third aspect, the feedback circuit further includes a slope compensator and an adder. The adder is coupled between the outer loop circuit and the inner loop circuit. The adder is configured to generate an algebraic sum of a signal from the slope compensator and the error signal to the inner loop circuit.

[0187] In a fourth implementation form of the power converter system according to the third aspect itself or any previous implementation form of the third aspect, the load is a vertical cavity surface emitting laser (VCSEL).

[0188] In a fifth implementation form of the power converter system according to the third aspect itself or any previous implementation form of the third aspect, the power converter system is configured to provide a regulated current to operate a vertical cavity surface emitting laser (VCSEL).

[0189] Although this description has been described in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. In the various figures, like elements are designated by like reference numerals. Moreover, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, because those of ordinary skill in the art will readily understand from the present disclosure that processes, machines, manufactures, compositions of matter, components, methods, or steps that exist now or will be developed later can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, components, methods, or steps within their scope.

[0190] Therefore, the specification and the drawings are simply regarded as illustrations of the present disclosure defined by the appended claims, and are contemplated to cover any and all modifications, variations, combinations, or equivalents falling within the scope of the present disclosure.

Claims

1. A feedback circuit for a power converter system, the feedback circuit comprising: An outer loop circuit, comprising: A current estimator configured to generate a first voltage based on a difference between an output current of the power converter system and an average current at an inductor of the power converter system; and A feedback controller configured to generate an error signal as a difference between the first voltage and a desired setpoint voltage; and An inner loop circuit configured to generate a pulse width modulation (PWM) signal based on the error signal to operate a switching element of the power converter system.

2. The feedback circuit according to claim 1, wherein the power converter system is configured to supply a regulated current to a vertical cavity surface emitting laser (VCSEL) driver, and the VCSEL driver is configured to drive a VCSEL.

3. The feedback circuit according to claim 1, wherein the power converter system comprises: A variable sensing capacitor arranged in parallel with a load of the power converter system; And A sensing resistor having a first terminal coupled to the variable sensing capacitor, and a second terminal of the sensing resistor coupled to the load.

4. The feedback circuit according to claim 1, wherein the power converter system comprises a DC-DC power stage, the DC-DC power stage comprising a switching element, wherein the switching element comprises a high-side switch and a low-side switch, and a shared terminal of the high-side switch and the low-side switch is coupled to a first terminal of the inductor, and a second terminal of the inductor is coupled to a load of the power converter system.

5. The feedback circuit according to claim 1, further comprising a slope compensator and an adder, the adder being coupled between the outer loop circuit and the inner loop circuit, the adder being configured to generate an algebraic sum of a signal from the slope compensator and the error signal to the inner loop circuit.

6. The feedback circuit according to claim 1, wherein a load of the power converter system is a vertical cavity surface emitting laser (VCSEL).

7. The feedback circuit according to claim 1, wherein the power converter system is configured to provide a regulated current to operate a vertical cavity surface emitting laser (VCSEL).

8. A feedback circuit for a power converter system, the feedback circuit comprising: An outer loop circuit, comprising: A current estimator configured to generate a first voltage based on a difference between an output current of the power converter system and a desired setpoint voltage, and A feedback controller configured to generate an error signal as a difference between the first voltage and an average current at an inductor of the power converter system; and an inner loop circuit configured to generate a pulse width modulation (PWM) signal based on the error signal to operate a switching element of the power converter system.

9. The feedback circuit according to claim 8, wherein the power converter system is configured to supply a regulated current to a vertical cavity surface emitting laser (VCSEL) driver, and the VCSEL driver is configured to drive a VCSEL.

10. The feedback circuit according to claim 8, wherein the power converter system comprises: A variable sensing capacitor arranged in parallel with the load of the power converter system; And A sensing resistor having a first terminal coupled to the variable sensing capacitor and a second terminal of the sensing resistor coupled to the load.

11. The feedback circuit according to claim 8, wherein the power converter system comprises a DC-DC power stage, the DC-DC power stage comprising switching elements, wherein the switching elements comprise a high-side switch and a low-side switch, wherein a shared terminal of the high-side switch and the low-side switch is coupled to a first terminal of the inductor, and wherein a second terminal of the inductor is coupled to the load of the power converter system.

12. The feedback circuit according to claim 8, further comprising a slope compensator and an adder, the adder being coupled between the outer loop circuit and the inner loop circuit, the adder being configured to generate an algebraic sum of a signal from the slope compensator and the error signal to the inner loop circuit.

13. The feedback circuit according to claim 8, wherein the load of the power converter system is a vertical cavity surface emitting laser (VCSEL).

14. The feedback circuit according to claim 8, wherein the power converter system is configured to provide a regulated current to operate a vertical cavity surface emitting laser (VCSEL).

15. A power converter system, comprising: A DC-DC power stage comprising switching elements and an inductor, wherein the switching elements comprise a high-side switch and a low-side switch, wherein a shared terminal of the high-side switch and the low-side switch is coupled to a first terminal of the inductor, and wherein a second terminal of the inductor is coupled to the load of the power converter system; A feedback circuit configured to regulate the output current of the DC-DC power stage for the load, the feedback circuit comprising: An outer loop circuit comprising: A current estimator configured to generate a first voltage based on a difference between the output current and an average current at the inductor or based on a difference between the output and a desired setpoint voltage, and A feedback controller configured to generate an error signal as a difference between the first voltage and the desired setpoint voltage or a difference between the first voltage and the average current at the inductor; and An inner loop circuit configured to generate a pulse width modulation (PWM) signal based on the error signal to operate the switching elements of the power converter system.

16. The power converter system according to claim 15, wherein the power converter system is configured to provide a regulated current to a vertical cavity surface emitting laser (VCSEL) driver, the VCSEL driver being configured to drive a VCSEL.

17. The power converter system according to claim 15, the power converter system comprising: A variable sensing capacitor arranged in parallel with the load; And A sensing resistor having a first terminal coupled to the variable sensing capacitor and a second terminal of the sensing resistor coupled to the load.

18. The power converter system according to claim 15, wherein the feedback circuit further includes a slope compensator and an adder, the adder being coupled between the outer loop circuit and the inner loop circuit, the adder being configured to generate an algebraic sum of a signal from the slope compensator and the error signal to the inner loop circuit.

19. The power converter system according to claim 15, wherein the load is a vertical cavity surface emitting laser (VCSEL).

20. The power converter system according to claim 15, wherein the power converter system is configured to provide a regulated current to operate a vertical cavity surface emitting laser (VCSEL).

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