Control circuit and power supply chip of constant on-time voltage converter

Abstract

The embodiment of the invention provides a control circuit of a constant on-time voltage converter and a power supply chip. The control circuit comprises a state detection module and a voltage regulation module, the state detection module determines the soft start process according to a soft start enable signal and a soft start voltage signal, and the voltage regulation module determines the soft start process according to the output sampling voltage of the constant on-time voltage converter and a first preset voltage in the soft start process. According to the invention, the sampling voltage of the switch node is adjusted, so that the output sampling voltage is stabilized in the preset voltage range, the common-mode bias voltage can be adaptively adjusted in the wide output voltage range, so that the common-mode bias voltage is kept in a certain voltage range, and the constant-on-time voltage converter can support the wide output voltage range. Besides, after the soft start is finished, the voltage regulation module stops working, and the quiescent current of normal working of the constant-on-time voltage converter is not influenced, so that unnecessary power consumption is avoided.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technologies, and in particular, to a control circuit for a constant on-time voltage converter and a power supply chip. Background Art

[0002] With the technological development of electronic products, their power supply systems can generally be configured to provide multiple different voltage outputs to support DC-DC voltage converters with a wide output range, so as to meet the power supply requirements of complex electronic systems. For example, on the main boards of computers or high-definition TVs, DC-DC voltage converters with a wide output range can supply power to different subsequent circuits to ensure the normal operation of each component of the system. At the same time, DC-DC voltage converters with a wide output range can reduce the types of power supply chips used to provide different output voltages, thereby simplifying system design and reducing overall costs, which is also a significant advantage for systems that require multi-voltage rail power supply.

[0003] In the prior art, due to the advantages of a simple peripheral circuit structure and fast transient response, the constant on-time architecture has been increasingly applied in DC-DC voltage converters. However, the constant on-time voltage converter is limited by the common-mode bias voltage of the internal circuit, resulting in difficulty in supporting a wide output voltage range. Summary of the Invention

[0004] The present disclosure provides a control circuit for a constant on-time voltage converter and a power supply chip, enabling the constant on-time voltage converter to support a wide output voltage range and avoid unnecessary power consumption.

[0005] In a first aspect, the present disclosure provides a control circuit for a constant on-time voltage converter. The constant on-time voltage converter includes an upper transistor and a lower transistor, and the connection point between the upper transistor and the lower transistor is a switching node. The control circuit includes a state detection module, a voltage regulation module, and a constant on-time control module.

[0006] The state detection module is configured to determine a soft start process according to a soft start enable signal and a soft start voltage signal. The voltage regulation module is configured to, during the soft start process, regulate a switch node sampling voltage according to an output sampling voltage of the constant on-time voltage converter and a first preset voltage, so that the output sampling voltage is stabilized within a preset voltage range; and stop working after the soft start ends. The constant on-time control module is configured to determine a ripple injection signal according to the output sampling voltage, determine a constant on-time signal according to the output sampling voltage and an input voltage of the constant on-time voltage converter, and control the turning on and off of the upper transistor and the lower transistor according to the ripple injection signal and the constant on-time signal, so as to stabilize the switching frequencies of the upper transistor and the lower transistor.

[0007] In some embodiments of the present disclosure, the voltage regulation module includes a voltage control unit and a voltage regulation unit. A first input terminal of the voltage control unit is connected to a second sampling node of the constant on-time control module. A second input terminal of the voltage control unit is connected to the first preset voltage. A third input terminal of the voltage control unit is connected to a lower transistor control signal. A fourth input terminal of the voltage control unit is connected to an output terminal of the state detection module. A fifth input terminal of the voltage control unit is connected to the soft start enable signal. An output terminal of the voltage control unit is connected to a control terminal of the voltage regulation unit. A first terminal of the voltage regulation unit is connected to a first sampling node of the constant on-time control module. A second terminal of the voltage regulation unit is connected to ground.

[0008] The voltage control unit is configured to, when the lower transistor is turned on during the soft start process and when the output sampling voltage is greater than the first preset voltage, connect the voltage regulation unit to the constant on-time control module; and after the soft start ends, control the voltage regulation unit to maintain the state at the end of the soft start. The voltage regulation unit is configured to, when connected to the constant on-time control module, reduce the switch node sampling voltage so as to reduce the output sampling voltage.

[0009] In some embodiments of the present disclosure, the voltage control unit includes a voltage comparator, an AND gate, and an S-R latch. The positive input terminal of the voltage comparator is connected to the second sampling node, the negative input terminal of the voltage comparator is connected to the first preset voltage, the output terminal of the voltage comparator is connected to the first input terminal of the AND gate, the second input terminal of the AND gate is connected to the lower transistor control signal, the third input terminal of the AND gate and the enable terminal of the voltage comparator are connected to the output terminal of the state detection module, the output terminal of the AND gate is connected to the input terminal of the S-R latch, the reset terminal of the S-R latch is connected to the soft start enable signal, and the output terminal of the S-R latch is connected to the control terminal of the voltage regulation unit.

[0010] In some embodiments of the present disclosure, the voltage regulation unit includes a first switch and a first regulating resistor. The control terminal of the first switch is connected to the output terminal of the voltage control unit, the first terminal of the first switch is connected to the first terminal of the first regulating resistor, the second terminal of the first switch is grounded, and the second terminal of the first regulating resistor is connected to the first sampling node.

[0011] In some embodiments of the present disclosure, the voltage regulation module further includes a discharging unit. The control terminal of the discharging unit is connected to the output terminal of the voltage control unit, the first terminal of the discharging unit is connected to the second sampling node, and the second terminal of the discharging unit is grounded.

[0012] The discharging unit is configured to release the charge on the second sampling node within a preset duration to reduce the output sampling voltage when the output sampling voltage is greater than the first preset voltage and the lower transistor is turned on during the soft start process. The preset duration is less than the minimum turn-off duration of the constant on-time voltage converter.

[0013] In some embodiments of the present disclosure, the discharging unit includes a pulse generator, a second switch, and a voltage dividing component. The input terminal of the pulse generator is connected to the output terminal of the voltage control unit, the output terminal of the pulse generator is connected to the control terminal of the second switch, the first terminal of the second switch and the input terminal of the voltage dividing component are connected to the second sampling node, and the second terminal of the second switch is connected to the output terminal of the voltage dividing component.

[0014] In some embodiments of the present disclosure, the voltage dividing component includes an operational amplifier, a second adjusting resistor, and a third adjusting resistor. The non-inverting input terminal of the operational amplifier is connected to the first terminal of the second switch and the second sampling node. The inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier and the first terminal of the second adjusting resistor. The second terminal of the second adjusting resistor is connected to the first terminal of the third adjusting resistor and the second terminal of the second switch. The second terminal of the third adjusting resistor is grounded. The enable terminal of the operational amplifier is connected to the output terminal of the state detection module.

[0015] In some embodiments of the present disclosure, the state detection module includes a state comparator and a logic unit. The non-inverting input terminal of the state comparator is connected to the soft start voltage signal. The inverting input terminal of the state comparator is connected to a second preset voltage. The output terminal of the state comparator is connected to the first input terminal of the logic unit. The second input terminal of the logic unit is connected to the soft start enable signal. The output terminal of the logic unit is connected to the enable terminal of the voltage regulation module and the enable terminal of the state comparator.

[0016] The logic unit is configured to generate an enable signal when the soft start voltage signal is less than the second preset voltage, and generate a non-enable signal when the soft start voltage signal is greater than or equal to the second preset voltage.

[0017] In some embodiments of the present disclosure, the logic unit includes an inverter and a NOR gate. The first input terminal of the NOR gate is connected to the output terminal of the state comparator. The soft start enable signal is connected to the second input terminal of the NOR gate through the inverter. The output terminal of the NOR gate is connected to the enable terminal of the voltage regulation module and the enable terminal of the state comparator.

[0018] In a second aspect, the present disclosure provides a power chip, including any one of the control circuits provided in the first aspect.

[0019] The technical solution of the present disclosure provides a control circuit for a constant-on-time voltage converter, including a state detection module, a voltage regulation module, and a constant-on-time control module. The state detection module determines the soft-start process according to the soft-start enable signal and the soft-start voltage signal. During the soft-start process, the voltage regulation module adjusts the switch-node sampling voltage according to the output sampling voltage of the constant-on-time voltage converter and a first preset voltage, so that the output sampling voltage is stabilized within a preset voltage range, and stops working after the soft-start ends. The constant-on-time control module determines the ripple injection signal according to the output sampling voltage, determines the constant-on-time signal according to the output sampling voltage and the input voltage of the constant-on-time voltage converter, and controls the turning on and off of the upper transistor and the lower transistor according to the ripple injection signal and the constant-on-time signal, so as to stabilize the switching frequency of the upper transistor and the lower transistor. It can adaptively adjust the common-mode bias voltage of the internal circuit within a wide output voltage range, so that the common-mode bias voltage can be maintained within a relatively small and narrow voltage range to ensure the normal operation of the internal circuit. Therefore, the constant-on-time voltage converter can support a wide output voltage range. In addition, after the soft-start of the constant-on-time voltage converter ends, the voltage regulation module stops working, which does not affect the static current of the normal operation of the constant-on-time voltage converter, thus avoiding unnecessary power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0021] Figure 1 FIG. is a circuit schematic diagram of a constant-on-time voltage converter provided by an embodiment of the present disclosure.

[0022] Figure 2 FIG. is a circuit schematic diagram of a ripple injection unit provided by an embodiment of the present disclosure.

[0023] Figure 3 FIG. is a circuit schematic diagram of a loop comparator provided by an embodiment of the present disclosure.

[0024] Figure 4 FIG. is a circuit schematic diagram of a constant-on-time generator provided by an embodiment of the present disclosure.

[0025] Figure 5 FIG. is a structural schematic diagram of a control circuit provided by an embodiment of the present disclosure.

[0026] Figure 6 FIG. is a circuit schematic diagram of a control circuit provided by an embodiment of the present disclosure.

[0027] Figure 7(a) and Figure 7 (b) is the timing diagram of the control circuit provided by the embodiment of the present disclosure.

[0028] Figure 8 (a) and Figure 8 (b) are the simulation diagrams of each signal in the control circuit at different output voltages provided by the embodiment of the present disclosure.

[0029] Figure 9 is the circuit schematic diagram of another control circuit provided by the embodiment of the present disclosure. Detailed implementation manners

[0030] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art without creative efforts based on the described embodiments of the present disclosure also fall within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. Further, it will be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless explicitly defined herein. As used herein, the statement of joining two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0032] Reference to "embodiment" in the present disclosure means that a particular feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The phrase "embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described in the present disclosure may be combined with other embodiments.

[0033] In addition, terms such as "first", "second", etc. in the specification and claims of the present disclosure or in the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order, and may explicitly or implicitly include one or more of such features.

[0034] The term "and / or" in this disclosure is merely a description of the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: the existence of A, the simultaneous existence of A and B, and the existence of B. Additionally, in this text, the character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0035] In the description of this disclosure, unless otherwise specified, the meanings of "multiple" and "at least two" refer to more than two (including two). Similarly, "multiple groups" and "at least two groups" refer to more than two groups (including two groups).

[0036] To enable those skilled in the art of this technology to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings.

[0037] Figure 1 A circuit schematic diagram of a constant on-time voltage converter provided for an embodiment of this disclosure, as Figure 1 shown, the constant on-time voltage converter 10 is a Buck converter, including a control circuit 100, an upper transistor HS, a lower transistor LS, an inductor L, an output capacitor Cout, a load Iout, a first feedback resistor Rf1, and a second feedback resistor Rf2.

[0038] The upper transistor HS and the lower transistor LS are connected in series between the power supply voltage and the ground. The connection point of the upper transistor HS and the lower transistor LS is the switch node SW. The voltage of the switch node SW is the switch node voltage Vsw. The switch node SW is connected to the voltage output terminal through the inductor L. The output capacitor Cout and the load Iout are connected in parallel between the voltage output terminal and the ground. The first feedback resistor Rf1 and the second feedback resistor Rf2 are connected in series between the voltage output terminal and the ground. The connection point of the first feedback resistor Rf1 and the second feedback resistor Rf2 is the feedback node FB. The voltage of the feedback node FB is the feedback voltage Vfb.

[0039] The control circuit 100 includes a constant on-time control module 110. The first output terminal of the constant on-time control module 110 is connected to the control terminal of the upper transistor HS. The second output terminal of the constant on-time control module 110 is connected to the control terminal of the lower transistor LS. The first input terminal of the constant on-time control module 110 is connected to the switch node SW to receive the switch node voltage Vsw. The second input terminal of the constant on-time control module 110 receives the soft start voltage signal Vss. The third input terminal of the constant on-time control module 110 receives the reference voltage Vref. The fourth input terminal of the constant on-time control module 110 is connected to the feedback node FB to receive the feedback voltage Vfb.

[0040] Exemplarily, as Figure 1As shown, the constant on-time control module 110 includes a first sampling resistor Rs1 and a second sampling resistor Rs2. The first sampling resistor Rs1 and the second sampling resistor Rs2 are connected in series between the switch node SW and the ground. The second sampling resistor Rs2 is grounded, and the connection point of the first sampling resistor Rs1 and the second sampling resistor Rs2 is the first sampling node. The first sampling resistor Rs1 and the second sampling resistor Rs2 can divide the voltage of the switch node Vsw. The voltage across the second sampling resistor Rs2 is the voltage of the first sampling node, that is, the switch node sampling voltage Vsw_sen.

[0041] The constant on-time control module 110 further includes a filtering resistor R and a filtering capacitor C. The first sampling node is grounded through the filtering resistor R and the filtering capacitor C in sequence. The connection point of the filtering resistor R and the filtering capacitor C is the second sampling node. The filtering resistor R and the filtering capacitor C form a low-pass filter. After low-pass filtering the switch node sampling voltage Vsw_sen, the average voltage of the switch node sampling voltage Vsw_sen is obtained. Since the average voltage of the switch node voltage Vsw is approximately equal to the output voltage Vout, the average voltage of the switch node sampling voltage Vsw_sen can be understood as the sampling voltage of the output voltage Vout. Then the voltage of the second sampling node is the output sampling voltage Vout_sen.

[0042] The constant on-time control module 110 further includes a minimum voltage output unit Min. The first input terminal of the minimum voltage output unit Min receives the soft start voltage signal Vss, and the second input terminal of the minimum voltage output unit Min receives the reference voltage Vref. The minimum voltage output unit Min can output the smaller voltage of the soft start voltage signal Vss and the reference voltage Vref. For example, when the soft start voltage signal Vss is greater than the reference voltage Vref, the reference voltage Vref is output. When the soft start voltage signal Vss is less than the reference voltage Vref, the soft start voltage signal Vss is output.

[0043] The constant on-time control module 110 further includes a ripple injection unit 112. The input terminal of the ripple injection unit 112 is connected to the second sampling node to receive the output sampling voltage Vout_sen, and the output sampling voltage Vout_sen is a square wave signal with a certain duty cycle.

[0044] Exemplarily, Figure 2 is a circuit schematic diagram of a ripple injection unit provided by an embodiment of the present disclosure. As Figure 2As shown, the ripple injection unit 112 includes a first resistor R1, a second resistor R2, a third resistor R3, and a first capacitor C1. The first resistor R1 and the second resistor R2 are serially connected between the input terminal of the ripple injection unit 112 and the ground. The connection point of the first resistor R1 and the second resistor R2 is connected to the output terminal of the ripple injection unit 112 through the third resistor R3. The first capacitor is connected between the output terminal of the ripple injection unit 112 and the ground.

[0045] The first resistor R1, the second resistor R2, the third resistor R3, and the first capacitor C1 form an integrating circuit. The integrating circuit can convert a square wave signal into a triangular wave signal. Therefore, the ripple injection unit 112 can convert the output sampling voltage Vout_sen into a corresponding triangular wave signal, that is, the ripple injection signal.

[0046] The constant on-time control module 110 further includes a loop comparator CMP_L. The first non-inverting input terminal of the loop comparator CMP_L is connected to the first output terminal of the ripple injection unit 112 to receive the ripple injection non-inverting signal. The first inverting input terminal of the loop comparator CMP_L is connected to the second output terminal of the ripple injection unit 112 to receive the ripple injection inverting signal. The second non-inverting input terminal of the loop comparator CMP_L is connected to the output terminal of the minimum voltage output unit Min to receive the smaller voltage of the output soft-start voltage signal Vss and the reference voltage Vref. The second inverting input terminal of the loop comparator CMP_L is connected to the feedback node FB to receive the feedback voltage Vfb.

[0047] Exemplarily, Figure 3 is a circuit schematic diagram of a loop comparator provided by an embodiment of the present disclosure. As Figure 3 shown, the loop comparator CMP_L includes a first non-inverting input transistor INP1, a first inverting input transistor INN1, a second non-inverting input transistor INP2, a second inverting input transistor INN2, a first current source IB1, a second current source IB2, a fourth resistor R4, a fifth resistor R5, a comparator COMP, and an inverter. Among them, the gains of the first non-inverting input transistor INP1 and the first inverting input transistor INN1 are the first gain Gm1, the gains of the second non-inverting input transistor INP2 and the second inverting input transistor INN2 are the second gain Gm2, and the resistance values of the fourth resistor R4 and the fifth resistor R5 are r.

[0048] The source of the first non-inverting input transistor INP1 and the source of the first inverting input transistor INN1 are connected to the power supply voltage VDD through a first current source IB1. The source of the second non-inverting input transistor INP2 and the source of the second inverting input transistor INN2 are connected to the power supply voltage VDD through a second current source IB2. The gate of the first non-inverting input transistor INP1 receives a ripple injection non-inverting signal, and the gate of the first inverting input transistor INN1 receives a ripple injection inverting signal. The gate of the second non-inverting input transistor INP2 receives the smaller voltage of the output soft-start voltage signal Vss and the reference voltage Vref, and the gate of the second inverting input transistor INN2 receives the feedback voltage Vfb.

[0049] The drain of the first non-inverting input transistor INP1 and the drain of the second non-inverting input transistor INP2 are connected to the non-inverting input terminal of the comparator COMP. The non-inverting input terminal of the comparator COMP is grounded through a fifth resistor R5. The drain of the first inverting input transistor INN1 and the drain of the second inverting input transistor INN2 are connected to the inverting input terminal of the comparator COMP. The inverting input terminal of the comparator COMP is grounded through a fourth resistor R4. The output terminal of the comparator COMP is connected to the output terminal of the loop comparator CMP_L through an inverter.

[0050] The first non-inverting input transistor INP1 amplifies the ripple injection non-inverting signal at a first ratio Gm1*r. The second non-inverting input transistor INP2 amplifies the smaller voltage of the output soft-start voltage signal Vss and the reference voltage Vref at a second ratio Gm2*r, and sums the two amplified signals to obtain the non-inverting input signal of the comparator COMP. The first inverting input transistor INN1 amplifies the ripple injection inverting signal at a first ratio Gm1*r. The second inverting input transistor INN2 amplifies the feedback voltage Vfb at a second ratio Gm2*r, and sums the two amplified signals to obtain the inverting input signal of the comparator COMP. The comparator COMP compares the non-inverting input signal and the inverting input signal of the comparator COMP, and the inverter inverts the output signal of the comparator COMP to obtain a comparison signal.

[0051] The constant on-time control module 110 further includes a constant on-time generator 111, and the input terminal of the constant on-time generator 111 is connected to the input voltage Vin. Exemplarily, Figure 4 is a circuit schematic diagram of a constant on-time generator provided by an embodiment of the present disclosure. As Figure 4 shown, the constant on-time generator 111 includes an error amplifier EA, a first transistor M1, a second transistor M2, a third transistor M3, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, and a control switch K.

[0052] The sixth resistor R6 and the seventh resistor R7 are connected in series between the input voltage Vin and the ground. The connection point of the sixth resistor R6 and the seventh resistor R7 is connected to the positive input terminal of the error amplifier EA. The negative input terminal of the error amplifier EA is connected to the first terminal of the eighth resistor R8 and the source of the third transistor M3. The output terminal of the error amplifier EA is connected to the gate of the third transistor M3. The drain of the third transistor M3 is connected to the gate of the first transistor M1, the drain of the first transistor M1, and the gate of the second transistor M2. The sources of the first transistor M1 and the second transistor M2 are connected to the power supply voltage VDD. The drain of the second transistor M2 is the output terminal of the constant on-time generator 111. The control switch K and the second capacitor C2 are connected in parallel between the output terminal of the constant on-time generator 111 and the ground.

[0053] The constant on-time generator 111 generates a charging current according to the input voltage Vin, and the charging current is proportional to the input voltage Vin. The second capacitor C2 is charged based on the charging current. The voltage across the second capacitor C2 is proportional to the charging current. The output of the constant on-time generator 111 is the voltage across the second capacitor C2.

[0054] The constant on-time control module 110 further includes a time comparator CMP_T. The positive input terminal of the time comparator CMP_T is connected to the output terminal of the constant on-time generator 111 to receive the voltage across the second capacitor C2. The negative input terminal of the time comparator CMP_T is connected to the second sampling node to receive the output sampling voltage Vout_sen. The time comparator CMP_T can compare the output sampling voltage Vout_sen and the voltage across the second capacitor C2 to obtain a constant on-time signal TON.

[0055] For example, when the voltage across the second capacitor C2 is greater than the output sampling voltage Vout_sen, the constant on-time signal TON is at a high level. When the voltage across the second capacitor C2 is less than or equal to the output sampling voltage Vout_sen, the constant on-time signal TON is at a low level.

[0056] The constant on-time control module 110 further includes an R-S latch Latch1, a NOT gate NOT, and a driving unit 113. The input terminal S of the R-S latch Latch1 is connected to the output terminal of the loop comparator CMP_L. The reset terminal R of the R-S latch Latch1 is connected to the output terminal of the time comparator CMP_T. The output terminal of the R-S latch Latch1 is connected to the first input terminal of the driving unit 113 and the input terminal of the NOT gate NOT. The output terminal of the NOT gate NOT is connected to the second input terminal of the driving unit 113. The first output terminal of the driving unit 113 is connected to the control terminal of the high-side switch HS. The second output terminal of the driving unit 113 is connected to the control terminal of the low-side switch LS.

[0057] The R-S latch Latch1 can generate a stable-frequency upper-switch control signal PWM according to a comparison signal and a constant on-time signal TON. The NOT gate can invert the upper-switch control signal PWM to obtain a lower-switch control signal PWMz. For example, when the comparison signal is at a high level, the upper-switch control signal PWM is at a high level, that is, an upper-switch turn-on signal is generated, and correspondingly, the lower-switch control signal PWMz is at a low level, that is, a lower-switch turn-off signal is generated. When the constant on-time signal TON is at a high level, the upper-switch control signal PWM is at a low level, that is, an upper-switch turn-off signal is generated, and correspondingly, the lower-switch control signal PWMz is at a high level, that is, a lower-switch turn-on signal is generated.

[0058] The driving unit 113 drives the upper switch HS to turn on or off according to the upper-switch control signal PWM. For example, the driving unit 113 drives the upper switch HS to turn on according to the upper-switch turn-on signal and drives the upper switch HS to turn off according to the upper-switch turn-off signal. The driving unit 113 drives the lower switch LS to turn on and off according to the lower-switch control signal PWMz. For example, the driving unit 113 drives the lower switch LS to turn on according to the lower-switch turn-on signal and drives the lower switch LS to turn off according to the lower-switch turn-off signal.

[0059] In this way, the constant on-time control module 110 determines a ripple injection signal according to the output sampled voltage Vout_sen, determines the constant on-time signal TON according to the output sampled voltage Vout_sen and the input voltage Vin of the constant on-time voltage converter, and controls the turning on and off of the upper switch HS and the lower switch LS according to the ripple injection signal and the constant on-time signal TON to stabilize the switching frequencies of the upper switch HS and the lower switch LS.

[0060] It should be noted that in the embodiments of the present disclosure, only the Buck converter is taken as an example to exemplarily illustrate the constant on-time voltage converter 10. In practical applications, the constant on-time voltage converter 10 can also be a DC-DC voltage converter such as a Boost converter or a Buck-Boost converter.

[0061] The common-mode bias voltages of the internal circuits of the constant on-time control module 110 are all related to the output voltage Vout. For example, the loop comparator CMP_L and the time comparator CMP_T. And the common-mode bias voltages of the internal circuits are usually set within a certain voltage range to prevent noise interference from affecting the circuit function while ensuring normal operation at a chip power supply voltage of 5V or even 3.3V, resulting in the constant on-time voltage converter not supporting a wide output voltage range.

[0062] To solve the above technical problems, the control circuit provided by the present disclosure further includes a state detection module and a voltage regulation module. The state detection module determines the soft start process according to the soft start enable signal and the soft start voltage signal. During the soft start process, the voltage regulation module adjusts the switch node sampling voltage according to the output sampling voltage of the constant on-time voltage converter and the first preset voltage, so that the output sampling voltage is stabilized within the preset voltage range. After the soft start is completed, the voltage regulation module stops working, and can adaptively adjust the common-mode bias voltage of the internal circuit within a wide output voltage range, so that the common-mode bias voltage can be maintained within a relatively small and narrow voltage range to ensure the normal operation of the internal circuit. Therefore, the constant on-time voltage converter can support a wide output voltage range. In addition, after the soft start of the constant on-time voltage converter is completed, the voltage regulation module stops working, which does not affect the static current of the normal operation of the constant on-time voltage converter, thereby avoiding unnecessary power consumption.

[0063] The following describes in detail the technical solutions provided by the present disclosure with several specific embodiments.

[0064] Figure 5 A schematic structural diagram of a control circuit provided by an embodiment of the present disclosure is shown in Figure 5 As shown, the control circuit 100 includes a constant on-time control module 110, a state detection module 120, and a voltage regulation module 130. Among them, the first input terminal of the state detection module 120 receives the soft start voltage signal Vss, and the second input terminal of the state detection module 120 receives the soft start enable signal SS_EN.

[0065] The enable terminal of the voltage regulation module 130 and the first input terminal of the voltage regulation module 130 are connected to the output terminal of the state detection module 120. The second input terminal of the voltage regulation module 130 is connected to the second sampling node to receive the output sampling voltage Vout_sen. The third input terminal of the voltage regulation module 130 receives the first preset voltage Vpre1. The fourth input terminal of the voltage regulation module 130 receives the lower transistor control signal PWMz. The fifth input terminal of the voltage regulation module 130 receives the soft start enable signal SS_EN. The output terminal of the voltage regulation module 130 is connected to the first sampling node.

[0066] The state detection module 120 is configured to determine the soft start process according to the soft start enable signal SS_EN and the soft start voltage signal Vss. The voltage regulation module 130 is configured to adjust the switch node sampling voltage Vsw_sen according to the output sampling voltage Vout_sen and the first preset voltage Vpre1 during the soft start process, so that the output sampling voltage Vout_sen is stabilized within the preset voltage range; after the soft start is completed, the voltage regulation module stops working.

[0067] Exemplarily,Figure 6 The circuit schematic diagram of a control circuit provided by an embodiment of the present disclosure is shown as Figure 6 in the figure. The state detection module 120 includes a state comparator CMP_SS and a logic unit 121. The positive input terminal of the state comparator CMP_SS is connected to the soft start voltage signal Vss, the negative input terminal of the state comparator CMP_SS is connected to the second preset voltage Vpre2, the output terminal of the state comparator CMP_SS is connected to the first input terminal of the logic unit 121, the second input terminal of the logic unit 121 is connected to the soft start enable signal SS_EN, and the output terminal of the logic unit 121 is connected to the enable terminal of the voltage regulation module 130 and the enable terminal of the state comparator CMP_SS.

[0068] The state comparator CMP_SS can compare the soft start voltage signal Vss and the second preset voltage Vpre2 to obtain a first comparison signal SS_END. Specifically, when the soft start voltage signal Vss is less than the second preset voltage Vpre2, the first comparison signal SS_END is at a low level, and when the soft start voltage signal Vss is greater than or equal to the second preset voltage Vpre2, the first comparison signal SS_END is at a high level, as Figure 7 shown in the figure. Figure 7 (a) and Figure 7 (b) are the working timing diagrams of the control circuit provided by the embodiment of the present disclosure.

[0069] Continuing to refer to Figure 6 , the logic unit 221 includes an inverter INV and a NOR gate NOR. The first input terminal of the NOR gate NOR is connected to the output terminal of the state comparator CMP_SS, and the soft start enable signal SS_EN is connected to the second input terminal of the NOR gate NOR through the inverter INV. The output terminal of the NOR gate NOR is connected to the enable terminal of the voltage regulation module 130 and the enable terminal of the state comparator CMP_SS.

[0070] The inverter INV performs an inversion process on the soft start enable signal SS_EN, and the NOR gate NOR performs a NOR operation on the inverted signal of the soft start enable signal SS_EN and the first comparison signal SS_END to obtain a soft start process indication signal EN_DET of the constant on-time voltage converter. The voltage regulation module 130 and the state comparator CMP_SS can be enabled or disabled according to the soft start process indication signal EN_DET.

[0071] Specifically, when the first comparison signal SS_END is at a low level and the soft-start enable signal SS_EN is at a high level, the constant-on-time voltage converter is in soft start, the soft-start process indication signal EN_DET is at a high level, that is, an enable signal is generated, and then the voltage regulation module 130 is enabled. When the first comparison signal SS_END and the soft-start enable signal SS_EN are at a high level, the soft start of the constant-on-time voltage converter is completed, the soft-start process indication signal EN_DET is at a low level, that is, a non-enable signal is generated, and then the voltage regulation module 130 and the state comparator CMP_SS are disabled.

[0072] In this way, during the soft start of the constant-on-time voltage converter, the voltage regulation module 130 works normally. After the soft start of the constant-on-time voltage converter ends, the voltage regulation module 130 and the state comparator CMP_SS stop working, without affecting the static current of the normal operation of the constant-on-time voltage converter, thus avoiding unnecessary power consumption.

[0073] Continue to refer to Figure 6 , the voltage regulation module 130 includes a voltage control unit 131 and a voltage regulation unit 132. Among them, the first input terminal of the voltage control unit 131 is connected to the second sampling node of the constant-on-time control module 110, the second input terminal of the voltage control unit 131 is connected to the first preset voltage Vpre1, the third input terminal of the voltage control unit 131 is connected to the lower transistor control signal PWMz, the fourth input terminal of the voltage control unit 131 is connected to the output terminal of the state detection module 120, and the fifth input terminal of the voltage control unit 131 is connected to the soft-start enable signal SS_EN.

[0074] The output terminal of the voltage control unit 131 is connected to the control terminal of the voltage regulation unit 132. The first terminal of the voltage regulation unit 132 is connected to the first sampling node of the constant-on-time control module 110, and the second terminal of the voltage regulation unit 132 is connected to the ground.

[0075] Exemplarily, as Figure 6 shown, the voltage control unit 131 includes a voltage comparator CMP, an AND gate AND, and an S-R latch Latch2. The non-inverting input terminal of the voltage comparator CMP is connected to the second sampling node, the inverting input terminal of the voltage comparator CMP is connected to the first preset voltage Vpre1, and the output terminal of the voltage comparator CMP is connected to the first input terminal of the AND gate AND.

[0076] The second input terminal of the AND gate AND is connected to the lower transistor control signal PWMz. The third input terminal of the AND gate AND and the enable terminal of the voltage comparator CMP are connected to the output terminal of the status detection module 120. The output terminal of the AND gate AND is connected to the input terminal S of the S-R latch Latch2. The reset terminal R of the S-R latch Latch2 is connected to the soft start enable signal SS_EN. The output terminal of the S-R latch Latch2 is connected to the control terminal of the voltage regulation unit 132.

[0077] As Figure 7 shown, during the soft start process of the constant on-time voltage converter, the output voltage Vout slowly rises to the preset output voltage value along with the slope of the soft start voltage signal Vss. If the preset output voltage value is low, during the soft start process, the output voltage Vout will not exceed the voltage threshold, and the corresponding output sampling voltage Vout_sen will not exceed the first preset voltage Vpre1. The second comparison signal Vout_H output by the voltage comparator CMP remains low level, as Figure 7 (a) shows.

[0078] At this time, the output signal of the AND gate AND remains low level, the soft start enable signal SS_EN is high level, and the first control signal Vdrv1 output by the S-R latch Latch2 maintains the state before the soft start, that is, the first control signal Vdrv1 remains low level, as Figure 7 (a) shows.

[0079] As the soft start process continues, the soft start voltage signal Vss gradually increases. When the soft start voltage signal Vss increases to be greater than the second preset voltage Vpre2, the soft start process indication signal EN_DET flips from high level to low level, and the soft start ends. After the soft start ends, the output signal of the AND gate AND maintains the state at the end of the soft start, that is, the output signal of the AND gate AND remains low level, then the locked first control signal Vdrv1 remains low level, as Figure 7 (a) shows.

[0080] If the preset output voltage value is high, during the soft start process, as the output voltage Vout increases, the output voltage Vout will exceed the voltage threshold, and the corresponding output sampling voltage Vout_sen will exceed the first preset voltage Vpre1. And when the output sampling voltage Vout_sen increases to be greater than the first preset voltage Vpre1, the second comparison signal Vout_H output by the voltage comparator CMP flips from low level to high level, as Figure 7 (b) shows.

[0081] At this time, the soft start enable signal SS_EN is at a high level, and the soft start process indication signal EN_DET is at a high level. When the lower transistor control signal PWMz is at a high level, that is, when the lower transistor LS is turned on, the output signal of the AND gate flips from a low level to a high level, and the first control signal Vdrv1 output by the S-R latch Latch2 flips from a low level to a high level, as shown in Figure 7 (b).

[0082] When the soft start voltage signal Vss rises to be greater than the second preset voltage Vpre2, the soft start process indication signal EN_DET flips from a high level to a low level, and the soft start ends. After the soft start ends, the output signal of the AND gate maintains the state at the end of the soft start, that is, the output signal of the AND gate remains at a high level, then the locked first control signal Vdrv1 remains at a high level, as shown in Figure 7 (b).

[0083] When the first control signal Vdrv1 is at a high level, the voltage regulation unit 132 is connected between the first sampling node of the constant on-time control module 110 and the ground. When the first control signal Vdrv1 is at a low level, the voltage regulation unit 132 is not connected between the first sampling node of the constant on-time control module 110 and the ground. In this way, when the lower transistor LS is turned on during the soft start process, when the output sampling voltage Vout_sen is greater than the first preset voltage Vpre1, the voltage control module 221 can connect the voltage regulation unit 132 to the constant on-time control module 110. After the soft start ends, the voltage control module 221 controls the voltage regulation unit 132 to maintain the state at the end of the soft start.

[0084] By controlling the voltage regulation unit 132 to maintain the state at the end of the soft start after the soft start ends, when there are changes in the output voltage Vout caused by load transient changes, under-voltage protection of the output voltage Vout, or over-voltage protection of the output voltage Vout after the circuit of the constant on-time voltage converter is stable, the constant on-time voltage converter can work normally, thereby ensuring the stability of the constant on-time voltage converter.

[0085] Continue to refer to Figure 6 , the voltage regulation unit 132 includes a first switch S1 and a first regulating resistor Rc1. The control end of the first switch S1 is connected to the output end of the voltage control unit 131. The first end of the first switch S1 is connected to the first end of the first regulating resistor Rc1. The second end of the first switch S1 is grounded. The second end of the first regulating resistor Rc1 is connected to the first sampling node.

[0086] Exemplarily, when the first control signal Vdrv1 is at a high level, the first switch S1 is turned on, and the first end of the first regulating resistor Rc1 is connected to the ground, which is equivalent to connecting the first regulating resistor Rc1 in parallel across the two ends of the second sampling resistor Rs2. Then, the switching node sampling voltage Vsw_sen can be reduced, thereby reducing the output sampling voltage Vout_sen. When the first control signal Vdrv1 is at a low level, the first switch S1 is turned off, and the first end of the first regulating resistor Rc1 is disconnected from the ground. At this time, it will not affect the switching node sampling voltage Vsw_sen, and thus will not affect the output sampling voltage Vout_sen.

[0087] In this way, when the voltage regulating unit 132 is connected to the constant on-time control module 110, the switching node sampling voltage Vsw_sen can be reduced to reduce the output sampling voltage Vout_sen.

[0088] Exemplarily, the common output voltages Vout of a constant on-time voltage converter with a 24V input voltage can be 1V, 3.3V, 5V, 12V, or 15V, etc. The internal supply voltage of the constant on-time voltage converter is 3.3V, the voltage threshold is 4V, and the first preset voltage Vpre1 is 1V. When the output voltage Vout is less than or equal to the voltage threshold, the sampling ratio is 1:4, that is, the output sampling voltage Vout_sen = Vout / 4. When the output voltage Vout is greater than the voltage threshold, the sampling ratio is 1:8, that is, the output sampling voltage Vout_sen = Vout / 8.

[0089] Figure 8 (a) and Figure 8 (b) are simulation diagrams of each signal in the control circuit for different output voltages provided by the embodiments of the present disclosure. As Figure 8 (a) shows, when the stabilized output voltage Vout of the constant on-time voltage converter is 1V, during the soft start process, the output voltage Vout must be less than 4V, the output sampling voltage Vout_sen must be less than 1V, the sampling ratio remains unchanged, and the output sampling voltage Vout_sen remains Vout / 4.

[0090] As Figure 8 (b) shows, when the stabilized output voltage Vout of the constant on-time voltage converter is 15V, during the soft start process, when the output voltage Vout is less than or equal to 4V, the output sampling voltage Vout_sen is less than or equal to 1V, the sampling ratio is 1:4, and the output sampling voltage Vout_sen = Vout / 4. When the output voltage Vout is greater than 4V, the output sampling voltage Vout_sen is greater than 1V, the sampling ratio is adjusted to 1:8, and the output sampling voltage Vout_sen is adjusted from Vout / 4 to Vout / 8.

[0091] For example, during the process in which the output voltage Vout rises from 0.6V to 15V, in the stage where the output voltage Vout rises from 0.6V to 4V, the output sampling voltage Vout_sen rises from 0.15V to 1V. In the stage where the output voltage Vout rises from 4V to 15V, the output sampling voltage Vout_sen drops from 1V to 0.5V and then rises from 0.5V to 1.875V.

[0092] In summary, when the output voltage Vout is relatively low, the output sampling voltage Vout_sen is not adjusted. When the output voltage Vout is relatively high, the output sampling voltage Vout_sen is reduced, so that the output sampling voltage Vout_sen is maintained within a relatively small and narrow voltage range. That is to say, within a wide output voltage range, the common-mode bias voltage of the internal circuit can be adaptively adjusted, so that the common-mode bias voltage can be maintained within a relatively small and narrow voltage range to ensure the normal operation of the internal circuit. Therefore, the constant-on-time voltage converter can support a wide output voltage range. In addition, after the soft start of the constant-on-time voltage converter ends, the voltage regulation module stops working, which does not affect the static current of the normal operation of the constant-on-time voltage converter, thus avoiding unnecessary power consumption.

[0093] In some embodiments, Figure 9 is a circuit schematic diagram of another control circuit provided by an embodiment of the present disclosure. As Figure 9 shown, the voltage regulation module 130 further includes a discharge unit 133. The control end of the discharge unit 133 is connected to the output end of the voltage control unit 131. The first end of the discharge unit 133 is connected to the second sampling node, and the second end of the discharge unit 133 is grounded.

[0094] The discharge unit 132 is configured to, when the lower transistor LS is turned on during the soft start process, and when the output sampling voltage Vout_sen is greater than the first preset voltage Vpre1, release the charge on the second sampling node within the preset duration Tpre to reduce the output sampling voltage Vout_sen. The preset duration Tpre is less than the minimum turn-off duration Tmin_off of the constant-on-time voltage converter.

[0095] Exemplarily, as Figure 9 shown, the discharge unit 132 includes a pulse generator one-shot, a second switch S2, and a voltage dividing component 1331. The input end of the pulse generator one-shot is connected to the output end of the voltage control unit 131. The output end of the pulse generator one-shot is connected to the control end of the second switch S2. The first end of the second switch S2 and the input end of the voltage dividing component 1331 are connected to the second sampling node, and the second end of the second switch S2 is connected to the output end of the voltage dividing component 1331.

[0096] When the first control signal Vdrv1 is at a low level, the second control signal Vdrv2 output by the pulse generator one-shot is at a low level. During the soft start process, when the lower transistor LS is turned on and the output sampling voltage Vout_sen is greater than the first preset voltage Vpre1, the first control signal Vdrv1 flips from a low level to a high level. The pulse generator one-shot pulls up the second control signal Vdrv2 and maintains it for a preset duration Tpre. For example, the preset duration Tpre is 100 ns to generate a pulse signal, as Figure 7 and Figure 8 shown.

[0097] At this time, under the action of the pulse signal, the second switch S2 conducts for a preset duration Tpre. During the preset duration Tpre when the second switch S2 conducts, the voltage dividing component 1331 is connected to the second sampling node and divides the output sampling voltage Vout_sen, which can quickly release the charge on the second sampling node, thereby quickly reducing the output sampling voltage Vout_sen, as Figure 7 and Figure 8 shown, which can improve the stability of the constant on-time voltage converter.

[0098] In addition, the preset duration Tpre is usually set to be less than the minimum off-time Tmin_off of the constant on-time voltage converter, which can ensure the rising slope of the output voltage Vout during the soft start process, thereby further improving the stability of the constant on-time voltage converter.

[0099] Continuing to refer to Figure 9 , the voltage dividing component 1331 includes an operational amplifier OP, a second adjustment resistor Rc2, and a third adjustment resistor Rc3. The positive input terminal of the operational amplifier OP is connected to the first end of the second switch S2 and the second sampling node. The negative input terminal of the operational amplifier OP is connected to the output terminal of the operational amplifier OP and the first end of the second adjustment resistor Rc2. The second end of the second adjustment resistor Rc2 is connected to the first end of the third adjustment resistor Rc3 and the second end of the second switch S2. The second end of the third adjustment resistor Rc3 is grounded. The enable terminal of the operational amplifier OP is connected to the output terminal of the status detection module 120.

[0100] The second adjustment resistor Rc2 and the third adjustment resistor Rc3 can divide the output sampling voltage Vout_sen. The voltage across the third adjustment resistor Rc3 is the target output sampling voltage Vout_sen_t. Obviously, the target output sampling voltage Vout_sen_t is less than the output sampling voltage Vout_sen. When the second switch S2 conducts, the output sampling voltage Vout_sen can be quickly reduced to the target output sampling voltage Vout_sen_t.

[0101] The present disclosure also provides a power chip, which includes the control circuit 100 provided in any of the above embodiments.

[0102] The power chip provided in the embodiments of the present disclosure includes the control circuit 100 provided in any of the above embodiments, and has the same functional modules and beneficial effects as the control circuit 100, which will not be elaborated herein.

[0103] Unless otherwise clearly specified in the context, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is usually included. Similarly, the terms "comprising" and "including" shall be interpreted as inclusive rather than exclusive. Likewise, the term "including" and "or" shall be interpreted as inclusive, unless such an interpretation is explicitly prohibited herein. Where the term "example" is used in this specification, the "example" is merely exemplary and explanatory, and should not be considered exclusive or extensive.

[0104] The above has described several embodiments of the present disclosure in detail. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A control circuit for a constant on-time voltage converter, the constant on-time voltage converter including an upper transistor and a lower transistor, a connection point between the upper transistor and the lower transistor being a switching node, characterized in that, The control circuit includes: a state detection module, a voltage regulation module, and a constant on-time control module; The state detection module is configured to determine a soft start process according to a soft start enable signal and a soft start voltage signal; The voltage regulation module is configured to, during the soft start process, adjust a switch node sampling voltage according to an output sampling voltage of the constant on-time voltage converter and a first preset voltage, so that the output sampling voltage is stabilized within a preset voltage range; after the soft start ends, stop working; The constant on-time control module is configured to determine a ripple injection signal according to the output sampling voltage, determine a constant on-time signal according to the output sampling voltage and an input voltage of the constant on-time voltage converter, and control the turning on and off of the upper transistor and the lower transistor according to the ripple injection signal and the constant on-time signal, so as to stabilize the switching frequency of the upper transistor and the lower transistor.

2. The control circuit according to claim 1, wherein The voltage regulation module includes a voltage control unit and a voltage regulation unit; A first input end of the voltage control unit is connected to a second sampling node of the constant on-time control module, a second input end of the voltage control unit is connected to the first preset voltage, a third input end of the voltage control unit is connected to a lower transistor control signal, a fourth input end of the voltage control unit is connected to an output end of the state detection module, a fifth input end of the voltage control unit is connected to the soft start enable signal, an output end of the voltage control unit is connected to a control end of the voltage regulation unit, a first end of the voltage regulation unit is connected to a first sampling node of the constant on-time control module, and a second end of the voltage regulation unit is connected to ground; The voltage control unit is configured to, when the lower transistor is turned on during the soft start process, connect the voltage regulation unit to the constant on-time control module when the output sampling voltage is greater than the first preset voltage; after the soft start ends, control the voltage regulation unit to maintain the state at the end of the soft start; The voltage regulation unit is configured to, when connected to the constant on-time control module, reduce the switch node sampling voltage to reduce the output sampling voltage.

3. The control circuit according to claim 2, wherein The voltage control unit includes a voltage comparator, an AND gate, and an S-R latch; A positive-phase input end of the voltage comparator is connected to the second sampling node, an anti-phase input end of the voltage comparator is connected to the first preset voltage, an output end of the voltage comparator is connected to a first input end of the AND gate, a second input end of the AND gate is connected to the lower transistor control signal, a third input end of the AND gate and an enable end of the voltage comparator are connected to the output end of the state detection module, an output end of the AND gate is connected to an input end of the S-R latch, a reset end of the S-R latch is connected to the soft start enable signal, and an output end of the S-R latch is connected to the control end of the voltage regulation unit.

4. The control circuit according to claim 2, characterized in that, The voltage regulation unit includes a first switch and a first regulating resistor; The control terminal of the first switch is connected to the output terminal of the voltage control unit. The first terminal of the first switch is connected to the first terminal of the first adjusting resistor. The second terminal of the first switch is grounded. The second terminal of the first adjusting resistor is connected to the first sampling node.

5. The control circuit according to claim 2, wherein The voltage regulation module further includes a discharging unit; The control terminal of the discharging unit is connected to the output terminal of the voltage control unit. The first terminal of the discharging unit is connected to the second sampling node. The second terminal of the discharging unit is grounded; The discharging unit is configured to, when the lower switch is turned on during the soft start process, and when the output sampling voltage is greater than the first preset voltage, release the charge on the second sampling node within a preset duration to reduce the output sampling voltage, and the preset duration is less than the minimum turn-off duration of the constant on-time voltage converter.

6. The control circuit according to claim 5, wherein The discharging unit includes a pulse generator, a second switch, and a voltage dividing component; The input terminal of the pulse generator is connected to the output terminal of the voltage control unit. The output terminal of the pulse generator is connected to the control terminal of the second switch. The first terminal of the second switch and the input terminal of the voltage dividing component are connected to the second sampling node. The second terminal of the second switch is connected to the output terminal of the voltage dividing component.

7. The control circuit according to claim 6, wherein The voltage dividing component includes an operational amplifier, a second adjusting resistor, and a third adjusting resistor; The non-inverting input terminal of the operational amplifier is connected to the first terminal of the second switch and the second sampling node. The inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier and the first terminal of the second adjusting resistor. The second terminal of the second adjusting resistor is connected to the first terminal of the third adjusting resistor and the second terminal of the second switch. The second terminal of the third adjusting resistor is grounded. The enable terminal of the operational amplifier is connected to the output terminal of the state detection module.

8. The control circuit according to any one of claims 1-7, characterized in that The state detection module includes a state comparator and a logic unit; The non-inverting input terminal of the state comparator is connected to the soft start voltage signal. The inverting input terminal of the state comparator is connected to the second preset voltage. The output terminal of the state comparator is connected to the first input terminal of the logic unit. The second input terminal of the logic unit is connected to the soft start enable signal. The output terminal of the logic unit is connected to the enable terminal of the voltage regulation module and the enable terminal of the state comparator; The logic unit is configured to generate an enable signal when the soft start voltage signal is less than the second preset voltage, and generate a non-enable signal when the soft start voltage signal is greater than or equal to the second preset voltage.

9. The control circuit according to claim 8, wherein The logic unit includes an inverter and a NOR gate; The first input terminal of the NOR gate is connected to the output terminal of the state comparator. The soft start enable signal is connected to the second input terminal of the NOR gate through the inverter. The output terminal of the NOR gate is connected to the enable terminal of the voltage regulation module and the enable terminal of the state comparator.

10. A power supply chip, characterized in that, A control circuit according to any one of claims 1-9 is included.

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