Control circuit and power supply chip of constant on-time voltage converter

Abstract

The embodiment of the invention provides a control circuit of a constant on-time voltage converter and a power supply chip. The control circuit comprises a voltage detection module and a voltage regulation module, when the output voltage rises, the voltage detection module determines a switching node sampling regulation signal according to the output sampling voltage and a first preset voltage, and when the output voltage drops, the voltage detection module determines the switching node sampling regulation signal according to the output sampling voltage and a second preset voltage. And the voltage regulation module regulates the sampling voltage of the switch node according to the sampling regulation signal of the switch node, so that the output sampling voltage is stabilized in a preset voltage range, the common-mode bias voltage can be adaptively regulated in a wide output voltage range, and the common-mode bias voltage is maintained in a normal working voltage range. Therefore, the constant on-time voltage converter can support a wide output voltage range. In addition, peripheral elements do not need to be adjusted, and the circuit complexity of the constant on-time voltage converter can be reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technologies, and in particular, to a control circuit for a constant on-time voltage converter and a power chip. Background Art

[0002] With the technological development of electronic products, their power supply systems can usually be configured to provide multiple different voltage outputs to support DC-DC voltage converters with a wide output voltage range, so as to meet the power supply requirements of complex electronic systems. For example, on the main board of a computer or a high-definition television, a DC-DC voltage converter with a wide output voltage range can supply power to different subsequent circuits to ensure the normal operation of each component of the system. At the same time, a DC-DC voltage converter with a wide output voltage range can reduce the types of power chips used to provide different output voltages, thereby simplifying the system design and reducing the overall cost, which is also a significant advantage for systems that require multi-voltage rail power supply.

[0003] In the prior art, due to the advantages of a simple peripheral circuit structure and fast transient response, the constant on-time architecture has been increasingly applied in DC-DC voltage converters. Constant on-time voltage converters usually adopt fixed peripheral components to simplify the circuit structure. However, the fixed peripheral components cannot support a wide output voltage range, resulting in an inability to balance circuit complexity and a wide output voltage range. Summary of the Invention

[0004] The present disclosure provides a control circuit for a constant on-time voltage converter and a power chip, enabling the constant on-time voltage converter to support a wide output voltage range and reducing circuit complexity.

[0005] In a first aspect, the present disclosure provides a control circuit for a constant on-time voltage converter. The constant on-time voltage converter includes an upper transistor and a lower transistor, and the connection point between the upper transistor and the lower transistor is a switching node. The control circuit includes a voltage detection module, a voltage regulation module, and a constant on-time control module.

[0006] The voltage detection module is configured to, when the output voltage of the constant on-time voltage converter increases, determine a switching node sampling adjustment signal according to the output sampling voltage of the constant on-time voltage converter and a first preset voltage; when the output voltage decreases, determine the switching node sampling adjustment signal according to the output sampling voltage and a second preset voltage; wherein the second preset voltage is less than the first preset voltage.

[0007] The voltage regulation module is configured to adjust the sampled voltage of the switching node according to the sampled regulation signal of the switching node, so as to stabilize the output sampled voltage within a preset voltage range. The constant on-time control module is configured to determine a ripple injection signal according to the output sampled voltage, determine a constant on-time signal according to the output sampled voltage and the input voltage of the constant on-time voltage converter, and control the turn-on and turn-off of the upper switch and the lower switch according to the ripple injection signal and the constant on-time signal, so as to stabilize the switching frequency of the upper switch and the lower switch.

[0008] In some embodiments of the present disclosure, the voltage detection module includes a comparison unit and a D flip-flop. A first input terminal of the comparison unit is connected to the first preset voltage, a second input terminal of the comparison unit is connected to the second preset voltage, a third input of the comparison unit is connected to an output voltage sampling node of the constant on-time control module, a first control terminal of the comparison unit is connected to a first output terminal of the comparison unit, a second control terminal of the comparison unit is connected to a second output terminal of the comparison unit and an input terminal of the D flip-flop, a clock terminal of the D flip-flop is connected to a lower switch control signal, and an output terminal of the D flip-flop is connected to an input terminal of the voltage regulation module.

[0009] The comparison unit is configured to compare the output sampled voltage with the first preset voltage to determine an output sampled comparison signal when the output voltage rises; and compare the output sampled voltage with the second preset voltage to determine the output sampled comparison signal when the output voltage drops. The D flip-flop is configured to sample the output sampled comparison signal to obtain the sampled regulation signal of the switching node when the lower switch is turned on.

[0010] In some embodiments of the present disclosure, the comparison unit includes a comparator, a first inverter, a first switch, and a second switch. The first preset voltage is connected to a positive input terminal of the comparator through the first switch, the second preset voltage is connected to the positive input terminal of the comparator through the second switch, a negative input terminal of the comparator is connected to the output voltage sampling node, a control terminal of the first switch is connected to an output terminal of the comparator and an input terminal of the first inverter, and a control terminal of the second switch is connected to an output terminal of the first inverter and an input terminal of the D flip-flop.

[0011] In some embodiments of the present disclosure, the voltage regulation module includes a third switch and a first regulating resistor. A control terminal of the third switch is connected to an output terminal of the voltage detection module. A first terminal of the third switch is connected to a switching node voltage sampling node of the constant on-time control module through the first regulating resistor, and a second terminal of the third switch is grounded.

[0012] The third switch is configured to conduct the first regulating resistor to ground when the sampling regulating signal of the switch node is at a high level, so as to reduce the sampling voltage of the switch node; and to disconnect the connection between the first regulating resistor and ground when the sampling regulating signal of the switch node is at a low level, so as to increase the sampling voltage of the switch node.

[0013] In some embodiments of the present disclosure, the voltage regulating module further includes a charge and discharge unit, the control end of the charge and discharge unit is connected to the output end of the voltage detection module, and the input-output end of the charge and discharge unit is connected to the output voltage sampling node of the constant on-time control module.

[0014] The charge and discharge unit is configured to release the charge on the output voltage sampling node within a first preset duration when the sampling regulating signal of the switch node is at a high level, so as to reduce the output sampling voltage; and to charge the output voltage sampling node within the first preset duration when the sampling regulating signal of the switch node is at a low level, so as to increase the output sampling voltage, and the first preset duration is less than the minimum off duration of the constant on-time voltage converter.

[0015] In some embodiments of the present disclosure, the charge and discharge unit includes a pulse generator and a fourth switch, the input end of the pulse generator is connected to the output end of the voltage detection module, the output end of the pulse generator is connected to the control end of the fourth switch, the first end of the fourth switch is connected to the output voltage sampling node, and the second end of the fourth switch is connected to the target output sampling voltage.

[0016] In some embodiments of the present disclosure, the voltage regulating module further includes a voltage generating unit and an output control unit, the input end of the voltage generating unit is connected to the first preset voltage, the first output end of the voltage generating unit is connected to the first input end of the output control unit, the second output end of the voltage generating unit is connected to the second input end of the output control unit, the output end of the output control unit is connected to the reference end of the charge and discharge unit, and the control end of the output control unit is connected to the output end of the voltage detection module.

[0017] The voltage generating unit is configured to generate a first target output sampling voltage and a second target output sampling voltage according to the first preset voltage, and the first target output sampling voltage is greater than the second target output sampling voltage. The output control unit is configured to extend the sampling regulating signal of the switch node by a second preset duration to obtain an output control signal, and the second preset duration is greater than the first preset duration; when the output control signal is at a high level, output the first target output sampling voltage, and when the output control signal is at a low level, output the second target output sampling voltage.

[0018] In some embodiments of the present disclosure, the voltage generation unit includes an operational amplifier, a second adjustment resistor, and a third adjustment resistor. The non-inverting input terminal of the operational amplifier is connected to the first preset voltage. The inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier, the first terminal of the second adjustment resistor, and the first input terminal of the output control unit. The second terminal of the second adjustment resistor is connected to the first terminal of the third adjustment resistor and the second input terminal of the output control unit. The second terminal of the third adjustment resistor is grounded.

[0019] In some embodiments of the present disclosure, the output control unit includes a delay element, a second inverter, a fifth switch, and a sixth switch. The input terminal of the delay element is connected to the output terminal of the voltage detection module. The output terminal of the delay element is connected to the input terminal of the second inverter and the control terminal of the fifth switch. The output terminal of the second inverter is connected to the control terminal of the sixth switch. The first terminal of the fifth switch is connected to the first output terminal of the voltage generation unit. The first terminal of the sixth switch is connected to the second output terminal of the voltage generation unit. The second terminals of the fifth switch and the sixth switch are connected to the reference terminal of the charge and discharge unit.

[0020] In a second aspect, the present disclosure provides a power supply chip, including any one of the control circuits provided in the first aspect.

[0021] In the technical solution of the present disclosure, a control circuit of a constant on-time voltage converter is provided, including a voltage detection module and a voltage regulation module. When the output voltage of the constant on-time voltage converter increases, the voltage detection module determines a switching node sampling adjustment signal according to the output sampling voltage of the constant on-time voltage converter and the first preset voltage. When the output voltage decreases, a switching node sampling adjustment signal is determined according to the output sampling voltage and the second preset voltage. The voltage regulation module adjusts the switching node sampling voltage according to the switching node sampling adjustment signal, so that the output sampling voltage is stabilized within a preset voltage range. The constant on-time control module determines a ripple injection signal according to the output sampling voltage, determines a constant on-time signal according to the output sampling voltage and the input voltage of the constant on-time voltage converter, and controls the turning on and off of the upper transistor and the lower transistor according to the ripple injection signal and the constant on-time signal, so as to stabilize the switching frequency of the upper transistor and the lower transistor. It is possible to adaptively adjust the common-mode bias voltage of the internal circuit within a wide output voltage range, so that the common-mode bias voltage can be maintained within the voltage range for the normal operation of the internal circuit. Therefore, the constant on-time voltage converter can support a wide output voltage range. In addition, there is no need to adjust the external components, which can reduce the circuit complexity of the constant on-time voltage converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. It should be understood that the accompanying drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0023] Figure 1 It is a circuit schematic diagram of a constant on-time voltage converter provided by an embodiment of the present disclosure.

[0024] Figure 2 It is a circuit schematic diagram of a ripple injection unit provided by an embodiment of the present disclosure.

[0025] Figure 3 It is a circuit schematic diagram of a loop comparator provided by an embodiment of the present disclosure.

[0026] Figure 4 It is a circuit schematic diagram of a constant on-time generator provided by an embodiment of the present disclosure.

[0027] Figure 5 It is a structural schematic diagram of a control circuit provided by an embodiment of the present disclosure.

[0028] Figure 6 It is a circuit schematic diagram of a control circuit provided by an embodiment of the present disclosure.

[0029] Figure 7 It is a working timing diagram of a control circuit provided by an embodiment of the present disclosure.

[0030] Figure 8 It is a simulation schematic diagram of each signal in a control circuit provided by an embodiment of the present disclosure.

[0031] Figure 9 It is a circuit schematic diagram of another control circuit provided by an embodiment of the present disclosure. Detailed implementation manners

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art without creative efforts based on the described embodiments of the present disclosure also fall within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Further, it will be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are directly joined together or joined through one or more intervening components.

[0034] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase "embodiment" appearing in various places in the specification is not necessarily all referring to the same embodiment, nor are they independent or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described in this disclosure can be combined with other embodiments.

[0035] Furthermore, the terms "first", "second", etc. in the description of this disclosure and the claims or in the above-mentioned drawings are used to distinguish different objects and not to describe a particular order, and may explicitly or implicitly include one or more of such features.

[0036] The term "and / or" in this disclosure is merely a description of the associated relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: the existence of A, the simultaneous existence of A and B, and the existence of B. Additionally, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0037] In the description of this disclosure, unless otherwise specified, "plural" and "at least two" mean more than two (including two). Similarly, "multiple groups" and "at least two groups" mean more than two groups (including two groups).

[0038] To enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings.

[0039] Figure 1 A circuit schematic diagram of a constant on-time voltage converter provided for an embodiment of this disclosure, as Figure 1 shown, the constant on-time voltage converter 10 is a Buck converter, including a control circuit 100, an upper transistor HS, a lower transistor LS, an inductor L, an output capacitor Cout, a load Iout, a first feedback resistor Rf1, a second feedback resistor Rf2, a feedback voltage-dividing resistor Rf0, and a feedback voltage-dividing switch S0.

[0040] The upper switch HS and the lower switch LS are connected in series between the power supply voltage and the ground. The connection point of the upper switch HS and the lower switch LS is the switching node SW. The voltage of the switching node SW is the switching node voltage Vsw. The switching node SW is connected to the voltage output terminal through an inductor L. The output capacitor Cout and the load Iout are connected in parallel between the voltage output terminal and the ground. The first feedback resistor Rf1 and the second feedback resistor Rf2 are connected in series between the voltage output terminal and the ground. The connection point of the first feedback resistor Rf1 and the second feedback resistor Rf2 is the feedback node FB. The voltage of the feedback node FB is the feedback voltage Vfb. The feedback voltage dividing resistor Rf0 and the feedback voltage dividing switch S0 are connected in series between the feedback node FB and the ground. The control terminal of the feedback voltage dividing switch S0 is connected to the output regulation signal Vset.

[0041] The constant on-time voltage converter 10 adopts an internally fixed stability compensation structure to simplify the peripheral circuit. In some application scenarios, such as the Type-c power supply scenario, the feedback voltage dividing resistor Rf0 is controlled by the feedback voltage dividing switch S0 to be connected or disconnected between the feedback node FB and the ground, so as to convert the output voltage Vout between different voltages without a protocol pin. For example, when the output regulation signal Vset flips from low level to high level, the feedback voltage dividing resistor Rf0 is connected between the feedback node FB and the ground, and the output voltage Vout increases. When the output regulation signal Vset flips from high level to low level, the connection between the feedback voltage dividing resistor Rf0 and the ground is disconnected, and the output voltage Vout decreases.

[0042] However, the fixed internal compensation is optimized for the medium output voltage Vout, resulting in that the constant on-time voltage converter 10 does not support a wide output voltage range. Generally, in order for the constant on-time voltage converter 10 to support a wide output voltage range, when the output voltage Vout is relatively high or low, it is necessary to modify the peripheral components, such as the output capacitor or add a feedforward capacitor, so that the circuit complexity and the wide output voltage range cannot be taken into account at the same time.

[0043] The control circuit 100 includes a constant on-time control module 110. The first output terminal of the constant on-time control module 110 is connected to the control terminal of the upper switch HS. The second output terminal of the constant on-time control module 110 is connected to the control terminal of the lower switch LS. The first input terminal of the constant on-time control module 110 is connected to the switching node SW to receive the switching node voltage Vsw. The second input terminal of the constant on-time control module 110 receives the soft start voltage signal Vss. The third input terminal of the constant on-time control module 110 receives the reference voltage Vref. The fourth input terminal of the constant on-time control module 110 is connected to the feedback node FB to receive the feedback voltage Vfb.

[0044] Exemplarily, such as Figure 1As shown, the constant on-time control module 110 includes a first sampling resistor Rs1 and a second sampling resistor Rs2. The first sampling resistor Rs1 and the second sampling resistor Rs2 are connected in series between the switch node SW and the ground. The second sampling resistor Rs2 is grounded, and the connection point of the first sampling resistor Rs1 and the second sampling resistor Rs2 is the switch node voltage sampling node. The first sampling resistor Rs1 and the second sampling resistor Rs2 can divide the voltage of the switch node voltage Vsw, and the voltage across the second sampling resistor Rs2 is the switch node sampling voltage Vsw_sen.

[0045] The constant on-time control module 110 further includes a filter resistor R and a filter capacitor C. The switch node voltage sampling node is grounded through the filter resistor R and the filter capacitor C in sequence. The connection point of the filter resistor R and the filter capacitor C is the output voltage sampling node. The filter resistor R and the filter capacitor C form a low-pass filter. After performing low-pass filtering on the switch node sampling voltage Vsw_sen, the average voltage of the switch node sampling voltage Vsw_sen is obtained. Since the average voltage of the switch node voltage Vsw is approximately equal to the output voltage Vout, the average voltage of the switch node sampling voltage Vsw_sen can be understood as the sampling voltage of the output voltage Vout, that is, the output sampling voltage Vout_sen.

[0046] The constant on-time control module 110 further includes a minimum voltage output unit Min. The first input terminal of the minimum voltage output unit Min receives the soft start voltage signal Vss, and the second input terminal of the minimum voltage output unit Min receives the reference voltage Vref. The minimum voltage output unit Min can output the smaller voltage of the soft start voltage signal Vss and the reference voltage Vref. For example, when the soft start voltage signal Vss is greater than the reference voltage Vref, the reference voltage Vref is output. When the soft start voltage signal Vss is less than the reference voltage Vref, the soft start voltage signal Vss is output.

[0047] The constant on-time control module 110 further includes a ripple injection unit 112. The input terminal of the ripple injection unit 112 is connected to the output voltage sampling node to receive the output sampling voltage Vout_sen, and the output sampling voltage Vout_sen is a square wave signal with a certain duty cycle.

[0048] Exemplarily, Figure 2 is a circuit schematic diagram of a ripple injection unit provided by an embodiment of the present disclosure, as Figure 2As shown, the ripple injection unit 112 includes a first resistor R1, a second resistor R2, a third resistor R3, and a first capacitor C1. The first resistor R1 and the second resistor R2 are connected in series between the input terminal of the ripple injection unit 112 and the ground. The connection point of the first resistor R1 and the second resistor R2 is connected to the output terminal of the ripple injection unit 112 through the third resistor R3. The first capacitor is connected between the output terminal of the ripple injection unit 112 and the ground.

[0049] The first resistor R1, the second resistor R2, the third resistor R3, and the first capacitor C1 form an integrating circuit. The integrating circuit can convert a square wave signal into a triangular wave signal. Therefore, the ripple injection unit 112 can convert the output sampling voltage Vout_sen into a corresponding triangular wave signal, that is, the ripple injection signal.

[0050] The constant on-time control module 110 further includes a loop comparator CMP_L. The first non-inverting input terminal of the loop comparator CMP_L is connected to the first output terminal of the ripple injection unit 112 to receive the ripple injection non-inverting signal. The first inverting input terminal of the loop comparator CMP_L is connected to the second output terminal of the ripple injection unit 112 to receive the ripple injection inverting signal. The second non-inverting input terminal of the loop comparator CMP_L is connected to the output terminal of the minimum voltage output unit Min to receive the smaller voltage of the output soft-start voltage signal Vss and the reference voltage Vref. The second inverting input terminal of the loop comparator CMP_L is connected to the feedback node FB to receive the feedback voltage Vfb.

[0051] Exemplarily, Figure 3 is a circuit schematic diagram of a loop comparator provided by an embodiment of the present disclosure. As Figure 3 shown, the loop comparator CMP_L includes a first non-inverting input transistor INP1, a first inverting input transistor INN1, a second non-inverting input transistor INP2, a second inverting input transistor INN2, a first current source IB1, a second current source IB2, a fourth resistor R4, a fifth resistor R5, a comparator COMP, and an inverter. Among them, the gains of the first non-inverting input transistor INP1 and the first inverting input transistor INN1 are the first gain Gm1, the gains of the second non-inverting input transistor INP2 and the second inverting input transistor INN2 are the second gain Gm2, and the resistance values of the fourth resistor R4 and the fifth resistor R5 are r.

[0052] The sources of the first non-inverting input transistor INP1 and the first inverting input transistor INN1 are connected to the power supply voltage VDD through the first current source IB1. The sources of the second non-inverting input transistor INP2 and the second inverting input transistor INN2 are connected to the power supply voltage VDD through the second current source IB2. The gate of the first non-inverting input transistor INP1 receives the ripple injection positive signal. The gate of the first inverting input transistor INN1 receives the ripple injection negative signal. The gate of the second non-inverting input transistor INP2 receives the smaller voltage of the output soft-start voltage signal Vss and the reference voltage Vref. The gate of the second inverting input transistor INN2 receives the feedback voltage Vfb.

[0053] The drains of the first non-inverting input transistor INP1 and the second non-inverting input transistor INP2 are connected to the non-inverting input terminal of the comparator COMP. The non-inverting input terminal of the comparator COMP is grounded through the fifth resistor R5. The drains of the first inverting input transistor INN1 and the second inverting input transistor INN2 are connected to the inverting input terminal of the comparator COMP. The inverting input terminal of the comparator COMP is grounded through the fourth resistor R4. The output terminal of the comparator COMP is connected to the output terminal of the loop comparator CMP_L through an inverter.

[0054] The first non-inverting input transistor INP1 amplifies the ripple injection positive signal at a first ratio Gm1*r. The second non-inverting input transistor INP2 amplifies the smaller voltage of the output soft-start voltage signal Vss and the reference voltage Vref at a second ratio Gm2*r, and sums the two amplified signals to obtain the non-inverting input signal of the comparator COMP. The first inverting input transistor INN1 amplifies the ripple injection negative signal at a first ratio Gm1*r. The second inverting input transistor INN2 amplifies the feedback voltage Vfb at a second ratio Gm2*r, and sums the two amplified signals to obtain the inverting input signal of the comparator COMP. The comparator COMP compares the non-inverting input signal and the inverting input signal of the comparator COMP, and the inverter inverts the output signal of the comparator COMP to obtain the loop comparison signal.

[0055] The constant on-time control module 110 further includes a constant on-time generator 111, and the input terminal of the constant on-time generator 111 is connected to the input voltage Vin. Exemplarily, Figure 4 is a circuit schematic diagram of a constant on-time generator provided by an embodiment of the present disclosure. As Figure 4 shown, the constant on-time generator 111 includes an error amplifier EA, a first transistor M1, a second transistor M2, a third transistor M3, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a second capacitor C2, and a control switch K.

[0056] The sixth resistor R6 and the seventh resistor R7 are connected in series between the input voltage Vin and the ground. The connection point of the sixth resistor R6 and the seventh resistor R7 is connected to the positive input terminal of the error amplifier EA. The negative input terminal of the error amplifier EA is connected to the first terminal of the eighth resistor R8 and the source of the third transistor M3. The output terminal of the error amplifier EA is connected to the gate of the third transistor M3. The drain of the third transistor M3 is connected to the gate of the first transistor M1, the drain of the first transistor M1, and the gate of the second transistor M2. The sources of the first transistor M1 and the second transistor M2 are connected to the power supply voltage VDD. The drain of the second transistor M2 is the output terminal of the constant on-time generator 111. The control switch K and the second capacitor C2 are connected in parallel between the output terminal of the constant on-time generator 111 and the ground.

[0057] The constant on-time generator 111 generates a charging current according to the input voltage Vin, and the charging current is proportional to the input voltage Vin. The second capacitor C2 is charged based on the charging current. The voltage across the second capacitor C2 is proportional to the charging current. The output of the constant on-time generator 111 is the voltage across the second capacitor C2.

[0058] The constant on-time control module 110 further includes a time comparator CMP_T. The positive input terminal of the time comparator CMP_T is connected to the output terminal of the constant on-time generator 111 to receive the voltage across the second capacitor C2. The negative input terminal of the time comparator CMP_T is connected to the output voltage sampling node to receive the output sampled voltage Vout_sen. The constant on-time generator 111 can compare the output sampled voltage Vout_sen and the voltage across the second capacitor C2 to obtain a constant on-time signal TON.

[0059] For example, when the voltage across the second capacitor C2 is greater than the output sampled voltage Vout_sen, the constant on-time signal TON is at a high level. When the voltage across the second capacitor C2 is less than or equal to the output sampled voltage Vout_sen, the constant on-time signal TON is at a low level.

[0060] The constant on-time control module 110 further includes an R-S latch Latch, a NOT gate NOT, and a driving unit 113. The input terminal S of the R-S latch Latch is connected to the output terminal of the loop comparator CMP_L. The reset terminal R of the R-S latch Latch is connected to the output terminal of the time comparator CMP_T. The output terminal of the R-S latch Latch is connected to the first input terminal of the driving unit 113 and the input terminal of the NOT gate NOT. The output terminal of the NOT gate NOT is connected to the second input terminal of the driving unit 113. The first output terminal of the driving unit 113 is connected to the control terminal of the high-side switch HS. The second output terminal of the driving unit 113 is connected to the control terminal of the low-side switch LS.

[0061] The R-S latch can generate a stable-frequency upper-switch control signal PWM based on the loop comparison signal and the constant on-time signal TON. The NOT gate can invert the upper-switch control signal PWM to obtain the lower-switch control signal PWMz. For example, when the loop comparison signal is at a high level, the upper-switch control signal PWM is at a high level, i.e., an upper-switch turn-on signal is generated, and correspondingly, the lower-switch control signal PWMz is at a low level, i.e., a lower-switch turn-off signal is generated. When the constant on-time signal TON is at a high level, the upper-switch control signal PWM is at a low level, i.e., an upper-switch turn-off signal is generated, and correspondingly, the lower-switch control signal PWMz is at a high level, i.e., a lower-switch turn-on signal is generated.

[0062] The driving unit 113 drives the upper switch HS to turn on or off according to the upper-switch control signal PWM. For example, the driving unit 113 drives the upper switch HS to turn on according to the upper-switch turn-on signal and drives the upper switch HS to turn off according to the upper-switch turn-off signal. The driving unit 113 drives the lower switch LS to turn on and off according to the lower-switch control signal PWMz. For example, the driving unit 113 drives the lower switch LS to turn on according to the lower-switch turn-on signal and drives the lower switch LS to turn off according to the lower-switch turn-off signal.

[0063] In this way, the constant on-time control module 110 determines the ripple injection signal according to the output sampled voltage Vout_sen, determines the constant on-time signal TON according to the output sampled voltage Vout_sen and the input voltage Vin of the constant on-time voltage converter, and controls the turn-on and turn-off of the upper switch HS and the lower switch LS according to the ripple injection signal and the constant on-time signal TON to stabilize the switching frequencies of the upper switch HS and the lower switch LS.

[0064] It should be noted that, in the embodiments of the present disclosure, only the Buck converter is taken as an example to exemplarily illustrate the constant on-time voltage converter 10. In practical applications, the constant on-time voltage converter 10 can also be a DC-DC voltage converter such as a Boost converter or a Buck-Boost converter.

[0065] The common-mode bias voltages of the internal circuits of the constant on-time control module 110 are all related to the output voltage Vout. For example, the loop comparator CMP_L and the time comparator CMP_T. And the common-mode bias voltages of the internal circuits are usually set within a certain voltage range to prevent noise interference from affecting the circuit function while ensuring normal operation at a chip power supply voltage of 5V or even 3.3V, resulting in the constant on-time voltage converter 10 not supporting a wide output voltage range.

[0066] To solve the above technical problems, the control circuit provided by the present disclosure further includes a voltage detection module and a voltage regulation module. When the output voltage of the constant on-time voltage converter increases, the voltage detection module determines a switching node sampling adjustment signal based on the output sampling voltage of the constant on-time voltage converter and a first preset voltage. When the output voltage decreases, the switching node sampling adjustment signal is determined based on the output sampling voltage and a second preset voltage. The voltage regulation module adjusts the switching node sampling voltage according to the switching node sampling adjustment signal to stabilize the output sampling voltage within a preset voltage range, which can adaptively adjust the common-mode bias voltage of the internal circuit within a wide output voltage range, so that the common-mode bias voltage can be maintained within the voltage range for the normal operation of the internal circuit. Therefore, the constant on-time voltage converter can support a wide output voltage range. In addition, there is no need to adjust the peripheral components, which can reduce the circuit complexity of the constant on-time voltage converter.

[0067] The following describes in detail the technical solutions provided by the present disclosure with several specific embodiments.

[0068] Figure 5 FIG. is a schematic structural diagram of a control circuit provided by an embodiment of the present disclosure. As Figure 5 shown, the control circuit 100 includes a constant on-time control module 110, a voltage detection module 120, and a voltage regulation module 130.

[0069] Among them, the first input terminal of the voltage detection module 120 is connected to the first preset voltage Vpre1, the second input terminal of the voltage detection module 120 is connected to the second preset voltage Vpre2, the third input terminal of the voltage detection module 120 is connected to the output voltage sampling node, the output terminal of the voltage detection module 120 is connected to the input terminal of the voltage regulation module 130, the output terminal of the voltage regulation module 130 is connected to the switching voltage sampling node, and the control terminal of the voltage regulation module 130 is connected to the lower transistor control signal PWMz.

[0070] The voltage detection module 120 is configured to determine a switching node sampling adjustment signal Vdrv1 based on the output sampling voltage Vout_sen and the first preset voltage Vpre1 when the output voltage Vout of the constant on-time voltage converter 10 increases; when the output voltage Vout decreases, determine the switching node sampling adjustment signal Vdrv1 based on the output sampling voltage Vout_sen and the second preset voltage Vpre2; wherein, the second preset voltage Vpre2 is less than the first preset voltage Vpre1.

[0071] The voltage regulation module 130 is configured to adjust the switching node sampling voltage Vsw_sen according to the switching node sampling adjustment signal Vdrv1 to stabilize the output sampling voltage Vout_sen within a preset voltage range.

[0072] Exemplarily, Figure 6 FIG. is a schematic circuit diagram of a control circuit provided by an embodiment of the present disclosure. As Figure 3 shown, the voltage detection module 120 includes a comparison unit 121 and a D flip-flop FF. The first input terminal of the comparison unit 121 is connected to a first preset voltage Vpre1, the second input terminal of the comparison unit 121 is connected to a second preset voltage Vpre2, the third input of the comparison unit 121 is connected to an output voltage sampling node, the first control terminal of the comparison unit 121 is connected to the first output terminal of the comparison unit 121, the second control terminal of the comparison unit 121 is connected to the second output terminal of the comparison unit 121 and the input terminal D of the D flip-flop FF, the clock terminal clk of the D flip-flop FF is connected to the lower transistor control signal PWMz, and the output terminal Q of the D flip-flop FF is connected to the input terminal of the voltage regulation module 130.

[0073] Continue to refer to Figure 3 , the comparison unit 121 includes a comparator CMP, a first inverter INV1, a first switch S1 and a second switch S2. The first preset voltage Vpre1 is connected to the positive input terminal of the comparator CMP through the first switch S1, the second preset voltage Vpre2 is connected to the positive input terminal of the comparator CMP through the second switch S2, the negative input terminal of the comparator CMP is connected to the output voltage sampling node, the control terminal of the first switch S1 is connected to the output terminal of the comparator CMP and the input terminal of the first inverter INV1, and the control terminal of the second switch S2 is connected to the output terminal of the first inverter INV1 and the input terminal D of the D flip-flop FF.

[0074] Figure 7 FIG. is a working timing diagram of a control circuit provided by an embodiment of the present disclosure. As Figure 4 shown, in the normal working state of the constant on-time voltage converter 10, when the output regulation signal Vset is at a low level, the output voltage Vout is a first voltage V1, the first switch S1 is turned on, the second switch S2 is turned off, and the positive input voltage of the comparator CMP is the first preset voltage Vpre1. The comparator CMP compares the output sampling voltage Vout_sen with the first preset voltage Vpre1. The first voltage V1 is less than the first preset voltage Vpre1, the comparator CMP outputs a high level, and the output sampling comparison signal Vcmp output by the first inverter INV1 is at a low level.

[0075] When the output adjustment signal Vset flips from a low level to a high level, the output voltage Vout starts to rise from the first voltage V1. During the rising process of the output voltage Vout, when the output sampling voltage Vout_sen is less than the first preset voltage Vpre1, the first switch S1 remains conducting, the second switch S2 remains off, the positive input voltage of the comparator CMP maintains the first preset voltage Vpre1, the output of the comparator CMP maintains a high level, and the output sampling comparison signal Vcmp maintains a low level.

[0076] When the output sampling voltage Vout_sen rises to the first preset voltage Vpre1, the output sampling comparison signal Vcmp flips from a low level to a high level, the first switch S1 turns off, the second switch S2 turns on, and the positive input voltage of the comparator CMP switches from the first preset voltage Vpre1 to the second preset voltage Vpre2. At this time, the comparator CMP can compare the output sampling voltage Vout_sen with the second preset voltage Vpre2, and the second preset voltage Vpre2 is less than the first preset voltage Vpre1, so the output of the comparator CMP maintains a low level, and the output sampling comparison signal Vcmp maintains a high level.

[0077] After the output adjustment signal Vset flips to a high level, the output voltage Vout finally stabilizes near the second voltage V2. When the output adjustment signal Vset flips from a high level to a low level, the output voltage Vout starts to drop from the second voltage V2. During the dropping process of the output voltage Vout, when the output sampling voltage Vout_sen is greater than the second preset voltage Vpre2, the first switch S1 remains off, the second switch S2 remains on, the positive input voltage of the comparator CMP maintains the second preset voltage Vpre2, the output of the comparator CMP maintains a low level, and the output sampling comparison signal Vcmp maintains a high level.

[0078] When the output sampling voltage Vout_sen drops to the second preset voltage Vpre2, the output sampling comparison signal Vcmp flips from a high level to a low level, the first switch S1 turns on, the second switch S2 turns off, and the positive input voltage of the comparator CMP switches from the second preset voltage Vpre2 to the first preset voltage Vpre1. At this time, the comparator CMP can compare the output sampling voltage Vout_sen with the first preset voltage Vpre1, so the output of the comparator CMP maintains a high level, and the output sampling comparison signal Vcmp maintains a low level.

[0079] After the output adjustment signal Vset flips to a low level, the output voltage Vout finally stabilizes near the first voltage V1.

[0080] Thus, when the output voltage Vout increases, the comparison unit 121 can compare the output sampled voltage Vout_sen with the first preset voltage Vpre1 to determine the output sampled comparison signal Vcmp. When the output voltage Vout decreases, the comparison unit 121 can compare the output sampled voltage Vout_sen with the second preset voltage Vpre2 to determine the output sampled comparison signal Vcmp.

[0081] Taking the output sampled comparison signal Vcmp as the input signal of the D flip-flop FF, when the lower transistor control signal PWMz flips from low level to high level, the D flip-flop FF samples the output sampled comparison signal Vcmp to obtain the switching node sampled adjustment signal Vdrv1. For example, when the lower transistor is turned on and the output sampled comparison signal Vcmp is high level, the switching node sampled adjustment signal Vdrv1 is low level. When the lower transistor is turned on and the output sampled comparison signal Vcmp is low level, the switching node sampled adjustment signal Vdrv1 is high level, as Figure 7 shown.

[0082] Exemplarily, continue to refer to Figure 6 , the voltage regulation module 130 includes a third switch S3 and a first regulation resistor Rc1. The control end of the third switch S3 is connected to the output end of the voltage detection module 120. The first end of the third switch S3 is connected to the switching node voltage sampling node through the first regulation resistor Rc1, and the second end of the third switch S3.

[0083] When the output sampled voltage Vout_sen reaches the first preset voltage Vpre1, the output voltage Vout is relatively high. The switching node sampled adjustment signal Vdrv1 flips from low level to high level, and the third switch S3 conducts. The first regulation resistor Rc1 conducts with the ground, and the first regulation resistor Rc1 can be connected between the switching node voltage sampling node and the ground. At this time, the first regulation resistor Rc1 is in parallel with the second sampling resistor Rs2, and the sampling ratio of the switching node voltage Vsw decreases, so that the switching node sampled voltage Vsw_sen can be reduced, thereby reducing the output sampled voltage Vout_sen.

[0084] When the output sampled voltage Vout_sen reaches the second preset voltage Vpre2, the output voltage Vout is relatively low. The switching node sampled adjustment signal Vdrv1 flips from high level to low level, and the third switch S3 turns off. The connection between the first regulation resistor Rc1 and the ground is disconnected, and the first regulation resistor Rc1 is not connected between the switching node voltage sampling node and the ground. At this time, the sampling ratio of the switching node voltage Vsw increases, so that the switching node sampled voltage Vsw_sen can be increased, thereby increasing the output sampled voltage Vout_sen.

[0085] Exemplarily, for a constant on-time voltage converter with a 24V input voltage under a 3A load, the first voltage V1 can be 3.3V, the second voltage V2 can be 15V, and the output voltage Vout can be switched from 3.3V to 15V. During the process of rising from 3.3V to 15V, the output sampling voltage Vout_sen varies within the voltage range of 0.5V to 2V, as Figure 8 shown, Figure 8 is a simulation schematic diagram of each signal in a control circuit provided by an embodiment of the present disclosure.

[0086] In summary, when the output voltage Vout is high, the output sampling voltage Vout_sen is reduced, and when the output voltage Vout is low, the output sampling voltage Vout_sen is increased, so as to ensure that the output sampling voltage Vout_sen is maintained within a certain voltage range under high and low output voltages. That is to say, within a wide output voltage range, the common-mode bias voltage of the internal circuit can be adaptively adjusted so that the common-mode bias voltage can be maintained within the voltage range for the normal operation of the internal circuit. Therefore, the constant on-time voltage converter can support a wide output voltage range. In addition, without modifying the peripheral components, the circuit complexity of the constant on-time voltage converter can be reduced.

[0087] In some embodiments, Figure 9 is a circuit schematic diagram of another control circuit provided by an embodiment of the present disclosure. As Figure 9 shown, the voltage regulation module 130 further includes a charge and discharge unit 131. The control end of the charge and discharge unit 131 is connected to the output end of the voltage detection module 120, and the input and output ends of the charge and discharge unit 131 are connected to the output voltage sampling node.

[0088] The charge and discharge unit 131 is configured to release the charge on the output voltage sampling node within a first preset duration Tpre1 to reduce the output sampling voltage Vout_sen when the switch node sampling adjustment signal Vdrv1 is at a high level; when the switch node sampling adjustment signal Vdrv1 is at a low level, charge the output voltage sampling node within the first preset duration Tpre1 to increase the output sampling voltage Vout_sen, and the first preset duration Tpre1 is less than the minimum turn-off duration Tmin_off of the constant on-time voltage converter.

[0089] Exemplarily, as Figure 9 shown, the charge and discharge unit 131 includes a pulse generator one-shot and a fourth switch S4. The input end of the pulse generator one-shot is connected to the output end of the voltage detection module 120, the output end of the pulse generator one-shot is connected to the control end of the fourth switch S4, the first end of the fourth switch S4 is connected to the output voltage sampling node, and the second end of the fourth switch S4 is connected to the target output sampling voltage Vsen.

[0090] When the switching node sampling regulation signal Vdrv1 is at a low level, the output sampling regulation signal Vdrv2 output by the pulse generator one-shot is at a low level. When the switching node sampling regulation signal Vdrv1 flips from a low level to a high level, the pulse generator one-shot pulls up the output sampling regulation signal Vdrv2 and maintains it for a first preset duration Tpre1 to generate a pulse signal, as Figure 4 and Figure 5 shown.

[0091] The fourth switch S4 is turned on for the first preset duration Tpre1 under the action of this pulse signal. During the first preset duration Tpre1 when the fourth switch S4 is turned on, the output voltage sampling node is connected to the target output sampling voltage Vsen. At this time, the target output sampling voltage Vsen is less than the output sampling voltage Vout_sen, and the charge on the output voltage sampling node can be quickly released to quickly reduce the output sampling voltage Vout_sen, as Figure 4 and Figure 5 shown.

[0092] As Figure 7 and Figure 8 shown, after the output sampling regulation signal Vdrv2 maintains a high level for the first preset duration Tpre1, the pulse generator one-shot pulls the output sampling regulation signal Vdrv2 to a low level. When the switching node sampling regulation signal Vdrv1 flips from a high level to a low level, the pulse generator one-shot pulls up the output sampling regulation signal Vdrv2 again and maintains it for the first preset duration Tpre1 to generate another pulse signal.

[0093] The fourth switch S4 is turned on for the first preset duration Tpre1 under the action of this pulse signal. During the first preset duration Tpre1 when the fourth switch S4 is turned on, the output voltage sampling node is connected to the target output sampling voltage Vsen. At this time, the target output sampling voltage Vsen is greater than the output sampling voltage Vout_sen, and the output voltage sampling node can be quickly charged to quickly increase the output sampling voltage Vout_sen, as Figure 7 and Figure 8 shown.

[0094] In this way, when the output voltage Vout is relatively high, the output sampling voltage Vout_sen can be quickly reduced, and when the output voltage Vout is relatively low, the output sampling voltage Vout_sen can be quickly increased. That is to say, the common-mode bias voltage can be quickly adjusted within a wide output voltage range, which can improve the stability of the constant on-time voltage converter.

[0095] In addition, the first preset duration Tpre1 is usually set to be less than the minimum off-duration Tmin_off of the constant-on-time voltage converter, which can ensure the change rate of the output voltage Vout, thereby further improving the stability of the constant-on-time voltage converter.

[0096] In some embodiments, referring still to Figure 9 , the voltage regulation module 130 further includes a voltage generation unit 132 and an output control unit 133. Among them, the input end of the voltage generation unit 132 is connected to the first preset voltage Vpre1, the first output end of the voltage generation unit 132 is connected to the first input end of the output control voltage 133, the second output end of the voltage generation unit 132 is connected to the second input end of the output control voltage 133, the output end of the output control unit 133 is connected to the reference end of the charge and discharge unit 131, and the control end of the output control unit 133 is connected to the output end of the voltage detection module 120.

[0097] The voltage generation unit 132 is configured to generate a first target output sampling voltage Vsen1 and a second target output sampling voltage Vsen2 according to the first preset voltage Vpre1, and the first target output sampling voltage Vsen1 is greater than the second target output sampling voltage Vsen2. The output control unit 133 is configured to extend the switch node sampling adjustment signal Vdrv1 for a second preset duration Tpre2 to obtain an output control signal. The second preset duration Tpre2 is greater than the first preset duration Tpre1. When the output control signal is at a high level, the first target output sampling voltage Vsen1 is output. When the output control signal is at a low level, the second target output sampling voltage Vsen2 is output.

[0098] Exemplarily, as Figure 9 shown, the voltage generation unit 132 includes an operational amplifier OP, a second adjustment resistor Rc2, and a third adjustment resistor Rc3. The non-inverting input end of the operational amplifier OP is connected to the first preset voltage Vpre1. The inverting input end of the operational amplifier OP is connected to the output end of the operational amplifier OP, the first end of the second adjustment resistor Rc2, and the first input end of the output control unit 133. The second end of the second adjustment resistor Rc2 is connected to the first end of the third adjustment resistor Rc3 and the second input end of the output control unit 133. The second end of the third adjustment resistor Rc3 is grounded.

[0099] The second adjustment resistor Rc2 and the third adjustment resistor Rc3 can divide the voltage of the first preset voltage Vpre1. The voltage across the third adjustment resistor Rc3 is the second target output sampling voltage Vsen2. The sum of the voltage across the second adjustment resistor Rc2 and the voltage across the third adjustment resistor Rc3 is the first target output sampling voltage Vsen1. Then, the first target output sampling voltage Vsen1 is greater than the second target output sampling voltage Vsen2.

[0100] Continue to refer to Figure 9 As shown in Figure 9 , the output control unit 133 includes a delay element Delay, a second inverter INV2, a fifth switch S5, and a sixth switch S6. The input terminal of the delay element Delay is connected to the output terminal of the voltage detection module 120. The output terminal of the delay element Delay is connected to the input terminal of the second inverter INV2 and the control terminal of the fifth switch S5. The output terminal of the second inverter INV2 is connected to the control terminal of the sixth switch S6. The first terminal of the fifth switch S5 is connected to the first output terminal of the voltage generation unit 132. The first terminal of the sixth switch S6 is connected to the second output terminal of the voltage generation unit 132. The second terminals of the fifth switch S5 and the sixth switch S6 are connected to the reference terminal of the charge and discharge unit 131.

[0101] The delay element Delay delays the switching node sampling adjustment signal Vdrv1 by a second preset duration Tpre2 to obtain an output control signal. Since the second preset duration Tpre2 is greater than the first preset duration Tpre1, within the first preset duration Tpre1 after the level inversion moment of the switching node sampling adjustment signal Vdrv1, the output control signal follows the switching node sampling adjustment signal Vdrv1 before inversion. After the second preset duration Tpre2 after the level inversion moment of the switching node sampling adjustment signal Vdrv1, the output control signal follows the switching node sampling adjustment signal Vdrv1 after inversion.

[0102] For example, within the first preset duration Tpre1 after the switching node sampling adjustment signal Vdrv1 changes from low level to high level, the output control signal remains low level. After the second preset duration Tpre2 after the switching node sampling adjustment signal Vdrv1 changes from low level to high level, the output control signal is high level. Within the first preset duration Tpre1 after the switching node sampling adjustment signal Vdrv1 changes from high level to low level, the output control signal remains high level. After the second preset duration Tpre2 after the switching node sampling adjustment signal Vdrv1 changes from high level to low level, the output control signal is low level.

[0103] The fifth switch S5 is controlled by the output control signal, and the sixth switch S6 is controlled by the inverted signal of the output control signal. When the output control signal is low level, the fifth switch S5 is turned off, and the sixth switch S6 is turned on, and the output control unit 133 outputs a second target output sampling voltage Vsen2. When the output control signal is high level, the fifth switch S5 is turned on, and the sixth switch S6 is turned off, and the output control unit 133 outputs a first target output sampling voltage Vsen1.

[0104] Thus, during the rising process of the output voltage Vout, when the output voltage Vout is relatively high, the charge-discharge unit 131 connects the second target output sampling voltage Vsen2 to the output voltage sampling node to reduce the output sampling voltage Vout_sen. After the adjustment of the output sampling voltage Vout_sen is completed, the output control unit 133 outputs the first target output sampling voltage Vsen1 to prepare for the next adjustment of the output sampling voltage Vout_sen.

[0105] During the falling process of the output voltage Vout, when the output voltage Vout is relatively low, the charge-discharge unit 131 connects the first target output sampling voltage Vsen1 to the output voltage sampling node to increase the output sampling voltage Vout_sen. After the adjustment of the output sampling voltage Vout_sen is completed, the output control unit 133 outputs the second target output sampling voltage Vsen2 to prepare for the next adjustment of the output sampling voltage Vout_sen.

[0106] In summary, adjusting the target output sampling voltage after the common-mode bias voltage adjustment is completed to prepare for the next common-mode bias voltage adjustment can improve the response speed of the circuit.

[0107] The present disclosure also provides a power chip, including the control circuit 100 provided in any of the above embodiments.

[0108] The power chip provided in the embodiments of the present disclosure includes the control circuit 100 provided in any of the above embodiments, and has the same functional modules and beneficial effects as the control circuit 100, which will not be elaborated here.

[0109] Unless otherwise explicitly stated in the context, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, it generally includes the plural of the corresponding term. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the term "including" and "or" should be interpreted as inclusive, unless such an interpretation is explicitly prohibited in this specification. Where the term "example" is used in this specification, the "example" is merely illustrative and explanatory, and should not be considered exclusive or extensive.

[0110] The above has described several embodiments of the present disclosure in detail. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A control circuit for a constant on-time voltage converter, characterized in that, The constant on-time voltage converter includes an upper transistor and a lower transistor, and the connection point between the upper transistor and the lower transistor is a switching node. The control circuit includes: a voltage detection module, a voltage regulation module, and a constant on-time control module; The voltage detection module is configured to, when the output voltage of the constant on-time voltage converter increases, determine a switching node sampling adjustment signal according to the output sampling voltage of the constant on-time voltage converter and a first preset voltage; when the output voltage decreases, determine the switching node sampling adjustment signal according to the output sampling voltage and a second preset voltage; wherein, the second preset voltage is less than the first preset voltage; The voltage regulation module is configured to adjust the switching node sampling voltage according to the switching node sampling adjustment signal, so that the output sampling voltage is stabilized within a preset voltage range; The constant on-time control module is configured to determine a ripple injection signal according to the output sampling voltage, determine a constant on-time signal according to the output sampling voltage and the input voltage of the constant on-time voltage converter, and control the turning on and off of the upper transistor and the lower transistor according to the ripple injection signal and the constant on-time signal, so as to stabilize the switching frequency of the upper transistor and the lower transistor.

2. The control circuit according to claim 1, wherein, The voltage detection module includes a comparison unit and a D flip-flop; A first input terminal of the comparison unit is connected to the first preset voltage, a second input terminal of the comparison unit is connected to the second preset voltage, a third input of the comparison unit is connected to an output voltage sampling node of the constant on-time control module, a first control terminal of the comparison unit is connected to a first output terminal of the comparison unit, a second control terminal of the comparison unit is connected to a second output terminal of the comparison unit and an input terminal of the D flip-flop, a clock terminal of the D flip-flop is connected to a lower transistor control signal, and an output terminal of the D flip-flop is connected to an input terminal of the voltage regulation module; The comparison unit is configured to, when the output voltage increases, compare the output sampling voltage and the first preset voltage to determine an output sampling comparison signal; when the output voltage decreases, compare the output sampling voltage and the second preset voltage to determine the output sampling comparison signal; The D flip-flop is configured to sample the output sampling comparison signal to obtain the switching node sampling adjustment signal when the lower transistor is turned on.

3. The control circuit according to claim 2, characterized in that, The comparison unit includes a comparator, a first inverter, a first switch, and a second switch; The first preset voltage is connected to a positive-phase input terminal of the comparator through the first switch, the second preset voltage is connected to the positive-phase input terminal of the comparator through the second switch, an inverting input terminal of the comparator is connected to the output voltage sampling node, a control terminal of the first switch is connected to an output terminal of the comparator and an input terminal of the first inverter, and a control terminal of the second switch is connected to an output terminal of the first inverter and an input terminal of the D flip-flop.

4. The control circuit according to any one of claims 1-3, characterized in that, The voltage regulation module includes a third switch and a first adjustment resistor; The control terminal of the third switch is connected to the output terminal of the voltage detection module. The first terminal of the third switch is connected to the switching node voltage sampling node of the constant on-time control module through the first adjustment resistor, and the second terminal of the third switch is grounded. The third switch is configured to conduct the first adjustment resistor to ground when the switching node sampling adjustment signal is at a high level, so as to reduce the switching node sampling voltage. When the switching node sampling adjustment signal is at a low level, the connection between the first adjustment resistor and ground is disconnected to increase the switching node sampling voltage.

5. The control circuit according to claim 4, wherein The voltage adjustment module further includes a charge and discharge unit. The control terminal of the charge and discharge unit is connected to the output terminal of the voltage detection module, and the input-output terminal of the charge and discharge unit is connected to the output voltage sampling node of the constant on-time control module. The charge and discharge unit is configured to release the charge on the output voltage sampling node within a first preset duration when the switching node sampling adjustment signal is at a high level, so as to reduce the output sampling voltage; when the switching node sampling adjustment signal is at a low level, charge the output voltage sampling node within the first preset duration to increase the output sampling voltage, and the first preset duration is less than the minimum turn-off duration of the constant on-time voltage converter.

6. The control circuit according to claim 5, characterized in that The charge and discharge unit includes a pulse generator and a fourth switch. The input terminal of the pulse generator is connected to the output terminal of the voltage detection module, the output terminal of the pulse generator is connected to the control terminal of the fourth switch, the first terminal of the fourth switch is connected to the output voltage sampling node, and the second terminal of the fourth switch is connected to the target output sampling voltage.

7. The control circuit according to claim 5, wherein The voltage adjustment module further includes a voltage generation unit and an output control unit. The input terminal of the voltage generation unit is connected to the first preset voltage. The first output terminal of the voltage generation unit is connected to the first input terminal of the output control unit, the second output terminal of the voltage generation unit is connected to the second input terminal of the output control unit, the output terminal of the output control unit is connected to the reference terminal of the charge and discharge unit, and the control terminal of the output control unit is connected to the output terminal of the voltage detection module. The voltage generation unit is configured to generate a first target output sampling voltage and a second target output sampling voltage according to the first preset voltage, and the first target output sampling voltage is greater than the second target output sampling voltage. The output control unit is configured to extend the switching node sampling adjustment signal by a second preset duration to obtain an output control signal, and the second preset duration is greater than the first preset duration. When the output control signal is at a high level, the first target output sampling voltage is output, and when the output control signal is at a low level, the second target output sampling voltage is output.

8. The control circuit according to claim 7, wherein The voltage generation unit includes an operational amplifier, a second adjustment resistor, and a third adjustment resistor. The non-inverting input terminal of the operational amplifier is connected to the first preset voltage, the inverting input terminal of the operational amplifier is connected to the output terminal of the operational amplifier, the first terminal of the second adjusting resistor, and the first input terminal of the output control unit. The second terminal of the second adjusting resistor is connected to the first terminal of the third adjusting resistor and the second input terminal of the output control unit. The second terminal of the third adjusting resistor is grounded.

9. The control circuit according to claim 7, wherein The output control unit includes a delay element, a second inverter, a fifth switch, and a sixth switch; The input terminal of the delay element is connected to the output terminal of the voltage detection module. The output terminal of the delay element is connected to the input terminal of the second inverter and the control terminal of the fifth switch. The output terminal of the second inverter is connected to the control terminal of the sixth switch. The first terminal of the fifth switch is connected to the first output terminal of the voltage generation unit. The first terminal of the sixth switch is connected to the second output terminal of the voltage generation unit. The second terminal of the fifth switch and the second terminal of the sixth switch are connected to the reference terminal of the charge and discharge unit.

10. A power chip, characterized in that, Comprising the control circuit according to any one of claims 1-9.

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