DC-DC power supply of four-switch three-level Cuk converter

Abstract

A DC-DC power supply of a four-switch three-level Cuk converter comprises the four-switch three-level Cuk converter, a driving circuit, an FPGA control circuit and a detection circuit, the FPGA control circuit generates four paths of PWM signals, the four paths of PWM signals are amplified by the driving circuit, a switching tube of the four-switch three-level Cuk converter is controlled, a direct current input voltage is converted into a relatively stable direct current output voltage, electric energy conversion is achieved, and the four paths of PWM signals are output through the detection circuit. And the detection circuit collects the output voltage, feeds the output voltage back to the FPGA control circuit, and performs iteration for many times until the output voltage tends to be stable, so that the voltage is stabilized and adjusted.

Description

Technical Field

[0001] The present invention belongs to the technical field of DC switching power supplies, and particularly relates to a four-switch three-level Cuk converter technology. Background Art

[0002] In non-isolated buck-boost converters, the input and output currents of the Cuk converter are both continuous, and it is widely used in some occasions. The traditional Cuk converter has a freewheeling diode, and there are two working modes: continuous current and discontinuous current, corresponding to different working principles and control strategies. The converter switches between the two modes, which is not conducive to the design of converter parameters and requires a high control strategy for the converter. The freewheeling diode has a voltage drop when conducting, generating losses, reducing the working efficiency of the power supply, and affecting the accuracy of power supply control. Summary of the Invention

[0003] In order to solve the technical problems of complex design, difficult control, and large losses of the freewheeling diode, a technical solution of using an FPGA to control the switching tube to replace the freewheeling diode is adopted, which has the technical effects of simple design, high working efficiency, and easy control.

[0004] The power supply includes a four-switch three-level Cuk converter, a driving circuit, an FPGA control circuit, and a detection circuit. The FPGA control circuit generates four PWM signals, which are amplified by the driving circuit to control the switching tubes of the four-switch three-level Cuk converter, convert the DC input voltage into a relatively stable DC output voltage, and realize the power conversion. The detection circuit collects the output voltage and feeds it back to the FPGA control circuit. After multiple iterations, until the output voltage tends to be stable, the voltage stabilization and adjustment are realized.

[0005] The four-switch three-level Cuk converter includes a DC source V in , inductors L1, L2, intermediate capacitors C1, C2, switching tubes Q1, Q2, Q3, Q4, a filter capacitor C o , a load R o , the positive pole of the DC source V in is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the anode of the intermediate capacitor C1, the cathode of the intermediate capacitor C1 is connected to one end of the inductor L2, and the other end of the inductor L2 is connected to one end of the load R o and serves as the negative pole of the output V o and is connected to the cathode of the filter capacitor C o , the other end of the load R o is connected to the anode of the intermediate capacitor C2 and serves as the positive pole of the output V o and is connected to the anode of the filter capacitor C o , the cathode of the intermediate capacitor C2 is connected to the negative pole of the DC source V in .

[0006] The drain of switch Q1 is connected to the anode of intermediate capacitor C1, the source of switch Q3 is connected to the cathode of intermediate capacitor C1, the source of switch Q2 is connected to the cathode of intermediate capacitor C2, the drain of switch Q4 is connected to the anode of intermediate capacitor C2, and the sources of switch Q1, the drain of switch Q3, the drain of switch Q2, and the source of switch Q4 are connected to each other.

[0007] The four-way PWM signals are square waves, where 1 represents high level and 0 represents low level, and are respectively input to the gates of Q1, Q2, Q3, and Q4. The buck modes are 1000, 0010, 0111, and 1101 respectively, and the boost modes are 1110, 1011, 0001, and 0100 respectively, corresponding to each cycle of t 0 to t 1, t 1 to t 2, t 2 to t 3, t 3 to t 4 four time periods.

[0008] The detection circuit and the FPGA control circuit and their corresponding control strategies generate switch drive signals to achieve precise power system control. The four-switch three-level Cuk converter improves the equivalent switching frequency of the system, reduces voltage and current ripples, reduces the voltage stress of the devices, and is conducive to the design of miniaturized and lightweight power supplies. The four-switch three-level Cuk converter uses switches to replace freewheeling diodes, enabling the converter to operate in the continuous current mode, which is conducive to the design of power supply parameters and control systems, reduces conduction losses, increases the operating efficiency of the converter, reduces line voltage drops, and improves the accuracy of the control system. Description of the Drawings

[0009] Figure 1 is the circuit schematic diagram.

[0010] Figure 2 is the converter circuit diagram.

[0011] Figure 3 is the waveform diagram of the four-way PWM signals in the buck mode.

[0012] Figure 4 is the waveform diagram of the four-way PWM signals in the boost mode.

[0013] Figure 5 is the boost mode t 0 to t 1 time period and t 2 to t 3 time period equivalent circuit diagram.

[0014] Figure 6 is the buck mode t 1 tot The equivalent circuit diagrams for the 2nd time period and t 3~ t the 4th time period.

[0015] Figure 7 is the buck mode t 0~ t the 1st time period and the boost mode t 1~ t the 2nd time period.

[0016] Figure 8 is the buck mode t 2~ t the 3rd time period and the boost mode t 3~ t the 4th time period. Specific implementation manners

[0017] The technical solution of the present invention will be specifically described below with reference to the accompanying drawings.

[0018] The FPGA control circuit generates four PWM signals, which are amplified by the drive circuit to control the switching tubes of the four-switch three-level Cuk converter, convert the DC input voltage into a relatively stable DC output voltage, realize the power conversion. The detection circuit collects the output voltage and feeds it back to the FPGA control circuit. After multiple iterations, until the output voltage tends to be stable, the voltage stabilization and adjustment are realized, as Figure 1 shown.

[0019] The positive pole of the DC source V of the four-switch three-level Cuk converter in is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the anode of the intermediate capacitor C1, the cathode of the intermediate capacitor C1 is connected to one end of the inductor L2, and the other end of the inductor L2 is connected to one end of the load R o and serves as the negative pole of the output V o and is connected to the cathode of the filter capacitor C o The other end of the load R o is connected to the anode of the intermediate capacitor C2 and serves as the positive pole of the output V o and is connected to the anode of the filter capacitor C o The cathode of the intermediate capacitor C2 is connected to the negative pole of the DC source V in The drain of the switching tube Q1 is connected to the anode of the intermediate capacitor C1, the source of the switching tube Q3 is connected to the cathode of the intermediate capacitor C1, the source of the switching tube Q2 is connected to the cathode of the intermediate capacitor C2, the drain of the switching tube Q4 is connected to the anode of the intermediate capacitor C2, and the source of the switching tube Q1, the drain of the switching tube Q3, the drain of the switching tube Q2, and the source of the switching tube Q4 are connected to each other. The circuit is as Figure 2 shown.

[0020] The switching transistor uses the IRFB4229PBF model metal-oxide semiconductor field-effect transistor of Infineon Technologies AG. The maximum on-state current is 46 A (25 °C) and 33 A (100 °C), the maximum reverse breakdown voltage is 250 V, and the maximum on-state resistance is 38 mΩ, with good high-frequency switching characteristics.

[0021] The drive circuit uses the 1ED3123MU12H model single-channel isolated gate driver of Infineon Technologies AG. The highest drive frequency is 1 MHz, suitable for high-frequency operating scenarios.

[0022] The four-channel PWM signals are square waves, with 1 representing high level and 0 representing low level, and are respectively input to the gates of Q1, Q2, Q3, and Q4, corresponding to each cycle's t 0 to t 1, t 1 to t 2, t 2 to t 3, t 3 to t 4 four time periods.

[0023] In the buck mode, the four-channel PWM signals input to Q1, Q2, Q3, and Q4 are respectively 1000, 0010, 0111, and 1101, as Figure 3 shown.

[0024] At t 0 to t 1 time period, switching transistors Q1 and Q4 are on, and switching transistors Q2 and Q3 are off. The equivalent circuit of the converter is as Figure 7 shown. The DC source V in , inductor L1, switching transistor Q1, switching transistor Q4, intermediate capacitor C2 form loop 1, and inductor L2, intermediate capacitor C1, switching transistor Q1, switching transistor Q4, filter capacitor C o , load R o form loop 2.

[0025] At t 1 to t 2 time period, switching transistors Q3 and Q4 are on, and switching transistors Q1 and Q2 are off. The equivalent circuit of the converter is as Figure 6 shown. The DC source V in , inductor L1, intermediate capacitor C1, switching transistor Q3, switching transistor Q4, intermediate capacitor C2 form loop 1, and inductor L2, switching transistor Q3, switching transistor Q4, filter capacitor C o , load R o form loop 2.

[0026] At t 2 to tDuring the 3rd time period, switch transistors Q2 and Q3 are turned on, and switch transistors Q1 and Q4 are turned off. The equivalent circuit of the converter is as Figure 8 shown, and the DC source V in , inductor L1, intermediate capacitor C1, switch transistor Q3, and switch transistor Q2 form Loop 1, and inductor L2, switch transistor Q3, switch transistor Q2, intermediate capacitor C2, filter capacitor C o , and load R o form Loop 2.

[0027] During t the 3rd to t 4th time periods, switch transistors Q3 and Q4 are turned on, and switch transistors Q1 and Q2 are turned off. The equivalent circuit of the converter is as Figure 6 shown, and the DC source V in , inductor L1, intermediate capacitor C1, switch transistor Q3, switch transistor Q4, and intermediate capacitor C2 form Loop 1, and inductor L2, switch transistor Q3, switch transistor Q4, filter capacitor C o , and load R o form Loop 2.

[0028] In the boost mode, the four PWM signals input to Q1, Q2, Q3, and Q4 are 1110, 1011, 0001, and 0100 respectively, as Figure 4 shown.

[0029] During t the 0th to t 1st time periods, switch transistors Q1 and Q2 are turned on, and switch transistors Q3 and Q4 are turned off. The equivalent circuit of the converter is as Figure 5 shown, and the DC source V in , inductor L1, switch transistor Q1, and switch transistor Q2 form Loop 1, and inductor L2, intermediate capacitor C1, switch transistor Q1, switch transistor Q2, intermediate capacitor C2, filter capacitor C o , and load R o form Loop 2.

[0030] During t the 1st to t 2nd time periods, switch transistors Q1 and Q4 are turned on, and switch transistors Q2 and Q3 are turned off. The equivalent circuit of the converter is as Figure 7 shown, and the DC source V in , inductor L1, switch transistor Q1, switch transistor Q4, and intermediate capacitor C2 form Loop 1, and inductor L2, intermediate capacitor C1, switch transistor Q1, switch transistor Q4, filter capacitor C o , and load R o form Loop 2.

[0031] During t the 2nd to t 3rd time periods, switch transistors Q1 and Q2 are turned on, and switch transistors Q3 and Q4 are turned off. The equivalent circuit of the converter is asFigure 5 As shown, the DC source V in , the inductor L1, the switching transistor Q1, and the switching transistor Q2 form Loop 1, and the inductor L2, the intermediate capacitor C1, the switching transistor Q1, the switching transistor Q2, the intermediate capacitor C2, the filter capacitor C o , and the load R o form Loop 2.

[0032] During t the time period from 3 to t 4, the switching transistors Q2 and Q3 are turned on, and the switching transistors Q1 and Q4 are turned off. The equivalent circuit of the converter is as shown in Figure 8 . The DC source V in , the inductor L1, the intermediate capacitor C1, the switching transistor Q3, and the switching transistor Q2 form Loop 1, and the inductor L2, the switching transistor Q3, the switching transistor Q2, the intermediate capacitor C2, the filter capacitor C o , and the load R o form Loop 2.

[0033] The above are the embodiments of the present invention and do not limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention are all included in the protection scope of the present invention.

Claims

1. A DC-DC power supply of a four-switch three-level Cuk converter, characterized in that, Including: A four-switch three-level Cuk converter, a driving circuit, an FPGA control circuit, and a detection circuit. The FPGA control circuit generates four PWM signals, which are amplified by the driving circuit to control the switching tubes of the four-switch three-level Cuk converter, converting the DC input voltage into a relatively stable DC output voltage to achieve power conversion. The detection circuit collects the output voltage and feeds it back to the FPGA control circuit. After multiple iterations, until the output voltage tends to be stable, the stabilization and adjustment of the voltage are realized.

2. The DC-DC power supply of the four-switch three-level Cuk converter according to claim 1, wherein The four-switch three-level Cuk converter includes: a DC source V in , inductors L1 and L2, intermediate capacitors C1 and C2, switching transistors Q1, Q2, Q3, and Q4, a filter capacitor C o , and a load R o . The positive terminal of the DC source V in is connected to one end of the inductor L1. The other end of the inductor L1 is connected to the anode of the intermediate capacitor C1. The cathode of the intermediate capacitor C1 is connected to one end of the inductor L2. The other end of the inductor L2 is connected to one end of the load R o and serves as the negative terminal of the output V o , which is connected to the cathode of the filter capacitor C o . The other end of the load R o is connected to the anode of the intermediate capacitor C2 and serves as the positive terminal of the output V o , which is connected to the anode of the filter capacitor C o . The cathode of the intermediate capacitor C2 is connected to the negative terminal of the DC source V in . The drain of the switching transistor Q1 is connected to the anode of the intermediate capacitor C1. The source of the switching transistor Q3 is connected to the cathode of the intermediate capacitor C1. The source of the switching transistor Q2 is connected to the cathode of the intermediate capacitor C2. The drain of the switching transistor Q4 is connected to the anode of the intermediate capacitor C2. The source of the switching transistor Q1, the drain of the switching transistor Q3, the drain of the switching transistor Q2, and the source of the switching transistor Q4 are connected to each other.

3. The DC-DC power supply of the four-switch three-level Cuk converter according to claim 2, characterized in that, The four-way PWM signals are square waves, where 1 represents high level and 0 represents low level, and are respectively input to the gates of Q1, Q2, Q3, and Q4. The buck modes are 1000, 0010, 0111, and 1101 respectively, and the boost modes are 1110, 1011, 0001, and 0100 respectively, corresponding to each cycle of t 0 to t 1, t 1 to t 2, t 2 to t 3, t 3 to t 4 four time periods.

4. The DC-DC power supply of the four-switch three-level Cuk converter according to claim 3, wherein The buck mode includes: At t 0 to t During the first time period, the switching transistors Q1 and Q4 are turned on, and the switching transistors Q2 and Q3 are turned off. The equivalent circuit of the converter is shown in Figure 7. The DC source V in , inductor L1, switching transistor Q1, switching transistor Q4, and intermediate capacitor C2 form Loop 1, and inductor L2, intermediate capacitor C1, switching transistor Q1, switching transistor Q4, filter capacitor C o , and load R o form Loop 2; At t 1 to t During the 2 time period, the switching transistors Q3 and Q4 are turned on, and the switching transistors Q1 and Q2 are turned off. The equivalent circuit of the converter is shown in Figure 6. The DC source V in , inductor L1, intermediate capacitor C1, switching transistor Q3, switching transistor Q4, and intermediate capacitor C2 form Loop 1, and inductor L2, switching transistor Q3, switching transistor Q4, filter capacitor C o , and load R o form Loop 2; At t 2~ t During the 3 time period, switch tubes Q2 and Q3 are turned on, and switch tubes Q1 and Q4 are turned off. The equivalent circuit of the converter is shown in Figure 8. The DC source V in , inductor L1, intermediate capacitor C1, switch tube Q3, and switch tube Q2 form Loop 1. Inductor L2, switch tube Q3, switch tube Q2, intermediate capacitor C2, filter capacitor C o , and load R o form Loop 2; At t 3 to t 4 time period, switch tubes Q3 and Q4 are turned on, and switch tubes Q1 and Q2 are turned off. The equivalent circuit of the converter is shown in Figure 6. The DC source V in , inductor L1, intermediate capacitor C1, switch tube Q3, switch tube Q4, and intermediate capacitor C2 form Loop 1, and inductor L2, switch tube Q3, switch tube Q4, filter capacitor C o , and load R o form Loop 2.

5. The DC-DC power supply of the four-switch three-level Cuk converter according to claim 3, characterized in that, The boost mode includes: At t 0 to t 1 time period, the switching transistors Q1 and Q2 are turned on, and the switching transistors Q3 and Q4 are turned off. The equivalent circuit of the converter is shown in Figure 5. The DC source V in , inductor L1, switching transistor Q1, and switching transistor Q2 form Loop 1. Inductor L2, intermediate capacitor C1, switching transistor Q1, switching transistor Q2, intermediate capacitor C2, filter capacitor C o , and load R o form Loop 2; At t 1 to t During the 2 time period, the switching transistors Q1 and Q4 are turned on, and the switching transistors Q2 and Q3 are turned off. The equivalent circuit of the converter is shown in Figure 7. The DC source V in , inductor L1, switching transistor Q1, switching transistor Q4, and intermediate capacitor C2 form Loop 1. Inductor L2, intermediate capacitor C1, switching transistor Q1, switching transistor Q4, filter capacitor C o , and load R o form Loop 2; At t 2~ t During the 3 time period, the switching transistors Q1 and Q2 are turned on, and the switching transistors Q3 and Q4 are turned off. The equivalent circuit of the converter is shown in Figure 5. The DC source V in , inductor L1, switching transistor Q1, and switching transistor Q2 form Loop 1, and inductor L2, intermediate capacitor C1, switching transistor Q1, switching transistor Q2, intermediate capacitor C2, filter capacitor C o , and load R o form Loop 2; At t 3 to t 4 time period, switch tubes Q2 and Q3 are turned on, and switch tubes Q1 and Q4 are turned off. The equivalent circuit of the converter is shown in Figure 8. DC source V in , inductor L1, intermediate capacitor C1, switch tube Q3, and switch tube Q2 form loop 1. Inductor L2, switch tube Q3, switch tube Q2, intermediate capacitor C2, filter capacitor C o , and load R o form loop 2.

Images