Low-noise analog lock-in amplification circuit

Abstract

The invention relates to a low-noise analog phase-locked amplification circuit, which comprises a first-stage gain unit, a demodulator and a low-pass filter circuit, and is characterized in that the first-stage gain unit is used for amplifying a differential input signal of a sensor and then outputting the amplified differential input signal to the demodulator; the demodulator is used for demodulating the amplified differential input signal to obtain a low-frequency signal and outputting the low-frequency signal to the low-pass filter circuit; and the low-pass filter circuit is used for filtering the low-frequency signal to obtain a differential output signal of the sensor. According to the low-noise analog phase-locked amplification circuit based on the'amplification-demodulation 'technology, differential input signals of a sensor are processed step by step, filtered low-frequency differential signals are finally output, and compared with a traditional reading circuit based on a'demodulation-amplification' structure, the low-noise analog phase-locked amplification circuit based on the'amplification-demodulation 'technology has the advantages that under the same amplification gain, the low-noise analog phase-locked amplification circuit based on the'amplification-demodulation' technology is obtained; and the method has lower noise and higher signal-to-noise ratio.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuit design, and particularly to a low-noise analog lock-in amplifier circuit. Background Art

[0002] In an inductive position sensor, the induced voltage V(t) in the receiving coil due to the electromagnetic field generated by the rotation of the rotor is a modulated signal, as shown in the following formula:

[0003] V(t) = A·sin(ω s t)·cos(ω exc t)

[0004] Wherein, A is the amplitude of the modulated signal, ω s is the induced voltage frequency, ω exc is the excitation voltage frequency, and t is time.

[0005] In order to obtain the frequency of the induced voltage, a common method is to demodulate, amplify, and filter this modulated signal, and then a voltage containing only the induced frequency can be obtained. Since the amplitude of the modulated signal is small, usually only a few millivolts, in order to achieve a better signal-to-noise ratio, the noise of the readout circuit should be low.

[0006] The traditional signal processing structure is to perform demodulation first and then amplification. The reason for adopting such a structure is that after demodulation, only the target signal, that is, the low-frequency signal, needs to be amplified. Therefore, the design of the subsequent amplifier is relatively simple. However, the disadvantage of this structure is that not only the signal is amplified, but at the same time, the input noise is also amplified by the same multiple. Even if some noise cancellation techniques are adopted in the subsequent circuit, the output noise is still large, which is not helpful for improving the output signal-to-noise ratio.

[0007] Therefore, designing a low-noise analog lock-in amplifier circuit is of great significance for improving the accuracy of inductive position sensors. Summary of the Invention

[0008] The purpose of the present invention is to provide a low-noise analog lock-in amplifier circuit, which has lower noise and higher signal-to-noise ratio under the same amplification gain compared with the traditional readout circuit based on the "demodulation-amplification" structure.

[0009] To achieve the above object, the present invention provides a low-noise analog lock-in amplifier circuit, including a first-stage gain unit, a demodulator, and a low-pass filter circuit. The first-stage gain unit is used to amplify the differential input signal of the sensor and then output it to the demodulator. The demodulator is used to demodulate the amplified differential input signal to obtain a low-frequency signal and output it to the low-pass filter circuit. The low-pass filter circuit is used to filter the low-frequency signal to obtain the differential output signal of the sensor.

[0010] Optionally, the first-stage gain unit adopts a capacitive feedback instrumentation amplifier structure with two operational amplifiers.

[0011] Optionally, the capacitive feedback instrumentation amplifier structure includes a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a first capacitor, a second capacitor, and a third capacitor;

[0012] The first operational amplifier has a first non-inverting input terminal, a first inverting input terminal, and a first output terminal. The first non-inverting input terminal receives the positive input of the differential input signal. The first resistor and the first capacitor are connected in parallel between the first inverting input terminal and the first output terminal;

[0013] The second operational amplifier has a second non-inverting input terminal, a second inverting input terminal, and a second output terminal. The second non-inverting input terminal receives the negative input of the differential input signal. The second resistor and the second capacitor are connected in parallel between the second inverting input terminal and the second output terminal;

[0014] Both ends of the third capacitor are respectively connected to the first inverting input terminal and the second inverting input terminal.

[0015] Optionally, the first resistor and the second resistor have the same resistance value, and the first capacitor and the second capacitor have the same capacitance value.

[0016] Optionally, both the first operational amplifier and the second operational amplifier adopt a two-stage cascode amplifier. The first stage adopts a non-folded cascode amplification structure to provide high gain, and the second stage adopts a common-source amplification structure to provide the ability to drive high loads.

[0017] Optionally, the two-stage cascode amplifier includes a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, a fifth power transistor, a sixth power transistor, a seventh power transistor, an eighth power transistor, a ninth power transistor, a tenth power transistor, and an eleventh power transistor. A first end of the first power transistor, a first end of the second power transistor, and a first end of the tenth power transistor are respectively connected to a working voltage. A control end of the first power transistor is connected to a control end of the second power transistor. A second end of the first power transistor is connected to a first end of the third power transistor. A second end of the second power transistor is connected to a first end of the fourth power transistor. A control end of the third power transistor is connected to a control end of the fourth power transistor. A second end of the third power transistor is connected to a control end of the first power transistor and a first end of the fifth power transistor. A second end of the fourth power transistor is connected to a first end of the sixth power transistor and a control end of the tenth power transistor. A control end of the fifth power transistor is connected to a control end of the sixth power transistor. A second end of the fifth power transistor is connected to a first end of the seventh power transistor. A second end of the sixth power transistor is connected to a first end of the eighth power transistor. A control end of the seventh power transistor and a control end of the eighth power transistor serve as differential signal input terminals of the two-stage cascode amplifier. A second end of the seventh power transistor and a second end of the eighth power transistor are connected to a first end of the ninth power transistor. A second end of the ninth power transistor and a second end of the eleventh power transistor are grounded. A control end of the ninth power transistor and a control end of the eleventh power transistor are respectively connected to a bias voltage. A second end of the tenth power transistor is connected to a first end of the eleventh power transistor and serves as a differential signal output terminal of the two-stage cascode amplifier.

[0018] Optionally, the first power transistor and the second power transistor are both PMOS transistors and form a current mirror load. The third power transistor and the fourth power transistor are cascode PMOS transistors. The fifth power transistor and the sixth power transistor are cascode NMOS transistors. The seventh power transistor and the eighth power transistor are both NMOS transistors and serve as input pair transistors of the cascode amplifier. The ninth power transistor is an NMOS bias current transistor. The tenth power transistor is a PMOS transistor. The eleventh power transistor is an NMOS transistor. And the tenth power transistor and the eleventh power transistor form a common source amplifier.

[0019] Optionally, the low-noise analog lock-in amplifier circuit further includes a Miller capacitor and a Miller resistor for Miller compensation. The Miller capacitor and the Miller resistor are connected in series between a gate of the tenth power transistor and a drain of the tenth power transistor.

[0020] Optionally, the low-noise analog lock-in amplifier circuit further includes a second-stage gain unit for amplifying the low-frequency signal and outputting it to the low-pass filter circuit.

[0021] Optionally, the second-stage gain unit includes a proportional amplifier, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor. The proportional amplifier has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The positive input of the second-stage gain unit is connected to the positive input terminal through the third resistor, the negative input of the second-stage gain unit is connected to the negative input terminal through the fourth resistor, the negative output terminal is connected to the positive input terminal through the fifth resistor, and the positive output terminal is connected to the negative output terminal through the sixth resistor.

[0022] In a low-noise analog lock-in amplifier circuit provided by the present invention, the first-stage gain unit is used to linearly amplify the differential input signal of the sensor, and then the demodulator is used to demodulate the amplified differential signal to separate the target low-frequency signal component. Then, the low-pass filter circuit is used to filter the demodulated low-frequency signal to filter out high-frequency noise and irrelevant frequency band components, and a clean differential output signal is output. This low-noise analog lock-in amplifier circuit based on the "amplification-demodulation" technology can not only implement the amplification and demodulation functions of the input modulation signal, but also the noise of the first-stage gain unit is modulated to a high frequency and removed. Therefore, the noise from the first-stage gain unit is well suppressed. Compared with the traditional readout circuit based on the "demodulation-amplification" structure, at the same amplification gain, the present invention has lower noise and a higher signal-to-noise ratio. Description of the Drawings

[0023] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0024] Figure 1 is the architecture diagram of the low-noise analog lock-in amplifier circuit provided by an embodiment of the present invention;

[0025] Figure 2 is the circuit structure diagram of the first-stage gain unit provided by an embodiment of the present invention;

[0026] Figure 3 is the circuit structure diagram of the two-stage cascode amplifier provided by an embodiment of the present invention;

[0027] Figure 4 is the circuit structure diagram of the second-stage gain unit provided by an embodiment of the present invention.

[0028] In the drawings:

[0029] 100 - First-stage gain unit; 110 - First operational amplifier; 120 - Second operational amplifier; 200 - Demodulator; 300 - Low-pass filter circuit; 400 - First-stage gain unit; 410 - Proportional amplifier;

[0030] V i,sen - Differential input signal of the sensor; V o,sen - Differential output signal of the sensor; R1 - First resistor; R2 - Second resistor; C1 - First capacitor, C2 - Second capacitor; C3 - Third capacitor; V IP1 - Positive input of the first - stage gain unit, V IN1 - Negative input of the first - stage gain unit, V OP1 、V ON1 - Output of the first - stage gain unit; M1 - First power transistor, M2 - Second power transistor, M3 - Third power transistor; M4 - Fourth power transistor; M5 - Fifth power transistor; M6 - Sixth power transistor; M7 - Seventh power transistor; M8 - Eighth power transistor; M9 - Ninth power transistor; M 10 - Tenth power transistor; M 11 - Eleventh power transistor; V DD - Operating voltage; V SS - Ground; vbn - Bias voltage; vcasp - Bias voltage of the third and fourth power transistors; vcasn - Bias voltage of the fifth and sixth power transistors; V IP2 - Positive input of the two - stage cascode amplifier; V IN2 - Negative input of the two - stage cascode amplifier; V O2 - Output of the two - stage cascode amplifier; C C - Miller capacitor; Z Z - Miller resistor; R3 - Third resistor; R4 - Fourth resistor; R5 - Fifth resistor; R6 - Sixth resistor; V IP3 - Positive input of the second - stage gain unit; V IN3 - Negative input of the second - stage gain unit; V OP3 - Positive output of the second - stage gain unit; V ON3 - Negative output of the second - stage gain unit. Detailed implementation manners

[0031] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. In order to make the objectives, features and advantages of the present invention more obvious and understandable, please refer to the accompanying drawings. It should be noted that the structures, scales, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Any modification of the structure, change of the proportional relationship or adjustment of the size, in the case of being the same or similar to the effects that the present invention can produce and the objectives that can be achieved, should still fall within the scope covered by the technical content disclosed by the present invention.

[0032] As used in the present invention, the singular forms "a", "an" and "the" include plural objects unless the context clearly indicates otherwise. As used in the present invention, the term "or" is generally used in the sense of including "and / or" unless the context clearly indicates otherwise. As used in the present invention, the term "several" is generally used in the sense of including "at least one" unless the context clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in the sense of including "two or more" unless the context clearly indicates otherwise.

[0033] Please refer to Figure 1 , an embodiment of the present invention provides a low-noise analog lock-in amplifier circuit, including a first-stage gain unit 100, a demodulator 200 and a low-pass filter circuit 300. The first-stage gain unit 100 is used to amplify the differential input signal V of the sensor i,sen and output it to the demodulator 200. The demodulator 200 is used to demodulate the amplified differential input signal to obtain a low-frequency signal and output it to the low-pass filter circuit 300. The low-pass filter circuit 300 is used to filter the low-frequency signal to obtain the differential output signal V of the sensor o,sen .

[0034] In this embodiment, the first-stage gain unit 100 is used to linearly amplify the differential input signal V of the sensor i,sen to increase the signal amplitude to a level suitable for subsequent processing; the demodulator 200 demodulates the amplified differential signal to separate the target low-frequency signal component, and the low-pass filter circuit 300 is used to filter the demodulated low-frequency signal to filter out high-frequency noise and irrelevant frequency band components and output a clean differential output signal V o,sen .

[0035] The low-noise analog lock-in amplifier circuit based on the "amplification - demodulation" technology provided by this embodiment processes the differential input signal V i,sen step by step, and finally outputs a filtered low-frequency differential signal. Compared with the traditional readout circuit based on the "demodulation - amplification" structure, under the same amplification gain, the present invention has lower noise and a higher signal-to-noise ratio.

[0036] Specifically, the differential input signal V of the sensor i,sen is usually a high-frequency signal. Since the first-stage gain unit 100 has to process this high-frequency signal, the design difficulty is relatively large, which is also the reason why the traditional signal processing structure does not adopt the technology of first amplifying and then demodulating. In this embodiment, in addition to the technology based on "amplification - demodulation", among them, the noise part of the first-stage gain unit 100 will also be modulated to a high frequency and eliminated by the subsequent low-pass filter circuit 300. Therefore, the noise of the first-stage gain unit 100 hardly contributes to the output noise, so applying the "amplification - demodulation" technology can improve the signal-to-noise ratio.

[0037] Preferably, the first-stage gain unit 100 adopts a capacitive feedback instrumentation amplifier structure with two operational amplifiers.

[0038] In some specific embodiments, as Figure 2 shown, the capacitive feedback instrumentation amplifier structure includes a first operational amplifier 110, a second operational amplifier 120, a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, and a third capacitor C3;

[0039] The first operational amplifier 110 has a first non-inverting input terminal, a first inverting input terminal, and a first output terminal. The first non-inverting input terminal receives the positive input of the differential input signal, and a first resistor R1 and a first capacitor C1 are connected in parallel between the first inverting input terminal and the first output terminal;

[0040] The second operational amplifier 120 has a second non-inverting input terminal, a second inverting input terminal, and a second output terminal. The second non-inverting input terminal receives the negative input of the differential input signal, and a second resistor R2 and a second capacitor C2 are connected in parallel between the second inverting input terminal and the second output terminal;

[0041] Both ends of the third capacitor C3 are respectively connected to the first inverting input terminal and the second inverting input terminal.

[0042] Figure 3 In, V IP1 is the positive input of the first-stage gain unit 100, V IN1 is the negative input of the first-stage gain unit 100, V OP1 and V ON1 is the output of the first - stage gain unit 100. Among them, the resistance values of the first resistor R1 and the second resistor R2 are the same, and the capacitance values of the first capacitor C1 and the second capacitor C2 are the same.

[0043] There are many advantages to using this feedback structure for the amplifier. First, since the input is a high - frequency signal in the MHz (megahertz) level with a very high bandwidth, compared with the resistor feedback that also uses RC to form a low - pass filter, the high - pass filter formed by RC in the capacitor feedback has a better suppression effect on the noise of the high - bandwidth operational amplifier, and at the same time, the capacitor feedback itself does not generate noise. In addition, the high - pass filter effect can well suppress the low - frequency interference caused by external factors. Although the two - operational - amplifier instrumentation amplifier structure still has a gain of 1 for low - frequency interference, compared with the fully differential operational amplifier, the two - operational - amplifier structure has a very high input impedance, and at the same time, it does not require common - mode feedback, and there will be no situation where it is difficult to establish common - mode feedback in the closed - loop system of the capacitor feedback structure.

[0044] Preferably, both the first operational amplifier 110 and the second operational amplifier 120 adopt a two - stage cascode amplifier. The first stage adopts an un - folded cascode amplification structure to provide high gain, and the second stage adopts a common - source amplification structure to provide the ability to drive high loads.

[0045] In some specific embodiments, as Figure 3 shown, the two - stage cascode amplifier includes the first power transistor M1, the second power transistor M2, the third power transistor M3, the fourth power transistor M4, the fifth power transistor M5, the sixth power transistor M6, the seventh power transistor M7, the eighth power transistor M8, the ninth power transistor M9, the tenth power transistor M 10 and the eleventh power transistor M 11 , the first ends of the first power transistor M1, the second power transistor M2, and the tenth power transistor M 10 are respectively connected to a working voltage V DD , the control end of the first power transistor M1 is connected to the control end of the second power transistor M2, the second end of the first power transistor M1 is connected to the first end of the third power transistor M3, the second end of the second power transistor M2 is connected to the first end of the fourth power transistor M4, the control end of the third power transistor M3 is connected to the control end of the fourth power transistor M4, the second end of the third power transistor M3 is connected to the control end of the first power transistor M1 and the first end of the fifth power transistor M5, the second end of the fourth power transistor M4 is connected to the first end of the sixth power transistor M6 and the tenth power transistor M 10The control terminal is connected, the control terminal of the fifth power transistor M5 is connected to the control terminal of the sixth power transistor M6, the second terminal of the fifth power transistor M5 is connected to the first terminal of the seventh power transistor M7, the second terminal of the sixth power transistor M6 is connected to the first terminal of the eighth power transistor M8, the control terminals of the seventh power transistor M7 and the eighth power transistor M8 serve as the differential signal input terminals of the two-stage cascode amplifier, the second terminals of the seventh power transistor M7 and the eighth power transistor M8 are connected to the first terminal of the ninth power transistor M9, and the second terminal of the ninth power transistor M9 and the second terminal of the eleventh power transistor M 11 The second terminal is grounded to V SS , the control terminal of the ninth power transistor M9 and the eleventh power transistor M 11 The control terminals are respectively connected to a bias voltage vbn, and the second terminal of the tenth power transistor M 10 is connected to the first terminal of the eleventh power transistor M 11 and serves as the differential signal output terminal of the two-stage cascode amplifier.

[0046] Preferably, the first power transistor M1 and the second power transistor M2 are both PMOS transistors and form a current mirror load. The third power transistor M3 and the fourth power transistor M4 are cascode PMOS transistors, and their purpose is to provide a larger output load. Vcasp is the bias voltage of the third power transistor M3 and the fourth power transistor M4. The fifth power transistor M5 and the sixth power transistor M6 are cascode NMOS transistors, and Vcasn is the bias voltage of the fifth power transistor M5 and the sixth power transistor M6. The seventh power transistor M7 and the eighth power transistor M8 are both NMOS transistors and serve as the input pair transistors of the cascode amplifier. The ninth power transistor M9 is an NMOS bias current transistor. The above components form the first-stage non-folded cascode amplification structure to provide high gain. The tenth power transistor M 10 is a PMOS transistor, and the eleventh power transistor M 11 is an NMOS transistor, and the tenth power transistor M 10 and the eleventh power transistor M 11 form a common-source amplifier. Among them, the current mirror load is used to convert the differential current of the input pair transistors into a single-ended output current and provide a high output impedance. The cascode structure is used to increase the output impedance. The bias current transistor is used to provide a stable bias current to ensure that the input pair transistors and the current mirror load operate in the saturation region. The common-source amplifier is used to convert the single-ended current signal of the first stage into an output signal with a high voltage swing and improve the driving ability for the second-stage gain unit.

[0047] Specifically, the source electrodes of the first power transistor M1, the second power transistor M2, and the tenth power transistor M 10 are respectively connected to the operating voltage V DD, the gate of the first power transistor M1 is connected to the gate of the second power transistor M2, the drain of the first power transistor M1 is connected to the source of the third power transistor M3, the drain of the second power transistor M2 is connected to the source of the fourth power transistor M4, the gate of the third power transistor M3 is connected to the gate of the fourth power transistor M4, the drain of the third power transistor M3 is connected to the gate of the first power transistor M1, the gate of the second power transistor M2, and the drain of the fifth power transistor M5, the drain of the fourth power transistor M4 is connected to the drain of the sixth power transistor M6 and the gate of the tenth power transistor M 10 , the gate of the fifth power transistor M5 is connected to the gate of the sixth power transistor M6, the source of the fifth power transistor M5 is connected to the drain of the seventh power transistor M7, the source of the sixth power transistor M6 is connected to the drain of the eighth power transistor M8, the gates of the seventh power transistor M7 and the eighth power transistor M8 serve as the differential signal input terminals of the two-stage cascode amplifier, V IP2 is the positive input of the two-stage cascode amplifier, V IN2 is the negative input of the two-stage cascode amplifier, the sources of the seventh power transistor M7 and the eighth power transistor M8 are connected to the drain of the ninth power transistor M9, the source of the ninth power transistor M9 and the source of the eleventh power transistor M 11 are grounded to V SS , the gate of the ninth power transistor M9 and the gate of the eleventh power transistor M 11 are respectively connected to the bias voltage vbn, the drain of the tenth power transistor M 10 is connected to the drain of the eleventh power transistor M 11 and serves as the differential signal output terminal of the two-stage cascode amplifier, V O2 is the output of the two-stage cascode amplifier.

[0048] Preferably, the low-noise analog lock-in amplifier circuit further includes a Miller capacitor C C and a Miller resistor Z Z , the Miller capacitor C C and the Miller resistor Z Z are connected in series between the gate and the drain of the tenth power transistor M 10 . High-frequency oscillation is suppressed through Miller compensation, balancing gain and stability. 10

[0049] Preferably, please continue to refer to Figure 1 , the low-noise analog lock-in amplifier circuit further includes a second-stage gain unit 400. The second-stage gain unit 400 is arranged between the demodulator 200 and the low-pass filter circuit 300. The second-stage gain unit 400 is used to amplify the demodulated signal again and then output it to the low-pass filter circuit 300 to ensure that the amplitude of the output signal is within the measurable range.

[0050] In this embodiment, the second-stage gain unit 400 is composed of a resistor ratio amplifier. As Figure 4 shown, the second-stage gain unit 400 includes a ratio amplifier 410, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6. The ratio amplifier 410 has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The positive input of the second-stage gain unit 400 is connected to the positive input terminal through the third resistor R3, the negative input of the second-stage gain unit 400 is connected to the negative input terminal through the fourth resistor R4, the negative output terminal is connected to the positive input terminal through the fifth resistor R5, and the positive output terminal is connected to the negative input terminal through the sixth resistor R6.

[0051] Among them, V IP3 and V IN3 are respectively the positive input and negative input of the second-stage gain unit 400, V OP3 and V ON3 are respectively the positive output and negative output of the second-stage gain unit 400. The third resistor R3 and the fourth resistor R4 are resistors with fixed resistance values, the fifth resistor R5 and the sixth resistor R6 are adjustable resistors, and the gain Av2 of the second-stage gain unit 400 is:

[0052]

[0053] In summary, the embodiment of the present invention provides a low-noise analog lock-in amplifier circuit based on the "amplification-demodulation" technology. Compared with the traditional readout circuit based on the "demodulation-amplification" structure, it has lower noise and higher signal-to-noise ratio under the same amplification gain.

[0054] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure belong to the protection scope of the present invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations are within the scope of the present invention and its equivalent technologies, the present invention also intends to include these modifications and variations.

Claims

1. A low-noise analog lock-in amplifier circuit, characterized in that, It includes a first-stage gain unit, a demodulator, and a low-pass filter circuit. The first-stage gain unit is used to amplify the differential input signal of the sensor and output it to the demodulator. The demodulator is used to demodulate the amplified differential input signal to obtain a low-frequency signal and output it to the low-pass filter circuit. The low-pass filter circuit is used to filter the low-frequency signal to obtain the differential output signal of the sensor.

2. The low-noise analog lock-in amplifier circuit according to claim 1, wherein The first-stage gain unit adopts a capacitive-feedback instrumentation amplifier structure with two operational amplifiers.

3. The low-noise analog lock-in amplifier circuit according to claim 2, wherein The capacitive-feedback instrumentation amplifier structure includes a first operational amplifier, a second operational amplifier, a first resistor, a second resistor, a first capacitor, a second capacitor, and a third capacitor; The first operational amplifier has a first non-inverting input terminal, a first inverting input terminal, and a first output terminal. The first non-inverting input terminal receives the positive input of the differential input signal. The first resistor and the first capacitor are connected in parallel between the first inverting input terminal and the first output terminal; The second operational amplifier has a second non-inverting input terminal, a second inverting input terminal, and a second output terminal. The second non-inverting input terminal receives the negative input of the differential input signal. The second resistor and the second capacitor are connected in parallel between the second inverting input terminal and the second output terminal; Both ends of the third capacitor are respectively connected to the first inverting input terminal and the second inverting input terminal.

4. The low-noise analog lock-in amplifier circuit according to claim 3, wherein The resistance values of the first resistor and the second resistor are the same, and the capacitance values of the first capacitor and the second capacitor are the same.

5. The low-noise analog lock-in amplifier circuit according to claim 3, characterized in that Both the first operational amplifier and the second operational amplifier adopt a two-stage cascode amplifier. The first stage adopts a non-folded cascode amplification structure to provide high gain, and the second stage adopts a common-source amplification structure to provide the ability to drive high loads.

6. The low-noise analog phase-locked amplifier circuit according to claim 5, wherein The two-stage cascode amplifier includes a first power transistor, a second power transistor, a third power transistor, a fourth power transistor, a fifth power transistor, a sixth power transistor, a seventh power transistor, an eighth power transistor, a ninth power transistor, a tenth power transistor, and an eleventh power transistor. The first ends of the first power transistor, the second power transistor, and the tenth power transistor are respectively connected to a working voltage. The control end of the first power transistor is connected to the control end of the second power transistor. The second end of the first power transistor is connected to the first end of the third power transistor. The second end of the second power transistor is connected to the first end of the fourth power transistor. The control end of the third power transistor is connected to the control end of the fourth power transistor. The second end of the third power transistor is connected to the control end of the first power transistor and the first end of the fifth power transistor. The second end of the fourth power transistor is connected to the first end of the sixth power transistor and the control end of the tenth power transistor. The control end of the fifth power transistor is connected to the control end of the sixth power transistor. The second end of the fifth power transistor is connected to the first end of the seventh power transistor. The second end of the sixth power transistor is connected to the first end of the eighth power transistor. The control ends of the seventh power transistor and the eighth power transistor serve as the differential signal input terminals of the two-stage cascode amplifier. The second ends of the seventh power transistor and the eighth power transistor are connected to the first end of the ninth power transistor. The second ends of the ninth power transistor and the eleventh power transistor are grounded. The control ends of the ninth power transistor and the eleventh power transistor are respectively connected to a bias voltage. The second end of the tenth power transistor is connected to the first end of the eleventh power transistor and serves as the differential signal output terminal of the two-stage cascode amplifier.

7. The low-noise analog phase-locked amplifier circuit according to claim 6, wherein The first power transistor and the second power transistor are both PMOS transistors and form a current mirror load. The third power transistor and the fourth power transistor are cascode PMOS transistors. The fifth power transistor and the sixth power transistor are cascode NMOS transistors. The seventh power transistor and the eighth power transistor are both NMOS transistors and serve as the input pair transistors of the cascode amplifier. The ninth power transistor is an NMOS bias current transistor. The tenth power transistor is a PMOS transistor. The eleventh power transistor is an NMOS transistor, and the tenth power transistor and the eleventh power transistor form a common-source amplifier.

8. The low-noise analog lock-in amplifier circuit according to claim 7, characterized in that, The low-noise analog lock-in amplifier circuit further includes a Miller capacitor and a Miller resistor for Miller compensation. The Miller capacitor and the Miller resistor are connected in series between the gate and the drain of the tenth power transistor.

9. The low-noise analog phase-locked amplifier circuit according to claim 1, characterized in that The low-noise analog lock-in amplifier circuit further includes a second-stage gain unit for amplifying the low-frequency signal and outputting it to the low-pass filter circuit.

10. The low-noise analog lock-in amplifier circuit according to claim 9, characterized in that, The second-stage gain unit includes a proportional amplifier, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor. The proportional amplifier has a positive input terminal, a negative input terminal, a positive output terminal, and a negative output terminal. The positive input of the second-stage gain unit is connected to the positive input terminal through the third resistor. The negative input of the second-stage gain unit is connected to the negative input terminal through the fourth resistor. The negative output terminal is connected to the positive input terminal through the fifth resistor. The positive output terminal is connected to the negative output terminal through the sixth resistor.

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