Novel ultra-wideband high-precision numerical control delayer and chip

Abstract

The invention provides a novel ultra-wideband high-precision numerical control delayer and a chip, and relates to the technical field of microwave monolithic integrated circuits and microelectronics. According to the numerical control delayer, the equalization unit is added on the delay branch, the equalization inductor is added on the reference branch, and an equalization n-shaped attenuation structure unit is formed, so that small amplitude fluctuation of the delayer is ensured, the delay dispersion effect caused by frequency change is reduced, and the delay precision of the numerical control delayer in a large delay scene is improved.

Description

Technical Field

[0001] The present invention relates to the fields of microwave monolithic integrated circuits and microelectronics technologies, and particularly relates to a novel ultra-wideband high-precision numerically controlled delay line and a chip thereof. Background Art

[0002] A numerically controlled delay line is an important component in a radio frequency transceiver delay component. In an antenna system, the delay line is used to introduce a delay of an echo signal, so as to realize distance measurement. By adjusting the delay time of the signal, the time difference of signal transmission can be compensated, signal synchronization can be ensured, and thus the performance and reliability of the system can be improved.

[0003] Currently, the large volume of the delay line limits its application scope. The miniaturized delay line chip solves this problem and has advantages such as a stable delay amount and strong anti-crosstalk ability, and is widely used in miniaturized antenna systems. Whether an antenna system can accurately locate and whether the main lobe of the beam can effectively suppress side lobes depend on the accuracy index of the phase shifter. The phase shifter is a frequency-independent control device, which will affect the instantaneous bandwidth of the antenna. Therefore, it is considered to use a delay line to replace it to obtain better performance. High-performance antenna systems also put forward different requirements for the delay line circuit, such as bandwidth, miniaturization, stability, high precision, etc. in various directions, making the delay line chip a research hotspot at home and abroad.

[0004] Due to the complexity of the working environment of modern antenna systems, a high-precision delay line is required to ensure accurate compensation of the phase difference caused by different frequencies. Since the echo signals introduced by the system are different, in order to ensure signal synchronization, different-step delay amounts are required. Therefore, numerically controlled delay line chips with different steps are widely used in modern broadband antenna systems.

[0005] A traditional delay line unit is composed of two groups of single-pole double-throw switches, a reference branch and a delay network branch. A constant-resistance network unit is adopted, and the delay is realized by controlling the two groups of single-pole double-throw switches to work complementarily in the reference state and the delay state. Thus, in some embodiments, when the delay is small, the loss and dispersion of the delay are small. When the delay amount is large, the insertion loss of the delay network branch will also increase with the increase of the delay unit, and the dispersion of the delay will be difficult to control with the increase of the delay unit in the delay network branch. The greater the phase dispersion of the delay, the worse the delay precision. Summary of the Invention

[0006] The present invention provides a novel ultra-wideband high-precision numerically controlled delay line and a chip thereof, which can improve the delay precision of the numerically controlled delay line in a large-delay scenario.

[0007] In a first aspect, the present invention provides a novel ultra-wideband high-precision numerically controlled delay line, comprising: a delay branch, a reference branch, a first isolation unit, a second isolation unit, a third isolation unit, and a fourth isolation unit; the radio frequency input end of the numerically controlled delay line is respectively connected to the first end of the delay branch through the first isolation unit and to the first end of the reference branch through the third isolation unit; the radio frequency output end of the numerically controlled delay line is respectively connected to the second end of the delay branch through the second isolation unit and to the second end of the reference branch through the fourth isolation unit; the delay branch includes a plurality of delay units and an equalization unit connected in series between the plurality of delay units; the reference branch includes a Π-type attenuation unit and an equalization inductor connected in parallel with the Π-type attenuation unit.

[0008] In a possible implementation, the equalization unit includes: a first equalization resistor, a second equalization resistor, a third equalization resistor, a first equalization inductor, and a first equalization capacitor; the first end of the first equalization resistor is connected to the previous delay unit, and the second end of the first equalization resistor is connected to the first end of the second equalization resistor and the first end of the third equalization resistor; the second end of the second equalization resistor is connected to the next delay unit; the second end of the third equalization resistor is connected to the first end of the first equalization inductor and the first end of the first equalization capacitor; the second end of the first equalization inductor is grounded; the second end of the first equalization capacitor is grounded.

[0009] In a possible implementation, the reference branch includes a Π-type attenuation unit and a second equalization inductor; the Π-type attenuation unit includes a first reference resistor, a second reference resistor, and a third reference resistor; the first ends of the first reference resistor, the second reference resistor, and the second equalization inductor are connected together as the input end of the reference branch; the first end of the third reference resistor, the second end of the second reference resistor, and the second end of the second equalization inductor are connected together as the output end of the reference branch; the second end of the first reference resistor is grounded, and the second end of the third reference resistor is grounded.

[0010] In a possible implementation, each delay unit includes: a first delay inductor and a first delay capacitor; the first end of the first delay inductor is connected to the previous delay unit, the first isolation unit, or the equalization unit; the second end of the first delay inductor is connected to the next delay unit, the second isolation unit, or the equalization unit; the third end of the first delay inductor is connected to the first end of the first delay capacitor; the second end of the first delay capacitor is grounded.

[0011] In a possible implementation, the first isolation unit includes a first isolation resistor, a second isolation resistor, a first disconnect switch, and a second disconnect switch; the second end of the first disconnect switch and the first end of the second disconnect switch are connected to the first end of the delay branch; the first end of the first disconnect switch is grounded; the second end of the second disconnect switch is connected to the third isolation unit and serves as the RF input terminal; the third end of the first disconnect switch is connected to the first control terminal through the first isolation resistor; the third end of the second disconnect switch is connected to the second control terminal through the second isolation resistor; wherein, the first control terminal outputs a reverse terminal voltage, and the second control terminal outputs a common-mode terminal voltage.

[0012] In a possible implementation, the second isolation unit includes a third isolation resistor, a fourth isolation resistor, a third disconnect switch, and a fourth disconnect switch; the second end of the third disconnect switch and the first end of the fourth disconnect switch are connected to the second end of the delay branch; the first end of the third disconnect switch is grounded; the second end of the fourth disconnect switch is connected to the fourth isolation unit and serves as the RF output terminal; the third end of the third disconnect switch is connected to the first control terminal through the third isolation resistor; the third end of the fourth disconnect switch is connected to the second control terminal through the fourth isolation resistor; wherein, the first control terminal outputs a reverse terminal voltage, and the second control terminal outputs a common-mode terminal voltage.

[0013] In a possible implementation, the third isolation unit includes a fifth isolation resistor, a sixth isolation resistor, a fifth disconnect switch, and a sixth disconnect switch; the second end of the fifth disconnect switch and the first end of the sixth disconnect switch are connected to the first end of the reference branch; the first end of the fifth disconnect switch is connected to the first isolation unit and serves as the RF input terminal; the second end of the sixth disconnect switch is grounded; the third end of the fifth disconnect switch is connected to the third control terminal through the fifth isolation resistor; the third end of the sixth disconnect switch is connected to the fourth control terminal through the sixth isolation resistor; wherein, the third control terminal outputs a reverse terminal voltage, and the fourth control terminal outputs a common-mode terminal voltage.

[0014] In a possible implementation, the fourth isolation unit includes a seventh isolation resistor, an eighth isolation resistor, a seventh disconnect switch, and an eighth disconnect switch; the second end of the seventh disconnect switch and the first end of the eighth disconnect switch are connected to the second end of the reference branch; the first end of the seventh disconnect switch is connected to the second isolation unit and serves as the RF output terminal; the second end of the eighth disconnect switch is grounded; the third end of the seventh disconnect switch is connected to the third control terminal through the seventh isolation resistor; the third end of the eighth disconnect switch is connected to the fourth control terminal through the eighth isolation resistor; wherein, the third control terminal outputs a reverse terminal voltage, and the fourth control terminal outputs a common-mode terminal voltage.

[0015] In a second aspect, the present invention provides a numerically controlled delay chip, which includes a circuit board and the numerically controlled delay as described in any one of the first aspects above.

[0016] The present invention provides a novel ultra-wideband high-precision numerically controlled delay line and chip. By adding an equalization unit to the delay branch and an equalization inductor to the reference branch, an equalization Π-type attenuation structure unit is formed, which not only ensures small amplitude fluctuations of the delay line but also reduces the delay dispersion effect caused by frequency variation, thereby improving the delay precision of the numerically controlled delay line in large-delay scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the following-described drawings are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0018] Figure 1 It is a schematic functional structure diagram of a numerically controlled delay line provided by an embodiment of the present invention;

[0019] Figure 2 It is a schematic circuit structure diagram of a numerically controlled delay line existing currently;

[0020] Figure 3 It is a schematic circuit structure diagram of a numerically controlled delay line provided by an embodiment of the present invention;

[0021] Figure 4 It is a schematic equivalent circuit diagram of a delay unit in a numerically controlled delay line provided by an embodiment of the present invention;

[0022] Figure 5 It is a schematic circuit diagram of a delay branch in a numerically controlled delay line provided by an embodiment of the present invention;

[0023] Figure 6 It is a schematic circuit diagram of a reference branch in a numerically controlled delay line provided by an embodiment of the present invention;

[0024] Figure 7 It is a schematic structure diagram of a numerically controlled delay line chip provided by an embodiment of the present invention;

[0025] Figure 8 It is a schematic diagram of the insertion loss of a traditional delay line provided by an embodiment of the present invention

[0026] Figure 9 It is a schematic diagram of the delay amount of a traditional delay line provided by an embodiment of the present invention;

[0027] Figure 10 It is a schematic diagram of the insertion loss of a numerically controlled delay line provided by an embodiment of the present invention;

[0028] Figure 11It is a schematic diagram of the amplitude fluctuation curves in all states of a numerical control delay provided by an embodiment of the present invention;

[0029] Figure 12 It is a schematic diagram of the delay quantity curve of a numerical control delay provided by an embodiment of the present invention;

[0030] Figure 13 It is a schematic diagram of the delay accuracy curve of a numerical control delay provided by an embodiment of the present invention;

[0031] Figure 14 It is a schematic diagram of the input voltage standing wave ratios in the zero state and the delay state of a numerical control delay provided by an embodiment of the present invention;

[0032] Figure 15 It is a schematic diagram of the output voltage standing wave ratios in the zero state and the delay state of a numerical control delay provided by an embodiment of the present invention. Detailed implementation manners

[0033] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present invention. However, those skilled in the art should clearly understand that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present invention.

[0034] In the description of the present invention, unless otherwise specified, " / " means "or". For example, A / B can represent A or B. The "and / or" herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, "at least one" and "multiple" refer to two or more. The words such as "first" and "second" do not limit the quantity and execution order, and the words such as "first" and "second" do not necessarily limit to be different.

[0035] In the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplary" or "for example" aims to present relevant concepts in a specific manner for easy understanding.

[0036] In addition, the terms "including" and "having" and any variations thereof mentioned in the description of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally further include other unlisted steps or modules, or may optionally further include other steps or modules inherent to these processes, methods, products, or devices.

[0037] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will be described through specific embodiments in conjunction with the drawings of the present invention.

[0038] As described in the background art, currently, traditional delay devices with a large delay amount have the technical problem of low delay accuracy.

[0039] As Figure 1 shown, the reference branch usually adopts a T-type or Π-type attenuation unit. The T-type and Π-type attenuation units are two common passive attenuator circuit topologies, which are widely used in radio frequency and microwave circuits to attenuate signals without changing the impedance matching of the circuit. The following is a detailed introduction to these two attenuation units:

[0040] T-type attenuation unit: It consists of a series resistor and two parallel resistors, one of the parallel resistors is grounded, and the other is connected to the output terminal. Its structure is similar to the letter "T". T-type attenuation unit: When the signal passes through the series resistor, part of the energy is consumed to achieve attenuation. At the same time, the two parallel resistors and the series resistor and the load impedance form a voltage dividing network to further adjust the signal amplitude. The T-type attenuation unit can achieve signal attenuation without changing the characteristic impedance of the input and output ports.

[0041] Π-type attenuation unit: It consists of a series resistor and two parallel resistors, and these two parallel resistors are respectively connected to the input terminal and the output terminal and are both grounded. Its structure is similar to the Greek letter "Π" (Pi). Π-type attenuation unit: The signal is attenuated when passing through the series resistor, and the two parallel resistors form a voltage dividing network with the load impedance to further adjust the signal amplitude. Similar to the T-type attenuation unit, the Π-type attenuation unit can also attenuate the signal while maintaining impedance matching.

[0042] The delay branch adopts Figure 2 the constant resistance network unit shown. The reference branch and the delay branch of this delay topology need two groups of single-pole double-throw switches to work complementarily in the reference state and the delay state to achieve delay. The associated switching devices mainly improve the isolation degree of this topology. Among them, VN is the control level of the delay device, VP is the common-mode terminal voltage, and VN is the reverse terminal voltage; Rg is the isolation resistor externally connected to the gate of the HEMT switch (usually greater than 1.5 kΩ), which plays the role of isolating radio frequency signals.

[0043] When the traditional delay structure is used for small delay bits (in the order of picoseconds or dozens of picoseconds), the loss and dispersion of the delay are small. For the reference branch, selecting the traditional T-type or Π-type attenuation can make the delay unit of the small bit have a small amplitude fluctuation and phase dispersion characteristic, as Figure 2 shown.

[0044] Definition and application of zero state and delay state. Zero state: The zero-state response refers to the response of the system when it has been in a stable state before the input signal changes. That is, the response of the system to the input signal without the influence of initial conditions. In signal processing and control systems, the zero-state response is used to analyze the response characteristics of the system to the input signal without considering the influence of the initial state of the system. This is very important for understanding and designing linear time-invariant systems (LTI systems).

[0045] Delay state: The delay state usually refers to the time delay experienced by a signal during transmission or processing. In a communication system, the delay state can refer to the propagation delay experienced by a signal from the transmitting end to the receiving end. In a communication network, the delay state is one of the important indicators for measuring network performance. For example, in SONET and SDH networks, zero-delay clock technology is used to ensure the synchronization of clock signals to reduce the time delay in communication. The traditional delay structure has been publicly reported, is relatively simple and mature, and has been applied in many numerically controlled delayers.

[0046] When the delay amount is large (in the order of hundreds of picoseconds), the insertion loss of the delay network branch will also increase with the increase of the delay unit, and the dispersion of the delay will also be difficult to control with the increase of the unit. The greater the phase dispersion of the delay, the worse the delay accuracy.

[0047] Based on GaAs PHEMT devices, the present invention invents a broadband, high-precision, and compact large-bit numerically controlled delay structure. The numerically controlled delay provided by the present invention can mainly compensate for the time difference of signal transmission by adjusting the delay time of the signal, ensure signal synchronization, and thus improve the performance and reliability of the system.

[0048] To solve the above technical problems, as Figure 3 shown, the embodiment of the present invention provides a novel ultra-wideband high-precision numerically controlled delay.

[0049] In the embodiment of the present invention, the numerically controlled delay includes: a delay branch, a reference branch, a first isolation unit, a second isolation unit, a third isolation unit, and a fourth isolation unit.

[0050] The RF input terminals of the numerically controlled delay line are respectively connected to the first ends of the delay branches through the first isolation unit and to the first ends of the reference branches through the third isolation unit; the RF output terminals of the numerically controlled delay line are respectively connected to the second ends of the delay branches through the second isolation unit and to the second ends of the reference branches through the fourth isolation unit.

[0051] The delay branch includes a plurality of delay units and an equalization unit connected in series between the plurality of delay units.

[0052] The reference branch includes a Π-type attenuation unit and an equalization inductor connected in parallel with the Π-type attenuation unit.

[0053] The present invention provides a novel ultra-wideband high-precision numerically controlled delay line. By adding an equalization unit to the delay branch and an equalization inductor to the reference branch to form an equalized Π-type attenuation structure unit, it not only ensures that the delay line has small amplitude fluctuations but also reduces the delay dispersion effect caused by frequency changes, improving the delay accuracy of the numerically controlled delay line in large-delay scenarios.

[0054] In some embodiments, the equalization unit includes: a first equalization resistor, a second equalization resistor, a third equalization resistor, a first equalization inductor, and a first equalization capacitor.

[0055] The first end of the first equalization resistor is connected to the previous delay unit, and the second end of the first equalization resistor is connected to the first ends of the second equalization resistor and the third equalization resistor.

[0056] The second end of the second equalization resistor is connected to the next delay unit.

[0057] The second end of the third equalization resistor is connected to the first ends of the first equalization inductor and the first equalization capacitor.

[0058] The second end of the first equalization inductor is grounded.

[0059] The second end of the first equalization capacitor is grounded.

[0060] In some embodiments, the reference branch includes a Π-type attenuation unit and a second equalization inductor.

[0061] The Π-type attenuation unit includes a first reference resistor, a second reference resistor, and a third reference resistor.

[0062] The first ends of the first reference resistor, the second reference resistor, and the first end of the second equalization inductor are connected together as the input end of the reference branch.

[0063] The first end of the third reference resistor, the second end of the second reference resistor, and the second end of the second equalization inductor are connected together as the output end of the reference branch.

[0064] The second terminal of the first reference resistor is grounded, and the second terminal of the third reference resistor is grounded.

[0065] In some embodiments, each delay unit includes: a first delay inductor and a first delay capacitor.

[0066] The first terminal of the first delay inductor is connected to the previous delay unit, the first isolation unit, or the equalization unit.

[0067] The second terminal of the first delay inductor is connected to the next delay unit, the second isolation unit, or the equalization unit.

[0068] The third terminal of the first delay inductor is connected to the first terminal of the first delay capacitor; the second terminal of the first delay capacitor is grounded.

[0069] In the embodiments of the present invention, a delay line topology with a compact structure is adopted to minimize the chip size; for the problem of delay accuracy (delay dispersion) with a large delay amount, while achieving a high-precision large-bit delay amount, a small amplitude fluctuation is ensured.

[0070] The present invention adopts a delay line topology with a compact structure to minimize the chip size. The delay unit is equivalent to a reactance element by periodically loading units in a microwave transmission line. As Figure 4 shown, compared with the traditional microstrip delay transmission line, to achieve the same time delay, the use of inductors and capacitors reduces the chip size, and this delay network has advantages such as low insertion loss and high delay flatness.

[0071] The present invention solves the problem of high-precision delay (delay dispersion) with a large delay amount, while ensuring a small amplitude fluctuation. When the delay amount is large (in the order of hundreds of picoseconds), the insertion loss of the delay network branch will also increase with the increase of the delay unit, and the delay dispersion will also be difficult to control with the increase of the unit. The greater the phase dispersion of the delay, the worse the delay accuracy. Therefore, based on the traditional delay line topology, the present invention adds an equalization unit to the delay unit of the delay line. As the frequency increases, the insertion loss of the delay changes less with the frequency. At the same time, the reference branch is improved from the traditional Π-type attenuation structure to an equalization Π-type attenuation structure unit. The use of these two structures not only ensures a small amplitude fluctuation of the delay line, but also reduces the delay dispersion effect caused by the frequency change, and it is easier to implement a high-precision large-bit digital control delay line.

[0072] The present invention selects an equalization unit to be added to the delay branch of the large-bit delay line structure as Figure 5 shown. The reference branch adopts an improved equalization Π-type attenuation structure as Figure 6 shown. The present invention not only improves the accuracy of the delay line but also does not increase the amplitude fluctuation of the delay line.

[0073] Optionally, as Figure 7As shown in the figure, an embodiment of the present invention further provides a numerically controlled delay chip, and the numerically controlled delay chip includes a circuit base plate and Figure 3 the numerically controlled delay shown.

[0074] An equalization unit is added to the delay branch of the large-bit delay structure provided by the present invention, and the schematic diagram of the specific design is as Figure 5 shown. T L1 and T L2 ... T Ln are the inductance parts in the constant-resistance network unit of the delay branch, and T C1 and T C2 ... T Cn are the capacitance parts in the constant-resistance network unit of the delay branch. R T1 and R T2 are the resistors in the equalization network unit for the delay branch, R L is the inductor in the equalization network unit for the delay branch, R C is the capacitor in the equalization network unit for the delay branch. RF in is the radio frequency input end, and RF out is the radio frequency output end.

[0075] In the case of ultra-wideband and large-delay amounts, the delay equalization unit has an obvious improvement effect on the amplitude and phase uniformity of the delay. First, in terms of the amplitude flatness of the delay, as Figure 8 shown, if the equalization unit is not added in the delay state, that is, the traditional delay, the insertion losses at 2 GHz and 18 GHz are 4 dB and 14 dB respectively. The flatness of the delay is about 10 dB as Figure 8 shown. As Figure 10 shown, when using the delay with the equalization unit, that is, the numerically controlled delay provided by the present invention, the insertion losses at 2 GHz and 18 GHz with a delay of 640 ps are 10 dB and 13 dB respectively, and the flatness of the delay is controlled within 3 dB. The present invention greatly improves the usability of the ultra-wideband chip. Second, in terms of the delay accuracy of the delay, if the delay equalization unit is not added, that is, the traditional delay, the broadband dispersion of the delay is large. As Figure 9 shown by the dotted line in the delay curve, it is an oblique line between 630 ps and 646 ps in the range of the delay amount, and the delay accuracy is poor. While the delay accuracy of the delay designed with the new structure provided by the present invention is between 638 ps and 642 ps, as Figure 9 shown by the solid line, the delay accuracy is higher. The delay equalization unit plays an important role in improving the flatness of the broadband insertion loss and improving the dispersion of the broadband delay.

[0076] The reference branch provided by the present invention adopts an improved equalization Π-type attenuation structure, and the specific schematic diagram is as Figure 6 shown. R b1and R b2 is the resistor in the balanced Π-type attenuation structure for the reference branch, and L b is the inductor in the balanced Π-type attenuation structure for the reference branch, RF in is the RF input terminal, RF out is the RF output terminal.

[0077] Table 1 shows the correspondence table between the control logic and working states of the GaAs one-bit numerically controlled delay line provided by the present invention. In Table 1, VEE is the power supply voltage, P is the control level, "0" represents a low level of 0V; "1" represents a high level of 5V.

[0078] Table 1

[0079]

[0080] The present invention has fabricated a one-bit 640ps numerically controlled delay line by adopting an innovative large-bit numerically controlled delay structure. The chip layout is as Figure 7 shown. Test results in the frequency range of 2GHz to 18GHz: insertion loss is less than 13.2dB, delay accuracy is less than ±2ps, the delay accuracy is as high as 3‰, and the amplitude fluctuation in each delay state is within ±0.5dB. The chip size is only 2.20mm × 3.20mm × 0.07mm. The main test performance curves are shown in Figures 10 - 15 shown. The circuit topology of the GaAs large-bit delay line provided by the present invention can be extended and applied to other semiconductor processes such as GaN. The large-bit delay line fabricated by applying the present invention in the T / R delay component of a modern antenna system is used to compensate for the time difference in signal transmission and ensure signal synchronization, and has broad application prospects.

[0081] In some embodiments, the first isolation unit includes a first isolation resistor, a second isolation resistor, a first isolation switch, and a second isolation switch.

[0082] The second end of the first isolation switch and the first end of the second isolation switch are connected to the first end of the delay branch; the first end of the first isolation switch is grounded.

[0083] The second end of the second isolation switch is connected to the third isolation unit and serves as the RF input terminal.

[0084] The third end of the first isolation switch is connected to the first control terminal through the first isolation resistor.

[0085] The third end of the second isolation switch is connected to the second control terminal through the second isolation resistor.

[0086] Among them, the first control terminal outputs a reverse terminal voltage, and the second control terminal outputs a common terminal voltage.

[0087] In some embodiments, the second isolation unit includes a third isolation resistor, a fourth isolation resistor, a third isolation switch, and a fourth isolation switch; the second end of the third isolation switch and the first end of the fourth isolation switch are connected to the second end of the delay branch; the first end of the third isolation switch is grounded.

[0088] The second end of the fourth isolation switch is connected to the fourth isolation unit and serves as the RF output terminal.

[0089] The third end of the third isolation switch is connected to the first control terminal through the third isolation resistor.

[0090] The third end of the fourth isolation switch is connected to the second control terminal through the fourth isolation resistor.

[0091] Wherein, the first control terminal outputs a reverse terminal voltage, and the second control terminal outputs a common terminal voltage.

[0092] In some embodiments, the third isolation unit includes a fifth isolation resistor, a sixth isolation resistor, a fifth isolation switch, and a sixth isolation switch.

[0093] The second end of the fifth isolation switch and the first end of the sixth isolation switch are connected to the first end of the reference branch; the first end of the fifth isolation switch is connected to the first isolation unit and serves as the RF input terminal.

[0094] The second end of the sixth isolation switch is grounded.

[0095] The third end of the fifth isolation switch is connected to the third control terminal through the fifth isolation resistor.

[0096] The third end of the sixth isolation switch is connected to the fourth control terminal through the sixth isolation resistor.

[0097] Wherein, the third control terminal outputs a reverse terminal voltage, and the fourth control terminal outputs a common terminal voltage.

[0098] In some embodiments, the fourth isolation unit includes a seventh isolation resistor, an eighth isolation resistor, a seventh isolation switch, and an eighth isolation switch.

[0099] The second end of the seventh isolation switch and the first end of the eighth isolation switch are connected to the second end of the reference branch; the first end of the seventh isolation switch is connected to the second isolation unit and serves as the RF output terminal.

[0100] The second end of the eighth isolation switch is grounded.

[0101] The third end of the seventh isolation switch is connected to the third control terminal through the seventh isolation resistor.

[0102] The third end of the eighth isolation switch is connected to the fourth control terminal through the eighth isolation resistor.

[0103] Among them, the third control terminal outputs the reverse terminal voltage, and the fourth control terminal outputs the non-inverting terminal voltage.

[0104] The present invention utilizes Figure 3 the described circuit structure to design a circuit and determine the parameters of the components in the circuit. First, optimize the delay basic unit bit to obtain the optimal topology and lumped parameter values, and then convert the lumped parameters into distributed parameters. According to the results of the basic bit, cascade simulation is performed on the single-pole double-throw switch and the attenuation equalization unit, and the zero state and the delay state of the digital controlled delay line are set according to Truth Table 1. The amplitude difference between the delay state and the zero state gives the amplitude fluctuation curve of the delay, and the phase difference between the delay state and the zero state is converted into the delay amount, that is, the delay error curve of the delay is obtained. Adjust the circuit according to the simulation results to improve the circuit indexes that do not meet the requirements, and finally achieve the optimal indexes.

[0105] In the layout, the electromagnetic compatibility problem should be fully considered. In the design, add isolation belts formed by multiple groups of cascaded common ground vias to achieve electromagnetic space isolation and prevent signal crosstalk. At the same time, reduce the crossing of microwave transmission lines and DC transmission lines and add filter capacitors on the DC transmission lines to reduce the crosstalk coupling of external signals to the internal circuit. In the layout, first connect the RF transmission path, then connect the DC path, and finally make full use of the flexibility of the control terminal signal to layout the layout to achieve the control of the attenuator, significantly improving the efficiency of the layout.

[0106] The present invention is fabricated using GaAs PHEMT microwave monolithic integrated circuit process technology. The main process steps of the GaAs process are: mesa isolation, ohmic contact, gate trenching and metallization, device passivation, metal lift-off, air bridge preparation, backside chemical thinning, via process, etc. Before the process processing, it is necessary to provide the GaAs process line with Figure 7 the chip layout of the broadband digital controlled delay line as shown.

[0107] The present invention uses a microwave probe platform to test the chip on-wafer. The test results are as Figures 10 - 15 shown. In the operating frequency band of 2 GHz to 18 GHz, the insertion loss of this chip is less than 13.2 dB, the delay accuracy is less than ±2 ps, the delay accuracy is as high as 3‰, and the amplitude fluctuation of each delay state is within ±0.5 dB. The chip size is only 2.20 mm × 3.20 mm × 0.07 mm.

[0108] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A novel ultra-wideband high-precision numerically controlled delay line, characterized in that, Including: A delay branch, a reference branch, a first isolation unit, a second isolation unit, a third isolation unit, and a fourth isolation unit; The RF input end of the digital controlled delay line is respectively connected to the first end of the delay branch through the first isolation unit and to the first end of the reference branch through the third isolation unit; the RF output end of the digital controlled delay line is respectively connected to the second end of the delay branch through the second isolation unit and to the second end of the reference branch through the fourth isolation unit; The delay branch includes a plurality of delay units and an equalization unit connected in series between the plurality of delay units; The reference branch includes a Π-type attenuation unit and an equalization inductor connected in parallel with the Π-type attenuation unit.

2. The novel ultra-wideband high-precision numerically controlled delay line according to claim 1, characterized in that, The equalization unit includes: a first equalization resistor, a second equalization resistor, a third equalization resistor, a first equalization inductor, and a first equalization capacitor; The first end of the first equalization resistor is connected to the previous delay unit, and the second end of the first equalization resistor is connected to the first end of the second equalization resistor and the first end of the third equalization resistor; The second end of the second equalization resistor is connected to the next delay unit; The second end of the third equalization resistor is connected to the first end of the first equalization inductor and the first end of the first equalization capacitor; The second end of the first equalization inductor is grounded; The second end of the first equalization capacitor is grounded.

3. The novel ultra-wideband high-precision numerically controlled delay line according to claim 1 or 2, characterized in that, The reference branch includes a Π-type attenuation unit and a second equalization inductor; The Π-type attenuation unit includes a first reference resistor, a second reference resistor, and a third reference resistor; The first ends of the first reference resistor, the second reference resistor, and the first end of the second equalization inductor are connected together as the input end of the reference branch; The first end of the third reference resistor, the second end of the second reference resistor, and the second end of the second equalization inductor are connected together as the output end of the reference branch; The second end of the first reference resistor is grounded, and the second end of the third reference resistor is grounded.

4. The novel ultra-wideband high-precision numerically controlled delay line according to claim 1, characterized in that, Each delay unit includes: a first delay inductor and a first delay capacitor; The first end of the first delay inductor is connected to the previous delay unit, the first isolation unit, or the equalization unit; The second end of the first delay inductor is connected to the next delay unit, the second isolation unit, or the equalization unit; The third end of the first delay inductor is connected to the first end of the first delay capacitor; the second end of the first delay capacitor is grounded.

5. The novel ultra-wideband high-precision numerically controlled delay line according to claim 1, wherein The first isolation unit includes a first isolation resistor, a second isolation resistor, a first disconnect switch, and a second disconnect switch; The second end of the first disconnect switch and the first end of the second disconnect switch are connected to the first end of the delay branch; the first end of the first disconnect switch is grounded; The second end of the second disconnect switch is connected to the third isolation unit and serves as the RF input end; The third end of the first disconnect switch is connected to the first control end through the first isolation resistor; The third end of the second disconnect switch is connected to the second control end through the second isolation resistor; Wherein, the first control end outputs a reverse terminal voltage, and the second control end outputs a common terminal voltage.

6. The novel ultra-wideband high-precision numerically controlled delay line according to claim 1, characterized in that, The second isolation unit includes a third isolation resistor, a fourth isolation resistor, a third disconnect switch, and a fourth disconnect switch; The second end of the third disconnecting switch and the first end of the fourth disconnecting switch are connected to the second end of the delay branch; the first end of the third disconnecting switch is grounded; The second end of the fourth disconnecting switch is connected to the fourth isolation unit and serves as the RF output terminal; The third end of the third disconnecting switch is connected to the first control terminal through a third isolation resistor; The third end of the fourth disconnecting switch is connected to the second control terminal through a fourth isolation resistor; Wherein, the first control terminal outputs a reverse terminal voltage, and the second control terminal outputs a common terminal voltage.

7. The novel ultra-wideband high-precision numerically controlled delay line according to claim 1, wherein The third isolation unit includes a fifth isolation resistor, a sixth isolation resistor, a fifth disconnecting switch, and a sixth disconnecting switch; The second end of the fifth disconnecting switch and the first end of the sixth disconnecting switch are connected to the first end of the reference branch; the first end of the fifth disconnecting switch is connected to the first isolation unit and serves as the RF input terminal; The second end of the sixth disconnecting switch is grounded; The third end of the fifth disconnecting switch is connected to the third control terminal through a fifth isolation resistor; The third end of the sixth disconnecting switch is connected to the fourth control terminal through a sixth isolation resistor; Wherein, the third control terminal outputs a reverse terminal voltage, and the fourth control terminal outputs a common terminal voltage.

8. The novel ultra-wideband high-precision numerically controlled delay line according to claim 1, wherein, The fourth isolation unit includes a seventh isolation resistor, an eighth isolation resistor, a seventh disconnecting switch, and an eighth disconnecting switch; The second end of the seventh disconnecting switch and the first end of the eighth disconnecting switch are connected to the second end of the reference branch; the first end of the seventh disconnecting switch is connected to the second isolation unit and serves as the RF output terminal; The second end of the eighth disconnecting switch is grounded; The third end of the seventh disconnecting switch is connected to the third control terminal through a seventh isolation resistor; The third end of the eighth disconnecting switch is connected to the fourth control terminal through an eighth isolation resistor; Wherein, the third control terminal outputs a reverse terminal voltage, and the fourth control terminal outputs a common terminal voltage.

9. A numerical control delay chip, characterized in that, The digital control delay chip includes a circuit board and the digital control delay as described in any one of claims 1 to 7.

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