Computing board phase-locked loop output clock phase adjustment method, device and equipment and medium
By obtaining the phase difference between the output clock of the intermediate chip and the source clock and adjusting the output clock phase of the phase lock loop, the problem of clock phase delay in the blockchain computing board is solved, efficient phase adjustment is achieved, and time-consuming clock training steps are avoided.
Patent Information
- Application Number
- CN202510467939.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2025-07-25
AI Technical Summary
In the multi-chip collaborative working architecture of blockchain computing boards, the clock phase delay problem caused by cascade topology is solved by the existing technology through clock training methods, but it is inefficient and takes a long time.
By obtaining the phase difference between the output clock of the intermediate chip and the source clock, and adjusting the output clock phase of the phase lock loop, the output clock of the intermediate chip is consistent with the phase of the source clock, eliminating the clock training steps, and automatically completing phase adjustment using the calculation board.
It realizes that without clock training, all chip output clock phases meet normal working requirements, improve work efficiency, and reduce manual intervention and time consumption.
Smart Images
Figure CN120377900A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip design, and particularly relates to a method, device, equipment and medium for adjusting the phase of the output clock of a phase-locked loop on a computing board. Background Art
[0002] In an application scenario of the multi-chip collaborative working architecture of a blockchain computing board, each computing chip usually uses a cascaded topology for serial communication. This physical connection method causes the source clock to pass through all the cascaded chips in sequence. Every time the clock passes through a chip, a phase delay will occur. If the phase delay is too large, the chip will not work properly. In order to make the phases of the output clocks of each chip meet the requirements, a clock training method is used to determine the phase of the output clock of the phase-locked loop. However, clock training requires multiple iterations, which takes a long time and has low efficiency. Summary of the Invention
[0003] Based on this, in view of the above technical problems, a method, device, equipment and medium for adjusting the phase of the output clock of a phase-locked loop on a computing board are provided.
[0004] The technical solution adopted by the present invention is as follows:
[0005] As a first aspect of the present invention, a method for adjusting the phase of the output clock of a phase-locked loop on a computing board is provided, which is characterized by including:
[0006] S101. Obtain the output clock of the middle chip among multiple cascaded chips, wherein the output clock of the middle chip is based on the original output clock of the phase-locked loop;
[0007] S102. Calculate the phase difference ΔΦ between the output clock of the middle chip and the source clock. If the phase difference ΔΦ is not 0°, adjust the phase of the output clock of the phase-locked loop to the difference between its original output clock phase and ΔΦ.
[0008] As a second aspect of the present invention, a device for adjusting the phase of the output clock of a phase-locked loop on a computing board is provided, which is characterized by including:
[0009] A first module for S101. Obtain the output clock of the middle chip among multiple cascaded chips, wherein the output clock of the middle chip is based on the original output clock of the phase-locked loop;
[0010] A second module for S102. Calculate the phase difference ΔΦ between the output clock of the middle chip and the source clock. If the phase difference ΔΦ is not 0°, adjust the phase of the output clock of the phase-locked loop to the difference between its original output clock phase and ΔΦ.
[0011] As a third aspect of the present invention, there is provided an electronic device, characterized in that it includes a storage module, and the storage module includes instructions loaded and executed by a processor, and when the instructions are executed, the processor is caused to execute a method for adjusting the output clock phase of a computing board phase-locked loop according to the first aspect above.
[0012] As a fourth aspect of the present invention, there is provided a computer-readable storage medium storing one or more programs, characterized in that when the one or more programs are executed by a processor, a method for adjusting the output clock phase of a computing board phase-locked loop according to the first aspect above is implemented.
[0013] The present invention adjusts the phase of the output clock of the phase-locked loop based on the output clock of the intermediate chip, so that the phase of the output clock of the intermediate chip is consistent with the phase of the source clock, ensuring that the output clock phases of all chips meet the requirements for normal operation. In this way, although there is no clock training, the same effect as clock training is achieved, saving the time-consuming clock training step. The whole process is automatically completed inside the computing board without manual intervention, improving work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The present invention will be described in detail below with reference to the drawings and specific embodiments:
[0015] Figure 1 It is a flowchart of a method for adjusting the output clock phase of a computing board phase-locked loop provided by an embodiment of the present invention;
[0016] Figure 2 It is a schematic diagram of a device for adjusting the output clock phase of a computing board phase-locked loop provided by an embodiment of the present invention;
[0017] Figure 3 It is a schematic diagram of an electronic device provided by an embodiment of the present invention;
[0018] Figure 4 It is a schematic diagram of the application environment of an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0019] The following will describe the embodiments of the present invention with reference to the accompanying drawings of the specification. It should be noted that the embodiments involved in this specification are not exhaustive and do not represent the only embodiments of the present invention. The following corresponding embodiments are only for clearly explaining the inventive content of the present invention and do not limit its embodiments. For those of ordinary skill in the art, different forms of changes and modifications can be made based on the description of this embodiment, and any obvious changes or modifications that belong to the technical concept and inventive content of the present invention are also within the protection scope of the present invention.
[0020] Figure 4The application environment of the embodiment of the present application is shown, that is, the structure of a computing board, which includes a controller 110, a phase-locked loop 120, and multiple chips 130. The controller 110 is connected to the phase-locked loop 120, and the phase-locked loop 120 is connected in series with multiple chips 130. The controller 110 can receive the feedback signal sent by the chip 130, and at the same time can send commands to control the phase of the phase-locked loop. The phase-locked loop 120 receives the source clock and passes through multiple chips 130 in sequence. In practical applications, there may be dozens or even hundreds of chips in the computing board. Let the total number of chips be N. When the clock passes through each chip, the phase delay will increase. When the phase difference between the chip output clock and the source clock is too large, the chip will not work properly. When the chip 130 is working, it will send a feedback signal indicating whether it is working properly. If the chip clock does not meet the requirements, the chip 130 will send a feedback signal of abnormal operation to the controller 110. If the chip clock meets the requirements, the chip 130 will send a feedback signal of normal operation to the controller 110.
[0021] For the convenience of description, a computing board including 6 chips 130 is taken as an example. At this time, N = 6. It is assumed that the clock will generate a phase delay of 1° when passing through each chip, and a phase delay of 6° will be generated when passing through 6 chips. It is assumed that the chip output clock can work properly only when the phase difference from the source clock is within 4°.
[0022] The phase-locked loop 120 receives the source clock and outputs the clock clk0. There is a phase difference between clk0 and the source clock, and the magnitude of the phase difference is controlled by the controller 110. The first chip 130 (hereinafter referred to as chip 1) receives clk0 and outputs clk1, the second chip receives clk1 and outputs clk2... and so on until the 6th chip receives clk5 and outputs clk6.
[0023] It is assumed that the clock will generate a phase delay of 1° when passing through each chip. When the phase difference between the chip output clock and the source clock is greater than 4°, the chip will not work properly. Assuming there is no controller and phase-locked loop, the phase difference between clk0 and the source clock is 0°. The clock phase offsets of the 6 chips are clk1 = 1°, clk2 = 2°, clk3 = 3°, clk4 = 4°, clk5 = 5°, clk6 = 6° respectively. clk5 and clk6 are greater than 4°, and chip 5 and chip 6 will not work properly.
[0024] To solve the above problems, in the prior art, the controller 110 will adjust the output clock of the phase-locked loop 120 and advance the phase of clk0. For example, if clk0 = -3°, then clk1 = -2°, clk2 = -1°, clk3 = 0°, clk4 = 1°, clk5 = 2°, clk6 = 3°. At this time, the phase differences between the output clocks of the 6 chips and the source clock are all less than 4°, and all chips can work properly.
[0025] However, in practical applications, it is very difficult to accurately calculate how many degrees the phase of the clock shifts after passing through each chip, and it is also very difficult to determine how many degrees the phase of clk0 should be advanced. Therefore, in traditional solutions, a clock training method is adopted, and the specific process of clock training is as follows:
[0026] First, advance the phase of clk0 by a relatively large degree. For example, clk0 = -15°. Then the output clocks of each chip are clk1 = -14°, clk2 = -13°, clk3 = -12°, clk4 = -11°, clk5 = -10°, clk6 = -9°. At this time, the phase differences between the output clocks of all chips and the source clock are greater than 4°, and all chips cannot work properly;
[0027] Then add a clock phase step value to the phase of clk0. For example, 1°. At this time, clk0 = -14°. Then the output clocks of each chip are clk1 = -13°, clk2 = -12°, clk3 = -11°, clk4 = -10°, clk5 = -9°, clk6 = -8°. At this time, the phase differences between the output clocks of all chips and the source clock are greater than 4°, and all chips cannot work properly;
[0028] ……
[0029] Then add another clock phase step value to the phase of clk0. For example, 1°. At this time, clk0 = -5°. Then the output clocks of each chip are clk1 = -4°, clk2 = -3°, clk3 = -2°, clk4 = -1°, clk5 = 0°, clk6 = 1°. At this time, the phase differences between the output clocks of all chips and the source clock are not greater than 4°, and all chips can work properly;
[0030] Then add another clock phase step value to the phase of clk0. For example, 1°. At this time, clk0 = -4°. Then the output clocks of each chip are clk1 = -3°, clk2 = -2°, clk3 = -1°, clk4 = 0°, clk5 = 1°, clk6 = 2°. At this time, the phase differences between the output clocks of all chips and the source clock are not greater than 4°, and all chips can work properly;
[0031] ……
[0032] Then add another clock phase step value to the phase of clk0. For example, 1°. At this time, clk0 = -2°. Then the output clocks of each chip are clk1 = -1°, clk2 = 0°, clk3 = 1°, clk4 = 2°, clk5 = 3°, clk6 = 4°. At this time, the phase differences between the output clocks of all chips and the source clock are not greater than 4°, and all chips can work properly;
[0033] Then, let the phase of clk0 be increased by a clock phase step value, such as 1°. At this time, clk0 = -1°. Then the output clocks of each chip are clk1 = 0°, clk2 = 1°, clk3 = 2°, clk4 = 3°, clk5 = 4°, clk6 = 5°. At this time, the phase difference between the output clock clk6 of chip 6 and the source clock is greater than 4°, and chip 6 cannot work properly;
[0034] ……
[0035] As can be seen from the above clock training process, when -5° ≤ clk0 ≤ -2°, all chips can work properly. clk0 finally takes the average value of -5° and -2°, clk0 = (-5 + -2) / 2 = -3.5°.
[0036] The above discussion is a simplification of the actual situation. In actual applications, there may be dozens or even hundreds of chips in the computing board, and the phase delay of the clock after passing through each chip is not necessarily 1°. During the clock training process, the clock phase step value may be very small, so the number of iterations of the clock phase will be very large, and the clock training will consume a long time.
[0037] The phase-locked loop 120 can adjust the phase of the output clock clk0 according to the signal transmitted by the controller 110. The phase-locked loop mainly includes a frequency discriminator and phase detector 121, a loop filter 122, and a voltage-controlled oscillator 123. The function of the frequency discriminator and phase detector 121 is to compare the frequency and phase differences between the clock to be detected and the source clock, and then output a signal related to the frequency and phase differences. In this embodiment, assuming that it is required that clk0 is 4° ahead of the source clock in phase, the frequency discriminator and phase detector 121 will detect whether the phase difference between clk0 and the source clock is 4°. If the phase difference is 4°, the frequency discriminator and phase detector 121 outputs 0. If the phase difference is greater than 4°, the frequency discriminator and phase detector 121 outputs a positive value. If the phase difference is less than 4°, the frequency discriminator and phase detector 121 outputs a negative value. The signal output by the frequency discriminator and phase detector 121 is sent to the loop filter 122. The function of the loop filter 122 is to filter out the noise signal and only retain the useful signal. The phase difference signal filtered by the loop filter 122 is sent to the voltage-controlled oscillator 123. The function of the voltage-controlled oscillator 123 is to change the phase of the output signal clk0 of the phase-locked loop 120 according to the magnitude of the phase difference. For example, if the target requires that clk0 is 4° ahead of the source clock in phase, and the frequency discriminator and phase detector 121 detects that clk0 is 5° ahead of the source clock in phase, which is 1° more advanced, the frequency discriminator and phase detector 121 sends out the phase difference value. After passing through the loop filter 122, when the voltage-controlled oscillator 123 receives the phase difference value, it adjusts the phase of the output clock clk0 of the phase-locked loop, and finally makes the phase of clk0 equal to the target phase.
[0038] In the above discussion, the phase of clk0 needs to satisfy -5° ≤ clk0 ≤ -2°. The final value of clk0 is = ((-5) + (-2)) / 2 = -3.5°. At this time, the clock phases of the 6 chips are clk1 = -2.5°, clk2 = -1.5°, clk3 = -0.5°, clk4 = 0.5°, clk5 = 1.5°, clk6 = 2.5°. Observing the above data, it can be found that there are a total of 6 chips, and the phase of the output clock of the chip in the middle (chip No. 3 or chip No. 4) is very close to the phase of the source clock. Thus, by generalization, assuming there are N chips (N > 1), when N is even, the phase of the output clock of the N / 2 or N / 2 + 1 chip is very close to the phase of the source clock. When N is odd, the phase of the output clock of the (N + 1) / 2 chip is very close to the phase of the source clock. In this embodiment, we call these chips intermediate chips. Based on this, as Figure 1 shown, the embodiment of the present application provides a method for adjusting the phase of the output clock of a computing board phase-locked loop, and its specific process is as follows:
[0039] S101. Obtain the output clock of the intermediate chip in a plurality of serially connected chips.
[0040] Among them, the output clock of the intermediate chip is based on the original output clock of the phase-locked loop.
[0041] In this embodiment, the output end of the intermediate chip is connected to the phase-locked loop 120. After the computing board is powered on, the frequency discriminator and phase detector 121 of the phase-locked loop 120 obtains the output clock of the intermediate chip from the output end of the intermediate chip.
[0042] S102. Calculate the phase difference ΔΦ between the output clock of the intermediate chip and the source clock. If the phase difference ΔΦ is not 0°, then adjust the phase of the output clock of the phase-locked loop to the difference between its original output clock phase and ΔΦ.
[0043] In this embodiment, when the controller 110 receives a feedback signal of abnormal operation from the chip, the controller 110 pre-sends a command to the phase-locked loop 120 to set the phase difference to be locked by the frequency discriminator and phase detector 121 of the phase-locked loop 120 to 0°. After the frequency discriminator and phase detector 121 obtains the output clock of the intermediate chip, calculate the phase difference ΔΦ between the output clock of the intermediate chip and the source clock. If the phase difference ΔΦ is not 0°, then the voltage-controlled oscillator 123 adjusts the phase of the output clock of the phase-locked loop to the difference between its original output clock phase and ΔΦ.
[0044] To Figure 4For example, after the computing board is powered on, the phase of the source clock is 0°, and the phase of the original output clock of the phase-locked loop 120 is clk0 = 1°. Assuming that the chip will introduce a phase delay of 1°, the clock phases of 6 chips are clk1 = 2°, clk2 = 3°, clk3 = 4°, clk4 = 5°, clk5 = 6°, clk6 = 7° respectively. Since clk4, clk5, and clk6 are greater than 4°, chips No. 4 to No. 6 cannot work properly. After the controller 110 receives the feedback signal of abnormal operation, it sets the phase difference to be locked of the frequency discriminator and phase detector 121 to 0°. The frequency discriminator and phase detector 121 obtains clk3 (4°) from chip No. 3, and the difference ΔΦ between it and the phase of the source clock (0°) is 4°, which is not 0°. At this time, the voltage-controlled oscillator 123 adjusts the phase of the output clock of the phase-locked loop 120 to its original output clock phase 1° - 4° = -3°. After adjustment, the clock phases of 6 chips are clk1 = -2°, clk2 = -1°, clk3 = 0°, clk4 = 1°, clk5 = 2°, clk6 = 3° respectively. The phase differences between the output clocks of all chips and the source clock are not greater than 4°, and all can work properly. Moreover, at this time, the phases of the output clocks of each chip are very close to the clock phases after training in the traditional method.
[0045] In the traditional method, the frequency discriminator and phase detector 121 compares the phase difference between the output clock of the phase-locked loop and the source clock. In the present invention, the output clock of the middle chip is connected to the frequency discriminator and phase detector 121, and the frequency discriminator and phase detector 121 compares the phase difference between the output clock of the middle chip and the source clock. In this way, when the phase of the output clock of the middle chip is consistent with the phase of the source clock, the effect of clock training is achieved.
[0046] As can be seen from the above, a method for adjusting the phase of the output clock of the phase-locked loop of a computing board provided by an embodiment of the present application adjusts the phase of the output clock of the phase-locked loop based on the output clock of the middle chip, so that the phase of the output clock of the middle chip is consistent with the phase of the source clock, ensuring that the phase differences of the output clocks of all chips meet the requirements for normal operation. In this way, although there is no clock training, the same effect as clock training is achieved, saving the time-consuming clock training step. The whole process is automatically completed inside the computing board without manual intervention, improving the work efficiency.
[0047] The following will describe in detail a device for adjusting the phase of the output clock of the phase-locked loop of a computing board according to one or more embodiments of the present invention. Those skilled in the art can understand that these devices can all be configured by using commercially available hardware components through the steps taught by this solution. Figure 2 FIG. shows a device for adjusting the phase of the output clock of the phase-locked loop of a computing board provided by an embodiment of the present invention, as Figure 2 shown. The device includes a first module 11 and a second module 12.
[0048] The first module 11 is configured to perform S101: obtain the output clock of the middle chip among multiple serially connected chips.
[0049] Among them, the output clock of the middle chip is based on the original output clock of the phase-locked loop.
[0050] In this embodiment, the output end of the middle chip is connected to the phase-locked loop 120. After the computing board is powered on, the frequency discriminator and phase detector 121 of the phase-locked loop 120 obtains the output clock of the middle chip from the output end of the middle chip.
[0051] The second module 12 is configured to perform S102: calculate the phase difference ΔΦ between the output clock of the middle chip and the source clock. If the phase difference ΔΦ is not 0°, then adjust the phase of the output clock of the phase-locked loop to the difference between its original output clock phase and ΔΦ.
[0052] In this embodiment, when the controller 110 receives a feedback signal of abnormal operation from the chip, the controller 110 pre-sends a command to the phase-locked loop 120 to set the phase difference to be locked by the frequency discriminator and phase detector 121 of the phase-locked loop 120 to 0°. After the frequency discriminator and phase detector 121 obtains the output clock of the middle chip, calculate the phase difference ΔΦ between the output clock of the middle chip and the source clock. If the phase difference ΔΦ is not 0°, then the voltage-controlled oscillator 123 adjusts the phase of the output clock of the phase-locked loop to the difference between its original output clock phase and ΔΦ.
[0053] In summary, the computing board phase-locked loop output clock phase adjustment device provided in the above embodiment can execute the computing board phase-locked loop output clock phase adjustment method provided in the foregoing embodiments.
[0054] With the same concept as above, the structure of the power consumption optimization device in the above Figure 2 shown chip design can be implemented as an electronic device. Figure 3 FIG. shows a schematic block diagram of the structure of an electronic device provided by an embodiment of the present invention.
[0055] Exemplarily, the electronic device includes a storage module 21 and a processor 22. The storage module 21 includes instructions loaded and executed by the processor 22. When the instructions are executed, the processor 22 executes the steps according to various exemplary embodiments of the present invention described in the above part of the computing board phase-locked loop output clock phase adjustment method of this specification.
[0056] It should be understood that the processor 22 can be a central processing unit (CPU), and the processor 22 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.
[0057] An embodiment of the present invention also provides a computer-readable storage medium that stores one or more programs. When the one or more programs are executed by a processor, the steps according to various exemplary embodiments of the present invention described in the above-described method for adjusting the output clock phase of a computing board phase-locked loop are implemented.
[0058] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof. In the hardware implementation, the division of the functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be executed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable storage medium, which can include a computer-readable storage medium (or non-transitory medium) and a communication medium (or transitory medium).
[0059] As is well known to those of ordinary skill in the art, the term computer-readable storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVDs) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, communication media typically contains computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.
[0060] Exemplarily, the computer-readable storage medium may be an internal storage unit of the electronic device in the foregoing embodiments, such as the hard disk or memory of the electronic device. The computer-readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the electronic device.
[0061] For the electronic device and the computer-readable storage medium provided in the foregoing embodiments, the phase of the output clock of the phase-locked loop is adjusted based on the output clock of the intermediate chip, so that the phase of the output clock of the intermediate chip is consistent with the phase of the source clock, ensuring that the output clock phases of all chips meet the requirements for normal operation. In this way, although there is no clock training, the same effect as clock training is achieved, saving the time-consuming clock training step. The whole process is automatically completed inside the computing board without manual intervention, improving work efficiency.
[0062] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these changes and modifications.
Claims
1. A method for adjusting the phase of the output clock of a computing board phase-locked loop, characterized in that, Including: S101. Obtain the output clock of the middle chip among multiple serially connected chips, where the output clock of the middle chip is based on the original output clock of the phase-locked loop; S102. Calculate the phase difference ΔΦ between the output clock of the middle chip and the source clock. If the phase difference ΔΦ is not 0°, then adjust the phase of the output clock of the phase-locked loop to the difference between its original output clock phase and ΔΦ.
2. A method for adjusting the phase of the output clock of a computing board phase-locked loop according to claim 1, characterized in that, The output end of the middle chip is connected to the phase-locked loop. S101 further includes: The frequency discriminator and phase detector of the phase-locked loop obtains the output clock of the middle chip from the output end of the middle chip.
3. A method for adjusting the phase of the output clock of a computing board phase-locked loop according to claim 1, characterized in that, When the total number N of chips on the computing board is even, the middle chip is the N / 2-th or (N / 2 + 1)-th chip. When the total number N of chips on the computing board is odd, the middle chip is the (N + 1) / 2-th chip.
4. A method for adjusting the phase of the output clock of a computing board phase-locked loop according to claim 3, characterized in that S102 further includes: The controller of the computing board pre-sends a command to the phase-locked loop to set the phase difference to be locked by the frequency discriminator and phase detector of the phase-locked loop to 0°; After the frequency discriminator and phase detector obtains the output clock of the middle chip, calculate the phase difference ΔΦ between the output clock of the middle chip and the source clock; If the phase difference ΔΦ is not 0°, then the voltage-controlled oscillator of the phase-locked loop adjusts the phase of the output clock of the phase-locked loop to the difference between its original output clock phase and ΔΦ.
5. A calculation board phase-locked loop output clock phase adjustment device, characterized in that, Including: The first module is used for S101. Obtain the output clock of the middle chip among multiple serially connected chips, where the output clock of the middle chip is based on the original output clock of the phase-locked loop; The second module is used for S102. Calculate the phase difference ΔΦ between the output clock of the middle chip and the source clock. If the phase difference ΔΦ is not 0°, then adjust the phase of the output clock of the phase-locked loop to the difference between its original output clock phase and ΔΦ.
6. The phase adjustment device for the output clock of the computing board phase-locked loop according to claim 5, characterized in that, The output end of the middle chip is connected to the phase-locked loop. S101 further includes: The frequency discriminator and phase detector of the phase-locked loop obtains the output clock of the middle chip from the output end of the middle chip.
7. A phase adjustment device for the output clock of a computing board phase-locked loop according to claim 5, characterized in that When the total number N of chips on the computing board is even, the middle chip is the N / 2-th or (N / 2 + 1)-th chip. When the total number N of chips on the computing board is odd, the middle chip is the (N + 1) / 2-th chip.
8. The phase adjustment device for the output clock of the computing board phase-locked loop according to claim 6, characterized in that, S102 further includes: The controller of the computing board pre-sends a command to the phase-locked loop to set the phase difference to be locked by the frequency discriminator and phase detector of the phase-locked loop to 0°; After the frequency discriminator and phase detector obtains the output clock of the middle chip, calculate the phase difference ΔΦ between the output clock of the middle chip and the source clock; If the phase difference ΔΦ is not 0°, then the voltage-controlled oscillator of the phase-locked loop adjusts the phase of the output clock of the phase-locked loop to the difference between its original output clock phase and ΔΦ.
9. An electronic device, characterized in that, Including a storage module, the storage module includes instructions loaded and executed by a processor. When the instructions are executed, the processor executes a method for adjusting the phase of the output clock of a phase-locked loop of a computing board according to any one of claims 1-4.
10. A computer-readable storage medium storing one or more programs, characterized in that, When executed by a processor, the one or more programs implement a method for adjusting the output clock phase of a computing board phase-locked loop according to any one of claims 1-4.