Automatic frequency calibration circuit and phase-locked loop

Abstract

The invention relates to the technical field of automatic frequency calibration, and discloses an automatic frequency calibration circuit and a phase-locked loop. The automatic frequency calibration circuit comprising a frequency discriminator and an analog-to-digital converter is constructed, and the frequency of a frequency division signal fdiv and the frequency of a reference clock signal fREF are compared by using a signal comparison circuit and an integrating circuit in the frequency discriminator; the frequency division signal fdiv and the reference clock signal fREF are subjected to signal current difference and converted into a voltage signal, so that a voltage signal in direct proportion to the frequency difference of the frequency division signal fdiv and the reference clock signal fREF is output, the voltage signal is converted into a frequency control word of the VCO through the analog-to-digital converter, the frequency of the VCO is controlled to be increased or decreased, and finally the output frequency of the frequency divider is located near the reference frequency after stabilization. Compared with a traditional method, the method has the advantages that the time for automatically selecting the frequency band is greatly shortened, so that the stable time for switching the frequency of the phase-locked loop is greatly shortened, and rapid frequency switching of an electronic system is facilitated, especially for the electronic system needing rapid scanning of the wide-range frequency band, such as detection.

Description

Technical Field

[0001] The present invention relates to the technical field of automatic frequency calibration, and particularly to an automatic frequency calibration circuit and a phase-locked loop. Background Art

[0002] The principle of a typical phase-locked loop is as Figure 1 shown. Its operation starts from an externally input reference clock signal (f REF ), which usually comes from a crystal oscillator, etc. The reference clock signal serves as one input signal of the frequency discriminator and phase comparator, and its other input signal comes from the output feedback signal (f div ) of the N-divider. The frequency discriminator and phase comparator compares the phase difference between the reference clock signal and the feedback signal, and outputs a voltage pulse signal, the pulse width of which is proportional to the input phase difference, used to control the current source switch in the charge pump, so that the voltage pulse signal is converted into a current pulse signal of the same width. The current pulse is converted into an approximately direct current voltage V T after passing through the low-pass filter, which is used to adjust the output signal frequency of the voltage-controlled oscillator (VCO) ( f out ). At steady state, after the output signal of the VCO passes through the N-divider, its frequency and phase are consistent with the reference clock signal, so that a corresponding single-tone signal with stable frequency is obtained at the output. The relationship between its output signal frequency and the reference clock signal frequency is: .

[0003] A typical VCO structure is as Figure 2 shown. Its working principle is to generate a resonant signal using a resonant cavity composed of an inductor and a capacitor. The oscillation signal frequency is 1 / 2π(LC) 1 / 2 , the inductor L is the sum of L0 and L1 in Figure 2 , the capacitor C is the combined effect of C0, C1 and the capacitors in the capacitor array in the figure. The transistors M0 and M1 generate a negative resistance effect, which is used to offset the influence of the parasitic resistance of the inductor and capacitor. The tail current I B provides the bias current for the entire circuit. In order to obtain better output noise characteristics, the gain K T from the VCO input voltage V f out to the output frequency VCO needs to be set as small as possible; then from the application perspective, it is desirable that the VCO output frequency range is as wide as possible to adapt to more application scenarios. To meet the application requirements of the above two aspects, the frequency adjustment function of the VCO is achieved in two forms. One is the variable capacitors C0 and C1, whose capacitance values are controlled by the voltage V T , and V T is generated after filtering the output of the charge pump in the phase-locked loop. In order to obtain better noise characteristics, the adjustment range of C0 and C1 is often small; another way of frequency adjustment is achieved through a capacitor array controlled by a switch. AsFigure 2 As shown in the figure, by controlling the control words B0, B1, ……, B N-1 control each switch. When the switch is closed, it means that the capacitor connected to it is connected to the oscillator circuit. Conversely, one end of the capacitor connected to it is in an open state and will not affect the value of the resonant cavity capacitance. The comprehensive effect of adjusting the output frequency of the VCO is as Figure 3 shown, and the overall output frequency range is f 0~ f 1, which is divided into N segments by the frequency control words B0 to B N-1 , and the frequency range of each segment is controlled by the voltage V T in the phase-locked loop.

[0004] Due to the above VCO output frequency control method, before each phase-locked loop starts to work, it is necessary to select the appropriate frequency control word states B0~B N-1 so that the desired output frequency f out is within the frequency band selected by the frequency control words B0~B N-1 , and then the frequency of the VCO can be accurately locked to f out through the phase-locked loop. The functional module that automatically realizes frequency band selection (and the correct state of the frequency control word output) in the phase-locked loop system is usually called the automatic frequency calibration (AFC) circuit. In the current electronic system, the requirement for the frequency stabilization time of the output signal is relatively high, and the shorter the better. Reducing the time for the AFC circuit to realize automatic correct frequency band selection has become one of the key technologies in the application of the phase-locked loop.

[0005] The traditional process of realizing automatic frequency band selection is to sequentially try the N states of the frequency band selection control words B0~B N-1 , wait for a sufficient long time t s in each state, and then detect whether the loop can be normally locked. t s needs to be greater than the establishment time when the phase-locked loop is normally locked. This time is determined by the loop bandwidth (for example, when the phase-locked loop bandwidth is 100 kHz, the time constant for the output frequency to be established is 1 / 2π*100k≈1.5 us, and the establishment time usually needs to be greater than or equal to 10 times the time constant, that is, 15 us, to achieve sufficient output frequency accuracy). Therefore, the total time for frequency band selection will exceed N*15 us. Summary of the Invention

[0006] The present invention provides an automatic frequency calibration circuit and a phase-locked loop, aiming to solve at least one of the above technical problems.

[0007] To achieve the above object, the present invention provides an automatic frequency calibration circuit, including: A frequency discriminator, having a frequency-divided signal input terminal, a reference clock signal input terminal, and a voltage signal output terminal; Among them, the frequency discriminator includes a signal comparison circuit and an integration circuit. The signal comparison circuit is configured to perform a difference operation on the signal currents of the divided-frequency signal transmitted from the divided-frequency signal input terminal and the reference clock signal transmitted from the reference clock signal input terminal. The integration circuit is configured to convert the current difference into an output voltage and output it through the voltage signal output terminal; Among them, the divided-frequency signal is configured to be a first divided-frequency signal obtained by an N-divider dividing the first frequency signal output by the voltage-controlled oscillator; An analog-to-digital converter having a voltage signal input terminal and a control signal output terminal; Among them, the analog-to-digital converter receives the voltage signal output by the frequency discriminator through the voltage signal input terminal, converts the voltage signal into a digital signal, and then outputs it as a frequency control word through the control signal output terminal; Among them, the frequency control word is configured to be transmitted to the voltage-controlled oscillator to control the voltage-controlled oscillator to generate a second frequency signal, and drive the frequency of the second divided-frequency signal obtained by dividing the second frequency signal by the N-divider to gradually approach the reference clock signal.

[0008] Optionally, the signal comparison circuit includes: a first comparison branch circuit and a second comparison branch circuit. The first ends of the first comparison branch circuit and the second comparison branch circuit are configured to be connected to a common-mode level, and the second ends of the first comparison branch circuit and the second comparison branch circuit are configured to be connected to an intermediate node; Among them, the first comparison branch circuit and the second comparison branch circuit respectively include a series group of diodes with opposite access directions and a coupling capacitor connected in parallel to the series group of diodes; Among them, the intermediate node is configured to perform a difference operation on the signal currents of the divided-frequency signal input through the coupling capacitor and the reference clock signal and output the current difference to the integration circuit.

[0009] Optionally, the first comparison branch circuit includes a first diode, a second diode and a first coupling capacitor, and the second comparison branch circuit includes a third diode, a fourth diode and a second coupling capacitor; Among them, the positive electrode of the first diode is connected to the intermediate node, the positive electrode of the second diode is connected to the negative electrode of the first diode, the negative electrode of the second diode is connected to the common-mode level, the first end of the first coupling capacitor is connected between the first diode and the second diode, and the second end of the first coupling capacitor is connected to the reference clock signal input terminal; Among them, the positive electrode of the third diode is connected to the common-mode level, the positive electrode of the fourth diode is connected to the negative electrode of the third diode, the negative electrode of the fourth diode is connected to the intermediate node, the first end of the second coupling capacitor is connected between the third diode and the fourth diode, and the second end of the second coupling capacitor is connected to the divided-frequency signal input terminal.

[0010] Optionally, the integrating circuit includes an operational amplifier and an integrating capacitor; Wherein, the non-inverting input terminal of the operational amplifier is connected to the output terminal of the signal comparison circuit, and the inverting input terminal of the operational amplifier is connected to the common-mode level; Wherein, the first end of the integrating capacitor is connected to the non-inverting input terminal of the operational amplifier, and the second end of the integrating capacitor is connected to the output terminal of the operational amplifier.

[0011] Optionally, the potential of the output terminal of the signal comparison circuit is clamped to the common-mode level by the operational amplifier, and the current flowing through the integrating capacitor is the current difference obtained by subtracting the signal current of the divided-frequency signal from the reference clock signal; Wherein, the expression of the current difference is specifically:

[0012] In the formula, is the current flowing through the integrating capacitor, is the current value of the reference clock signal flowing into the intermediate node, is the current value of the reference clock signal flowing out from the intermediate node, is the charge injected into the intermediate node by the reference clock signal and the charge extracted from the intermediate node by each divided-frequency signal period in each reference period, is the value of the coupling capacitor, is the swing of the reference clock signal and the divided-frequency signal.

[0013] Optionally, the output voltage of the voltage signal output terminal of the integrating circuit is related to the charge accumulation amount at both ends of the integrating capacitor and is proportional to the integral of the current difference with respect to time, and the expression of the output voltage is specifically:

[0014] In the formula, C0 is the capacitance value of the integrating capacitor, is the output voltage varying with time t.

[0015] Optionally, the frequency discriminator further includes a filtering circuit disposed between the integrating circuit and the voltage signal output terminal, and the filtering circuit includes a filtering resistor connected in series between the frequency discriminator and the analog-to-digital converter and a filtering capacitor connected in parallel between the filtering resistor and the analog-to-digital converter. Optionally, when the automatic frequency calibration circuit controls the voltage-controlled oscillator to generate a second frequency signal and drives the second divided-frequency signal obtained by dividing the second frequency signal by the N-divider to gradually approach the frequency of the reference clock signal, the expression of the open-loop transfer function relied on is specifically: Wherein, MVCO is the gain of the output frequency change of the voltage-controlled oscillator controlled by the frequency control word converted from the voltage signal output by the frequency discriminator through the analog-to-digital converter, is the amplitude of the reference clock signal and the divided-frequency signal, is the value of the coupling capacitor, and C0 is the capacitance value of the integrating capacitor, is the filtering resistor, is the filtering capacitor, and s is the complex frequency domain variable.

[0016] Optionally, during the process that the automatic frequency calibration circuit controls the voltage-controlled oscillator to generate a second frequency signal and drives the frequency of the second divided-frequency signal obtained after dividing the second frequency signal by the N-divider to gradually approach the reference clock signal, the expression of the loop bandwidth is specifically: Wherein, MVCO is the gain of the output frequency change of the voltage-controlled oscillator controlled by the frequency control word converted from the voltage signal output by the frequency discriminator through the analog-to-digital converter, is the amplitude of the reference clock signal and the divided-frequency signal, is the value of the coupling capacitor, and C0 is the capacitance value of the integrating capacitor.

[0017] In addition, to achieve the above object, the present invention also provides a phase-locked loop, including: a voltage-controlled oscillator, an N-divider, and the automatic frequency calibration circuit described in any one of the above.

[0018] The beneficial effect of the present invention is that: an automatic frequency calibration circuit and a phase-locked loop are proposed. By constructing an automatic frequency calibration circuit including a frequency discriminator and an analog-to-digital converter, using the signal comparison circuit and the integration circuit in the frequency discriminator, the divided-frequency signal f div is compared with the reference clock signal f REF in terms of frequency. The signal currents of the divided-frequency signal f div and the reference clock signal f REF are subtracted to convert it into a voltage signal, so as to output a voltage signal proportional to the frequency difference between the two. After being converted by the analog-to-digital converter into the frequency control word of the VCO, the frequency of the VCO is controlled to increase or decrease. Finally, after stabilization, the output frequency of the divider is near the reference frequency. Compared with the traditional method, the present invention greatly reduces the time for automatic frequency band selection, thereby significantly reducing the stabilization time of the phase-locked loop frequency switching, which is beneficial to the fast frequency switching of the electronic system, especially for electronic systems such as detection that require fast scanning of a wide range of frequency bands. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1It is a typical architecture diagram of a phase-locked loop in the prior art; Figure 2 It is a typical VCO structure diagram; Figure 3 It is a schematic diagram of VCO frequency band control of a typical VCO structure; Figure 4 It is a schematic diagram of the automatic frequency calibration circuit of the present invention in the phase-locked loop; Figure 5 It is a circuit diagram of the frequency discriminator in the automatic frequency calibration circuit of the present invention; Figure 6 It is a schematic diagram of the simulation result of the automatic calibration loop bandwidth; Figure 7 It is a schematic diagram of the simulation result of the frequency stabilization time of the automatic calibration loop. Detailed implementation manners

[0020] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0021] The embodiment of the present invention provides an automatic frequency calibration circuit, including: A frequency discriminator, having a frequency-divided signal input terminal, a reference clock signal input terminal and a voltage signal output terminal; Wherein, the frequency discriminator includes a signal comparison circuit and an integration circuit. The signal comparison circuit is configured to perform a difference operation on the signal currents of the frequency-divided signal transmitted from the frequency-divided signal input terminal and the reference clock signal transmitted from the reference clock signal input terminal. The integration circuit is configured to convert the current difference into an output voltage and output it through the voltage signal output terminal; Wherein, the frequency-divided signal is configured to be a first frequency-divided signal obtained by dividing the first frequency signal output by a voltage-controlled oscillator by an N frequency divider; An analog-to-digital converter, having a voltage signal input terminal and a control signal output terminal; Wherein, the analog-to-digital converter receives the voltage signal output by the frequency discriminator through the voltage signal input terminal, converts the voltage signal into a digital signal and outputs it as a frequency control word through the control signal output terminal; Wherein, the frequency control word is configured to be transmitted to the voltage-controlled oscillator to control the voltage-controlled oscillator to generate a second frequency signal, and drive the frequency of the second frequency-divided signal obtained by dividing the second frequency signal by the N frequency divider to gradually approach the reference clock signal.

[0022] Specifically, as Figure 4As shown, the automatic frequency calibration circuit of this embodiment consists of a frequency discriminator circuit and an analog-to-digital converter (ADC) circuit. When the automatic frequency calibration circuit works, the VCO output signal enters the frequency discriminator through the N-divider, and the frequency discriminator compares the divided signal f div with the reference clock signal f REF in terms of frequency and outputs a voltage signal V FD that is proportional to the frequency difference between the two. After being converted by the analog-to-digital converter, it becomes the frequency control word of the VCO.

[0023] As Figure 5 shown, in the frequency discriminator circuit, the reference clock signal and the divided signal respectively pass through two coupling capacitors C C to the middle nodes of two groups of series diodes. Both groups of series diodes are connected to the common-mode level V CM on one side and V MID on the other side, but the directions of the two groups of series diodes are opposite. V MID goes through the integration circuit to V AMP , where the integration circuit is composed of an operational amplifier AMP and an integration capacitor C0. V AMP is filtered by the capacitor R and C1 and then goes to the output V FD of the frequency discriminator. Assuming that the diodes in the figure are ideal diodes, that is, the forward conduction voltage is 0 and there is no reverse leakage current (the analysis process of actual non-ideal diodes is similar and the same result can be obtained). If the swing amplitudes of the reference clock signal and the divided signal are both V A , then the charge injected into the V MID node by the reference clock signal in each reference period is C C *V A . Similarly, in each divided signal period, the charge drawn from the V MID node is also C C *V A , which is converted into current as:

[0024] Due to the clamping effect of the operational amplifier in the integrator, the potential of V MID is always clamped to V CM , then the current flowing through the integration capacitor C0 is equal to the difference between I REF and I div , that is, The output voltage V AMP of the integrator depends on the charge accumulation amount across the capacitor C0, that is, it is proportional to the integral of the current I AMP with respect to time, VAMP The voltage value filtered by the filter composed of resistor R and capacitor C1 is the output voltage V of the frequency discriminator FD .

[0025] As can be seen from the above description, when the frequency of the frequency divider is lower than the reference frequency, the current I AMP is positive, and the terminal voltage of V AMP gradually decreases with time accumulation, and the same is true for V FD . The output voltage V of the frequency discriminator FD is converted into a digital signal by the ADC to obtain the frequency control word of the VCO, which controls the increase of the frequency of the VCO; conversely, when the frequency of the frequency divider is higher than the reference frequency, the output voltage of the frequency discriminator rises, and after being converted into the VCO frequency control word by the ADC, it controls the decrease of the frequency of the VCO. Finally, after stabilization, the output frequency of the frequency divider is near the reference frequency, that is, the frequency of the VCO is at the output frequency desired by the application. The stabilization time of the entire automatic calibration depends on the bandwidth of the entire loop. From the above analysis process, the open-loop transfer function of the loop is where M VCO is the gain of the output voltage V of the frequency discriminator FD after being converted into the frequency control word through the ADC and controlling the change of the output frequency of the VCO. The loop bandwidth is By reasonably designing the above parameter values, the bandwidth of the AFC loop can be set, thereby determining the stabilization time of the AFC loop. For example, when setting V A = 1V, N = 100, C C = C0 = 10 pF, M VCO = 1 GHz / V, the AFC loop bandwidth is about 1.5 MHz, and the establishment time constant of the AFC loop is 0.1 us. After ten times the establishment time constant, that is, after 1 us, the AFC loop can reach sufficient stability, and the appropriate VCO frequency band control word can be obtained. Compared with the traditional method, the method described in the present invention greatly reduces the time for automatic frequency band selection, thereby significantly reducing the stabilization time of the PLL frequency switching, which is beneficial to the fast frequency switching of the electronic system, especially for electronic systems such as detection that require fast scanning of a wide range of frequency bands.

[0026] In order to more clearly demonstrate the performance superiority of the automatic frequency calibration circuit proposed by the present invention, the following provides the simulation result data of the automatic frequency calibration circuit of the present invention.

[0027] As Figure 6 shown,[[]] Figure 6 is the simulation result of the automatic calibration loop bandwidth. As can be seen from the figure, the AFC loop bandwidth is set to about 1.6 MHz. As Figure 7 shown,[[]] Figure 7This is the simulation result of the automatic calibration loop frequency stabilization time. As can be seen from the figure, when the AFC loop bandwidth is set to 1.6 MHz and the reference frequency is 100 MHz, after 1 us, the frequency of the VCO output signal after frequency division stabilizes to around 100 MHz.

[0028] In another embodiment, the present invention further provides a phase-locked loop, including: a voltage-controlled oscillator, an N-frequency divider, and the automatic frequency calibration circuit described in any one of the above.

[0029] For other embodiments or specific implementation manners of the phase-locked loop of the present invention, reference may be made to the above embodiments of each automatic frequency calibration circuit, which will not be elaborated herein.

[0030] It can be understood that in the description of this specification, the reference terms "an embodiment", "another embodiment", "other embodiments", or "the first embodiment to the Nth embodiment", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0031] It should be noted that in this article, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or system including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article, or system. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or system including that element.

[0032] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structure or equivalent process transformation made by using the description of the present invention specification and the accompanying drawings, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. An automatic frequency calibration circuit, characterized in that, Comprising: A frequency discriminator, having a frequency-divided signal input terminal, a reference clock signal input terminal, and a voltage signal output terminal; Wherein, the frequency discriminator includes a signal comparison circuit and an integration circuit. The signal comparison circuit is configured to perform a difference operation on the signal currents of the frequency-divided signal transmitted from the frequency-divided signal input terminal and the reference clock signal transmitted from the reference clock signal input terminal. The integration circuit is configured to convert the current difference into an output voltage and output it through the voltage signal output terminal; Wherein, the frequency-divided signal is configured to be a first frequency-divided signal obtained by dividing the first frequency signal output by a voltage-controlled oscillator by an N-divider; An analog-to-digital converter, having a voltage signal input terminal and a control signal output terminal; Wherein, the analog-to-digital converter receives the voltage signal output by the frequency discriminator through the voltage signal input terminal, converts the voltage signal into a digital signal, and outputs it as a frequency control word through the control signal output terminal; Wherein, the frequency control word is configured to be transmitted to the voltage-controlled oscillator to control the voltage-controlled oscillator to generate a second frequency signal, driving the frequency of the second frequency-divided signal obtained by dividing the second frequency signal by the N-divider to gradually approach the reference clock signal.

2. The automatic frequency calibration circuit according to claim 1, wherein, The signal comparison circuit includes: a first comparison branch circuit and a second comparison branch circuit. The first ends of the first comparison branch circuit and the second comparison branch circuit are configured to be connected to a common-mode level, and the second ends of the first comparison branch circuit and the second comparison branch circuit are configured to be connected to an intermediate node; Wherein, the first comparison branch circuit and the second comparison branch circuit respectively include a series diode group with opposite access directions and a coupling capacitor connected in parallel to the series diode group; Wherein, the intermediate node is configured to perform a difference operation on the signal currents of the frequency-divided signal input through the coupling capacitor and the reference clock signal and output the current difference to the integration circuit.

3. The automatic frequency calibration circuit according to claim 2, wherein The first comparison branch circuit includes a first diode, a second diode, and a first coupling capacitor. The second comparison branch circuit includes a third diode, a fourth diode, and a second coupling capacitor; Wherein, the positive electrode of the first diode is connected to the intermediate node, the positive electrode of the second diode is connected to the negative electrode of the first diode, the negative electrode of the second diode is connected to the common-mode level, the first end of the first coupling capacitor is connected between the first diode and the second diode, and the second end of the first coupling capacitor is connected to the reference clock signal input terminal; Wherein, the positive electrode of the third diode is connected to the common-mode level, the positive electrode of the fourth diode is connected to the negative electrode of the third diode, the negative electrode of the fourth diode is connected to the intermediate node, the first end of the second coupling capacitor is connected between the third diode and the fourth diode, and the second end of the second coupling capacitor is connected to the frequency-divided signal input terminal.

4. The automatic frequency calibration circuit according to claim 1, wherein The integration circuit includes an operational amplifier and an integration capacitor; Wherein, the non-inverting input terminal of the operational amplifier is connected to the output terminal of the signal comparison circuit, and the inverting input terminal of the operational amplifier is connected to the common-mode level; Wherein, the first end of the integration capacitor is connected to the non-inverting input terminal of the operational amplifier, and the second end of the integration capacitor is connected to the output terminal of the operational amplifier.

5. The automatic frequency calibration circuit according to claim 4, characterized in that The potential at the output terminal of the signal comparison circuit is clamped to the common-mode level by the operational amplifier, and the current flowing through the integration capacitor is the current difference obtained by subtracting the signal current of the frequency-divided signal from the signal current of the reference clock signal; Among them, the expression of the current difference is specifically: Wherein, is the current flowing through the integrating capacitor, is the current value of the reference clock signal flowing into the intermediate node, is the current value of the reference clock signal flowing out from the intermediate node, is the charge injected into the intermediate node by the reference clock signal and the charge drawn from the intermediate node in each period of the divided frequency signal in each reference period, is the value of the coupling capacitor, is the swing of the reference clock signal and the divided frequency signal.

6. The automatic frequency calibration circuit according to claim 5, wherein The output voltage of the voltage signal output terminal of the integrating circuit is related to the charge accumulation amount across the integrating capacitor and is proportional to the integral of the current difference over time. The expression of the output voltage is specifically as follows: ​ where C0 is the capacitance value of the integrating capacitor, is the output voltage varying with time t.

7. The automatic frequency calibration circuit according to claim 1, wherein The frequency discriminator further includes a filter circuit disposed between the integration circuit and the voltage signal output terminal. The filter circuit includes a filter resistor connected in series between the frequency discriminator and the analog-to-digital converter and a filter capacitor connected in parallel between the filter resistor and the analog-to-digital converter.

8. The automatic frequency calibration circuit according to claim 7, characterized in that, When the automatic frequency calibration circuit controls the voltage-controlled oscillator to generate a second frequency signal and drives the frequency of the second divided signal obtained after dividing the second frequency signal by the N-frequency divider to gradually approach the reference clock signal, the expression of the open-loop transfer function is specifically: Wherein, MVCO is the gain of the output frequency change of the voltage-controlled oscillator controlled by the frequency control word obtained by converting the voltage signal output by the frequency discriminator through the analog-to-digital converter, is the swing of the reference clock signal and the divided-frequency signal, is the value of the coupling capacitor, and C0 is the capacitance value of the integrating capacitor, is the filter resistor, is the filter capacitor, and s is the complex frequency domain variable.

9. The automatic frequency calibration circuit according to claim 1, wherein When the automatic frequency calibration circuit controls the voltage-controlled oscillator to generate a second frequency signal and drives the frequency of the second divided signal obtained after dividing the second frequency signal by the N-frequency divider to gradually approach the reference clock signal, the expression of the loop bandwidth is specifically: Wherein, MVCO is the gain of the output frequency change of the voltage-controlled oscillator controlled by the frequency control word converted from the voltage signal output by the frequency discriminator through the analog-to-digital converter, is the swing of the reference clock signal and the divided-frequency signal, is the value of the coupling capacitor, and C0 is the capacitance value of the integrating capacitor.

10. A phase-locked loop, characterized in that, Including: A voltage-controlled oscillator, an N-frequency divider, and the automatic frequency calibration circuit according to any one of claims 1-9.

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