Data processing method and device, electronic equipment, chip and storage medium

Abstract

The invention provides a data processing method and device, electronic equipment, a chip and a storage medium, and relates to the technical field of data processing.The method comprises the steps that a first index of to-be-decoded data in an index set is determined; obtaining an initial interleaving address associated with the first index; and determining an interleaving code associated with the first index based on the initial interleaving address and a preset row and column operation rule. Therefore, the interleaving code associated with the first index is calculated through the first index and the row and column operation rule, the use condition of modular operation can be reduced through row and column operation, consumption of calculation resources is avoided, efficiency can be well improved under the condition of high speed or large data flow, and in some low-power-consumption or resource-limited environments, the interleaving code associated with the first index is calculated through the interleaving code associated with the first index. Power consumption and performance requirements can be balanced, and the reliability of a communication system is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data processing, and in particular, to a method, apparatus, electronic device, chip, and storage medium for processing data. Background Art

[0002] The function of channel coding is to perform error control. Digital signals are affected by noise and other factors during transmission and may experience errors. To reduce errors, the channel encoder adds protection components (supervisory code elements) to the transmitted information code elements according to certain rules to form anti-interference coding.

[0003] The Turbo code decoder can be used for channel coding in the LTE (Long Term Evolution) system.

[0004] However, when generating the interleaving order of the inner interleaver, the Turbo code decoder needs to perform a lot of modulo operations, with a relatively high computational complexity and a large consumption of computing resources. Summary of the Invention

[0005] The present disclosure provides a method, apparatus, electronic device, chip, and storage medium for processing data, aiming to at least solve one of the technical problems in the related art to some extent.

[0006] The first aspect of the embodiments of the present disclosure provides a method for processing data, including:

[0007] Determine a first index of the data to be decoded in the index set;

[0008] Obtain an initial interleaving address associated with the first index;

[0009] Determine an interleaved code associated with the first index based on the initial interleaving address and a preset row-column operation rule.

[0010] The second aspect of the embodiments of the present disclosure provides a data processing apparatus, including:

[0011] A first determination module, configured to determine a first index of the data to be decoded in the index set;

[0012] An acquisition module, configured to obtain an initial interleaving address associated with the first index;

[0013] A second determination module, configured to determine an interleaved code associated with the first index based on the initial interleaving address and a preset row-column operation rule.

[0014] A third aspect embodiment of the present disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the data processing method of the embodiments of the present disclosure.

[0015] A fourth aspect embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the data processing method disclosed in the embodiments of the present disclosure.

[0016] A fifth aspect embodiment of the present disclosure provides a chip, including a processor and an interface, where the processor is configured to read instructions to execute the data processing method disclosed in the embodiments of the present disclosure.

[0017] In the embodiments of the present disclosure, first, a first index of the data to be decoded in the index set is determined, then an initial interleaving address associated with the first index is obtained, and finally, based on the initial interleaving address and a preset row-column operation rule, an interleaved code associated with the first index is determined. Thus, by calculating the interleaved code associated with the first index through the first index and the row-column operation rule, the use of modulo operations can be reduced through row-column operations, thereby avoiding the consumption of computing resources. In the case of high rates or large data traffic, the efficiency can be improved well. In some low-power or resource-constrained environments, the power consumption and performance requirements can be balanced, improving the reliability of the communication system.

[0018] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, where:

[0020] Figure 1 is a flowchart of the data processing method according to the first embodiment of the present disclosure;

[0021] Figure 2 is a flowchart of the data processing method according to the second embodiment of the present disclosure;

[0022] Figure 3 is a schematic diagram of the data processing device according to the embodiments of the present disclosure;

[0023] Figure 4 is a block diagram of a chip for implementing the data processing method according to the embodiments of the present disclosure;

[0024] Figure 5 It is a block diagram of an electronic device for implementing the data processing method of the embodiments of the present disclosure. Specific embodiments

[0025] Here, some embodiments of the present disclosure will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. Various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described herein will become apparent after understanding the present disclosure. For example, the order of the operations described herein is merely an example and is not limited to those set forth herein, but may be changed as will be apparent after understanding the present disclosure, except for operations that must be performed in a specific order. Additionally, descriptions of features known in the art may be omitted for the sake of clarity and conciseness.

[0026] The embodiments described in some embodiments of the present disclosure below do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0027] The function of channel coding is to perform error control. Digital signals are affected by noise and other factors during transmission and may experience errors. To reduce errors, the channel encoder adds a protection component (supervisory symbol) to the transmitted information symbols according to certain rules to form "anti-interference coding". The channel decoding at the receiving end decodes according to the corresponding inverse rules to detect or correct errors and improve the reliability of the communication system.

[0028] Turbo codes are used for channel coding in the LTE (Long Term Evolution) system.

[0029] It should be noted that the core idea of Turbo codes is that they are formed by parallel concatenation of two or more systematic convolutional encoders with feedback via an interleaver. The original data first passes through a component encoder (usually referred to as component encoder 1), and then through a random interleaver for rearrangement of the data. The interleaved data then enters a second component encoder (component encoder 2) for encoding. In this way, the original data is encoded twice, and different redundant information is added each time. Through parallel combination, Turbo codes can provide redundancy at different times and frequencies, improving the reliability and anti-interference ability of data transmission.

[0030] Among them, it should be noted that the execution subject of the data processing method in this embodiment can be a data processing device, which can be implemented in software and / or hardware. The execution subject of the data processing method in the embodiments of the present disclosure is any type of electronic device, such as a mobile phone, a smart bracelet, a tablet, a notebook, a desktop computer, a vehicle-mounted terminal, a smart home appliance, a wearable device, etc., or it can also be an Internet of Things device, or it can also be a processing chip inside the terminal, which is not limited herein.

[0031] In the embodiments of the present disclosure, the data processing method will be described by taking the "data processing device" as the execution subject to execute the data processing method, hereinafter simply referred to as the "device", which is not limited herein.

[0032] Figure 1 It is a schematic flowchart of the data processing method provided in the first embodiment of the present disclosure.

[0033] As Figure 1 shown, the method includes:

[0034] S101: Determine the first index of the data to be decoded in the index set.

[0035] It should be noted that in digital communication, sounds, images, or texts can all be converted into binary codes of 0 and 1. The converted data can be called raw data or raw information sequence.

[0036] Among them, the raw information sequence can be a string of binary bit sequences, consisting of 0 and 1. These bits represent the information content to be transmitted.

[0037] Among them, the data to be decoded can be any character unit in the raw information sequence, that is, a binary bit (0 or 1), which is not limited herein. For example, X = [0, 1, 1, 0, 1, 1, 1, 0] is an 8-bit raw information sequence, containing 8 data to be decoded. Optionally, the index values can be marked for each bit in the order from left to right.

[0038] It should be noted that in the LTE system, when processing the data to be decoded through a Turbo code interleaver, the range of the code length that can be selected can be from 40 to 6144, which is not limited herein.

[0039] Among them, the index set can adopt various forms and can be selected according to the application requirements and the nature of the data. For example, the index set can be in the form of an ordered array, a hash table, an inverted index, a search tree, a bitmap index, a spatial index, a table, etc., which is not limited herein.

[0040] As a possible implementation, in the embodiments of the present disclosure, the index set is embodied in the form of a numerical table. The index set can be constructed according to the current decoding method and the decoding. Different numerical values in the index set represent different index codes. In the following embodiments, the index table is taken as an example of the index set for exemplary illustration.

[0041] As shown in Table 1, this table is an index table with 16 rows and 8 columns. Col represents the column and row represents the row. A total of 128 numbers from 0 to 127 are divided into 16 rows and 8 columns.

[0042] Table 1 col_0 col_1 col_2 col_3 col_4 col_5 col_6 col_7 row_0 0 16 32 48 64 80 96 112 row_1 1 17 33 49 65 81 97 113 row_2 2 18 34 50 66 82 98 114 row_3 3 19 35 51 67 83 99 115 row_4 4 20 36 52 68 84 100 116 row_5 5 21 37 53 69 85 101 117 row_6 6 22 38 54 70 86 102 118 row_7 7 23 39 55 71 87 103 119 row_8 8 24 40 56 72 88 104 120 row_9 9 25 41 57 73 89 105 121 row_10 10 26 42 58 74 90 106 122 row_11 11 27 43 59 75 91 107 123 row_12 12 28 44 60 76 92 108 124 row_13 13 29 45 61 77 93 109 125 row_14 14 30 46 62 78 94 110 126 row_15 15 31 47 63 79 95 111 127

[0043] In the embodiments of the present disclosure, each value in the index table has corresponding row and column numbers. For example, the value 20 in Table 1 corresponds to row_4 and column col_1, that is, the 5th row and the 2nd column.

[0044] Among them, the first index can be the index information corresponding to the data to be decoded in the index table.

[0045] For example, in a raw information sequence with a code length of 128, the first index corresponding to the data A to be decoded in the index table is 46, and the first index corresponding to the data B to be decoded in the index table is 47.

[0046] Optionally, the index table can be constructed based on the decoding method and the code length used for decoding.

[0047] Among them, the decoding method can be a single-row decoding method, a double-parallel decoding method, a quadruple-parallel decoding method, an octuple-parallel decoding method, a sixteen-parallel decoding method, etc., which are not limited herein.

[0048] Among them, the code length can be determined according to actual needs, such as 40, 6144, etc., which are not limited herein.

[0049] It should be noted that different code lengths usually adopt different decoding methods. For example, for a relatively large code length, such as 6144, an octuple-parallel decoding method can be adopted, or other methods can also be adopted, which are not limited herein.

[0050] It should be noted that when constructing the index table, it can be constructed according to the decoding method and the code length.

[0051] For example, if the code length is 40, then the index table can include 40 index information (from 0 to 39). If the code length is 6144, then the index table can contain 6144 index information (from 0 to 6143).

[0052] Among them, the number of rows and columns of the index table can be determined according to the decoding method.

[0053] For example, if the current decoding method is an eight-parallel decoding method, the index table can be set as an 8-column table (alternatively, it can also be an 8-row table), which is not limited here. If the current decoding method is a four-parallel decoding method, the index table can be set as a 4-column table (alternatively, it can also be a 4-row table), which is not limited here.

[0054] For instance, if the current code length is 6144 and the decoding method is an eight-parallel decoding method, the index table can be constructed as an 8-column and 768-row table. If the current code length is 128 and the decoding method is an eight-parallel decoding method, the index table can be constructed as an 8-column and 16-row table (as shown in Table 1), which is not limited here.

[0055] S102: Obtain the initial interleaving address associated with the first index.

[0056] Among them, the interleaving address can be the position information corresponding to the interleaved code of any index in the index table.

[0057] Among them, the initial interleaving address can be the interleaving address of the reference index corresponding to the first index.

[0058] It should be noted that the interleaved codes and interleaving addresses of each reference index can be stored in the memory in advance, and the number of memories can be the same as the number of reference indexes.

[0059] Among them, the number of reference indexes can be determined by the decoding method. For example, if the current decoding method is an eight-parallel decoding method and the number of columns of the decoding table is 8 columns, then the number of reference indexes can be 8, and the interleaved codes and interleaving addresses and other information of each reference index are stored in 8 different memories respectively, which is not limited here.

[0060] Taking Table 1 in the above steps as an example, Table 1 is the index table corresponding to the eight-parallel decoding structure. Then, the interleaved codes and interleaving addresses corresponding to the indexes (reference indexes) in the first row of each column can be stored in memories w1, w2, w3, w4, w5, w6, w7, and w8 respectively. The 8 reference indexes in Table 1 are 0, 16, 30, 48, 64, 80, 96, and 112 respectively.

[0061] That is to say, w1 can store the interleaved code and interleaved address corresponding to "0", w2 can store the interleaved code and interleaved address corresponding to "16", w3 can store the interleaved code and interleaved address corresponding to "32", w4 can store the interleaved code and interleaved address corresponding to "48", w5 can store the interleaved code and interleaved address corresponding to "64", w6 can store the interleaved code and interleaved address corresponding to "80", w7 can store the interleaved code and interleaved address corresponding to "96", and w8 can store the interleaved code and interleaved address corresponding to "112".

[0062] As a possible implementation, the index in the first row of the column where any index is located can be used as the reference index corresponding to the any index. For example, for the index "78", the column where it is located is the 5th column, and the index in the first row of the 5th column is "64", so "64" is the reference index corresponding to "78".

[0063] Optionally, first determine the second index according to the position of the first index in the index table, and then read the initial interleaved address corresponding to the second index from the memory.

[0064] Among them, the second index can be the reference index corresponding to the first index in the index table.

[0065] For example, if the first index is "20" and its position in the index table is (col_1, row_4), that is, the 2nd column and the 5th row, the reference index corresponding to the first index is "16" in the first row of the 2nd column. Therefore, "16" can be used as the second index corresponding to the first index "20".

[0066] Among them, the initial interleaved address can be the interleaved address corresponding to the second index, that is, the interleaved address corresponding to the reference index of the first index.

[0067] Specifically, after determining the second index, the interleaved address corresponding to the second index can be read from the memory corresponding to the second index as the initial interleaved address.

[0068] S103: Determine the interleaved code associated with the first index based on the initial interleaved address and the preset row-column operation rule.

[0069] Among them, the preset row-column operation rule can be a preset interleaved calculation method, and this interleaved calculation method can be implemented by means of row-column decomposition.

[0070] Optionally, if (x_c, x_r) and (y_c, y_r) are added, the row-column operation rule can be as follows:

[0071] {z_c, z_r} = qr_cal(x_c, x_r, y_c, y_r)

[0072] delta = x_r + y_r - row_num

[0073] if (delta >= 0)

[0074] z_c = (x_c + y_c + 1) % col_num

[0075] z_r = x_r + y_r - row_num

[0076] else

[0077] z_c = (x_c + y_c) % col_num

[0078] z_r = x_r + y_r

[0079] Wherein, delta is the first discrimination value, z_c is the calculated column value, z_r is the calculated column value, x_c and x_r are the column and row corresponding to the index value x in the index table, y_c and y_r are the column and row corresponding to the index value y in the index table, row_num is the number of rows of the index table, and col_num is the number of columns of the index table.

[0080] In Table 1, each index value has a col and a row. Taking "25" as an example, its col and row are 1 and 9 respectively, and the col and row of "60" are 3 and 12 respectively. According to the above operation rules, "25" + "60" = (1, 9) + (3, 12) = (5, 5), that is, 85.

[0081] Wherein, the interleaved code associated with the first index can be the value corresponding to the interleaved address corresponding to the first index in the index table. For example, if the interleaved address corresponding to the first index is (5, 5), then the interleaved code associated with the first index is 85.

[0082] Optionally, the interleaved code Π(i) associated with the first index can be calculated by the following formula:

[0083] Π(i) = (i - 1) + d(i) i = 1, 2,..., K - 1; Π(0) = 0

[0084] In the above formula, d(i) is calculated as follows:

[0085] d(1) = f1 + f2

[0086] d(i) = d(i - 1) + f2 * 2 i = 2,..., K - 1; Π(0) = 0

[0087] Wherein, f1 and f2 are interleaver parameters (known parameters), K is the code length, and Π(0) is the interleaved code corresponding to the index value 0.

[0088] It should be noted that if the second index is m and the first index is n, where m < n, after determining the initial interleaving address Π(m), Π(n) can be deduced according to the above formula. For example, if the initial interleaving address is Π(16) and the first index is 18, then Π(17) = (16) + d(17) can be calculated first, and then Π(18) = (17) + d(18).

[0089] Among them, Π(18) is the interleaved code associated with the first index.

[0090] It should be noted that the addition operation in the formula for calculating the interleaved code Π(i) above adopts the row-column operation rule. The above example is only an illustrative description and is not limited here.

[0091] In the embodiments of the present disclosure, first, the first index of the data to be decoded in the index table is determined, then the initial interleaving address associated with the first index is obtained, and finally, based on the initial interleaving address and the preset row-column operation rule, the interleaved code associated with the first index is determined. Thus, by calculating the interleaved code associated with the first index through the first index and the row-column operation rule, the use of modulo operation can be reduced through row-column operation, thereby avoiding the consumption of computing resources. In the case of high rate or large data traffic, the efficiency can be improved well. In some low-power or resource-constrained environments, the power consumption and performance requirements can be balanced, and the reliability of the communication system is improved.

[0092] Figure 2 It is a schematic flowchart of the data processing method according to the second embodiment of the present disclosure. As Figure 2 shown, the method includes:

[0093] S201: Determine the first index of the data to be decoded in the index table.

[0094] S202: Obtain the initial interleaving address associated with the first index.

[0095] It should be noted that the specific implementation manners of steps S201 and S202 can refer to the above embodiments and will not be elaborated here.

[0096] S203: Determine multiple groups of accumulated values based on the interleaver parameters, where each group of accumulated values corresponds to an index.

[0097] It should be noted that the calculation of the interleaving order of the Turbo code inner interleaver involves two key interleaver parameters: f1 and f2, which are used to define the interleaving methods in two different stages of the interleaver respectively.

[0098] Among them, the interleaver parameters can be obtained by looking up a table. The interleaver parameters corresponding to different code lengths are usually different. Each code length has corresponding interleaver parameters. In the embodiments of the present disclosure, the interleaver parameters corresponding to the current code length of the Turbo code can be determined based on the code length.

[0099] As an example, the interleaver parameters can be determined from Table 5.1.3-3 in LTE protocol 36212. Among them, the specification 36212 in the LTE protocol refers to the protocol specification of the radio access network (E-UTRAN) of LTE. In LTE protocol 36212, Table 5.1.3-3 is related to the internal interleaver parameters of the Turbo code.

[0100] Table 2 is an index table with a code length K = 6144, f1 = 263, and f2 = 480 as an example, and decoding is performed in an eight-parallel manner.

[0101]

[0102]

[0103] Optionally, each accumulated value d(i) can be calculated through the following formula:

[0104] d(1) = f1 + f2

[0105] d(i) = d(i - 1) + f2 * 2i for i = 2,..., K - 1; Π(0) = 0

[0106] Among them, f1 and f2 are interleaver parameters, K is the code length, and Π(0) is the interleaved code corresponding to the index value 0.

[0107] Optionally, based on the interleaver parameters, calculations can be performed sequentially from the third index to the first index to obtain the accumulated value corresponding to each index, where the third index is greater than the second index and is adjacent to the second index.

[0108] For example, if the second index is 0, the third index is greater than the second index and is adjacent to the second index, so the third index is 1. If the first index is 3, then calculations can start from the third index 1 to respectively determine the accumulated values corresponding to "1", "2", and "3".

[0109] If f1 = 263 and f2 = 480, then in Table 2, the interleaved address (f1_c, f1_r) corresponding to f1 = (0, 263), and the interleaved address (f2_c, f2_r) corresponding to f2 = (0, 480).

[0110] Furthermore, it can be calculated that d(1) = f1 + f2 = (f1_c, f1_r) + (f2_c, f2_r) = (0, 743) = 743;

[0111] d(2) = d(1) + f2·2 = (0, 743) + (1, 192) = (2, 167) = 1703;

[0112] d(3) = d(2) + f2·2 = (2, 167) + (1, 192) = (3, 359) = 2663.

[0113] Wherein, f1_c and f1_r are respectively the column number and row number corresponding to the interleaver parameter f1 in the index table, and f2_c and f2_r are respectively the column number and row number corresponding to the interleaver parameter f2 in the index table. Therefore, the accumulated value corresponding to index "1" is 743, the accumulated value corresponding to index "2" is 1703, and the accumulated value corresponding to index "3" is "2663".

[0114] S204: According to the preset row-column operation rule, sequentially accumulate the initial interleaving address and each group of accumulated values in the first order to obtain the interleaved code corresponding to the first index.

[0115] Wherein, the first order is the order from the second index to the first index.

[0116] Optionally, the initial interleaving address and each group of accumulated values can be first decomposed into rows and columns to obtain the first row number and first column number corresponding to the initial interleaving address, and the second row number and second column number corresponding to each group of accumulated values. Then, according to the preset row-column operation rule and the first order, the second row number and second column number corresponding to each group of accumulated values, and the first row number and first column number can be accumulated to obtain the interleaved code corresponding to the first index.

[0117] Optionally, according to the preset row-column operation rule, the second row number and second column number corresponding to the third index, and the first row number and first column number can be added.

[0118] Wherein, the first row number and first column number refer to the row number and column number corresponding to the initial interleaving address in the index table.

[0119] Wherein, the second row number and second column number refer to the row number and column number corresponding to the third index in the accumulated value in the index table.

[0120] Wherein, the second row number and second column number corresponding to the third index are the row number and column number corresponding to the accumulated value corresponding to the third index in the index table.

[0121] Hereinafter, the accumulated value corresponding to any index x is denoted as d(x). Each index has a corresponding accumulated value, and each accumulated value has a corresponding second row number and second column number in the index table. For example, if the accumulated value is "2305", the second row number corresponding to "2305" in Table 2 is 1, and the second column number is 3.

[0122] For example, taking Table 2 as the index table, if the second index is "0", the third index is "1", and the first index is "3", the accumulated value corresponding to the third index is d(1), d(1) = f1 + f2 = (f1_c, f1_r) + (f2_c, f2_r) = (0, 743) = 743. Among them, the second row number and the second column number corresponding to "743" in Table 2 are 743 and 0 respectively. Therefore, the second row number and the second column number corresponding to the third index "1" are 743 and 0 respectively.

[0123] Among them, the interleaved code Π(0) corresponding to the second index = 0. The initial interleaved address is (0, 0), so the first row number and the first column number are 0 and 0 respectively.

[0124] Optionally, the first discrimination value can be determined first according to the second row number corresponding to the third index, the first row number corresponding to the initial interleaved address, and the number of rows of the index table.

[0125] Among them, the number of rows of the index table is the total number of rows of the index table. Taking Table 2 as an example, the number of rows of the index table corresponding to Table 2 is 768 rows.

[0126] Among them, the number of columns of the index table is the total number of columns of the index table. Taking Table 2 as an example, the number of columns of the index table corresponding to Table 2 is 8 columns.

[0127] As an exemplary illustration, when adding two numbers X and Y through the row-column operation rule, the row number and column number corresponding to X can be determined first, denoted as x_r and x_c, and the row number and column number corresponding to Y can be determined, denoted as y_r and y_c. Then, the row number and column number obtained by adding the two numbers X and Y through the row-column operation rule can be denoted as z_r and z_c respectively, that is, it can be expressed as {z_c, z_r} = qr_cal(x_c, x_r, y_c, y_r). qr_cal represents the row-column operation rule adopted.

[0128] It should be noted that when adding the second row number "743" and the second column number "0" corresponding to the third index "1" to the first row number "0" and the first column number "0" corresponding to the initial interleaved address, it can be denoted as {z_c, z_r} = qr_cal(0, 0, 0, 743).

[0129] The first discrimination value delta can be calculated by the following formula:

[0130] delta = x_r + y_r - row_num

[0131] Substituting the above parameters, delta = x_r + y_r - row_num = 0 + 743 - 768 = -25.

[0132] Further, when the first discrimination value is greater than or equal to the first threshold, the sum of the number of columns of the second column corresponding to the third index and the number of columns of the first column can be determined first, and then, based on the sum of the number of columns and the number of columns of the index table, the first cumulative number of columns corresponding to the third index can be determined. After that, the first discrimination value can be used as the first cumulative number of rows corresponding to the third index.

[0133] Among them, the first cumulative number of columns can be the number of columns obtained through the row-column operation rule when the first discrimination value is greater than or equal to the first threshold.

[0134] Among them, the first cumulative number of rows can be the number of rows obtained through the row-column operation rule when the first discrimination value is greater than or equal to the first threshold.

[0135] Among them, the first threshold can be determined according to actual needs. In the embodiments of the present disclosure, the first threshold can be 0, which is not limited herein.

[0136] Optionally, when calculating the first cumulative number of columns z_c1 and the first cumulative number of rows z_r1, the following formulas can be used:

[0137] z_c1 = (x_c + y_c + 1) % col_num

[0138] z_r1 = x_r + y_r - row_num

[0139] Alternatively, when the first discrimination value is less than the first threshold, the number of columns of the index table can be modulo-calculated based on the sum of the number of columns to obtain the second cumulative number of columns corresponding to the third index. Then, the sum of the number of rows of the second row corresponding to the third index and the number of rows of the first row corresponding to the initial interleaved address can be used as the second cumulative number of rows corresponding to the third index.

[0140] Among them, the second cumulative number of columns can be the number of columns obtained through the row-column operation rule when the first discrimination value is less than the first threshold.

[0141] Among them, the second cumulative number of rows can be the number of rows obtained through the row-column operation rule when the first discrimination value is less than the first threshold.

[0142] Combined with the above example, the value of the first discrimination value delta is "-25", which is less than the first threshold 0. Then, the second cumulative number of columns z_c2 and the second cumulative number of rows z_r2 can be further calculated through the following formulas:

[0143] z_c2 = (x_c + y_c) % col_num

[0144] z_r2 = x_r + y_r

[0145] Substituting the above parameters, z_c2 = (0 + 0) % 8 = 0, z_r2 = 0 + 743 = 743.

[0146] It should be noted that according to the calculation method described in the above example, when adding the second row number and the second column number corresponding to each accumulated value, and the first row number and the first column number in accordance with the preset row-column operation rules and the first order to obtain the interleaved code corresponding to the first index, the following process can be referred to:

[0147] Π(0) = (0,0) = 0

[0148] Π(1) = Π(0) + d(1) = (0,0) + (0,743) = (0,743) = 743

[0149] Π(2) = Π(1) + d(2) = (0,743) + (2,167) = (3,142) = 2446

[0150] Π(3) = Π(2) + d(3) = (3,142) + (3,359) = (6,501) = 5109

[0151] Wherein, d(1), d(2), and d(3) are the accumulated values corresponding to the indexes "1", "2", and "3" respectively, Π(0), Π(1), Π(2), and Π(3) are the interleaved codes corresponding to the indexes "0", "1", "2", and "3" respectively, (0,0), (0,743), (3,142), and (6,501) are the interleaved addresses corresponding to the interleaved codes "0", "743", "2446", and "5109" respectively, that is, the interleaved addresses corresponding to the indexes "0", "1", "2", and "3" respectively.

[0152] Wherein, (0,0) is the initial interleaved address. Since each index has a uniquely associated reference index (the reference index associated with the first index is denoted as the second index), and the uniquely associated reference index of the first index "3" is "0", thus the interleaved address (0,0) corresponding to the index "0" is used as the initial interleaved address associated with the first index.

[0153] Wherein, the interleaved address (6,501) corresponding to the first index "3", that is, the interleaved address corresponding to the data to be decoded, and the interleaved code "5109" corresponding to the first index "3", that is, the interleaved code corresponding to the data to be decoded.

[0154] In an embodiment of the present disclosure, first, a first index of the data to be decoded in the index set is determined, then an initial interleaving address associated with the first index is obtained, and then based on the interleaver parameters, multiple sets of accumulated values are determined, where each set of accumulated values corresponds to an index. Finally, according to the preset row-column operation rule, the initial interleaving address and each set of accumulated values are accumulated in the first order to obtain the interleaved code corresponding to the first index. Thus, by splitting the first index into a row-column format for accumulation, the modulo operation can be bypassed, and the next interleaving address can be directly calculated, reducing the use of the modulo operation, thereby avoiding the consumption of computing resources. In the case of high rate or large data traffic, the efficiency can be improved well. In some low-power or resource-constrained environments, the power consumption and performance requirements can be balanced, improving the reliability of the communication system.

[0155] Figure 3 is a schematic diagram of a data processing device according to an embodiment of the present disclosure. As Figure 3 shown, the data processing device 300 includes:

[0156] A first determination module 310, configured to determine a first index of the data to be decoded in the index set;

[0157] An acquisition module 320, configured to acquire an initial interleaving address associated with the first index;

[0158] A second determination module 330, configured to determine the interleaved code associated with the first index based on the initial interleaving address and the preset row-column operation rule.

[0159] Optionally, the first determination module 310 is further configured to:

[0160] Construct the index set based on the decoding method and code length used for decoding.

[0161] Optionally, the acquisition module 320 is specifically configured to:

[0162] Determine a second index according to the position of the first index in the index set;

[0163] Read the initial interleaving address corresponding to the second index from the memory.

[0164] Optionally, the second determination module 330 includes:

[0165] A first calculation unit, configured to determine multiple sets of accumulated values based on the interleaver parameters, where each set of accumulated values corresponds to an index;

[0166] An accumulation unit, configured to accumulate the initial interleaving address and each set of accumulated values in the first order according to the preset row-column operation rule to obtain the interleaved code corresponding to the first index,

[0167] Among them, the first order is the order from the second index to the first index.

[0168] Optionally, the first calculation unit is specifically configured to:

[0169] Based on the interleaver parameters, perform calculations sequentially from the third index to the first index to obtain the accumulated value corresponding to each index, where the third index is greater than the second index and the third index is adjacent to the second index.

[0170] Optionally, the accumulation unit includes:

[0171] A decomposition subunit, configured to perform row-column decomposition on the initial interleaving address and each group of accumulated values to obtain the first number of rows and the first number of columns corresponding to the initial interleaving address, and the second number of rows and the second number of columns corresponding to each group of accumulated values;

[0172] An accumulation subunit, configured to accumulate the second number of rows and the second number of columns corresponding to each group of accumulated values, and the first number of rows and the first number of columns according to a preset row-column operation rule and the first order to obtain the interleaved code corresponding to the first index.

[0173] Optionally, the accumulation unit includes an addition subunit, and the addition subunit is specifically configured to:

[0174] Add the second number of rows and the second number of columns corresponding to the third index, and the first number of rows and the first number of columns according to a preset row-column operation rule, including:

[0175] Determine a first discrimination value according to the second number of rows corresponding to the third index, the first number of rows corresponding to the initial interleaving address, and the number of rows of the index set;

[0176] When the first discrimination value is greater than or equal to a first threshold, determine the sum of the number of columns of the second number of columns corresponding to the third index and the first number of columns;

[0177] Determine the first accumulated number of columns corresponding to the third index according to the sum of the number of columns and the number of columns of the index set;

[0178] Take the first discrimination value as the first accumulated number of rows corresponding to the third index;

[0179] When the first discrimination value is less than the first threshold, perform modulo operation on the number of columns of the index set based on the sum of the number of columns to obtain the second accumulated number of columns corresponding to the third index;

[0180] Take the sum of the number of rows of the second number of rows corresponding to the third index and the first number of rows corresponding to the initial interleaving address as the second accumulated number of rows corresponding to the third index.

[0181] In the embodiments of the present disclosure, first, the first index of the data to be decoded in the index set is determined. Then, the initial interleaving address associated with the first index is obtained. Finally, based on the initial interleaving address and the preset row-column operation rule, the interleaved code associated with the first index is determined. Thus, by calculating the interleaved code associated with the first index through the first index and the row-column operation rule, the use of modulo operations can be reduced through row-column operations, thereby avoiding the consumption of computing resources. In the case of high rates or large data traffic, the efficiency can be improved well. In some low-power or resource-constrained environments, the power consumption and performance requirements can be balanced, and the reliability of the communication system is improved.

[0182] To implement the above embodiments, the present disclosure also proposes a chip, which includes a processor configured to execute the method provided in the foregoing embodiments.

[0183] Figure 4 It is a schematic structural diagram of the chip proposed in the embodiments of the present disclosure. Reference can be made to Figure 4 the schematic structural diagram of the chip 1100 shown, but not limited thereto.

[0184] The chip 1100 includes a processor 1101 configured to execute any of the above methods.

[0185] In some embodiments, the chip 1100 further includes one or more interfaces 1102. Optionally, the interface 1102 is connected to the memory 1103. The interface 1102 can be used to receive signals from the memory 1103 or other devices, and the interface 1102 can be used to send signals to the memory 1103 or other devices. For example, the interface 1102 can read the instructions stored in the memory 1103 and send the instructions to the processor 1101.

[0186] In some embodiments, the interface 1102 executes at least one of the communication steps such as sending and / or receiving in the above method, and the processor 1101 executes other steps.

[0187] In some embodiments, terms such as interface circuit, interface, transceiver pin, transceiver, etc. can be replaced with each other. In some embodiments, the chip 1100 further includes one or more memories 1103 for storing instructions. Optionally, all or part of the memories 1103 can be outside the chip 1100.

[0188] It should be noted that the chip 1100 proposed in the embodiments of the present disclosure can be a SOC chip, which is not limited herein.

[0189] Among them, SOC (System-on-a-Chip) is a system-level chip or system-on-chip, which is a programmable chip integrating multiple functions. By integrating multiple functional modules and peripheral interfaces on a single chip, it realizes various functions such as communication, computing, and control.

[0190] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0191] Figure 5 The block diagram of an exemplary electronic device suitable for implementing the embodiments of the present disclosure is shown. Figure 5 The displayed electronic device 12 is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present disclosure.

[0192] As Figure 5 shown, the electronic device 12 is presented in the form of a general-purpose computing device. The components of the electronic device 12 may include, but are not limited to: one or more processors or processing units 16, a system memory 28, and a bus 18 connecting different system components (including the system memory 28 and the processing unit 16).

[0193] The bus 18 represents one or more of several types of bus structures, including a memory bus or a memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the multiple bus structures. For example, these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnection (PCI) bus.

[0194] The electronic device 12 typically includes a variety of computer system-readable media. These media can be any available media accessible by the electronic device 12, including volatile and non-volatile media, removable and non-removable media.

[0195] The memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. The electronic device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 34 may be used for reading and writing on a non-removable, non-volatile magnetic medium ( Figure 5 not shown, commonly referred to as a "hard disk drive").

[0196] Although Figure 5 not shown in the figure, a disk drive for reading and writing on a removable non-volatile disk (such as a "floppy disk") and an optical disk drive for reading and writing on a removable non-volatile optical disk (such as a compact disc read only memory (CD-ROM), digital video disc read only memory (DVD-ROM) or other optical media) may be provided. In these cases, each drive may be connected to the bus 18 through one or more data media interfaces. The memory 28 may include at least one program product having a set (such as at least one) of program modules configured to perform the functions of the embodiments of the present disclosure.

[0197] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in the memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules 42 generally perform the functions and / or methods in the embodiments described in the present disclosure.

[0198] The electronic device 12 can also communicate with one or more external devices 14 (such as a keyboard, a pointing device, a display 24, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 12, and / or communicate with any device that enables the electronic device 12 to communicate with one or more other computing devices (such as a network card, a modem, etc.). Such communication can be carried out through the input / output (I / O) interface 22. Moreover, the electronic device 12 can also communicate with one or more networks (such as a Local Area Network (LAN), a Wide Area Network (WAN), and / or a public network, such as the Internet) through the network adapter 20. As shown in the figure, the network adapter 20 communicates with other modules of the electronic device 12 through the bus 18. It should be understood that although not shown in the figure, other hardware and / or software modules can be used in combination with the electronic device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0199] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the data processing method mentioned in the foregoing embodiments.

[0200] Those skilled in the art will readily think of other embodiments of the present disclosure after considering the specification and practicing the application disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include well-known common general knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0201] It should be understood that the present disclosure is not limited to the exact structures already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

[0202] It should be noted that in the description of the present disclosure, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0203] Any process or method description depicted in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present disclosure includes additional implementations where functions may be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0204] It should be understood that various parts of the present disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits with logic gate circuits for implementing logical functions on data signals, application specific integrated circuits with appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0205] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the method of implementing the above embodiments can be completed by instructing relevant hardware through a program. The said program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0206] In addition, in each of the embodiments of the present disclosure, the functional units can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage media mentioned above can be read-only memory, magnetic disks, optical discs, etc.

[0207] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0208] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A method for processing data, characterized in that, Including: Determine a first index of the data to be decoded in the index set; Obtain an initial interleaving address associated with the first index; Based on the initial interleaving address and a preset row-column operation rule, determine an interleaved code associated with the first index.

2. The method according to claim 1, wherein Before determining the first index of the data to be decoded in the index set, it further includes: Construct the index set based on the decoding method and code length used for decoding.

3. The method according to claim 1, wherein The obtaining of the initial interleaving address associated with the first index includes: Determine a second index according to the position of the first index in the index set; Read the initial interleaving address corresponding to the second index from the memory.

4. The method according to claim 3, wherein The determining of the interleaved code associated with the first index based on the initial interleaving address and a preset row-column operation rule includes: Based on the interleaver parameters, determine multiple groups of accumulated values, where each group of accumulated values corresponds to an index; According to the preset row-column operation rule, sequentially accumulate the initial interleaving address and each group of accumulated values in a first order to obtain the interleaved code corresponding to the first index, where the first order is the order from the second index to the first index.

5. The method according to claim 4, characterized in that, The determining of multiple groups of accumulated values based on the interleaver parameters includes: Based on the interleaver parameters, calculate sequentially from a third index to the first index to obtain the accumulated value corresponding to each index, where the third index is greater than the second index and the third index is adjacent to the second index.

6. The method according to claim 4, wherein The sequentially accumulating the initial interleaving address and each group of accumulated values in a first order according to the preset row-column operation rule to obtain the interleaved code corresponding to the first index includes: Perform row-column decomposition on the initial interleaving address and each group of accumulated values to obtain a first number of rows and a first number of columns corresponding to the initial interleaving address, and a second number of rows and a second number of columns corresponding to each group of accumulated values; According to the preset row-column operation rule and the first order, accumulate the second number of rows and the second number of columns corresponding to each group of accumulated values, and the first number of rows and the first number of columns to obtain the interleaved code corresponding to the first index.

7. The method according to claim 6, wherein Adding the second number of rows and the second number of columns corresponding to the third index, and the first number of rows and the first number of columns according to the preset row-column operation rule includes: Determine a first discrimination value according to the second number of rows corresponding to the third index, the first number of rows corresponding to the initial interleaving address, and the number of rows of the index set; When the first discrimination value is greater than or equal to a first threshold, determine the sum of the number of columns of the second number of columns corresponding to the third index and the first number of columns; Determine a first accumulated column number corresponding to the third index according to the sum of the number of columns and the number of columns of the index set; Use the first discrimination value as the first accumulated row number corresponding to the third index; When the first discrimination value is less than the first threshold, take the modulus of the number of columns of the index set based on the sum of the number of columns to obtain a second accumulated column number corresponding to the third index; Use the sum of the number of rows of the second number of rows corresponding to the third index and the first number of rows corresponding to the initial interleaving address as the second accumulated row number corresponding to the third index.

8. A data processing device, characterized in that, Including: A first determination module, configured to determine a first index of the data to be decoded in the index set; An acquisition module, configured to acquire an initial interleaved address associated with the first index; A second determination module, configured to determine an interleaved code associated with the first index based on the initial interleaved address and a preset row-column operation rule.

9. An electronic device, comprising: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the method according to any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-7.

11. A chip, characterized in that, Comprising a processor and an interface; The processor is configured to read instructions to execute the method according to any one of claims 1-7.

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