Determining interference in test channel

Abstract

The invention relates to determining interference in a test channel. An exemplary test system includes a signal receiver configured to receive (i) a reference signal and (ii) a test channel signal, and one or more processing devices configured to compare a pattern of the reference signal to a pattern of the test channel signal, to determine whether there is a predefined amount of interference in the test channel signal.

Description

Technical Field

[0001] This specification describes exemplary embodiments of techniques for determining interference in a test channel. Background Art

[0002] Interference can include electrical signals that can affect communication between devices. In the context of testing an electronic device, interference in a test channel can adversely affect tests performed by a test system on a device under test (DUT). Summary of the Invention

[0003] The present invention relates to an exemplary test system that includes a signal receiver and one or more processing devices. The signal receiver is configured to receive (i) a reference signal and (ii) a test channel signal. The one or more processing devices are configured to compare the pattern of the reference signal with the pattern of the test channel signal to determine whether a predefined amount of interference is present in the test channel signal. The exemplary test system can include one or more of the following features (individually or in combination).

[0004] The test system can include a signal generator configured to output a reference signal. The signal receiver can be configured to receive the reference signal from the signal generator and receive at least a portion of the test channel signal from the test channel. The test channel signal can include at least a portion of a copy of the reference signal. The one or more processing devices can be configured to compare the pattern of the reference signal with the pattern of the test channel signal to determine whether there is a difference between the pattern of the reference signal and the pattern of the test channel signal.

[0005] If the difference is less than a predefined threshold, the test channel signal does not have a predefined amount of interference. If the difference is greater than a predefined threshold, the test channel signal has a predefined amount of interference. The one or more processing devices can be configured to, in the case where the difference is greater than the predefined threshold, cause the signal generator to output a copy of the reference signal again. The predefined threshold can be at least partially based on the radio frequency (RF) and baseband stability of the test system.

[0006] The signal generator can include a vector signal generator (VSG). The signal receiver can include a vector signal analyzer (VSA) and an antenna. The test system can further include switches configured to connect the VSG to the VSA in a first configuration, connect the VSG to the antenna in a second configuration, and connect the VSA to the antenna in the second configuration.

[0007] Determining whether there is a predefined amount of interference in a test channel signal may include performing a correlation between a pattern of a reference signal and a pattern of the test channel signal. The one or more processing devices may be configured to synchronize the pattern of the reference signal with the pattern of the test channel signal before determining whether there is a predefined amount of interference in the test channel signal.

[0008] The reference signal and the test channel signal may include radio frequency (RF) signals. The test channel may be a wireless test channel. The test channel may be a wired test channel. The test channel signal may include at least one of the following interferences: one or more other signals in the test channel, or signals directed by a device under test (DUT) to the test system. The test channel signal may include data packets that would cause an acknowledgment if received by a device.

[0009] When the one or more processing devices determine that there is a predefined amount of interference in the test channel signal, the one or more processing devices may be configured to ignore data packets from the test channel.

[0010] An exemplary method includes receiving, at a signal receiver, (i) a reference signal and (ii) a test channel signal; and comparing the pattern of the reference signal with the pattern of the test channel signal to determine whether there is a predefined amount of interference in the test channel signal. The exemplary method may include one or more of the following features (individually or in combination).

[0011] The method may include: outputting a reference signal from a signal generator. The signal receiver may receive the reference signal from the signal generator and receive at least a portion of the test channel signal from the test channel. The test channel signal may include at least a portion of a copy of the reference signal. Comparing the pattern of the reference signal with the pattern of the test channel signal may include comparing the pattern of the reference signal with the pattern of the test channel signal to determine whether there is a difference between the pattern of the reference signal and the pattern of the test channel signal.

[0012] If the difference is less than a predefined threshold, the test channel signal does not have a predefined amount of interference. If the difference is greater than the predefined threshold, the test channel signal has a predefined amount of interference. The method may include, in the case where the difference is greater than the predefined threshold, causing the signal generator to output a copy of the reference signal again. The predefined threshold is at least partially based on the radio frequency (RF) and baseband stability of the system performing the method.

[0013] The signal generator may include a vector signal generator (VSG). The signal receiver may include a vector signal analyzer (VSA) and an antenna. The method may include configuring a switch to connect the VSG to the VSA in a first configuration, connect the VSG to the antenna in a second configuration, or connect the VSA to the antenna in the second configuration.

[0014] Determining whether there is a predefined amount of interference in a test channel signal may include performing a correlation between a pattern of a reference signal and a pattern of the test channel signal. The method may include synchronizing the pattern of the reference signal with the pattern of the test channel signal before determining whether there is interference in the test channel signal. The reference signal and the test channel signal may include radio frequency (RF) signals. The test channel may include a wireless test channel. The test channel may include a wired test channel.

[0015] The test channel signal may include at least one interference from: one or more other signals in the test channel, or signals directed by the DUT to the system performing the method. The test channel signal may include a data packet that would cause an acknowledgement if received by the device. When there is a predefined amount of interference in the test channel signal, the method may include ignoring data packets from the test channel.

[0016] An exemplary test system includes: a signal generator for outputting a data packet to a test channel; a signal receiver configured to receive (i) a reference signal and (ii) a test channel signal; and one or more processing devices configured to compare the pattern of the reference signal with the pattern of the test channel signal to make an inference as to whether the data packet has reached a device under test (DUT) via the test channel and to determine a performance metric based on the inference. The exemplary test system may include one or more of the following features (individually or in combination).

[0017] The one or more processing devices may be configured to ignore data packets on a test channel if it is inferred that a data packet has not reached the DUT. The one or more processing devices may be configured to determine that there is a predefined amount of interference on the test channel if a difference between a pattern of a reference signal and a pattern of a test channel signal exceeds a threshold. If the predefined amount of interference is determined, the inference may be that a data packet has not reached the DUT. The one or more processing devices may be configured to cause a signal receiver to implement a long capture consisting of a predefined number of data packets when interference is detected. The one or more processing devices may be configured to output a trigger in response to determining that there is a predefined amount of interference on the test channel. The trigger may be used to indicate that a subsequent action is to be taken. The one or more processing devices may be configured to ignore data packets received when there is a predefined amount of interference on the test channel. A performance metric may include a packet error rate.

[0018] Any two or more of the features described in this specification (including the summary section) may be combined to form a specific implementation not specifically described in this specification.

[0019] At least a portion of the devices, systems, and processes described in this specification may be configured, controlled, and / or implemented by executing instructions stored on one or more non-transitory machine-readable storage media on one or more processing devices. Examples of non-transitory machine-readable storage media include read-only memory, optical disk drives, memory disk drives, and random access memory. At least a portion of the devices, systems, and processes described in this specification may be configured, controlled, and / or implemented using a computing system consisting of one or more processing devices and a memory storing instructions that may be executed by the one or more processing devices to perform various control operations. The devices, systems, and processes described in this specification may be configured, for example, by design, construction, composition, arrangement, placement, programming, operation, activation, deactivation, and / or control.

[0020] Details of one or more specific implementations are set forth in the accompanying drawings and the following detailed description. Other features and advantages will be apparent from the specific implementation and drawings and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a block diagram showing an exemplary circuit configured to determine interference on a test channel.

[0022] Figure 2 is a block diagram showing Figure 1 the circuit in a first switch configuration.

[0023] Figure 3 is a block diagram showing Figure 1 the circuit in a second switch configuration different from the first switch configuration.

[0024] Figure 4 is a flowchart showing operations included in an exemplary process for determining interference on a test channel.

[0025] Figure 5 is showing Figure 1 an exemplary variation of a circuit.

[0026] Figure 6 is a graph showing cross-correlation values of signals captured from a test channel when no interference is known to be present on the test channel, and noise corresponding to those cross-correlation values generated by the test system.

[0027] Figure 7 is a graph showing correlation values for different interference signal powers.

[0028] Figure 8 includes an exemplary automatic test equipment component including a circuit similar to Figures 1 to 3 as well as Figure 5 a circuit.

[0029] Like reference numerals in different figures indicate like elements. Detailed Description

[0030] A test system, such as an automatic test equipment (ATE), is configured to test the operation of an electronic device referred to as a device under test (DUT). Examples of DUTs that can be tested by the test system include electronic devices such as wireless transmitters or microprocessors, and system-level devices such as smart phones.

[0031] The test system can include test instruments for testing the DUT. Part of the test process can include: transmitting signals (including data packets) between the test instruments and the DUT via one or more test channels. Exemplary test channels can be or include air / wireless transmission media and / or wired transmission media. Interference, especially on wireless test channels, can adversely affect communication between the DUT and the test instruments. Interference can include electrical signals on the test channel that affect communication. For example, interference can include stray electrical signals in the environment, and / or electrical signals sent to or received from other DUTs being tested or other devices not being tested. For example, interference can be caused by a collision of data packets. A data packet collision can be formed by two or more devices transmitting two or more data packets simultaneously onto the test channel.

[0032] The amount of interference that is tolerable for the DUT is referred to herein as an acceptable amount of interference. If there is more interference than the acceptable amount (which is referred to herein as an unacceptable amount of interference) present in the test channel, the communication between the DUT and the test instrument may be adversely affected. In one example, an unacceptable amount of interference may prevent the transmission and / or reception of data packets. In another example, an unacceptable amount of interference may corrupt data packets during transmission, preventing the DUT and / or the test instrument from decoding the data packets.

[0033] Described herein are examples of systems and processes for determining whether there is more than a predefined amount (e.g., an unacceptable amount of interference) present on a test channel and for taking action based on whether there is more than a predefined amount of interference present on the test channel. For example, if the test system or its components (such as a test instrument) determine that there is an unacceptable amount of interference present on the test channel, the test system may retransmit a test signal (including data packets) to the DUT. By having the test system retransmit the signal when there is an unacceptable amount of interference present on the test channel, the likelihood that the test system and / or the DUT will receive the transmitted signals and be able to understand them can be increased. Additionally, by analyzing the source signal, the systems and processes can infer whether the signal has degraded at the DUT and then flag such a condition and take appropriate action.

[0034] In some embodiments, the exemplary systems and processes may be configured to determine performance metrics for the communication between the test system and the DUT, such as a bit error rate (BER) or a packet error rate (PER). The BER is a metric related to signal integrity and is a measure based on the number of bits transmitted by a first device and received by a second device. The PER is a metric related to signal integrity and is a measure based on the number of data packets transmitted by a first device and received by a second device.

[0035] The test system or its components (such as a test instrument) may make an inference as to whether a data packet has reached the DUT via the test channel based on the amount of interference determined in the test channel. The test system may determine a performance metric based on this inference. For example, if the inference is that the data packet has reached the DUT, the PER may be determined to be less than in the case where the inference is that the data packet has not reached the DUT.

[0036] In some embodiments, the exemplary systems and processes may be configured to ignore data packets when it is determined that there is an unacceptable amount of interference present in the test channel. For example, when a data packet is marked as being among the interference at an unacceptable level, the test instrument transmitter counter may ignore the data packet. By ignoring data packets in these cases, the test system reduces the chance of relying on data packets that have been corrupted by interference during the test.

[0037] Figure 1 FIG. 1 is a block diagram of an exemplary circuit 10 that may be included in an exemplary test system 12. The circuit 10 is for use in an exemplary process of determining whether there is interference in a test channel. In this example, the circuit 10 is part of a test instrument 11 on the test system 12; however, the circuit 10 may be included in components of the test system other than the test instrument. In this example, the circuit 10 is configured to communicate wirelessly with a DUT 14, as described below. The DUT 14 may be any type of wireless electronic device, such as those identified herein.

[0038] As described below, the exemplary test instrument 11 is a hardware device. The test instrument 11 may include one or more processing devices 15 (examples of such one or more processing devices are described herein) for controlling the operation of the circuit 10 and for determining interference in the test channel. The test instrument 11 is configured to send a test signal to the DUT 14, receive a response from the DUT in the form of a response signal, and analyze these response signals to determine whether the DUT is operating correctly. The test signal may include a data packet indicating the operation of the DUT, and the response signal may include a data packet containing information on how to operate the DUT in response to the test signal. The exemplary test instrument 11 may also be configured to establish a connection to the DUT 14 before sending the test signal to the DUT 14. Any protocol may be used to establish such a connection. In a non-limiting example, the DUT 14 may be configured to output broadcast packets over a wireless test channel 16 within the range of the test instrument 11 such that the test instrument 11 can identify the DUT 14 for a wireless connection. The test instrument 11 may respond to the broadcast packet by sending a request packet to the DUT 14 requesting a wireless connection to the DUT 14. The DUT 14 may respond to the request packet by sending an acknowledgment packet to the test instrument 11. The acknowledgment packet may indicate that the DUT 14 has successfully received the request packet and that the wireless connection between the DUT 14 and the test instrument 11 is available or established. Examples of wireless connections that may be established in this manner include, but are not limited to, short-range wireless connections, such as those implemented under a standard. In some examples, the short-range wireless connection may be 40 meters (m) or less, 30 m or less, 20 m or less, 10 m or less, and so on.

[0039] In some embodiments, the circuit 10 includes a vector signal generator (VSG) 17, a vector signal analyzer (VSA) 19, an antenna 20, a splitter 21, switches 22 and 24, and an internal loopback (ILO) circuit 25.

[0040] Antenna 20 is an electrical conductor configured to transmit signals (such as data packets) to DUT 14 via wireless test channel 16. Antenna 20 is also configured to receive signals (such as data packets) from DUT 14 and other devices via wireless test channel 16. In this example, wireless test channel 16 includes one or more frequencies through which signals can be wirelessly transmitted between test system 12 and DUT 14. Some specific implementations may include a wired or partially wired test channel that replaces wireless test channel 16, as described herein. In a wired implementation, antenna 20 may be omitted from the hardware.

[0041] Exemplary VSG 17 is a hardware device configured to generate signals (including data packets) and output these signals to DUT 14 via wireless test channel 16. The signals may be or include radio frequency (RF) signals for testing the DUT and / or for establishing a connection to the DUT. For example, VSG 17 may be configured to: generate a request packet and output the request packet via wireless test channel 16 to establish a connection with the DUT; and / or generate data packets containing test vectors for testing the DUT and output those data packets containing the test vectors to DUT 14 via wireless test channel 16.

[0042] Exemplary VSA 19 is a hardware device configured to receive signals containing data packets from wireless test channel 16 and identify these signals by measuring parameters of the received signals (such as amplitude and / or phase). For example, VSA 19 may be configured to compare the received signals with one or more reference signals or with one or more thresholds to identify one or more parameters for the received signals. VSA 19 may be configured to provide an analog or digital form of the received signals to processing device 15 in test instrument 11 for processing.

[0043] In some specific implementations, VSG 17 and VSA 19 may be separate hardware devices. In some specific implementations, VSG 17 and VSA 19 may be combined into a single hardware device. In some specific implementations, one or more semiconductor devices (such as transistors, diodes, and / or integrated circuits) may be used to implement VSG 17 and VSA 19. In some specific implementations, one or more processing devices (such as those described herein) may be used to implement VSG 17 and VSA 19, the one or more processing devices being configured to execute instructions stored in a memory to implement VSA and VSG functions. In some specific implementations, a combination of one or more semiconductor devices and one or more processing devices may be used to implement VSG 17 and VSA 19.

[0044] In some specific embodiments, the splitter 21 is a hardware device that can be electrically connected to the VSG 17 and the VSA 19 via switches 22 and 24 respectively, and the hardware device is electrically connected to the antenna 20. The splitter 21 includes active and / or passive circuits for receiving, copying, routing, and outputting signals. In some specific embodiments, the splitter 21 is configured to receive a signal from the VSG 17 at port 21a and output copies of the received signal at ports 21b and 21c. The copies of the signal output by the splitter 21 at ports 21b and 21c may have a lower (reduced) power than the initial signal at the input port 21a. For example, each signal output at ports 21b and 21c may have approximately half of the signal power of the corresponding signal received at port 21a. The splitter 21 is also configured to receive signals from the antenna 20 (such as but not limited to interference signals on a test channel) at port 21c and output those same signals to the VSA 19 at port 21b. If there is interference while the VSG 17 is transmitting, the output of the splitter 21 to the VSA 19 becomes the signal from the VSG plus the interference signal.

[0045] The switches 22 and 24 can be electronic switches, mechanical switches, or electromechanical switches. In some specific embodiments, the switches 22 and 24 can be controlled to switch back and forth between a first configuration and a second configuration along arcuate members 22a and 24a respectively, which will be described below.

[0046] The processing device 15 on the test instrument 11 can control the operations of the switches 22 and 24 and the operations of the VSG 17 and the VSA 19 according to a test program executed on the processing device. The processing device 15 can include any type of device programmable to perform functions. Examples of different types of processing devices that can be used are described herein.

[0047] In some specific embodiments, a control system of the type described below can include a processing device 26. The control system, either alone or in combination with the test instrument 11, can control the operations of the switches 22 and 24 and the operations of the VSG 17 and the VSA 19 according to a test program executed on the processing device 26.

[0048] The ILO circuit 25 can be or include a conductive conduit that can be connected to the switches 22 and 24 at its different ends 25a and 25b respectively. The connections between the two ends 25a and 25b of the ILO circuit 25 and the corresponding switches 22 and 24 form a circuit between the VSA 17 and the VSG 19, through which electrical signals can be directly transmitted between the VSA 17 and the VSG 19 within the test instrument 11.

[0049] As Figure 2As shown, in the first configuration, switches 22 and 24 are configured to be electrically connected to the ILO circuit 25, and thereby electrically connect the VSG 17 to the VSA 19 via the ILO circuit 25. In the first configuration, signals are directly transmitted between the VSG 17 and the VSA 19 - for example, transmitted from the VSG 17 to the VSA 19 through the ILO circuit 25. In this exemplary configuration, the signal from the VSG 17 does not pass through the splitter 21 to the antenna 20.

[0050] As Figure 3 shown, in the second configuration, the switch 22 is configured to electrically connect the VSG 17 to the splitter 17, and thereby electrically connect the VSG to the antenna 20 via the splitter 21. The switch 24 is configured to electrically connect the VSA 19 to the splitter 21, and thereby electrically connect the VSA 19 to the antenna 20 via the splitter 21. In the second configuration, signals are transmitted between the splitter 21, the VSG 17, the antenna 20, and the VSA 19. In an exemplary operation in the second configuration, the VSG 17 outputs a signal, and the splitter 21 generates a power-reduced copy of the signal from the VSG 17 and sends these power-reduced copies to the VSA 19 and the antenna 20. At the same time, the splitter 21 receives the signal from the antenna 20, and outputs those received signals from the antenna 20 to the VSA 19.

[0051] The splitter 21 is configured to simultaneously output to the VSA 19 the signal received from the antenna 20 and the power-reduced copy of the signal received from the VSG 17 via the port 21b (which is electrically connected to the VSA 19 in the second configuration), such that the signal received from the antenna 20 overlaps with the power-reduced copy of the signal received from the VSG 17 at the port 21b. In the examples described herein, "simultaneously" includes: at least a portion of the power-reduced copy of the signal from the VSG 17 and at least a portion of the signal from the antenna 20 that are simultaneously output from the port 21b to the VSA 19. The effect of the signal overlap can be to incorporate the interference (if any) from the test channel 16 into the signal output by the VSG 17 (including its power-reduced copy), thereby allowing the VSA 19 to sense the combined VSG signal and interference as if they would appear on the wireless test channel 16. The combined VSG signal and interference are thus referred to as the test channel signal because the combined VSG signal and interference are similar to or equivalent to the combination of the VSG signal and interference that would appear on the wireless test channel 16. For example, the interference fading (path loss) to the test instrument and the DUT may be unknown. Therefore, the ratio of the combined signals may be different from the ratio on the test channel 16.

[0052] In the foregoing example, the interference that is part of the test channel signal includes the signal received from the wireless test channel 16. The VSG signal is received at the VSA 19 from the VSG 17 via the splitter. In some specific embodiments, the splitter 21 is configured such that all VSG signals are output from the antenna 20 to the wireless test channel 16 and then received by the antenna 20 on the wireless test channel 16 while the antenna 20 receives interference. In this example, the entire test channel signal is detected by the antenna 20 and passed from the antenna 20 to the splitter 21 and from the splitter 21 to the VSA 19. The following describes this example with respect to Figure 5 This example is described.

[0053] Figure 4 is a flowchart showing operations included in an exemplary process 30 that can be performed by components of Figures 1 to 3 to determine whether there is an unacceptable amount of interference in the test channel and to take action based on whether there is an unacceptable amount of interference in the test channel. The exemplary operations of process 30 under "one or more processing devices" can be performed in whole or in part by the processing device 15; the exemplary operations of process 30 under "VSG" can be performed in whole or in part by the VSG 17; and the exemplary operations of process 30 under "VSA" can be performed in whole or in part by the VSA 19.

[0054] Process 30 includes: the processing device 15 configures (30a) the switches 22 and 24 to be electrically connected to the ILO circuit 25 in the Figure 2 configuration shown (i.e., the first configuration) such that the signal output from the VSG 17 can be directly passed from the VSG 17 to the VSA 19; in other words, such that those signals do not pass through the splitter 21 and the antenna 20. Also see Figure 2 , the processing device 15 controls the VSG 17 to output (30b) the reference signal 31. In some specific embodiments, as part of the test process, the reference signal 31 can be a signal that the test instrument 11 will send to the DUT 14 or that the test instrument 11 is sending to the DUT 14. For example, the reference signal 31 can be any type of signal, such as the above test signal or request packet. In some specific embodiments, the reference signal 31 can be a random signal that is not sent to the DUT. For example, the reference signal 31 can be a random signal generated by the VSG just for testing interference on the wireless test channel 16.

[0055] The VSA 19 receives (30c) a reference signal 31 via the ILO circuit 25. The VSA 19 is configured to identify (30d) the reference signal 31. The VSA 19 can identify the reference signal 31 by measuring parameters of the reference signal 31 such as amplitude and / or phase. The VSA 19 outputs (30d) the reference signal 31 to the processing device 15. The output reference signal can be an analog or digital form of the original reference signal 31, which itself can be an analog or digital signal.

[0056] In some specific embodiments, techniques other than the internal loopback of the ILO circuit 25 can be used to obtain the reference signal. For example, the switches 22 and 24 can be configured and the VSG 17 can be controlled to output the reference signal to the wireless test channel 16 or directly to another device. The reference signal can be obtained from the wireless test channel 16 in the absence of interference.

[0057] The process 30 includes: the processing device 15 configures (30e) the switches 22 and 24 to be electrically connected to the splitter 21 in the Figure 3 configuration shown (i.e., the second configuration), such that the signal output from the VSG 17 is passed through the splitter 21. The processing device 15 controls the VSG 17 to output (30f) a signal as a copy 32 of the reference signal 31. The output copy 32 of the reference signal 31 can be referred to herein as a retransmitted or re - transmitted reference signal 31, or as another instance of the output reference signal 31. In this example, the splitter 21 receives the copy 32 of the reference signal 31 at port 21a and outputs a copy 33a of the reference signal 31 with reduced power at port 21b. As described above, each signal output at ports 21b and 21c can have approximately half of the signal power of the corresponding signal received at port 21a. Port 21b is electrically connected to the VSA 19 in the second configuration.

[0058] The splitter 21 can also output a copy 33b of the reference signal 31 with reduced power at port 21c electrically connected to the antenna 20. The copies 33a and 33b with reduced power can each have approximately half of the signal power of the reference signal 31. In this example, the antenna 20 transmits the copy 33b of the reference signal 31 with reduced power to the wireless test channel 16. The splitter 21 is also configured to receive the interference signal 34 obtained from the wireless test channel 16 from the antenna 20 at port 21c and output the interference signal 34 at port 21b. In some specific embodiments, the interference signal 34 can include any signal on the wireless test channel 16 that is not part of the communication between the test system 12 and the DUT 14 and that can be detected by the antenna 20. The interference signal 34 (if any) can also include signals attributable to the copy 33b of the reference signal 31 with reduced power output from the splitter 21 to the wireless test channel 16.

[0059] In this example, the VSA 19 receives (30g) a test channel signal 35 from port 21b of the splitter 21. The test channel signal includes: (i) a power-reduced copy 33a of the reference signal 31 from the splitter 21, and (ii) an interference signal 34 (if any) from the antenna 20.

[0060] The copy 32 of the reference signal 31 and the interference signal 34 may reach the splitter 21 from the VSG 17 and the antenna 20 simultaneously or substantially simultaneously, and thus, the power-reduced copy 33a of the reference signal 31 and the interference signal 34 may overlap to generate the test channel signal 35 at the splitter 21. Therefore, the test channel signal 35 received at the VSA 19 is similar to (although not necessarily equivalent to) the combination of the reference signal and any interference, as the two signals will appear on the wireless test channel 16. As described above, the problem of interference fading (path loss) may affect this combination. The VSA 19 is configured to identify (30h) the test channel signal 35. As described above, the VSA 19 may identify the test channel signal 35 by measuring parameters of the test channel signal 35 such as amplitude and / or phase. The VSA 19 outputs (30h) the test channel signal 35 to the processing device 15. The output test channel signal may be an analog or digital form of the original test channel signal 35, which itself may be an analog or digital signal.

[0061] As described above, in some specific embodiments, the splitter 21 may be configured such that a full-power copy 32 of the reference signal 31 received on port 21a of the splitter 21 is output from the antenna 20 to the wireless test channel 16 and is then detected by the antenna 20 together with the interference signal 34 on the wireless test channel 16. In this configuration, the signal paths between the VSG 17, the splitter 21, the antenna 20, and the VSA 19 are as Figure 5 shown. As Figure 5 shown, in this example, the entire test channel signal 35 is detected by the antenna 20 and then passed from the splitter 21 to the VSA 19. As described above, the VSA 19 identifies and outputs (30h) the test channel signal in analog or digital form.

[0062] As described above, the processing device 15 receives (30i) the reference signal 31 and the test channel signal 35 from the VSA 17. The processing device 15 synchronizes (30j) the reference signal 31 and the test channel signal 35. In some specific embodiments, the synchronization is performed with respect to the time, amplitude, phase, and frequency offsets of the reference signal 31 and the test channel signal 35. In some specific embodiments, the synchronization may include identifying portions of each signal (such as their preambles) such that when the reference signal 31 and the test channel signal 35 are compared in operation 30k of process 30 described below, the two signals are compared with respect to the same time points of each signal. The processing device 15 may also demodulate (30j) the reference signal 31 and the test channel signal 35. Demodulation may include obtaining an initial information signal from a modulated carrier signal (such as a frequency-modulated carrier signal). In some specific embodiments, the reference signal 31 and the test channel signal 35 may not be modulated and thus demodulation does not need to be performed.

[0063] The processing device 15 compares (30k) the form of the reference signal 31 with the form of the test channel signal 35 to determine whether there is a difference between the reference signal and the test channel signal. In some specific embodiments, the form of the reference signal 31 is the demodulated form of the reference signal 31, and the form of the test channel signal 35 is the demodulated form of the test channel signal 35. In some specific embodiments, the form of the reference signal 31 is the reference signal itself unchanged, and the form of the test channel signal 35 is the test channel signal itself unchanged. As described above, the comparison (30k) may be performed with respect to the same time points of each signal.

[0064] After synchronization (e.g., synchronization of time, amplitude, phase, frequency, and / or other characteristics), the difference (if any) between the reference signal and the test channel signal indicates the presence and amount of interference in the test channel signal. More specifically, since the test channel signal 35 is based on the reference signal 31 plus an interference signal 34 (if any) from the wireless test channel 16, the difference between the test channel signal 35 and the reference signal 31 (or their forms) may be attributed to interference on the wireless test channel 16.

[0065] In some specific implementations, the comparison (30k) can be performed by the processing device 15 that performs the cross-correlation between the pattern of the reference signal 31 and the pattern of the test channel signal 35. The cross-correlation is a measure of the difference between the pattern of the reference signal 31 and the pattern of the test channel signal 35. In one example, the cross-correlation is a measure of the difference between the pattern of the reference signal 31 and the pattern of the test channel signal 35 as a function of the displacement of one signal relative to the other signal. If the two signals are the same, the cross-correlation should produce a value of one. If the signals are different, the cross-correlation should produce a value other than one, where the magnitude of the value is based on the amount of the difference. For example, if the two signals have a cross-correlation value of zero, this means that the two signals do not have the same components.

[0066] In some specific implementations, the comparison (30k) can be performed by the processing device 15 subtracting one signal from the other. For example, since the pattern of the reference signal 31 and the pattern of the test channel signal 35 are time-synchronized, the processing device 15 can subtract the pattern of the reference signal 31 from the pattern of the test channel signal 35, or subtract the pattern of the test channel signal 35 from the pattern of the reference signal 31. The resulting difference is a measure based on or equal to the amount of interference on the wireless test channel 16.

[0067] The processing device 15 compares the determined difference between the pattern of the reference signal 31 and the pattern of the test channel signal 35 with a predefined threshold to determine (30l) whether there is interference greater than a predefined amount (e.g., an unacceptable amount) in the wireless test channel 16. The predefined threshold can be programmed into the processing device 15 by the user before the test, or the predefined threshold can be programmed into the processing device 15 by the test program. The predefined threshold can be at least partially based on the RF and baseband stability of the test system 12. The predefined threshold can be based on distribution data for the cross-correlation results when there is no interference in the test channel.

[0068] By way of example, Figure 6FIG. is a diagram showing the cross - correlation value 39 of a signal captured from the wireless test channel 16 when there is no interference on the known wireless test channel 16. The count 36 represents a random variation generated during the operation of the test system 12, which may be referred to as "tester uncertainty" 37. A predefined threshold can be selected to reduce the chance that this noise will affect the determination of the presence of interference on the test channel. For example, by selecting the threshold 40 as the predefined threshold, the likelihood that the noise (corresponding to the count 36) in the test system is identified as interference on the wireless test channel can be reduced. For example, by selecting the threshold 41 as the predefined threshold, the likelihood that the noise (corresponding to the count 36) in the test system prevents the process 30 from indicating the absence of interference or the presence of less than an acceptable amount of interference on the wireless test channel can be reduced. In this example, the threshold 41 can be used as the predefined threshold. In this regard, in some specific implementations, it may be more important to ensure that interference on the wireless test channel 16 is identified rather than preventing the noise in the test system from being identified as interference on the wireless test channel. Since the test system 12 is independent of the presence or absence of interference, false positive identifications (e.g., no interference but the process 30 indicates interference) will only increase the number of data packets transmitted, but have no effect on the true PER.

[0069] Referring back Figure 4 , in some specific implementations, if the difference is less than a predefined threshold, the wireless test channel 16 is considered to have no unacceptable amount of interference. For example, if the difference is less than the predefined threshold, the wireless test channel 16 can be considered to have no interference. In this case, the test can end (30m), start again, or continue. In some specific implementations, if the difference is greater than or equal to the predefined threshold, the wireless test channel 16 is considered to have an unacceptable amount of interference. For example, if the difference is greater than the predefined threshold, the wireless test channel 16 can be considered to have non - zero interference. In this case, the processing device can output a trigger indicating that one or more actions 44 are to be taken (30n).

[0070] In some specific implementations, the processing device 15 can configure the switches 22 and 24 such that the VSG 17 is in a second configuration ( Figure 3)The central electrical connection is to antenna 20, and the VSG 17 can be controlled to re - transmit (44a) a copy 32 of the reference signal 31, such that a copy 33b of the reference signal 31 with reduced power is again transmitted by antenna 20 onto the wireless test channel 16. This can be done, for example, in the case of interference testing and concurrently with communication with the DUT. For example, if process 30 determines that there is an unacceptable amount of interference (30l) on the wireless test channel 16, then the processing device 15 can make an inference as to whether the copy 33b of the reference signal with reduced power and one or more data packets contained therein reach the DUT 14 via the test channel 16 and / or are understandable by the DUT 14. That is, the processing device 15 can infer that one or more of the data packets in the data packet do not reach the DUT 14 and / or are not understandable by the DUT 14. In this case, re - transmitting the copy 33b of the reference signal with reduced power onto the wireless test channel 16 can increase the likelihood that the DUT 14 will receive the form 33 of the reference signal 31 (e.g., by trying again). When there is an unacceptable amount of interference on the test channel, the copy 33b of the reference signal with reduced power can be re - transmitted any number of times. In some specific implementations, the DUT 14 can confirm the copy 33b of the reference signal with reduced power, in which case the re - transmission (44a) can stop.

[0071] In some specific implementations, when it is determined that an unacceptable amount of interference exists on the test channel, the processing device can ignore (44b) the received data packets. The rationale here is that these data packets may be corrupted and that: (i) the corrupted data packets may adversely affect the test, and / or (ii) attempting to interpret and process the corrupted data packets may waste processing resources. The processing device 15 can wait until the amount of interference on the test channel is at an acceptable level before the processing device stops ignoring (44b) the data packets.

[0072] In some specific implementations, the processing device 15 can determine (44c) the PER and / or BER caused by the interference determined to exist on the test channel. This can be done in part by: tracking a first number of packets in the test channel signal containing interference, and subtracting the first number of packets from a second number of packets received from the DUT 14 that does not have interference. In some specific implementations, the PER determination is triggered only when the DUT does not reply with an acknowledgement to a transmitted signal (such as a request packet). In some specific implementations, the PER or BER determination can be performed at any time.

[0073] In some specific implementations, when an unacceptable amount of interference is determined to exist on the test channel, the processing device 15 may control the VSA 19 to perform a long capture (44d) of data packets on the wireless test channel 16. The long capture may include capturing a predefined number of data packets from the wireless test channel before and / or after a certain time point. For example, the predefined number of data packets may be 10, 15, 20, etc. Implementing the long capture may reduce the proportion of corrupted data packets received by the test system at a given time and may enable the corrupted data packets to be recovered.

[0074] In some specific implementations, the processing device 15 may concurrently perform two or more of the operations 44a to 44d. For example, operation 44c may be performed concurrently with operations 44a and / or 44d.

[0075] In some specific implementations, the process 30 may be configured to detect interference caused by a collision of data packets on the wireless test channel 16. For example, signals for a short-range wireless protocol (such as a standard) may include: broadcast packets (ADV) sent from the DUT 14, request packets (such as SCAN-REQ packets) sent by the test system 12 in response to these broadcast packets, and acknowledgment packets (such as SCAN_RESP packets) sent by the DUT to the test system in the case where the DUT correctly decodes the request packet. The request packet (such as SCAN_REQ) requests a connection to the DUT. The acknowledgment packet (such as the SCAN_RESP packet) serves as an acknowledgment that the DUT has correctly received the request packet (such as the SCAN-REQ packet).

[0076] In In standard communication, interference may be caused by the collision of data packets. For example, in a multi-DUT or open environment test configuration, a SCAN_REQ packet sent by the test system may collide with other data packets on the wireless test channel 16 (e.g., ADV or SCAN_RESP packets from other DUTs), which generates spurious, unexpected, and / or unintended interference signals on the wireless test channel. A DUT (such as DUT 14) may be unable to correctly decode the SCAN_REQ packet due to this interference formed by the collision. Process 30 can be used to infer one or more SCAN_REQ packets that have collided with other packets in the wireless test channel 16 based on their transmission time and the time of detecting the interference. To determine the PER, the processing device 15 can ignore the SCAN_REQ packets that are considered to have collided with other packets on the wireless test channel. Therefore, the accuracy of receiver-side PER determination can be improved. In some specific implementations, process 30 can be executed when the DUT does not respond to the SCAN_REQ packet (which means the SCAN_REQ may have collided with another packet).

[0077] Figure 7 is a graph showing the correlation values 45 for different interference signal powers 46 measured in dBm (decibels-milliwatts). As shown, when the VSG 17 transmits the SCAN_REQ packet at a power 47 of -30 dBm, the correlation threshold is approximately 0.999, and process 30 can mark the interference when the interference power is higher than approximately

[0078] -70 dBm 48 (which is where the correlation starts to decline). This interference may be the result of a collision of the transmitted SCAN_REQ packets on the wireless test channel.

[0079] Figures 1 to 3 and Figure 5 The circuit 10 can be part of the ATE. Figure 8 is a block diagram showing exemplary components of an exemplary ATE 50 including a test device / apparatus (also referred to as a "tester") 51 and a control system 52.

[0080] The ATE 50 includes a test head 54. The test head 54 includes a plurality of test instruments 54a to 54n (where n > 3), each of which can be configured to implement Figures 1 to 3 and Figure 5 the test and / or functionality of the test instrument 11. Although only four test instruments are shown, the ATE 50 can include any appropriate number of test instruments, including one or more test instruments located outside the test head 54. The test instruments can be hardware devices that can each include Figures 1 to 3 and Figure 5one or more processing devices 15 and / or circuitry 10 (shown only for test instrument 54n). The test instrument may be configured (e.g., programmed) to output test signals to test a DUT, such as DUT 14. Test signals for testing a DUT may be or include: commands, instructions, data, parameters, variables, test vectors, and / or any other information designed to elicit a response from the DUT. Each test instrument may be configured to establish a wireless connection with the DUT, as described with respect to test instrument 11. Signals for establishing the wireless connection (such as RF signals) may include data packets (such as request packets), including those used in short-range wireless protocols, such as standards). These signals may include test signals, such as those previously described. One or more processing devices 15 may also execute instructions to communicate with control system 52 and / or analyze responses to test signals.

[0081] One or more wireless test channels, such as test channel 16, are configured between the test head and various DUTs to enable communication between the DUT and the test instrument. Signals (such as RF signals) may be transmitted between the test system and the DUT via the wireless test channel. One or more of the test channels in the test channel may be a wired test channel (not shown), through which signals (such as RF signals) may be transmitted between the test system and the DUT. For example, the wired test channel may include a transmission line or coaxial cable for transmitting RF signals. In some embodiments, the test channel may include a combination of a wired test channel and a wireless test channel. In some embodiments, an individual test channel may have one or more wired portions and one or more wireless portions.

[0082] The control system 52 may be configured (e.g., programmed) to communicate with test instruments 54a to 54n to direct and / or control the testing of the DUT and to configure the circuit 10 during implementation of process 30. In some embodiments, this communication 57 may be via a computer network or via a direct connection (such as a computer bus or optical medium). In some implementations, the computer network may be or include a local area network (LAN) or a wide area network (WAN). The control system may be or include a computing system that includes: one or more processing devices 26 (e.g., microprocessors), and a memory 56 for storing instructions for controlling the operation of the ATE and / or the testing. Memory 55 also stores one or more test programs 55 for execution and / or for sending to the test instruments for execution. In this regard, the control system 52 may be configured to provide test programs 55 and / or test signals to test instruments 54a to 54n in the test head, and these test instruments use the test programs and / or test signals to test the DUT. The control system 52 may also be configured to receive DUT response signals (e.g., measurement data) from the test instruments and determine whether the corresponding DUT has passed or failed the test.

[0083] In some embodiments, the control functionality is centralized in the processing device 26. In some embodiments, all or part of the functionality attributable to the control system 52 may also be or alternatively implemented on the test instruments, and / or all or part of the functionality attributable to one or more test instruments may also be or alternatively implemented on the control system 52. For example, the control system may be distributed across the processing device 15 and one or more test instruments 54a to 54n.

[0084] All or part of the systems and processes described herein (including but not limited to process 30) and their modifications may be implemented, configured, and / or controlled at least in part by one or more computers using one or more computer programs tangibly embodied in one or more information carriers, such as one or more non-transitory machine-readable storage media. The computer programs may be written in any form of programming language, including compiled or interpreted languages, and they may be deployed in any form, including as stand-alone programs or as modules, parts, subroutines, or other units suitable for the computing environment. The computer programs may be deployed to execute on one computer or on multiple computers that are distributed at one site or across multiple sites and interconnected.

[0085] Actions associated with implementing, configuring, or controlling the test systems and processes described herein may be performed by one or more programmable processors that execute one or more computer programs to control or perform all or some of the operations described herein. All or part of the test systems and processes may be implemented, configured, or controlled by dedicated logic circuitry, such as FPGAs (field programmable gate arrays) and / or ASICs (application specific integrated circuits), or embedded microprocessors localized to instrument hardware.

[0086] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only storage area or a random access storage area or both. Elements of a computer include one or more processors for executing instructions and one or more storage area devices for storing instructions and data. Generally, a computer will also include (or be operatively coupled to receive data from or transfer data to, or both) one or more machine readable storage media, such as mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks. Non-transitory machine readable storage media suitable for embodying computer program instructions and data include all forms of non-volatile storage area, including by way of example semiconductor storage area devices, such as EPROM (erasable programmable read only memory), EEPROM (electrically erasable programmable read only memory), and flash storage area devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM (compact disc read only memory) and DVD-ROM (digital versatile disc read only memory).

[0087] The processes described herein are not limited to use with any particular wireless transmission protocol, such as . For example, and Wi-Fi may operate at the same frequency, and signals from both protocols may interfere. Performing process 30 in such a case will enable the identification of the presence of interference (including cases where lost data packets are identified), and will enable the identification of cases where there is no co-channel interference. Performing process 30 can be used to flag algorithmic issues that allow interference to exist. For example, some algorithms may attempt to ensure that there is no interference. Process 30 may be useful during the development of such algorithms. When interference occurs, process 30 can also be used to evaluate the robustness of the receiver. When interference is present, process 30 can be used to capture the behavior of all packets, such as timing information, etc. This information can be used to perform an analysis to identify the events on the test channel that caused the interference. In this regard, the test system can be designed to avoid interference, so there may be vulnerabilities in the system if interference occurs.

[0088] All of the examples described herein are non-limiting.

[0089] In the specification and claims provided herein, the adjectives "first", "second", "third", etc. do not specify a priority or order, unless the context otherwise indicates. Instead, these adjectives are merely used to distinguish the nouns they modify.

[0090] Any mechanical or electrical connection herein may include a direct physical connection or an indirect physical connection including one or more intermediate components. A connection between two conductive components includes an electrical connection, unless the context otherwise indicates. Signals described herein are electrical signals, unless the context otherwise indicates.

[0091] Elements of the different specific implementations described may be combined together to form other specific implementations not specifically set forth previously. Elements may be omitted from the previously described systems without generally adversely affecting their operation or the operation of the system. Additionally, the individual elements may be combined into one or more single elements to perform the functions described in this specification.

[0092] Other specific implementations not specifically described in this specification are also within the scope of the following claims.

Claims

1. A test system, comprising: A signal receiver configured to receive (i) a reference signal and (ii) a test channel signal; And One or more processing devices configured to compare the pattern of the reference signal with the pattern of the test channel signal to determine whether a predefined amount of interference is present in the test channel signal.

2. The test system according to claim 1, further comprising: A signal generator configured to output the reference signal; Wherein the signal receiver is configured to receive the reference signal from the signal generator and receive at least a portion of the test channel signal from the test channel, the test channel signal including at least a portion of a copy of the reference signal; And Wherein the one or more processing devices are configured to compare the pattern of the reference signal with the pattern of the test channel signal to determine whether there is a difference between the pattern of the reference signal and the pattern of the test channel signal.

3. The test system according to claim 2, wherein if the difference is less than a predefined threshold, the test channel signal does not have the predefined amount of interference.

4. The test system according to claim 3, wherein the predefined threshold is at least partially based on the radio frequency (RF) and baseband stability of the test system.

5. The test system according to claim 2, wherein if the difference is greater than a predefined threshold, the test channel signal has the predefined amount of interference; and Wherein the one or more processing devices are configured to cause the signal generator to output a copy of the reference signal again when the difference is greater than the predefined threshold.

6. The test system according to claim 3, wherein the predefined threshold is at least partially based on the radio frequency (RF) and baseband stability of the test system.

7. The test system according to claim 2, wherein the signal generator includes a vector signal generator (VSG); Wherein the signal receiver includes a vector signal analyzer (VSA) and an antenna; and Wherein the test system further includes a switch configured to connect the VSG to the VSA in a first configuration, connect the VSG to the antenna in a second configuration, and connect the VSA to the antenna in the second configuration.

8. The test system according to claim 1, wherein determining whether there is the predefined amount of interference in the test channel signal includes: Perform the correlation between the pattern of the reference signal and the pattern of the test channel signal.

9. The test system according to claim 1, wherein the one or more processing devices are configured to synchronize the pattern of the reference signal with the pattern of the test channel signal before determining whether the predefined amount of interference is present in the test channel signal.

10. The test system according to claim 1, wherein the reference signal and the test channel signal include radio frequency (RF) signals; and Wherein the test channel includes a wireless test channel.

11. The test system according to claim 1, wherein the reference signal and the test channel signal include radio frequency (RF) signals; and wherein the test channel includes a wired test channel.

12. The test system according to claim 1, wherein the test channel signal includes at least one interference from the following interferences: one or more other signals in the test channel, or signals guided by the device under test to the test system.

13. The test system according to claim 1, wherein the test channel signal includes data packets that would cause an acknowledgment if received by the device.

14. The test system according to claim 1, wherein when the one or more processing devices determine that there is the predefined amount of interference in the test channel signal, the one or more processing devices are configured to ignore data packets from the test channel.

15. A method, comprising: receiving at a signal receiver (i) a reference signal and (ii) a test channel signal; and comparing a pattern of the reference signal with a pattern of the test channel signal to determine whether there is a predefined amount of interference in the test channel signal.

16. The method according to claim 15, further comprising: outputting the reference signal from a signal generator; wherein the signal receiver receives the reference signal from the signal generator and receives at least a portion of the test channel signal from the test channel, the test channel signal including at least a portion of a copy of the reference signal; and wherein comparing the pattern of the reference signal with the pattern of the test channel signal includes comparing the pattern of the reference signal with the pattern of the test channel signal to determine whether there is a difference between the pattern of the reference signal and the pattern of the test channel signal.

17. The method according to claim 16, wherein if the difference is less than a predefined threshold, the test channel signal does not have the predefined amount of interference.

18. The method according to claim 17, wherein the predefined threshold is at least partially based on radio frequency (RF) and baseband stability of the system performing the method.

19. The method according to claim 16, wherein if the difference is greater than a predefined threshold, the test channel signal has the predefined amount of interference; and wherein the method includes, in the case where the difference is greater than a predefined threshold, causing the signal generator to output a copy of the reference signal again.

20. The method according to claim 17, wherein the predefined threshold is at least partially based on radio frequency (RF) and baseband stability of the system performing the method.

21. The method according to claim 16, wherein the signal generator includes a vector signal generator (VSG); wherein the signal receiver includes a vector signal analyzer (VSA) and an antenna; and The method further includes configuring the switch to connect the VSG to the VSA in a first configuration, to connect the VSG to the antenna in a second configuration, or to connect the VSA to the antenna in the second configuration.

22. The method of claim 15, wherein determining whether there is the predefined amount of interference in the test channel signal includes performing a correlation between the pattern of the reference signal and the pattern of the test channel signal.

23. The method of claim 15 further includes: Synchronizing the pattern of the reference signal with the pattern of the test channel signal before determining whether there is interference in the test channel signal.

24. The method of claim 15, wherein the reference signal and the test channel signal include radio frequency (RF) signals; and wherein the test channel includes a wireless test channel.

25. The method of claim 15, wherein the reference signal and the test channel signal include radio frequency (RF) signals; and wherein the test channel includes a wired test channel.

26. The method of claim 15, wherein the test channel signal includes at least one of the following interferences: one or more other signals in the test channel, or signals directed by the DUT to the system performing the method.

27. The method of claim 15, wherein the test channel signal includes a data packet that would cause an acknowledgment if received by the device.

28. The method of claim 15, wherein when there is the predefined amount of interference in the test channel signal, the method further includes ignoring data packets from the test channel.

29. A test system, comprising: A signal generator for outputting data packets to a test channel; A signal receiver configured to receive (i) a reference signal and (ii) a test channel signal; and One or more processing devices configured to compare the pattern of the reference signal with the pattern of the test channel signal to make an inference as to whether a data packet has reached a device under test (DUT) via the test channel, and to determine a performance metric based on the inference.

30. The test system of claim 29, wherein the one or more processing devices are configured to ignore data packets on the test channel if the inference is that the data packet has not reached the DUT.

31. The test system of claim 30, wherein the one or more processing devices are configured to determine that there is a predefined amount of interference on the test channel if a difference between the pattern of the reference signal and the pattern of the test channel signal exceeds a threshold, and if the predefined amount of interference is determined, the inference is that the data packet has not reached the DUT.

32. The test system according to claim 31, wherein the one or more processing devices are configured to cause the signal receiver to effect a long capture consisting of a predefined number of data packets when interference is detected.

33. The test system according to claim 31, wherein the one or more processing devices are configured to determine that there is a predefined amount of interference on the test channel if the difference between the pattern of the reference signal and the pattern of the test channel signal exceeds a threshold; and wherein the one or more processing devices are configured to output a trigger in response to determining that there is the predefined amount of interference on the test channel, the trigger being for indicating a subsequent action to be taken.

34. The test system according to claim 31, wherein the one or more processing devices are configured to ignore data packets received when there is the predefined amount of interference on the test channel.

35. The test system according to claim 29, wherein the performance metric includes a packet error rate.

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