Equipment interconnection test method and system, electronic equipment and storage medium

Abstract

The invention discloses an equipment interconnection test method and system, electronic equipment and a storage medium, and relates to the technical field of data processing. Through automatic identification and comparison of target debugging parameters, target performance indexes and target specification data, couplet test processing is performed by applying the target debugging parameters in an actual test task execution process; throughput data information for data transmission with the to-be-tested device is obtained, the target response rate for information interaction processing of the network port of the to-be-tested device is determined, then data analysis is carried out through the target performance index and the target response rate, and a final test report, namely the target test report, is output. The technical problem of how to reduce human intervention in the equipment testing process and improve the testing quality and accuracy can be solved, and the technical effects of reducing human intervention in the equipment testing process and improving the testing quality and accuracy are achieved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a device interconnection testing method and system, an electronic device and a storage medium. Background Art

[0002] Servers are usually equipped with Peripheral Component Interconnect Express (PCI-E) devices (such as network cards, host channel adapters (HCA), etc.) to achieve the purpose of communication and data transmission between servers. Therefore, during the server testing process, PCI-E devices need to be tested to ensure that the bandwidth rate of the PCI-E devices meets the factory specification standards.

[0003] The PCI-E devices on the current server are tested by interconnecting the network ports. During the test, the test engineer assembles two servers according to the configuration list. The PCI-E devices must meet the requirements of consistent network port type and quantity to maintain interconnection testing. However, the existing device testing method has high requirements for material consistency and requires the full participation of test engineers. The workload of test engineers is large, resulting in large resource consumption and long test time. Therefore, how to reduce human intervention in the device testing process and improve test quality and accuracy is a problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a device interconnection testing method and system, an electronic device and a storage medium, so as to at least solve the problem in the related art of how to reduce human intervention in the device testing process and improve the testing quality and accuracy.

[0005] The present application provides a device interconnection testing method, comprising:

[0006] Extracting target debugging parameters corresponding to the device to be tested from a first preset database according to the device information of the device to be tested, wherein the preset database stores a plurality of debugging parameters corresponding to a plurality of devices respectively;

[0007] Extracting target performance indicators and target specification data corresponding to the device to be tested from a second preset database according to the device information, wherein the second preset database stores multiple performance indicators and multiple specification data corresponding to multiple devices respectively;

[0008] Performing a pairwise test process on the device to be tested according to the target debugging parameters and the target specification data to obtain device test data, wherein the device test data at least includes throughput data information, and the throughput data information is at least used to determine a target response rate of the network port of the device to be tested for information interaction processing;

[0009] Data analysis and processing are performed according to the target response rate and the target performance index to obtain a target test report.

[0010] The present application provides a device interconnection test system, which is characterized by including: a dynamic parameter module, a task execution module, a data processing module, and a standardization module.

[0011] The task execution module is used to extract the target debugging parameters corresponding to the device to be tested from the dynamic parameter module according to the device information of the device to be tested, and extract the target specification data corresponding to the device to be tested from the standardization module.

[0012] The task execution module is further used to perform a connection test process on the device to be tested according to the target debugging parameters and the target specification data to obtain device test data, where the device test data at least includes throughput data information, and the throughput data information is at least used to determine the target response rate for information interaction processing of the network interface of the device to be tested.

[0013] The data processing module is used to extract the target performance index corresponding to the device to be tested from the standardization module, and perform data analysis and processing according to the target response rate and the target performance index to obtain a target test report.

[0014] The present application also provides a device interconnection test device, including:

[0015] An extraction unit is used to extract the target debugging parameters corresponding to the device to be tested from a first preset database according to the device information of the device to be tested, where multiple debugging parameters corresponding to multiple devices are stored in the preset database.

[0016] The extraction unit is further used to extract the target performance index and the target specification data corresponding to the device to be tested from a second preset database according to the device information, where multiple performance indexes and multiple specification data corresponding to multiple devices are stored in the second preset database.

[0017] A test unit is used to perform a connection test process on the device to be tested according to the target debugging parameters and the target specification data to obtain device test data, where the device test data at least includes throughput data information, and the throughput data information is at least used to determine the target response rate for information interaction processing of the network interface of the device to be tested.

[0018] An analysis unit is used to perform data analysis and processing according to the target response rate and the target performance index to obtain a target test report.

[0019] The present application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any one of the above device interconnection testing methods when executing the computer program.

[0020] The present application also provides a computer-readable storage medium storing a computer program, wherein the computer program implements the steps of any one of the above device interconnection testing methods when executed by a processor.

[0021] The present application also provides a computer program product including a computer program, which implements the steps of any one of the above device interconnection testing methods when executed by a processor.

[0022] Through the device interconnection testing method and system, electronic device, and storage medium of the present application, through the automatic identification and comparison of target debugging parameters, target performance indicators, and target specification data, during the execution of the actual test task, the target debugging parameters are applied for the joint test processing to obtain the throughput data information for data transfer with the device to be tested, determine the target response rate for information interaction processing of the network interface of the device to be tested, and then through the data analysis of the target performance indicators and the target response rate, the final test report, i.e., the target test report, is output. Therefore, the technical problem of how to reduce the human intervention in the device testing process and improve the test quality and accuracy can be solved, and the technical effect of reducing the human intervention in the device testing process and improving the test quality and accuracy can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] To more clearly illustrate the embodiments of the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0024] Figure 1 It is a schematic flowchart of a device interconnection testing method provided by an embodiment of the present application;

[0025] Figure 2 It is a schematic flowchart of another device interconnection testing method provided by an embodiment of the present application;

[0026] Figure 3 It is a schematic structural diagram of a device interconnection testing system provided by an embodiment of the present application;

[0027] Figure 4 It is a schematic working flowchart of a dynamic parameter module provided by an embodiment of the present application;

[0028] Figure 5Schematic diagram of the workflow of a task execution module provided by an embodiment of the present application;

[0029] Figure 6 Schematic diagram of the workflow of a data processing module provided by an embodiment of the present application;

[0030] Figure 7 Schematic diagram of the workflow of a statistical module provided by an embodiment of the present application;

[0031] Figure 8 Schematic diagram of the structure of a device interconnection test device provided by an embodiment of the present application;

[0032] Figure 9 Schematic diagram of the structure of another device interconnection test device provided by an embodiment of the present application. Detailed implementation manners

[0033] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0034] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0035] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0036] Figure 1 Schematic diagram of the workflow of a device interconnection test method provided by an embodiment of the present application. The method will be described in detail in combination with the execution process of the device interconnection test method.

[0037] As Figure 1 shown, the device interconnection test method includes:

[0038] Step 101: Extract the target debugging parameters corresponding to the device to be tested from the first preset database according to the device information of the device to be tested, where multiple debugging parameters corresponding to multiple devices are stored in the preset database.

[0039] In the embodiments of the present application, at the beginning of the test, the test requirements and test modes for the device to be tested (such as: PCI-E device) are obtained in advance, and debugging parameters are set for different models or component configuration combinations corresponding to the device to be tested. That is, the target debugging parameters at least include test requirements, test modes, and debugging parameters. The debugging parameters include but are not limited to: test time, number of test times, speed-up rate, speed-down rate (speed reduction strategy), etc.

[0040] Furthermore, it should be noted that the device interconnection test method in the present application can be executed through a device interconnection test system. The device interconnection test system mainly includes a dynamic parameter module, a task execution module, a data processing module, a standardization module, and a statistics module. Among them, the first preset database is equivalent to the dynamic parameter module in the device interconnection test system. The first preset database stores the debugging parameters of multiple devices configured in advance. Among them, through the device information of the device to be tested, the target debugging parameters can be directly matched and extracted from the debugging parameters of multiple devices in the first preset database;

[0041] Furthermore, regarding the specific type and usage process of the first preset database, it includes but is not limited to the following: The first preset database can adopt a relational database architecture to store the set of debugging strategies (including debugging parameters, etc.) for different device combinations in historical test projects. The debugging parameters can cover adjustable variables such as test time window (test time), number of stress test cycles (number of test times), rate climb gradient (speed-up rate), speed-down rate (speed reduction strategy), etc. Among them, the rate climb gradient defines the increasing step size and time interval of the network transmission rate during the test, and the speed-down rate (speed reduction strategy) is set as the decreasing step size and time interval of the network transmission rate during the test.

[0042] The process of extracting the target debugging parameters includes but is not limited to: implementing based on the hash value matching mechanism of the device information of the device to be tested. By calculating the characteristic hash value of the hardware configuration of the device to be tested, the debugging scheme with the highest similarity is retrieved in the first preset database as the benchmark template, and parameter fine-tuning is performed in combination with the stage attributes of the current test project.

[0043] Step 102, extract the target performance indicators and target specification data corresponding to the device to be tested from the second preset database, where the second preset database stores multiple performance indicators and multiple specification data corresponding to multiple devices respectively.

[0044] In an embodiment of the present application, the second preset database is a standardized specification library, which is equivalent to the standardized module in the device interconnection test system, and is mainly used to store the specification data and performance indicators of PCI-E devices (multiple devices), as well as the specification data when multiple devices are paired with other types of components. The specification data is used to provide data for comparison during the test execution process;

[0045] After the test task is completed, according to the configuration combination (i.e., the device information of the device to be tested), the performance indicators that the device to be tested should meet, namely the target performance indicators, are screened. The test value (target response rate) is compared and verified with the actual value (target performance indicator). The content of the comparison and verification is the content of data analysis and processing, including but not limited to: whether it can reach the physical speed limit, whether it is high-frequency throughout the process, whether the single-port test / double-port test can respectively reach the maximum performance value, etc.

[0046] Furthermore, regarding the specific type and usage process of the second preset database, it includes but is not limited to the following content: a mixed architecture of a time-series database and a document database is adopted to store the theoretical performance benchmarks (performance indicators) and compatibility specifications (specification data) of PCI-E devices. The performance indicators include but are not limited to: the theoretical value of the standard bandwidth, the physical layer signal integrity tolerance, the high-frequency continuous load stability coefficient, etc. Among them, the physical layer signal integrity tolerance stipulates the critical threshold of signal attenuation and bit error rate, and the high-frequency continuous load stability coefficient quantifies the proportion of the duration of stable transmission maintained by the device at the limit rate.

[0047] The specification data involves the interface protocol version support matrix, the type of transmission error correction algorithm, the interrupt response delay standard, etc. Among them, the interface protocol version support matrix defines the compatibility mode of the device under different PCI-E generation standards, and the interrupt response delay standard sets the maximum allowable time difference from the hardware interrupt trigger to the response of the device interconnection test system.

[0048] The extraction of the target performance indicators and target specification data can adopt but is not limited to: multi-dimensional index query technology, and precise matching is performed according to the protocol version and hardware identifier in the device information.

[0049] Step 103, perform a pairing test process on the device to be tested according to the target debugging parameters and the target specification data to obtain device test data. The device test data at least includes throughput data information, and the throughput data information is at least used to determine the target response rate of the network interface of the device to be tested for information interaction processing.

[0050] In the embodiments of the present application, various debugging behaviors can be sequentially executed according to the target debugging parameters. During the execution of the test, comparison is made through the target specification data to obtain the result data of the test, that is, the device test data. For example: first, debugging processing is performed through the target debugging parameters, that is, the network interface of the device under test transmits information at a preset rate, and the device interconnection test system responds to the information at the corresponding rate. Then, the throughput data and packet information (i.e., throughput data information) during the information interaction process are collected; according to the actual concurrent or serial test mode (i.e., the test mode), after reaching the verification interval duration (the test interval duration in the test mode), the reaction of the network interface is checked (including at least the first response rate of the network interface of the device under test for information interaction processing).

[0051] Then, comparison is made through the target specification data to obtain the device test data, that is, if the reaction of the network interface meets the specification requirement percentage of the target specification data, the number of information transmission threads is increased and the same test is continued; if the reaction of the network interface fails to meet the specification requirement percentage of the target specification data, according to the speed reduction strategy, the information transmission rate at the network interface end is adjusted, and at the same time, the response of the device interconnection test system changes accordingly until the specification requirement percentage is reached after the verification interval duration.

[0052] Among them, the coupled test processing includes but is not limited to: simulating the response verification mechanism of dual-machine interaction, and simulating the communication behavior of the remote device through the device interconnection test system. During the test, the device interconnection test system dynamically adjusts the maximum transmission unit value (Maximum Transmission Unit, MTU) and the transmission direction control strategy of the network interface of the device under test according to the target debugging parameters. Among them, the adjustment of the MTU value follows the principle of segmented probing, gradually increasing from the standard value to the maximum frame length supported by the device to detect the throughput limit. The transmission direction control strategy includes but is not limited to: unidirectional saturation test, bidirectional alternating load test, and mixed traffic mode test, etc.

[0053] Among them, the bidirectional alternating load test switches between the sending and receiving states through the time slice rotation mechanism to simulate the real network environment. During the test, the device interconnection test system captures the throughput data information in real time. This information includes but is not limited to: key indicators such as the effective payload transmission rate, packet loss rate, and retransmission request frequency. The effective payload transmission rate is used to strip the protocol header overhead to calculate the net data throughput, and the retransmission request frequency is used to count the number of packet repeat requests triggered by network congestion or hardware errors.

[0054] Further, regarding the determination of the target response rate for information interaction processing of the network interface of the device under test by throughput data information, the following methods can be used but are not limited to: using the sliding window analysis method, dividing continuous evaluation windows on the test time axis, and calculating the average value and standard deviation of the throughput within each window. When the fluctuation amplitude of the average values of three consecutive windows is lower than the preset ratio of the standard deviation threshold, it is determined that this rate segment is a stable response interval, and the highest average value among them is taken as the target response rate. For scenarios with rate fluctuations, trigger the speed reduction strategy and re-evaluate until the maximum sustainable rate that meets the stability requirements is found as the target response rate.

[0055] Step 104: Perform data analysis and processing based on the target response rate and the target performance indicators to obtain the target test report.

[0056] In the embodiments of the present application, the target test report can be generated by comparing the target response rate with the target performance indicators. Specifically, the process of generating the target test report includes but is not limited to: determining the data transmitted by the network interface of the device under test, the interface reaction rate, and the throughput data of the system response, the parameter values of dynamic debugging, etc.; (2) determining the packet transmission rate (target response rate) before and after the dynamic debugging parameters according to the current server configuration combination (i.e., the device under test) and the test mode, as well as the target performance indicators, and generating data for determining whether the standard is met; after determination, generate the test report of the current configuration combination (target test report).

[0057] The target test report includes but is not limited to: the project to which the test task belongs, the running stage, the type and version of the operating system of the device under test, the model, manufacturer, architecture, quantity, cores, etc. of the configured central processing unit (CPU), the model, manufacturer, capacity, test frequency, etc. of the configured memory, the capacity, quantity, connection mode, interface rate, etc. of the configured storage devices (including RAID / serial attached SCSI (SAS) cards, hard disks, etc.), the type, interface type, transmission protocol, theoretical value of the standard bandwidth, etc. of the PCI-E devices.

[0058] Specifically, the process of generating the target test report includes but is not limited to: collecting process data (i.e., throughput data information) and test strategies (target debugging parameters), and then generating the target test report by comparing with the target performance indicators. The target test report includes but is not limited to: the test project, stage, system information of the test device, theoretical values and debugging parameters of the PCI-E device itself, other configuration combinations such as the configured CPU, memory, storage devices, etc., and the final evaluation result.

[0059] Furthermore, data analysis and processing are carried out on the target response rate and target performance metrics, including but not limited to: integrating the rule engine and machine learning model to establish a comprehensive evaluation system for the achievement degree of performance metrics. The rule engine sets a baseline according to the theoretical bandwidth value in the target performance metrics, calculates the percentage achievement rate of the target response rate and the theoretical value, and combines the signal integrity tolerance of the physical layer to deduct points for abnormal error code events. The machine learning model analyzes the performance patterns of similar device combinations in historical test data, predicts potential performance bottlenecks of the current configuration, and generates optimization suggestions. The target test report includes but not limited to: integrating the original throughput data trend chart, rate stability heat map, and hardware compatibility scoring matrix. Among them, the rate stability heat map can reflect the transmission fluctuations under different load intensities through color gradients, and the hardware compatibility scoring matrix quantifies the influence weights of the CPU, memory, and storage subsystems on the performance of PCI-E devices.

[0060] The precise matching and dynamic optimization of the test strategy are achieved through the dual-database collaboration mechanism, overcoming the adaptability limitations of traditional fixed-parameter testing; the device interconnection test system is used to simulate the dual-server interaction scenario in a single-machine environment, greatly reducing the hardware dependence and time cost of test environment setup; an intelligent data analysis model is introduced to convert the original performance data into actionable optimization suggestions, providing decision support for hardware selection and system tuning. At the same time, the database architecture can support horizontal expansion, and the verification requirements of future new interface devices can be adapted by adding new device feature dimensions and test case modules.

[0061] The establishment of the dynamic debugging parameter model (i.e., the disadvantages of the target debugging parameters), and the device testers maintain the dynamic debugging parameter model (target debugging parameters) to ensure that the test plan can be flexibly adjusted to adapt to different projects and stages; during the actual test task execution, the debugging parameter model is applied to formulate the dual-server test strategy (dynamic adjustment of rate and MTU value, verification of disconnection mechanism, etc.); according to the data transfer of the system as the response end, the transmission data throughput and data packets are collected to verify the percentage of network port rate compliance; the standardized specification management clarifies the judgment criteria and outputs the final test report;

[0062] And the device test system is used as the dual-server party for the transmission data port, and is implemented in the test task through dynamic debugging parameters and displayed in a visual report.

[0063] The device interconnection test method and system, electronic device, and storage medium of the present application, through the automatic identification and comparison of target debugging parameters, target performance indicators, and target specification data, during the execution of the actual test task, apply the target debugging parameters to perform the interconnection test process, obtain the throughput data information for data transfer with the device under test, determine the target response rate for information interaction processing of the network interface of the device under test, and then perform data analysis through the target performance indicator and the target response rate, and output the final test report, that is, the target test report. Therefore, it can solve the technical problem of how to reduce human intervention in the device test process and improve the test quality and accuracy, and achieve the technical effect of reducing human intervention in the device test process and improving the test quality and accuracy.

[0064] In an implementable manner of the embodiment of the present application, when performing the interconnection test process, it can also be implemented by, but not limited to, the following methods: according to the test mode and information transmission rate in the target debugging parameters, perform information interaction processing with the network interface of the device under test to obtain the throughput data information; and / or, perform disconnection verification processing on the network interface of the device under test based on the target debugging parameters to obtain the disconnection verification data, where the device test data includes the throughput data information and the disconnection verification data.

[0065] In the embodiment of the present application, it should be noted that during the interconnection test process, it can include various test contents, for example: network interface debugging and system response, etc. Network interface debugging is to perform information interaction processing with the network interface of the device under test according to the test mode and information transmission rate in the target debugging parameters; system response is to perform disconnection verification processing on the network interface of the device under test based on the target debugging parameters.

[0066] The specific process includes but is not limited to the following methods: (1) First, perform debugging processing through the target debugging parameters, that is, the network interface of the device under test transmits information at a preset rate, and the device interconnection test system responds to the information at the corresponding rate, and then collect the throughput data and packet information (i.e., the throughput data information) during the information interaction process; according to the actual concurrent or serial test mode (i.e., the test mode), after reaching the verification interval duration (the test interval duration in the test mode), check the reaction of the network interface (including at least the first response rate of the network interface of the device under test for information interaction processing); (2) Verify the disconnection mechanism at the network interface end. After the device under test transmits a data packet to the device interconnection test system, the device interconnection test system does not respond, and then capture the disconnection verification data of the device under test until after the verification interval duration, the device under test no longer continues to respond. (3) The verification of other speed increases or reduction of the number of threads is similar to the above process.

[0067] During the device interconnection test, the process of performing joint test processing according to the target debugging parameters and target specification data to obtain device test data is specifically manifested in, but not limited to: the device interconnection test system performs in-depth performance detection on the network interface of the device to be tested through a preset communication mode and rate control mechanism. The test modes include, but are not limited to: unidirectional transmission verification, bidirectional alternating load test, and mixed traffic pressure test, etc. Among them, the unidirectional transmission verification applies continuous pressure through a data stream in a fixed direction to measure the maximum stable throughput of the network interface of the device to be tested in the simplex mode; the bidirectional alternating load test uses a time slice rotation mechanism to periodically switch the data transmission direction to simulate the bidirectional interaction scenario in a real network environment; the mixed traffic pressure test combines data streams with different priorities and packet sizes to verify the scheduling ability of the network interface in a complex traffic mode.

[0068] The information transmission rate is a custom-set rate. During the test, it can be, but not limited to: controlled by a dynamic rate climbing algorithm. According to the rate increase rate, rate decrease rate (rate reduction strategy), etc. in the target debugging parameters, the information transmission rate is controlled in an increasing or decreasing manner within a preset time interval, while monitoring the throughput fluctuation threshold. When the detected packet loss rate exceeds the rate reduction trigger threshold, a rate fallback operation is automatically performed to form a closed-loop feedback control.

[0069] The disconnection verification process evaluates the fault recovery ability of the network interface of the device to be tested in the physical layer and protocol layer by simulating a network abnormal disconnection scenario. The device interconnection test system actively interrupts the response packets according to the disconnection trigger rule in the target debugging parameters during a specific test stage, triggering the link layer renegotiation mechanism of the network interface of the device to be tested. The disconnection verification process includes, but is not limited to: three core indicators such as the link interruption detection duration, the number of automatic reconnection attempts, and the negotiation recovery time. Among them, the link interruption detection duration refers to the time difference of the interrupt event triggered when the last valid packet arrives at the network interface driver layer of the device to be tested, reflecting the hardware interrupt response delay; the number of automatic reconnection attempts is the number of physical layer negotiation requests initiated by the network interface within a unit time, used to evaluate the interface stability; the negotiation recovery time records the total duration from the disconnection event to the re-establishment of a stable connection, measuring the self-healing ability of the device in an abnormal state.

[0070] The throughput data information can be obtained through, but not limited to: deep packet inspection technology. Capture the original frame structure at the data link layer, parse the payload length and transmission timestamp, and exclude the protocol header overhead when calculating the net data throughput to ensure that the measurement results truly reflect the physical transmission performance of the network interface.

[0071] The information interaction process can adopt, but not limited to: the adaptive protocol stack simulation technology. The device interconnection test system dynamically loads the corresponding communication protocol stack according to the interface protocol version in the target specification data to construct a virtual peer device response environment.

[0072] During the testing process, the device interconnection test system traces the end-to-end transmission path by injecting marked data packets, where the marked data packets carry unique serial numbers and timestamp information for accurately measuring transmission delay and path consistency. For the network interfaces of the devices under test that support multi-queue technology, the device interconnection test system enables queue load balancing testing according to the target debugging parameters and verifies the effectiveness of the multi-queue scheduling algorithm through parallel data stream allocation.

[0073] The process of generating device test data includes, but is not limited to: generating through the embedded real-time anomaly detection mechanism. When it is detected that the hardware error counters (such as: checksum errors, number of timeout retransmissions) exceed the tolerance threshold set by the target specification data, the test is automatically paused and the anomaly context information is recorded to prevent the test results from being distorted due to hardware failures.

[0074] Through the combination of multi-dimensional test modes and dynamic rate adjustment, the accurate mapping of the performance boundaries of the network interfaces of the devices under test is achieved, revealing the non-linear performance degradation phenomena that are difficult to discover by traditional fixed-rate testing; secondly, the disconnection verification mechanism deeply integrates the anomaly simulation of the physical layer and the protocol layer to comprehensively evaluate the robustness of the device in a non-ideal network environment; finally, the adaptive protocol stack simulation technology ensures a high degree of consistency between the test process and the real networking environment, eliminating test biases caused by protocol version differences. The refined collection and analysis of test data provide a quantitative basis for optimizing hardware design, especially forming a traceable improvement path in key performance dimensions such as high-frequency signal integrity and interrupt response efficiency.

[0075] In an implementable manner of the embodiment of the present application, when performing information interaction processing to obtain throughput data information, the following manner can also be adopted but is not limited thereto: after reaching the test interval duration in the test mode, obtain the first response rate of the network interface of the device under test for information interaction processing, and calculate the ratio of the first response rate to the preset response rate in the target specification data to obtain the first rate ratio, where the test mode at least includes concurrent testing and serial testing; in the case where the first rate ratio is greater than the preset rate ratio threshold, increase the number of interaction threads for information interaction processing with the network interface of the device under test according to the thread increase strategy in the target debugging parameters to obtain the second test mode, and the second test mode and the information transmission rate, perform information interaction processing with the network interface of the device under test to obtain the first throughput information, where the first throughput information at least includes the second response rate of the network interface of the device under test for information interaction processing; calculate the ratio of the second response rate to the target response rate in the target specification data to obtain the second rate ratio, in the case where the second rate ratio is less than the preset rate ratio threshold, perform a reduction process on the information transmission rate according to the rate reduction strategy in the target debugging parameters to obtain the second transmission rate; according to the second test mode and the second transmission rate, perform information interaction processing with the network interface of the device under test to obtain the second throughput information, where the second throughput information at least includes the third response rate of the network interface of the device under test for information interaction processing; repeat the above steps until the response rate of the network interface of the device under test for information interaction processing is greater than the preset ratio threshold again to obtain the throughput data information.

[0076] In the embodiment of the present application, the process of performing information interaction processing according to the test mode and information transmission rate in the target debugging parameters to obtain throughput data information can be embodied as: a progressive performance detection system based on a dynamic feedback mechanism. The test mode at least covers two basic forms: concurrent testing and serial testing. Among them, concurrent testing simulates a high-load scenario by simultaneously activating multiple data transmission threads, and is used to evaluate the resource scheduling efficiency of the network interface of the device under test when processing multiple tasks in parallel; serial testing uses a single thread to sequentially execute data transmission tasks, focusing on measuring the basic performance baseline of the network interface of the device under test in a deterministic working mode. The test interval duration is defined as the time window of a data transmission task. For example: the time window for performing a data transmission task in the parallel test mode is shorter, which is multi-threaded parallel processing; the time window for performing a data transmission task in the serial test mode is longer, which is single-threaded sequential execution processing.

[0077] The acquisition of the first response rate can adopt, but is not limited to: time slice polling technology. After reaching the test interval duration, the device interconnection test system reads the number of transmitted bytes of the network interface hardware counter of the device to be tested through the kernel-level driver interface, and calculates the effective data throughput per unit time in combination with an accurate clock source. The preset response rate is the theoretical performance index of the device defined in the target specification data, and usually a specific percentage of the standard bandwidth value is taken as the reference value. The calculation of the first rate ratio can adopt, but is not limited to: normalization processing algorithm, which makes a dimensionless comparison between the measured response rate and the theoretical value to eliminate the interference of different rate dimensions on the result judgment. The preset rate ratio threshold is dynamically adjusted according to the device type and test level. For example, a higher threshold is set in the acceptance test to screen high-performance devices, while a lower threshold is adopted in the compatibility test to ensure the verification of basic functions.

[0078] When the first rate ratio exceeds the preset threshold, the device interconnection test system triggers a thread increase strategy. The thread increase strategy includes, but is not limited to: linear increment and exponential expansion, etc. Linear increment means increasing the number of interaction threads by a fixed step, which is suitable for controlled load improvement in resource-constrained environments; exponential expansion means multiplying the current number of threads, quickly approaching the theoretical concurrent processing limit of the network interface of the device to be tested. The generation of the second test mode involves the reconstruction of thread scheduling parameters, including, but not limited to: thread priority assignment, memory buffer expansion, and interrupt binding optimization, to ensure that the newly added threads can effectively utilize the multi-queue processing ability of the network interface of the device to be tested. During the execution of the second test mode, the device interconnection test system obtains real-time transmission data by polling the status registers of each thread, and can use the weighted average algorithm to calculate the overall second response rate. Among them, a greater weight is given to the transmission volume of high-priority threads in the calculation to reflect the characteristics of the actual business scenario.

[0079] The determination of the second rate ratio can introduce a hysteresis comparison mechanism to avoid misjudgment caused by instantaneous fluctuations. When it is detected that the ratios in three consecutive sampling periods are all lower than the threshold, the device interconnection test system activates a rate reduction strategy. This strategy can adopt an adaptive step algorithm, and dynamically adjust the reduction amplitude according to the deviation between the current transmission rate and the target rate: when the deviation is large, a larger step size is used for rapid convergence, and when approaching the target value, it switches to a fine-tuning mode. The calculation of the second transmission rate incorporates fuzzy control theory, and optimizes and adjusts parameters in combination with historical rate reduction effect data to ensure a smooth and stable rate adjustment process and avoid data stream disorders caused by rate mutations.

[0080] In the test loop executed at the second transmission rate, the system enables the packet loss compensation mechanism to fill the data packets in the transmission gaps caused by the speed reduction and maintain the continuity of the test traffic. The measurement of the third response rate introduces the sliding window filtering technology to eliminate the influence of random interference on the test results. When it is monitored that the response rate exceeds the threshold again, the system records the current test parameter combination and the environmental status as the optimal operating point, and at the same time integrates the complete test trajectory, including the number of rate adjustments, the change curve of the number of threads, and the stability index, to form the final throughput data information. This data set not only includes the absolute values of the response rates in each stage, but also additional derived indicators such as the relative performance achievement rate and the load fluctuation coefficient, providing a multi-dimensional quantitative basis for the device performance evaluation.

[0081] Through the feedback-driven dynamic adjustment of parameters, the self-adaptive mapping of the device performance boundary is realized, overcoming the overload risk and test blind spots existing in the traditional stepped stress test; the cooperative optimization mechanism of thread management and rate control effectively balances the resource utilization rate and system stability, ensuring that the test process always runs at the critical state of the device capacity; the fusion application of the hysteresis comparison and fuzzy control technologies improves the fault tolerance ability of the test system for complex hardware behaviors and avoids misjudgments caused by instantaneous anomalies. This method establishes an extensible framework model for the performance verification of high-speed interface devices. By adjusting the threshold parameters and policy algorithms, it can adapt to the test requirements of different generations of PCI-E standards, and at the same time provides a technical basis for automated performance tuning.

[0082] In an implementable manner of the embodiment of the present application, after obtaining the target test report, the following methods can also be adopted but are not limited to: updating the target debugging parameters according to the target test report.

[0083] In the embodiment of the present application, the process of updating the target debugging parameters according to the target test report can constitute the core feedback mechanism of the closed-loop self-optimization system. The target test report contains multi-dimensional performance evaluation data, covering key indicators such as the response rate achievement rate, the throughput stability coefficient, the abnormal event trigger frequency, and the hardware compatibility score.

[0084] The update process can be implemented by but not limited to: a parameter optimization engine, which dynamically iterates the debugging parameters by integrating an incremental learning algorithm and a rule inference model.

[0085] The updated target debugging parameters are written into the first preset database through a version control mechanism to form a parameter evolution trajectory. Each update operation generates a parameter change log, recording the adjustment items, adjustment basis, and expected effects for reference in subsequent test tasks. At the same time, a parameter rollback mechanism is established. When the new parameters cause performance degradation or a surge in abnormal events during subsequent tests, they are automatically restored to the previous stable version and an artificial review process is triggered. The update process also includes an exception diagnosis module. When the target test report shows that a specific hardware combination continuously fails to meet the performance expectations, this module analyzes the timing data in the test log through a decision tree model, locates potential bottleneck factors (such as transmission delays caused by insufficient memory bandwidth), and adjusts the relevant items in the debugging parameters accordingly (such as reducing the number of concurrent threads to relieve memory pressure).

[0086] Through closed-loop parameter optimization, the continuous evolution ability of the test strategy is formed, enabling the device interconnection test system to adapt to the iteration speed of new hardware devices; the configuration feature matching mechanism breaks through the rigid limitations of traditional parameter templates and realizes intelligent parameter migration across generations of hardware combinations. This process significantly improves the self-adaptability of the test plan, enables the debugging parameters to always dynamically align with the true performance boundaries of the device, and at the same time reduces the risk of incomplete test coverage caused by lagging manual experience, laying a technical foundation for the automated testing of large-scale heterogeneous hardware environments.

[0087] In one implementable manner of the embodiments of the present application, when performing data analysis and processing to obtain a target test report, the following methods can also be used but are not limited to: performing data analysis and processing on the throughput data information to obtain the target response rate of the network interface of the device under test for information interaction processing, and performing a ratio processing on the target response rate and the response rate index in the target performance index to obtain a rate index ratio; in the case where the rate index ratio is greater than or equal to the preset index ratio threshold, it is determined that the network interface of the device under test passes the test; in the case where the rate index ratio is less than the preset index ratio threshold, it is determined that the network interface of the device under test fails the test.

[0088] In the embodiments of the present application, the throughput data information includes but is not limited to: the real-time transmission feature set captured by the network interface during the test cycle, specifically including: the time series fluctuation curve of the payload transmission rate, the distribution pattern of the packet loss rate, and the statistical histogram of the hardware interrupt response delay. When performing data analysis and processing, methods such as but not limited to the sliding window analysis method can be used. The continuous test time axis is divided into equal-length evaluation intervals, the average effective throughput rate is calculated in each window, and transient interference peaks are removed. The smooth rate trend line is fitted through the cubic spline interpolation algorithm, and the maximum continuous rate in the steady-state transmission stage is extracted as the target response rate.

[0089] The response rate index in the target performance metrics refers to the theoretical bandwidth value defined in the device specification document of the device under test. After calibration by the signal attenuation coefficient and the environmental interference tolerance, it forms an actual reference benchmark value. The calculation of the rate index ratio can adopt normalization processing technology. The preset index ratio threshold is dynamically configured according to the test scenario type: a higher-order threshold (e.g., 95% of the theoretical value (target performance metric)) is adopted in the extreme stress test to screen high-performance devices; a basic threshold (e.g., 80% of the theoretical value (target performance metric)) is adopted in the compatibility verification test, etc., to ensure functional availability. The threshold setting process can be carried out in the following way: integrating the statistical distribution characteristics of historical test data and determining a reasonable critical point through confidence interval analysis.

[0090] When the rate index ratio reaches or exceeds the preset threshold, the device interconnection system triggers a pass determination mechanism. This mechanism not only verifies that the numerical value meets the standard, but also requires additional stability review: checking whether the fluctuation coefficient of the target response rate is within the allowable range of the specification, and confirming that there is no continuous frequency reduction or intermittent transmission interruption phenomenon. The devices that pass the determination will generate a test report containing a green label, detailing core parameters such as peak rate, average fluctuation amplitude, and abnormal event occurrence rate, and at the same time associating the hardware configuration fingerprint information to form a traceable performance profile. For devices that do not reach the threshold, the system starts a root cause analysis process. By correlating the packet loss timing in the throughput data, the increment of the hardware error counter, and the interrupt response delay data, it locates the performance bottleneck in specific dimensions such as physical layer signal attenuation, protocol stack processing delay, or hardware resource contention, and marks the key defect items with a red warning label in the test report.

[0091] The dynamic threshold mechanism takes into account the test severity and device generation differences, avoiding misjudgment or missed detection caused by traditional fixed thresholds; the dual verification of stability review and numerical compliance determination ensures the comprehensiveness of performance evaluation, preventing transient peaks from masking real performance defects; converting the failed results into actionable improvement suggestions provides a clear direction for hardware optimization. This method constructs a complete evaluation chain from data collection to intelligent decision-making, significantly enhancing the engineering guidance value of test conclusions. At the same time, through machine-readable determination criteria, it realizes seamless integration with the automated production line test system, providing an efficient solution for large-scale device quality inspection.

[0092] In an implementable manner of the embodiment of the present application, before testing the device to be tested, the following methods may also be used but are not limited to: identifying the device to be tested, setting a network port address for the network port of the device to be tested, and obtaining the configuration information of the device to be tested, where the network port address is used for information interaction with the device to be tested; comparing the configuration information with the preset configuration information, and when it is determined that the configuration information is consistent with the preset configuration information, extracting the target debugging parameters corresponding to the device to be tested from the first preset database according to the device information of the device to be tested; when it is determined that the configuration information is inconsistent with the preset configuration information, determining that the device to be tested fails the test.

[0093] In the embodiment of the present application, the device identification and configuration verification stage constitutes the initialization verification link of the test process. The built server (device to be tested) is connected to the device interconnection test system; the device interconnection test system automatically identifies the device and the entire configuration combination of the device to be tested. After the identification is completed, it will compare the actual device configuration under test with the test requirement configuration to ensure that the test conditions are consistent.

[0094] Through a multi-layer configuration verification mechanism, eliminate the interference of hardware environment deviation on the test results, ensure the unity of the benchmark for performance evaluation, and the automatic implementation of static address allocation and topology identification realizes zero-touch deployment of the test environment, significantly reducing the risk of manual configuration errors.

[0095] In an implementable manner of the embodiment of the present application, for the convenience of understanding the specific implementation process of the device interconnection test method, the embodiment of the present application also provides a flow schematic diagram of another device interconnection test method, as Figure 2 shown, where the specific steps of the device interconnection test method include but are not limited to the following methods:

[0096] The device tester maintains the dynamic debugging parameter model that needs to be followed in each project and stage; the device tester formulates a test plan in advance;

[0097] The device tester applies for materials according to the configuration list, and then builds a complete server (device to be tested) and connects it to the system; the system automatically identifies the device and the entire configuration combination of the device to be tested. After the identification is completed, it will compare the actual device configuration under test with the test requirement configuration to ensure that the test conditions are consistent; set the network port IP for the PCI-E device and execute the test task according to the test cases for the interconnection test.

[0098] After the test starts, read the interface rate of each network port according to the port number in advance, set the MTU value according to the available rate, and set the maximum transmission rate in one direction or both directions according to the actual test scenario; at the same time, query the debugging parameters to be executed in this scenario.

[0099] During the execution process, the system starts debugging parameters: (1) The network interface of the device under test transmits information at a preset rate, and the system responds at the corresponding rate, capturing and collecting throughput data and packet information; according to the actual concurrent or serial test mode, after reaching the verification interval duration, check the reaction of the network interface; if the percentage meeting the specification requirements is satisfied under the initial intensity, increase the number of threads and continue to execute the same test; if it cannot be satisfied at this time, according to the speed reduction strategy, adjust the transmission rate of the network interface side, and at the same time the system changes its response accordingly until the percentage meeting the specification requirements is reached after the verification interval duration; (2) For the network interface end verification disconnection mechanism, after transmitting the data packet, the system does not respond, then capture the reaction of the network interface end until the network interface end no longer responds after the verification interval duration; (3) The verification of other speed increases or reduction of the number of threads is similar to the above process.

[0100] After the test task ends, collect the process data and the test strategy, and then compare with the performance indicators under the configuration combination formulated with the device tester to generate a test report: The report includes the test items, stages, system information of the test device, theoretical values and debugging parameters of the PCI-E device itself, other configuration combinations such as the CPU, memory, storage device, etc. matched, and the final judgment result.

[0101] The above report is presented to the device tester in a visual form for viewing to determine the effectiveness of the test.

[0102] Figure 3 The following is a schematic structural diagram of a device interconnection test system provided by an embodiment of the present application. In combination with the execution process of the device interconnection test method, the system is described in detail.

[0103] As Figure 3 shown, the device interconnection test system includes: a dynamic parameter module 31, a task execution module 32, a data processing module 33, and a standardization module 34.

[0104] The task execution module 32 is used to extract the target debugging parameters corresponding to the device under test from the dynamic parameter module 31 and the target specification data corresponding to the device under test from the standardization module 34 according to the device information of the device under test.

[0105] The task execution module 32 is further used to perform a connection test process on the device under test according to the target debugging parameters and the target specification data to obtain device test data, where the device test data at least includes throughput data information, and the throughput data information is at least used to determine the target response rate for information interaction processing of the network interface of the device under test.

[0106] The data processing module 33 is used to extract the target performance indicators corresponding to the device under test from the standardization module 34, and perform data analysis and processing based on the target response rate and the target performance indicators to obtain a target test report.

[0107] Among them, the device interconnection test system realizes the interconnection test of PCI-E devices on the server. According to the configuration list, only one server (the device under test) is connected to the system. After setting the network port addresses of each, ensure that the network ports of the device under test can communicate with the device interconnection test system. The device interconnection test system performs parameter debugging tests on the network ports of the device under test, sets the MTU debugging strategy for comparison to make a response, and simultaneously collects and processes its transmission data to verify whether the bandwidth rate of the network ports of the device under test reaches the specified standard percentage. It saves the time and material resources for building the interconnection server, and after the construction is completed, it can be compatible with the tests of various configuration combinations, further improving the test efficiency.

[0108] In an implementable manner of the embodiment of the present application, the system further includes: a statistics module 35,

[0109] The dynamic parameter module 31 is used to store multiple debugging parameters corresponding to multiple devices respectively;

[0110] The standardization module 34 is used to store multiple performance indicators and multiple specification data corresponding to multiple devices respectively;

[0111] The statistics module 35 is used to perform visualization processing on the target test report.

[0112] Among them, the dynamic parameter module 31 is the dynamic debugging parameter module, which is used to persistently store the adjustments and debugging parameters in the test process in the module. Specifically, for the function of the dynamic parameter module 31, the embodiment of the present application provides a schematic diagram of the working process of the dynamic parameter module, as Figure 4 shown:

[0113] Among them, at the beginning of the test, the device tester will issue the test requirements and test modes for the device under test, as well as the debugging parameters for different models or component configuration combinations. The debugging parameters include but are not limited to: test time, test times, speed-up rate, speed-down rate, etc. Through but not limited to the preset persistence method, such as: the mysql method, it is persistently stored in the database of the dynamic parameter module 31 for storage;

[0114] During the actual test process, combined with the results of the statistics module 35 and the combination method of each component in the configuration (the configuration information of the device under test), optimize the debugging parameter model (i.e., the target debugging parameter) to generate recommended parameters for the PCI-E device and other component types.

[0115] The task execution module 32 is the test task execution module, which is used to execute the interconnection test task. Specifically, regarding the functions of the task execution module 32, the embodiments of the present application provide a schematic diagram of the work flow of the task execution module, as Figure 5 shown below:

[0116] After the server is set up according to the configuration list and connected to the system, the system automatically identifies all PCI-E devices and sets static network interface addresses for each network port. The system reads the debugging parameter model in this test scenario from the database according to the configuration requirements and starts the test task. During the test process, the system starts the debugging parameters and sequentially executes various debugging behaviors (for example: when remotely sending commands to adjust the network port MTU value, the system collects throughput data to verify the network port rate, and then adjusts the response rate to verify the interface response of the network port; when triggering the disconnection mechanism, after the network port sends data, the system collects throughput data to verify the network port rate, and the response is to interrupt the interconnection and calibrate the interface response of the network port, etc.). After the test is completed, the system collects the interface response results of the network port sending and receiving, and determines whether there is a frequency drop or rate inconsistency of the network port rate.

[0117] The data processing module 33 is the data collection and processing module, which is mainly used to collect the data and test strategies during the execution of the test task, and then generate a target test report by comparing with the target performance indicators. Specifically, regarding the functions of the data processing module 33, the embodiments of the present application provide a schematic diagram of the work flow of the data processing module, as Figure 6 shown below:

[0118] Collect the data and test strategies during the execution of the test task, and then generate a target test report by comparing with the target performance indicators: (1) The data transmitted from the network port, the interface response rate, etc., as well as the throughput data of the system response, the dynamically debugged parameter values, etc.; (2) According to the current server configuration combination and test mode, and the performance indicators in this mode formulated by TDE, query the packet transmission rate before and after dynamically debugging the parameters, and generate a rule for determining whether the standard is met. After determination, generate a test report for the current configuration combination: the project to which the test task belongs, the running stage, the type and version of the operating system of the device under test, the model, manufacturer, architecture, quantity, kernel, etc. of the paired CPU, the model, manufacturer, capacity, test frequency, etc. of the paired memory, the capacity, quantity, connection mode, interface rate, etc. of the paired storage devices (including RAID / SAS cards, hard disks, etc.), the type, interface type, transmission protocol, theoretical standard bandwidth value, etc. of the PCI-E devices, the percentage of the evaluation standard reaching the theoretical value, and the final evaluation result.

[0119] The standardization module 34 is the standard specification management module, which is mainly used to manage the specifications of PCI-E devices and the output efficiency when paired with other types of components, and provide data for comparison during the test execution process. After the test task is completed, according to the configuration combination, the standard ratio that the configuration should meet is screened, and the test value is compared with the actual value for verification. For example, whether it can reach the physical speed limit, whether it is high-frequency throughout the process, and whether the single-port test / double-port test can respectively reach the maximum performance value, etc.

[0120] The statistics module 35 is the test efficiency statistics module. Specifically, regarding the functions of the statistics module 35, the embodiments of the present application provide a schematic workflow diagram of the statistics module, as Figure 7 shown:

[0121] Among them, it is used to display the transmission rate of the server built with each configuration list in each test item during the test process, as well as the improvement ratio after each debugging parameter.

[0122] By connecting the server (device to be tested) to the system that performs the PCI-E device interconnection test. The system applies the dynamic debugging parameter model (target debugging parameter), and performs data transmission and rate adjustment with the peer of the PCI-E device. After collecting the transmission data for analysis, it is compared with the specification standard to generate a test report and provide a visual display.

[0123] In summary, the present application can achieve the following technical effects:

[0124] 1. Through the automatic identification and comparison of the target debugging parameter, target performance index, and target specification data, during the actual test task execution process, the target debugging parameter is applied for the peer test processing to obtain the throughput data information for data transfer with the device to be tested, determine the target response rate for information interaction processing of the network port of the device to be tested, and then perform data analysis through the target performance index and the target response rate to output the final test report, that is, the target test report. Therefore, it can solve the technical problem of how to reduce human intervention in the device test process and improve the test quality and accuracy, and achieve the technical effect of reducing human intervention in the device test process and improving the test quality and accuracy.

[0125] 2. The dynamic debugging parameter model (target debugging parameter) is identified and compared with the automatic configuration, reducing the error caused by manual intervention and improving the test quality and accuracy;

[0126] 3. Support multi-scenario tests (unidirectional / bidirectional, serial / concurrent, etc.) and dynamic parameter adjustment strategies (rate adjustment, thread number adjustment, etc.), and adapt to different test requirements;

[0127] 4. By taking full advantage of the complete consistency between the network interface of the device under test and that of the device interconnection test system, and receiving the response from the device interconnection test system as the response to the pairing response, it ensures that the test conditions and requirements are met, and avoids errors caused by configuration differences.

[0128] 5. The test results and configuration overview are presented in a visual form, facilitating the device testers to analyze and determine the effectiveness of the test results.

[0129] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0130] The embodiments of the present application also provide a device interconnection test device. Figure 8 The following is a schematic structural diagram of a device interconnection test device provided by the application, as Figure 8 shown, including:

[0131] An extraction unit 81, configured to extract the target debugging parameters corresponding to the device under test from a first preset database according to the device information of the device under test, wherein a plurality of debugging parameters corresponding to each of the multiple devices are stored in the preset database;

[0132] The extraction unit 81 is further configured to extract the target performance indicators and target specification data corresponding to the device under test from a second preset database according to the device information, wherein a plurality of performance indicators and a plurality of specification data corresponding to each of the multiple devices are stored in the second preset database;

[0133] A test unit 82, configured to perform pairing test processing on the device under test according to the target debugging parameters and the target specification data to obtain device test data, wherein the device test data at least includes throughput data information, and the throughput data information is at least used to determine the target response rate for information interaction processing of the network interface of the device under test;

[0134] An analysis unit 83, configured to perform data analysis processing according to the target response rate and the target performance indicators to obtain a target test report.

[0135] In an embodiment of the present application, the test unit 82 is further configured to:

[0136] Perform information interaction processing with the network interface of the device under test according to the test mode and information transmission rate in the target debugging parameters to obtain throughput data information; and / or,

[0137] Perform disconnection verification processing on the network interface of the device under test based on the target debugging parameters to obtain disconnection verification data, wherein the device test data includes throughput data information and disconnection verification data.

[0138] In one embodiment of the present application, the test unit 82 is further configured to:

[0139] After reaching the test interval duration in the test mode, obtain the first response rate of the network interface of the device under test for information interaction processing, and calculate the ratio of the first response rate to the preset response rate in the target specification data to obtain the first rate ratio, where the test mode includes at least concurrent testing and serial testing;

[0140] When the first rate ratio is greater than the preset rate ratio threshold, increase the number of interaction threads for information interaction processing with the network interface of the device under test according to the thread increase strategy in the target debugging parameters to obtain a second test mode, and perform information interaction processing with the network interface of the device under test in the second test mode and at the information transmission rate to obtain the first throughput information, where the first throughput information includes at least the second response rate of the network interface of the device under test for information interaction processing;

[0141] Calculate the ratio of the second response rate to the target response rate in the target specification data to obtain the second rate ratio. When the second rate ratio is less than the preset rate ratio threshold, perform a reduction process on the information transmission rate according to the rate reduction strategy in the target debugging parameters to obtain the second transmission rate;

[0142] Perform information interaction processing with the network interface of the device under test according to the second test mode and the second transmission rate to obtain the second throughput information, where the second throughput information includes at least the third response rate of the network interface of the device under test for information interaction processing;

[0143] Repeat the above steps until the response rate of the network interface of the device under test for information interaction processing is greater than the preset ratio threshold again to obtain the throughput data information.

[0144] In one embodiment of the present application, as Figure 9 shown, the device interconnection test device further includes:

[0145] An update unit 84, configured to perform an update process on the target debugging parameters according to the target test report.

[0146] In one embodiment of the present application, the analysis unit 83 is further configured to:

[0147] Perform data analysis processing on the throughput data information to obtain the target response rate of the network interface of the device under test for information interaction processing, and perform a ratio process on the target response rate and the response rate index in the target performance index to obtain the rate index ratio;

[0148] When the rate index ratio is greater than or equal to the preset index ratio threshold, determine that the network interface of the device under test passes the test;

[0149] When the ratio of rate indicators is less than the preset ratio threshold of the indicators, it is determined that the network interface of the device under test fails the test.

[0150] In an embodiment of the present application, as Figure 9 shown, the device interconnection test device further includes:

[0151] A processing unit 85, configured to identify the device under test, set a network interface address for the network interface of the device under test, and obtain the configuration information of the device under test, where the network interface address is used for information interaction with the device under test;

[0152] The processing unit 85 is further configured to compare the configuration information with the preset configuration information. When it is determined that the configuration information is consistent with the preset configuration information, extract the target debugging parameters corresponding to the device under test from the first preset database according to the device information of the device under test;

[0153] The processing unit 85 is further configured to determine that the device under test fails the test when it is determined that the configuration information is inconsistent with the preset configuration information.

[0154] For the description of the features in the corresponding embodiment of the device interconnection test device, reference can be made to the relevant description in the corresponding embodiment of the device interconnection test method, which will not be elaborated here one by one.

[0155] An embodiment of the present application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above-mentioned embodiments of the device interconnection test method.

[0156] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any one of the above-mentioned embodiments of the device interconnection test method when running.

[0157] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs that can store computer programs.

[0158] An embodiment of the present application further provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the above-mentioned embodiments of the device interconnection test method.

[0159] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, where the computer program, when executed by a processor, implements the steps in any of the above-described embodiments of the device interconnection testing method.

[0160] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0161] The above has introduced in detail a device interconnection testing method and system, an electronic device, and a storage medium provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A device interconnection test method, characterized in that, Including: Extracting the target debugging parameters corresponding to the device to be tested from a first preset database according to the device information of the device to be tested, wherein multiple debugging parameters corresponding to multiple devices are stored in the preset database; Extracting the target performance indicators and target specification data corresponding to the device to be tested from a second preset database according to the device information, wherein multiple performance indicators and multiple specification data corresponding to the multiple devices are stored in the second preset database; Performing a connection test process on the device to be tested according to the target debugging parameters and the target specification data to obtain device test data, wherein the device test data at least includes throughput data information, and the throughput data information is at least used to determine the target response rate of the network interface of the device to be tested for information interaction processing; Performing data analysis processing according to the target response rate and the target performance indicators to obtain a target test report.

2. The device interconnection test method according to claim 1, wherein The performing a connection test process on the device to be tested according to the target debugging parameters and the target specification data to obtain device test data includes: Performing information interaction processing with the network interface of the device to be tested according to the test mode and information transmission rate in the target debugging parameters to obtain the throughput data information; and / or, Performing a disconnection verification process on the network interface of the device to be tested based on the target debugging parameters to obtain disconnection verification data, wherein the device test data includes the throughput data information and the disconnection verification data.

3. The device interconnection test method according to claim 2, wherein The performing information interaction processing with the network interface of the device to be tested according to the test mode and information transmission rate in the target debugging parameters to obtain throughput data information includes: After reaching the test interval duration in the test mode, obtaining the first response rate of the network interface of the device to be tested for information interaction processing, and calculating the ratio of the first response rate to the preset response rate in the target specification data to obtain a first rate ratio, wherein the test mode at least includes concurrent testing and serial testing; In the case where the first rate ratio is greater than a preset rate ratio threshold, increasing the number of interaction threads for performing information interaction processing with the network interface of the device to be tested according to the thread increase strategy in the target debugging parameters to obtain a second test mode, and performing information interaction processing with the network interface of the device to be tested in the second test mode and the information transmission rate to obtain first throughput information, wherein the first throughput information at least includes the second response rate of the network interface of the device to be tested for information interaction processing; Calculating the ratio of the second response rate to the target response rate in the target specification data to obtain a second rate ratio, and in the case where the second rate ratio is less than the preset rate ratio threshold, performing a reduction process on the information transmission rate according to the rate reduction strategy in the target debugging parameters to obtain a second transmission rate; Perform information interaction processing with the network interface of the device under test according to the second test mode and the second transmission rate, and obtain second throughput information, where the second throughput information at least includes a third response rate of the network interface of the device under test for information interaction processing; Repeat the above steps until the response rate of the network interface of the device under test for information interaction processing is greater than the preset rate ratio threshold again, and obtain the throughput data information.

4. The device interconnection test method according to claim 2, wherein After performing data analysis processing on the device test data and the target performance indicators to obtain a target test report, the method further includes: Update and process the target debugging parameters according to the target test report.

5. The device interconnection test method according to claim 3, wherein The performing data analysis processing on the target response rate and the target performance indicators to obtain a target test report includes: Perform data analysis processing on the throughput data information to obtain the target response rate of the network interface of the device under test for information interaction processing, and perform a ratio processing on the target response rate and the response rate indicator in the target performance indicators to obtain a rate indicator ratio; When the rate indicator ratio is greater than or equal to a preset indicator ratio threshold, determine that the network interface of the device under test passes the test; When the rate indicator ratio is less than the preset indicator ratio threshold, determine that the network interface of the device under test fails the test.

6. The device interconnection test method according to claim 2, characterized in that Before extracting the target debugging parameters corresponding to the device under test from the first preset database according to the device information of the device under test, the method further includes: Identify the device under test, set a network interface address for the network interface of the device under test, and obtain the configuration information of the device under test, where the network interface address is used for information interaction with the device under test; Compare the configuration information with the preset configuration information, and when it is determined that the configuration information is consistent with the preset configuration information, extract the target debugging parameters corresponding to the device under test from the first preset database according to the device information of the device under test; When it is determined that the configuration information is inconsistent with the preset configuration information, determine that the device under test fails the test.

7. An equipment interconnection test system, characterized in that, Includes: A dynamic parameter module, a task execution module, a data processing module, a standardization module, The task execution module is configured to extract the target debugging parameters corresponding to the device under test from the dynamic parameter module and extract the target specification data corresponding to the device under test from the standardization module according to the device information of the device under test; The task execution module is further configured to perform a pairing test process on the device under test according to the target debugging parameters and the target specification data to obtain device test data, where the device test data at least includes throughput data information, and the throughput data information is at least used to determine the target response rate of the network interface of the device under test for information interaction processing; The data processing module is configured to extract the target performance indicators corresponding to the device under test from the standardization module, and perform data analysis and processing based on the target response rate and the target performance indicators to obtain a target test report.

8. The device interconnection test system according to claim 7, wherein, The system further includes: a statistics module, The dynamic parameter module is used to store multiple debugging parameters corresponding to multiple devices respectively; The standardization module is used to store multiple performance indicators and multiple specification data corresponding to multiple devices respectively; The statistics module is used to perform visualization processing on the target test report.

9. An electronic device, characterized in that, including: a memory for storing computer programs; a processor, configured to implement the steps of the device interconnection test method according to any one of claims 1 to 6 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the device interconnection test method according to any one of claims 1 to 6.

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