Bit stream processing method and device

Abstract

The invention provides a bit stream processing method and device, relates to the technical field of media, and can smoothly realize sub-bit stream extraction and clarify an indication mode of hierarchical information. The method comprises the steps that a bit stream of a target image is obtained, the bit stream comprises first layering information, and the first layering information comprises first indication information used for indicating the number of layers contained in the bit stream and second indication information used for indicating layering identifiers of layers contained in the bit stream; constructing a target layer list corresponding to a to-be-extracted target layer in the target image; processing the bit stream of the target image on the basis of the target hierarchical list, and outputting a sub-bit stream, the sub-bit stream comprising the hierarchical bit stream in the target hierarchical list and second hierarchical information, the second layer information comprises second indication information used for indicating the layer number of the layers contained in the sub-bit stream and third indication information used for indicating the layer identification of the layers contained in the sub-bit stream in the target image.

Description

[0001] This application claims the priority of a Chinese patent application with the application number 202410102813.5 and the application title "A Bitstream Processing Method and Device", which was filed with the National Intellectual Property Administration on January 24, 2024. The entire content of the Chinese patent application is incorporated herein by reference. Technical Field

[0002] This application relates to the field of media technology, and in particular, to a bitstream processing method and device. Background Art

[0003] During the video / image encoding and decoding process, the image to be encoded can be encoded in layers, and layer-related information (such as the number of layers and inter-layer dependency information) can be transmitted in the encoded bitstream (or called bitstream).

[0004] In some cases, the decoding end can extract the bitstream of a specific layer in the bitstream for independent decoding. After extracting the bitstream of the specific layer, the layer-related information of the bitstream changes. Therefore, how to perform bitstream extraction and how to process layer-related information need to be solved urgently. Summary of the Invention

[0005] This application provides a bitstream processing method and device, which can successfully implement sub-bitstream extraction and clarify the indication method of layer information.

[0006] This application adopts the following technical solutions:

[0007] In a first aspect, this application provides a bitstream processing method, including: obtaining the bitstream of a target image, where the bitstream includes the bitstreams of at least one layer after hierarchical encoding of the target image, and the bitstream includes first layer information, and the first layer information includes first indication information for indicating the number of layers included in the bitstream and second indication information for indicating the layer identifier of the layer included in the bitstream; and constructing a target layer list corresponding to the target layer, where the target layer is the layer to be extracted in the target image, and the target layer list includes the target layer; when there is an inter-layer reference layer in at least one layer of the target layer, the target layer list further includes at least one inter-layer reference layer; and based on the target layer list, processing the bitstream of the target image to output a sub-bitstream; the sub-bitstream includes the bitstreams of the layers in the target layer list and second layer information, and the second layer information includes third indication information and fourth indication information; where the third indication information is used to indicate the number of layers included in the sub-bitstream, and the fourth indication information is used to indicate the layer identifier of the layer included in the sub-bitstream.

[0008] The bitstream processing method provided by this application can create a target layer list according to the layers to be extracted, and then extract the bitstreams of the layers in the target layer list to obtain sub-bitstreams. Moreover, the layer information after bitstream extraction can be carried in the sub-bitstreams, enabling the successful extraction of sub-bitstreams and clarifying the indication method of layer information.

[0009] In a possible implementation, the supplementary enhancement information in the bitstream of the target image includes first layer information; and / or, the supplementary enhancement information in the sub-bitstream includes second layer information. Specifically, the first layer information or the second layer information is carried in the payload where nal_unit_type is 6 (the supplementary enhancement information is included in the NAL unit with nal_unit_type of 6) and PayloadType is equal to 25.

[0010] In a possible implementation, the second layer information is the layer information after updating the first layer information. By updating the layer information in the bitstream, the layer situation included in the bitstream can be known according to the updated layer information, improving the coding and decoding performance.

[0011] In a possible implementation, constructing the target layer list corresponding to the target layer includes: parsing the bitstream of the target image to obtain the layer independent coding identifier of at least one layer and the reference layer identifier of at least one layer; the layer independent coding identifier of a layer is used to indicate independent coding or inter-layer dependent coding of the layer; and adding the layer identifier of the target layer to the target layer list. If the layer independent coding identifier of the target layer indicates inter-layer dependent coding of the target layer, the reference layer identifier of the target layer is added to the target layer list.

[0012] In a possible implementation, processing the bitstream of the target image based on the target layer list includes: removing from the bitstream of the target image the NAL units in the bitstreams of the layers that do not exist in the target layer list and whose network abstraction layer NAL unit types are not 5, 6, 7, 8, 9, 10, 11, or 16. Since the NAL units with nal_unit_type of 5, 6, 7, 8, 9, 10, 11, or 16 contain the common information for decoding the bitstream, they need to be retained (i.e., extracted into the sub-bitstream).

[0013] In a possible implementation, the authentication flag of the network abstraction layer NAL unit containing the first layer information or the second layer information is the first value, and the first value is used to indicate that the NAL unit containing the first layer information or the second layer information is not authenticated.

[0014] The above-mentioned first value is specifically used to indicate to the decoding end that the NAL unit containing the first layer information or the second layer information is not to be authenticated. In this way, the decoding end does not need to authenticate the NAL unit containing the first layer information or the second layer information.

[0015] In a possible implementation, the encryption flag of the network abstraction layer (NAL) unit containing the first layer information or the second layer information is a second value, and the second value is used to indicate that the NAL unit containing the first layer information or the second layer information is not to be encrypted.

[0016] The above-mentioned second value is specifically used to indicate to the decoding end that the encoding end has not encrypted the NAL unit containing the first layer information or the second layer information. In this way, the decoding end does not need to decrypt the NAL unit containing the first layer information or the second layer information.

[0017] In a possible implementation, the network abstraction layer (NAL) unit containing the first layer information or the second layer information is carried in the bitstream of the first layer of the target image.

[0018] In a second aspect, the present application provides a bitstream processing device. The bitstream processing device includes various modules for implementing the method described in any one of the first aspect and its possible implementations. The bitstream processing device has the function of implementing the behavior in the method example of any one of the above-mentioned first aspect and its possible implementations. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0019] In a third aspect, the present application provides a bitstream processing device, including at least one processor and a memory. The at least one processor executes a program or instruction stored in the memory so that the bitstream processing device implements the method described in any one of the above-mentioned first aspect or its possible implementations.

[0020] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium for storing a computer program, and the computer program includes a method for implementing the method described in any one of the above-mentioned first aspect or its possible implementations.

[0021] In a fifth aspect, an embodiment of the present application further provides a computer program product containing instructions. When it runs on a computer, it causes the computer to implement the method described in any one of the above-mentioned first aspect or its possible implementations.

[0022] In a sixth aspect, an embodiment of the present application further provides a chip, including: an input interface, an output interface, and at least one processor. Optionally, the chip further includes a memory. The at least one processor is configured to execute the code in the memory, and when the at least one processor executes the code, the chip implements the method described in the above first aspect or any possible implementation manner thereof.

[0023] Optionally, the above chip may also be an integrated circuit.

[0024] The bitstream processing device, computer storage medium, computer program product, and chip provided by the present application are all used to execute the bitstream processing method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the bitstream processing method provided above, and will not be elaborated here. Description of the Drawings

[0025] Figure 1a It is an exemplary block diagram of a decoding system provided by an embodiment of the present application;

[0026] Figure 1b It is an exemplary block diagram of a video decoding system provided by an embodiment of the present application;

[0027] Figure 2 It is an exemplary block diagram of a video encoder provided by an embodiment of the present application;

[0028] Figure 3 It is an exemplary block diagram of a video decoder provided by an embodiment of the present application;

[0029] Figure 4 It is an exemplary schematic diagram of a candidate image block provided by an embodiment of the present application;

[0030] Figure 5 It is an exemplary block diagram of a video decoding device provided by an embodiment of the present application;

[0031] Figure 6 It is an exemplary block diagram of a device provided by an embodiment of the present application;

[0032] Figure 7 It is a schematic flowchart of a bitstream processing method provided by an embodiment of the present application;

[0033] Figure 8 It is a schematic diagram of a bitstream processing device provided by an embodiment of the present application;

[0034] Figure 9 It is a schematic structural diagram of a chip provided by an embodiment of the present application;

[0035] Figure 10 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0036] Figure 11 This is a schematic structural diagram of a bitstream processing device provided by an embodiment of the present application. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the embodiments of the present application.

[0038] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone.

[0039] The terms "first" and "second" in the description of the embodiments of the present application are used to distinguish different objects or different processes for the same object, rather than to describe the specific order of the objects.

[0040] In addition, the terms "including" and "having" and any variations thereof mentioned in the description of the embodiments of the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may alternatively include other steps or units not listed, or may alternatively include other steps or units inherent to these processes, methods, products, or devices.

[0041] It should be noted that in the description of the embodiments of the present application, words such as "exemplarily" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplarily" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplarily" or "for example" is intended to present relevant concepts in a specific manner.

[0042] Data encoding and decoding include two parts: data encoding and data decoding. Data encoding is performed on the source side (or usually referred to as the encoder side), and generally includes processing (such as compressing) the original data to reduce the amount of data required to represent the original data (so as to store and / or transmit more efficiently). Data decoding is performed on the destination side (or usually referred to as the decoder side), and generally includes performing inverse processing relative to the encoder side to reconstruct the original data. The "encoding and decoding" of the data involved in the embodiments of the present application should be understood as the "encoding" or "decoding" of the data. The encoding part and the decoding part are also collectively referred to as encoding and decoding (encoding and decoding, CODEC).

[0043] In the case of lossless data coding, the original data can be reconstructed, that is, the reconstructed original data has the same quality as the original data (assuming no transmission loss or other data loss during storage or transmission). In the case of lossy data coding, further compression is performed through quantization, etc., to reduce the amount of data required to represent the original data, and the decoder side cannot fully reconstruct the original data, that is, the quality of the reconstructed original data is lower or worse than that of the original data.

[0044] The embodiments of the present application can be applied to video data and other data with compression / decompression requirements, etc. The following takes the coding of video data (hereinafter referred to as video coding) as an example to illustrate the embodiments of the present application. Other types of data (such as image data, audio data, integer data, and other data with compression / decompression requirements) can refer to the following description, and the embodiments of the present application will not be elaborated herein. It should be noted that, compared with video coding, during the coding process of data such as audio data and integer data, there is no need to divide the data into blocks, but the data can be directly coded.

[0045] Video coding generally refers to processing an image sequence that forms a video or a video sequence. In the field of video coding, the terms "picture", "frame", or "image" can be used as synonyms.

[0046] Several video coding standards belong to "lossy hybrid video coding and decoding" (that is, combining spatial and temporal prediction in the pixel domain with 2D transform coding for applying quantization in the transform domain). Each image in a video sequence is usually divided into a set of non-overlapping blocks, and coding is usually performed at the block level. In other words, the encoder usually processes and encodes the video at the block (video block) level. For example, prediction blocks are generated through spatial (intra-frame) prediction and temporal (inter-frame) prediction; the prediction blocks are subtracted from the current block (the currently processed / block to be processed) to obtain a residual block; the residual block is transformed and quantized in the transform domain to reduce the amount of data to be transmitted (compressed), and the decoder side applies the inverse processing part relative to the encoder to the encoded or compressed block to reconstruct the current block for representation. In addition, the encoder needs to repeat the processing steps of the decoder so that the encoder and the decoder generate the same predictions (such as intra-frame prediction and inter-frame prediction) and / or reconstruct pixels for processing, that is, for encoding subsequent blocks.

[0047] In the following embodiments of the decoding system 10, the encoder 20 and the decoder 30 are described according to Figures 1a to 3 as follows.

[0048] Figure 1aAn exemplary block diagram of the decoding system 10 provided by an embodiment of the present application. For example, a video decoding system 10 (or simply referred to as the decoding system 10) that can utilize the technology of the embodiments of the present application. The video encoder 20 (or simply referred to as the encoder 20) and the video decoder 30 (or simply referred to as the decoder 30) in the video decoding system 10 represent devices that can be used to execute various techniques according to the various examples described in the embodiments of the present application.

[0049] As Figure 1a shown, the decoding system 10 includes a source device 12, and the source device 12 is used to provide encoded image data 21 such as encoded images to a destination device 14 for decoding the encoded image data 21.

[0050] The source device 12 includes an encoder 20, and additionally, optionally, may include an image source 16, a pre-processor (or pre-processing unit) 18 such as an image pre-processor, and a communication interface (or communication unit) 22.

[0051] The image source 16 may include or may be any type of image capture device for capturing real-world images, etc., and / or any type of image generation device, such as a computer graphics processor for generating computer animation images or any type of device for acquiring and / or providing real-world images, computer-generated images (e.g., screen content, virtual reality (VR) images, and / or any combination thereof (e.g., augmented reality (AR) images)). The above image source may be any type of memory or storage device that stores any of the above images.

[0052] To distinguish the processing performed by the pre-processor (or pre-processing unit) 18, the image (or image data) 17 may also be referred to as the original image (or original image data) 17.

[0053] The pre-processor 18 is used to receive the original image data 17 and pre-process the original image data 17 to obtain pre-processed images (or pre-processed image data) 19. For example, the pre-processing performed by the pre-processor 18 may include trimming, color format conversion (e.g., from RGB to YCbCr), color correction, or denoising. It can be understood that the pre-processing unit 18 may be an optional component.

[0054] The video encoder (or encoder) 20 is used to receive the pre-processed image data 19 and provide the encoded image data 21 (which will be further described below according to Figure 2 etc.).

[0055] The communication interface 22 in the source device 12 can be used to: receive the encoded image data 21 and send the encoded image data 21 (or any other processed version) to another device such as the destination device 14 or any other device via the communication channel 13 for storage or direct reconstruction.

[0056] The destination device 14 includes a decoder 30 and, additionally or alternatively, may include a communication interface (or communication unit) 28, a post-processor (or post-processing unit) 32, and a display device 34.

[0057] The communication interface 28 in the destination device 14 is used to directly receive the encoded image data 21 (or any other processed version) from the source device 12 or from any other source device such as a storage device. For example, the storage device is an encoded image data storage device, and provide the encoded image data 21 to the decoder 30.

[0058] The communication interface 22 and the communication interface 28 can be used to send or receive the encoded image data (or encoded data) 21 via a direct communication link between the source device 12 and the destination device 14, such as a direct wired or wireless connection, etc., or via any type of network, such as a wired network, a wireless network, or any combination thereof, any type of private network and public network or any combination of any type thereof.

[0059] For example, the communication interface 22 can be used to encapsulate the encoded image data 21 into a suitable format such as a message, and / or use any type of transmission encoding or processing to process the above-mentioned encoded image data for transmission over the communication link or communication network.

[0060] The communication interface 28 corresponds to the communication interface 22. For example, it can be used to receive the transmission data and use any type of corresponding transmission decoding or processing and / or de-encapsulation to process the transmission data to obtain the encoded image data 21.

[0061] Both the communication interface 22 and the communication interface 28 can be configured as Figure 1a a unidirectional communication interface as indicated by the arrow of the corresponding communication channel 13 pointing from the source device 12 to the destination device 14 in the figure, or a bidirectional communication interface, and can be used to send and receive messages, etc., to establish a connection, confirm and exchange any other information related to the communication link and / or data transmission such as the transmission of the encoded image data, etc.

[0062] The video decoder (or decoder) 30 is used to receive the encoded image data 21 and provide the decoded image data (or decoded image data) 31 (which will be further described below according to Figure 3 etc.).

[0063] The post-processor 32 is configured to perform post-processing on the decoded image or decoded image data 31 (also referred to as the reconstructed image data) to obtain post-processed image or post-processed image data 33. The post-processing performed by the post-processing unit 32 may include, for example, color format conversion (e.g., from YCbCr to RGB), color grading, cropping, or resampling, or any other processing for generating the decoded image data 31 for display on a display device 34 or the like.

[0064] The display device 34 is configured to receive the post-processed image data 33 to display an image to a user, viewer, or the like. The display device 34 may be or include any type of display for representing the reconstructed image, e.g., an integrated or external display screen or monitor. For example, the display screen may include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro LED display, a liquid crystal on silicon (LCoS) display, a digital light processor (DLP), or any other type of display screen.

[0065] The decoding system 10 further includes a training engine 25 configured to train the encoder 20 (especially the entropy encoding unit 270 in the encoder 20) or the decoder 30 (especially the entropy decoding unit 304 in the decoder 30) to perform entropy encoding on the image blocks to be encoded according to the estimated probability distribution. For a detailed description of the training engine 25, please refer to the following method test embodiments.

[0066] Although Figure 1a the source device 12 and the destination device 14 are shown as separate devices, device embodiments may also include both the source device 12 and the destination device 14 or the functions of both the source device 12 and the destination device 14 simultaneously, i.e., including both the source device 12 or corresponding functions and the destination device 14 or corresponding functions. In these embodiments, the source device 12 or corresponding functions and the destination device 14 or corresponding functions may be implemented using the same hardware and / or software, or by separate hardware and / or software, or any combination thereof.

[0067] According to the description, Figure 1a the presence and (exact) partitioning of different units or functions in the illustrated source device 12 and / or destination device 14 may vary depending on the actual device and application, which is obvious to those skilled in the art.

[0068] Please refer to Figure 1b , Figure 1bAn exemplary block diagram of a video decoding system 40 provided by an embodiment of the present application. The encoder 20 (e.g., video encoder 20) or the decoder 30 (e.g., video decoder 30) or both can be implemented by a processing circuit in the video decoding system 40 as shown in Figure 1b , for example, one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, video encoding dedicated processors, or any combination thereof. Please refer to Figure 2 and Figure 3 . Figure 2 An exemplary block diagram of a video encoder provided by an embodiment of the present application. Figure 3 An exemplary block diagram of a video decoder provided by an embodiment of the present application. The encoder 20 can be implemented by a processing circuit 46 to include various modules discussed with reference to Figure 2 the encoder 20 and / or any other encoder system or subsystem described herein. The decoder 30 can be implemented by a processing circuit 46 to include various modules discussed with reference to Figure 3 the decoder 30 and / or any other decoder system or subsystem described herein. The above-mentioned processing circuit 46 can be used to perform various operations discussed below. As shown in Figure 5 , if some technologies are implemented in software, the device can store the instructions of the software in a suitable non-transitory computer-readable storage medium and execute the instructions in hardware using one or more processors, thereby implementing the technologies of the embodiments of the present application. One of the video encoder 20 and the video decoder 30 can be integrated as part of a combined codec (encoder / decoder, CODEC) in a single device, as shown in Figure 1b .

[0069] The source device 12 and the destination device 14 can include any of a variety of devices, including any type of handheld device or fixed device, such as, for example, a laptop or notebook computer, a mobile phone, a smartphone, a tablet or tablet computer, a camera, a desktop computer, a set-top box, a television, a display device, a digital media player, a video game console, a video streaming device (e.g., a content service server or a content distribution server), a broadcast receiving device, a broadcast transmitting device, and a monitoring device, etc., and may or may not use any type of operating system. The source device 12 and the destination device 14 can also be devices in a cloud computing scenario, such as virtual machines in a cloud computing scenario. In some cases, the source device 12 and the destination device 14 can be equipped with components for wireless communication. Therefore, the source device 12 and the destination device 14 can be wireless communication devices.

[0070] The source device 12 and the destination device 14 can install virtual scene application programs (applications, APPs) such as virtual reality (VR) applications, augmented reality (AR) applications, or mixed reality (MR) applications, and can run VR applications, AR applications, or MR applications based on user operations (such as clicking, touching, swiping, shaking, voice control, etc.). The source device 12 and the destination device 14 can collect images / videos of any object in the environment through a camera and / or sensors, and then display virtual objects on a display device according to the collected images / videos. The virtual objects can be virtual objects in a VR scene, an AR scene, or an MR scene (i.e., objects in a virtual environment).

[0071] It should be noted that in the embodiments of the present application, the virtual scene application programs in the source device 12 and the destination device 14 can be application programs built into the source device 12 and the destination device 14 themselves, or can be application programs provided by third-party service providers installed by users themselves, and no specific limitation is made thereto.

[0072] In addition, the source device 12 and the destination device 14 can install real-time video transmission applications, such as live broadcast applications. The source device 12 and the destination device 14 can collect images / videos through a camera and then display the collected images / videos on a display device.

[0073] In some cases, Figure 1aThe illustrated video decoding system 10 is merely exemplary, and the techniques provided by embodiments of the present application are applicable to video coding settings (e.g., video encoding or video decoding), which may not necessarily include any data communication between an encoding device and a decoding device. In other examples, data is retrieved from local memory, sent over a network, and so on. A video encoding device may encode data and store the data in memory, and / or a video decoding device may retrieve data from memory and decode the data. In some examples, encoding and decoding are performed by devices that do not communicate with each other but only encode data into memory and / or retrieve and decode data from memory.

[0074] Please refer to Figure 1b , Figure 1b FIG. 40 is an exemplary block diagram of a video decoding system provided by an embodiment of the present application. As Figure 1b shown, the video decoding system 40 may include an imaging device 41, a video encoder 20, a video decoder 30 (and / or a video codec implemented by processing circuitry 46), an antenna 42, one or more processors 43, one or more memory memories 44, and / or a display device 45.

[0075] As Figure 1b shown, the imaging device 41, the antenna 42, the processing circuitry 46, the video encoder 20, the video decoder 30, the processor 43, the memory memory 44, and / or the display device 45 are capable of communicating with each other. In different instances, the video decoding system 40 may include only the video encoder 20 or only the video decoder 30.

[0076] In some instances, antenna 42 can be used to transmit or receive an encoded bitstream of video data. Additionally, in some instances, display device 45 can be used to present video data. Processing circuitry 46 can include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like. Video decoding system 40 can also include optional processor 43, which can similarly include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like. Additionally, memory 44 can be any type of memory, such as volatile memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) or non-volatile memory (e.g., flash memory, etc.). In a non-limiting example, memory 44 can be implemented by cache memory. In other instances, processing circuitry 46 can include memory (e.g., cache, etc.) for implementing an image buffer and the like.

[0077] In some instances, video encoder 20 implemented by logic circuitry can include an image buffer (e.g., implemented by processing circuitry 46 or memory 44) and a graphics processing unit (e.g., implemented by processing circuitry 46). The graphics processing unit can be communicatively coupled to the image buffer. The graphics processing unit can include video encoder 20 implemented by processing circuitry 46 to implement various modules discussed with reference to Figure 2 and / or any other encoder system or subsystem described herein. The logic circuitry can be used to perform the various operations discussed herein.

[0078] In some instances, video decoder 30 can be implemented by processing circuitry 46 in a similar manner to implement video decoder 30 discussed with reference to Figure 3 and / or any other decoder system or subsystem described herein. In some instances, video decoder 30 implemented by logic circuitry can include an image buffer (implemented by processing circuitry 46 or memory 44) and a graphics processing unit (e.g., implemented by processing circuitry 46). The graphics processing unit can be communicatively coupled to the image buffer. The graphics processing unit can include video decoder 30 implemented by processing circuitry 46 to implement various modules discussed with reference to Figure 3 and / or any other decoder system or subsystem described herein.

[0079] In some examples, antenna 42 can be used to receive an encoded bitstream of video data. As discussed, the encoded bitstream can include data, indicators, index values, mode selection data, etc. related to the encoded video frames discussed herein, such as data related to encoded partitions (e.g., transform coefficients or quantized transform coefficients, optional indicators as discussed, and / or data defining the encoded partitions). The video decoding system 40 can also include a video decoder 30 coupled to the antenna 42 and configured to decode the encoded bitstream. A display device 45 is used to present video frames.

[0080] It should be understood that for the examples described with reference to the video encoder 20 in the embodiments of the present application, the video decoder 30 can be used to perform the reverse process. Regarding signaling syntax elements, the video decoder 30 can be used to receive and parse such syntax elements and accordingly decode the relevant video data. In some examples, the video encoder 20 can entropy encode the syntax elements into an encoded video bitstream. In such examples, the video decoder 30 can parse such syntax elements and accordingly decode the relevant video data.

[0081] For ease of description, the embodiments of the present application are described with reference to the versatile video coding (VVC) reference software or the high-efficiency video coding (HEVC) developed by the video coding experts group (VCEG) of ITU-T and the joint collaboration team on video coding (JCT-VC) of the ISO / IEC motion picture experts group (MPEG). Those of ordinary skill in the art understand that the embodiments of the present application are not limited to HEVC or VVC.

[0082] Encoder and encoding method

[0083] As Figure 2 As shown, the video encoder 20 includes an input end (or input interface) 201, a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a loop filter 220, a decoded picture buffer (DPB) 230, a mode selection unit 260, an entropy encoding unit 270, and an output end (or output interface) 272. The mode selection unit 260 can include an inter prediction unit 244, an intra prediction unit 254, and a partitioning unit 262. The inter prediction unit 244 can include a motion estimation unit and a motion compensation unit (not shown).Figure 2 The illustrated video encoder 20 may also be referred to as a hybrid video encoder or a video encoder based on a hybrid video codec.

[0084] See Figure 2 , the inter-frame prediction unit is a trained target model (also referred to as a neural network), and the neural network is used to process an input image or an image region or an image block to generate a predicted value of the input image block. For example, the neural network for inter-frame prediction is used to receive an input image or an image region or an image block and generate a predicted value of the input image or an image region or an image block.

[0085] The residual calculation unit 204, the transform processing unit 206, the quantization unit 208, and the mode selection unit 260 form the forward signal path of the encoder 20, while the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the decoded picture buffer (DPB) 230, the inter-frame prediction unit 244, and the intra-frame prediction unit 254 form the backward signal path of the encoder, where the backward signal path of the encoder 20 corresponds to the signal path of the decoder (see Figure 3 the decoder 30 in). The inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded picture buffer 230, the inter-frame prediction unit 244, and the intra-frame prediction unit 254 also form the "built-in decoder" of the video encoder 20.

[0086] Images and image segmentation (images and blocks)

[0087] The encoder 20 can be used to receive an image (or image data) 17 through the input terminal 201, etc. For example, an image in an image sequence forming a video or a video sequence. The received image or image data may also be a preprocessed image (or preprocessed image data) 19. For simplicity, the following description uses the image 17. The image 17 may also be referred to as the current image or the image to be encoded (especially when distinguishing the current image from other images in video coding, such as previously encoded and / or decoded images in the same video sequence, i.e., the video sequence including the current image).

[0088] (Digital) images are or can be regarded as two-dimensional arrays or matrices composed of pixel points with intensity values. Pixel points in the array can also be referred to as pixels (pixel or pel, short for picture element). The number of pixel points in the horizontal and vertical directions (or axes) of the array or image determines the size and / or resolution of the image. To represent color, usually three color components are adopted, that is, the image can be represented as or include three pixel point arrays. In the RBG format or color space, the image includes corresponding red, green, and blue pixel point arrays. However, in video coding, each pixel is usually represented in a luminance / chrominance format or color space, such as YCbCr, including a luminance component indicated by Y (sometimes also denoted by L) and two chrominance components denoted by Cb and Cr. The luminance (luma) component Y represents the luminance or gray-level intensity (e.g., the two are the same in a grayscale image), while the two chrominance components Cb and Cr represent the chrominance or color information components. Correspondingly, an image in the YCbCr format includes a luminance pixel point array of luminance pixel point values (Y) and two chrominance pixel point arrays of chrominance values (Cb and Cr). An image in the RGB format can be converted or transformed into the YCbCr format, and vice versa, and this process is also called color transformation or conversion. If the image is black and white, then the image can only include a luminance pixel point array. Correspondingly, the image can be, for example, a luminance pixel point array in a monochrome format or a luminance pixel point array and two corresponding chrominance pixel point arrays in 4:2:0, 4:2:2, and 4:4:4 color formats.

[0089] In one embodiment, an embodiment of the video encoder 20 may include an image segmentation unit ( Figure 2 not shown in the figure) for segmenting the image 17 into a plurality of (usually non-overlapping) image blocks 203. These blocks may also be referred to as root blocks, macroblocks (H.264 / AVC), or coding tree blocks (CTB), or coding tree units (CTU) in the H.265 / HEVC and VVC standards. The segmentation unit can be used to use the same block size for all images in the video sequence and use a corresponding grid defining the block size, or change the block size between images or subsets or groups of images, and segment each image into corresponding blocks.

[0090] In other embodiments, the video encoder can be used to directly receive the blocks 203 of the image 17, for example, one, several, or all of the blocks constituting the above-mentioned image 17. The image block 203 can also be referred to as the current image block or the image block to be encoded.

[0091] Similar to image 17, image block 203 is also or can be considered as a two-dimensional array or matrix composed of pixel points with intensity values (pixel values), but image block 203 is smaller than image 17. In other words, block 203 can include an array of pixel points (e.g., the luminance array in the case of a monochrome image 17 or the luminance array or chrominance arrays in the case of a color image) or three arrays of pixel points (e.g., one luminance array and two chrominance arrays in the case of a color image 17) or any other number and / or type of arrays according to the color format adopted. The number of pixel points in the horizontal and vertical directions (or axes) of block 203 defines the size of block 203. Accordingly, the block can be an array of M×N (M columns × N rows) pixel points, or an array of M×N transform coefficients, etc.

[0092] In one embodiment, Figure 2 The illustrated video encoder 20 is used to encode image 17 block by block. For example, encoding and prediction are performed on each block 203.

[0093] In one embodiment, Figure 2 The illustrated video encoder 20 can also be used to segment and / or encode an image using slices (also called video slices), where the image can be segmented or encoded using one or more slices (usually non-overlapping). Each slice can include one or more blocks (e.g., coding tree unit CTU) or one or more groups of blocks (e.g., coding blocks (tile) in the H.265 / HEVC / VVC standards and bricks in the VVC standard).

[0094] In one embodiment, Figure 2 The illustrated video encoder 20 can also be used to segment and / or encode an image using slice / coding block group (also called video coding block group) and / or coding block (also called video coding block), where the image can be segmented or encoded using one or more slice / coding block groups (usually non-overlapping), and each slice / coding block group can include one or more blocks (e.g., CTU) or one or more coding blocks, etc., where each coding block can be in a shape such as a rectangle and can include one or more complete or partial blocks (e.g., CTU).

[0095] Residual calculation

[0096] The residual calculation unit 204 is used to calculate the residual block 205 based on the image block (or original block) 203 and the prediction block 265 (the prediction block 265 is introduced in detail later) in the following way: for example, subtracting the pixel values of the prediction block 265 from the pixel values of the image block 203 pixel by pixel (pixel by pixel) to obtain the residual block 205 in the pixel domain.

[0097] Transformation

[0098] The transform processing unit 206 is used to perform a discrete cosine transform (DCT) or a discrete sine transform (DST), etc. on the pixel values of the residual block 205 to obtain transform coefficients 207 in the transform domain. The transform coefficients 207 can also be referred to as transform residual coefficients, representing the residual block 205 in the transform domain.

[0099] The transform processing unit 206 can be used to apply an integer approximation of DCT / DST, such as the transform specified for H.265 / HEVC. Compared with the orthogonal DCT transform, this integer approximation is usually scaled by a certain factor. To maintain the norm of the residual block after forward and inverse transform processing, other scaling factors are used as part of the transform process. The scaling factors are usually selected according to certain constraints, such as the power of 2 for shift operations, the bit depth of the transform coefficients, the trade-off between accuracy and implementation cost, etc. For example, specific scaling factors are specified for the inverse transform by the inverse transform processing unit 212 on the encoder 20 side (and for the corresponding inverse transform by, for example, the inverse transform processing unit 312 on the decoder 30 side), and correspondingly, the corresponding scaling factors can be specified for the forward transform by the transform processing unit 206 on the encoder 20 side.

[0100] In one embodiment, the video encoder 20 (correspondingly, the transform processing unit 206) can be used to output transform parameters such as the type of one or more transforms, for example, directly output or output after being encoded or compressed by the entropy encoding unit 270, such that the video decoder 30 can receive and use the transform parameters for decoding.

[0101] Quantization

[0102] The quantization unit 208 is used to quantize the transform coefficients 207 through, for example, scalar quantization or vector quantization to obtain quantized transform coefficients 209. The quantized transform coefficients 209 can also be referred to as quantized residual coefficients 209.

[0103] The quantization process may reduce the bit depth associated with some or all of the transform coefficients 207. For example, an n-bit transform coefficient may be rounded down to an m-bit transform coefficient during quantization, where n is greater than m. The degree of quantization can be modified by adjusting the quantization parameter (QP). For example, for scalar quantization, different degrees of scaling can be applied to achieve finer or coarser quantization. A smaller quantization step size corresponds to finer quantization, while a larger quantization step size corresponds to coarser quantization. The appropriate quantization step size can be indicated by the quantization parameter (QP). For example, the quantization parameter can be an index of a predefined set of appropriate quantization step sizes. For example, a smaller quantization parameter may correspond to fine quantization (smaller quantization step size), and a larger quantization parameter may correspond to coarse quantization (larger quantization step size), and vice versa. Quantization may include dividing by the quantization step size, and the corresponding or inverse dequantization performed by a dequantization unit 210 etc. may include multiplying by the quantization step size. Embodiments according to some standards such as HEVC may be used to determine the quantization step size using the quantization parameter. Generally, the quantization step size can be calculated using a fixed-point approximation of an equation involving division based on the quantization parameter. Other scaling factors may be introduced for quantization and dequantization to recover the norm of the residual block that may have been modified due to the scaling used in the fixed-point approximation of the equations for the quantization step size and quantization parameter. In one exemplary implementation, the scaling of the inverse transform and dequantization can be combined. Alternatively, a custom quantization table can be used and indicated from the encoder to the decoder in the bitstream etc. Quantization is a lossy operation, where the larger the quantization step size, the greater the loss.

[0104] In one embodiment, the video encoder 20 (correspondingly, the quantization unit 208) may be used to output the quantization parameter (QP), for example, directly output or output after being encoded or compressed by the entropy encoding unit 270, such that the video decoder 30 can receive and use the quantization parameter for decoding.

[0105] Dequantization

[0106] The dequantization unit 210 is used to perform dequantization of the quantization unit 208 on the quantization coefficients to obtain dequantized coefficients 211. For example, it performs a dequantization scheme that is the inverse of the quantization scheme performed by the quantization unit 208 according to or using the same quantization step size as the quantization unit 208. The dequantized coefficients 211 may also be referred to as dequantized residual coefficients 211 and correspond to the transform coefficients 207. However, due to the loss caused by quantization, the dequantized coefficients 211 are usually not exactly the same as the transform coefficients.

[0107] Inverse transform

[0108] The inverse transform processing unit 212 is configured to perform the inverse transform of the transform performed by the transform processing unit 206, such as inverse discrete cosine transform (DCT) or inverse discrete sine transform (DST), to obtain a reconstructed residual block 213 (or corresponding dequantized coefficients 213) in the pixel domain. The reconstructed residual block 213 may also be referred to as the transform block 213.

[0109] Reconstruction

[0110] The reconstruction unit 214 (e.g., adder 214) is configured to add the transform block 213 (i.e., the reconstructed residual block 213) to the prediction block 265 to obtain a reconstructed block 215 in the pixel domain, e.g., adding the pixel point values of the reconstructed residual block 213 and the pixel point values of the prediction block 265.

[0111] Filtering

[0112] The loop filter unit 220 (or simply referred to as "loop filter" 220) is configured to filter the reconstructed block 215 to obtain a filtered block 221, or generally configured to filter the reconstructed pixel points to obtain filtered pixel point values. For example, the loop filter unit is used to smoothly perform pixel transitions or improve video quality. The loop filter unit 220 may include one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as an adaptive loop filter (ALF), a noise suppression filter (NSF), or any combination. For example, the loop filter unit 220 may include a deblocking filter, an SAO filter, and an ALF filter. The order of the filtering process may be a deblocking filter, an SAO filter, and an ALF filter. For another example, a process called luma mapping with chroma scaling (LMCS) (i.e., adaptive in-loop shaper) is added. This process is performed before deblocking. For another example, the deblocking filtering process may also be applied to internal sub-block edges, such as affine sub-block edges, ATMVP sub-block edges, sub-block transform (SBT) edges, and intra sub-partition (ISP) edges. Although the loop filter unit 220 is shown as a loop filter in Figure 2 it may be implemented as a post-loop filter in other configurations. The filtered block 221 may also be referred to as the filtered reconstructed block 221.

[0113] In one embodiment, the video encoder 20 (correspondingly, the loop filter unit 220) can be used to output loop filter parameters (such as SAO filter parameters, ALF filter parameters, or LMCS parameters), for example, directly output or output after entropy coding by the entropy coding unit 270, such that the decoder 30 can receive and use the same or different loop filter parameters for decoding.

[0114] Decoded picture buffer

[0115] The decoded picture buffer (DPB) 230 can be a reference image memory for storing reference image data for use by the video encoder 20 when encoding video data. The DPB 230 can be formed of any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of storage devices. The decoded picture buffer 230 can be used to store one or more filtered blocks 221. The decoded picture buffer 230 can also be used to store other previously filtered blocks of the same current image or different images, such as previously reconstructed images, e.g., previously reconstructed and filtered blocks 221, and can provide the complete previously reconstructed i.e., decoded image (and corresponding reference blocks and pixel points) and / or partially reconstructed current image (and corresponding reference blocks and pixel points), for example, for inter-frame prediction. The decoded picture buffer 230 can also be used to store one or more unfiltered reconstructed blocks 215, or generally store unfiltered reconstructed pixel points, e.g., reconstructed blocks 215 that have not been filtered by the loop filter unit 220, or reconstructed blocks or reconstructed pixel points that have not undergone any other processing.

[0116] Mode selection (segmentation and prediction)

[0117] The mode selection unit 260 includes a segmentation unit 262, an inter-frame prediction unit 244, and an intra-frame prediction unit 254, and is used to receive or obtain original image data such as the original block 203 (the current block 203 of the current image 17) and reconstructed image data from the decoded picture buffer 230 or other buffers (e.g., column buffer, Figure 2 not shown in the figure), for example, filtered and / or unfiltered reconstructed pixel points or reconstructed blocks of the same (current) image and / or one or more previously decoded images. The reconstructed image data is used as reference image data required for prediction such as inter-frame prediction or intra-frame prediction to obtain a predicted block 265 or a predicted value 265.

[0118] The mode selection unit 260 can be used to determine or select a segmentation for the current block (including no segmentation) and a prediction mode (e.g., intra-frame or inter-frame prediction mode), generate a corresponding prediction block 265, to calculate the residual block 205 and reconstruct the reconstructed block 215.

[0119] In one embodiment, the mode selection unit 260 can be used to select a segmentation and a prediction mode (e.g., from the prediction modes supported or available by the mode selection unit 260), where the above prediction mode provides the best match or the smallest residual (the smallest residual means better compression in transmission or storage), or provides the smallest signaling overhead (the smallest signaling overhead means better compression in transmission or storage), or considers or balances both of the above at the same time. The mode selection unit 260 can be used to determine the segmentation and the prediction mode according to rate distortion optimization (RDO), that is, select the prediction mode that provides the smallest rate distortion optimization. The terms "best", "lowest", "optimal", etc. in this article do not necessarily refer to "the best", "the lowest", "the most optimal" in general, but can also refer to the situation that meets the termination or selection criteria. For example, values or other limitations that exceed or are lower than the threshold may lead to "sub-optimal selection", but will reduce the complexity and processing time.

[0120] In other words, the segmentation unit 262 can be used to segment the images in the video sequence into a sequence of coding tree units (CTUs), and the CTU 203 can be further segmented into smaller block parts or sub-blocks (forming blocks again), for example, by iteratively using quadtree (QT) partitioning, binary tree (BT) partitioning, or triple-tree (TT) partitioning or any combination thereof, and used to perform predictions on, for example, each of the block parts or sub-blocks, where mode selection includes selecting the tree structure for segmenting the block 203 and selecting the prediction mode applied to each of the block parts or sub-blocks.

[0121] The segmentation (e.g., performed by the segmentation unit 262) and the prediction processing (e.g., performed by the inter-frame prediction unit 244 and the intra-frame prediction unit 254) performed by the video encoder 20 will be described in detail below.

[0122] Segmentation

[0123] The splitting unit 262 can split (or divide) an image block (or CTU) 203 into smaller parts, such as small blocks in the shape of a square or a rectangle. For an image with an array of three pixel points, a CTU consists of an N×N block of luminance pixel points and two corresponding chrominance pixel point blocks. The maximum allowable size of the luminance block in the versatile video coding (VVC) standard under development is specified as 128×128, but it may be specified as a value different from 128×128 in the future, such as 256×256. The CTUs of an image can be centralized / grouped into slices / coding tree units, coding tree blocks, or tiles. A coding tree block covers a rectangular area of an image, and a coding tree block can be divided into one or more tiles. A tile consists of multiple CTU rows within a coding tree block. A coding tree block that is not divided into multiple tiles can be called a tile. However, a tile is a true subset of a coding tree block and is therefore not called a coding tree block. VVC supports two coding tree unit modes, namely the raster scan slice / coding tree unit mode and the rectangular slice mode. In the raster scan coding tree unit mode, a slice / coding tree unit contains a sequence of coding tree blocks in the raster scan of the coding tree blocks of an image. In the rectangular slice mode, a slice contains multiple tiles of an image, and these tiles together form a rectangular area of the image. The tiles within a rectangular slice are arranged in the tile raster scan order of the slice. These smaller blocks (also called sub-blocks) can be further divided into even smaller parts. This is also called tree splitting or hierarchical tree splitting, where a root block at the root tree level 0 (hierarchical level 0, depth 0), etc., can be recursively split into two or more blocks at the next lower tree level, such as nodes at tree level 1 (hierarchical level 1, depth 1). These blocks can be split into two or more blocks at the next lower level, such as tree level 2 (hierarchical level 2, depth 2), etc., until the splitting ends (because an end criterion is met, such as reaching the maximum tree depth or the minimum block size). Blocks that are not further split are also called leaf blocks or leaf nodes of the tree. A tree split into two parts is called a binary-tree (BT), a tree split into three parts is called a ternary-tree (TT), and a tree split into four parts is called a quad-tree (QT).

[0124] For example, a coding tree unit (CTU) may be or include a CTB of luminance pixel points, two corresponding CTBs of chrominance pixel points of an image having three pixel point arrays, or a CTB of pixel points of a monochrome image or a CTB of pixel points of an image encoded using three independent color planes and a syntax structure (for encoding pixel points). Accordingly, a coding tree block (CTB) may be a block of N×N pixel points, where N may be set to a certain value such that the component is divided into CTBs, which is segmentation. A coding unit (CU) may be or include a coding block of luminance pixel points, two corresponding coding blocks of chrominance pixel points of an image having three pixel point arrays, or a coding block of pixel points of a monochrome image or a coding block of pixel points of an image encoded using three independent color planes and a syntax structure (for encoding pixel points). Accordingly, a coding block (CB) may be a block of M×N pixel points, where M and N may be set to a certain value such that the CTB is divided into coding blocks, which is segmentation.

[0125] For example, in an embodiment, according to HEVC, a coding tree unit (CTU) may be divided into multiple CUs by using a quadtree structure represented as a coding tree. A decision on whether to use inter (temporal) prediction or intra (spatial) prediction to encode an image region is made at the leaf CU level. Each leaf CU may be further divided into one, two, or four PUs according to the PU partition type. The same prediction process is used within one PU, and relevant information is transmitted to the decoder in units of PUs. After obtaining a residual block by applying the prediction process according to the PU partition type, the leaf CU may be segmented into transform units (TUs) according to another quadtree structure similar to the coding tree used for the CU.

[0126] For example, in an embodiment, according to the latest video coding standard currently under development (referred to as Versatile Video Coding (VVC)), a combined quadtree using nested multi-type trees (such as binary trees and ternary trees) is used to divide the segmentation structure for dividing coding tree units. In the coding tree structure within a coding tree unit, a CU can be square or rectangular. For example, a coding tree unit (CTU) is first divided by a quadtree structure. A quadtree leaf node is further divided by a multi-type tree structure. The multi-type tree structure has four division types: vertical binary tree division (SPLIT_BT_VER), horizontal binary tree division (SPLIT_BT_HOR), vertical ternary tree division (SPLIT_TT_VER), and horizontal ternary tree division (SPLIT_TT_HOR). The multi-type tree leaf node is called a coding unit (CU), unless the CU is too large for the maximum transform length. Such a segmentation is used for prediction and transform processing without any further segmentation. In most cases, this means that the CU, PU, and TU have the same block size in the coding block structure of the quadtree nested multi-type tree. This exception occurs when the maximum supported transform length is less than the width or height of the color component of the CU. VVC has developed a unique signaling mechanism for the segmentation division information in the coding structure with a quadtree nested multi-type tree. In the signaling mechanism, a coding tree unit (CTU), as the root of the quadtree, is first divided by the quadtree structure. Then each quadtree leaf node (when large enough to be) is further divided into a multi-type tree structure. In the multi-type tree structure, it is indicated by the first identifier (mtt_split_cu_flag) whether the node is further divided. When the node is further divided, the division direction is first indicated by the second identifier (mtt_split_cu_vertical_flag), and then it is indicated by the third identifier (mtt_split_cu_binary_flag) whether the division is a binary tree division or a ternary tree division. According to the values of mtt_split_cu_vertical_flag and mtt_split_cu_binary_flag, the decoder can derive the multi-type tree division mode (MttSplitMode) of the CU based on predefined rules or tables. It should be noted that for a certain design, such as the 64×64 luma block and 32×32 chroma pipeline design in a VVC hardware decoder, when the width or height of the luma coding block is greater than 64, TT division is not allowed. When the width or height of the chroma coding block is greater than 32, TT division is also not allowed. The pipeline design divides the image into multiple virtual pipeline data units (VPDUs), and each VPDU is defined as a non-overlapping unit in the image. In a hardware decoder, consecutive VPDUs are processed simultaneously in multiple pipeline stages. In most pipeline stages, the VPDU size is roughly proportional to the buffer size, so it is necessary to keep the VPDU small.In most hardware decoders, the VPDU size can be set to the maximum transform block (TB) size. However, in VVC, the splitting of the ternary tree (TT) and binary tree (BT) may increase the VPDU size.

[0127] In addition, it should be noted that when a part of the tree node block extends beyond the bottom or the right image boundary, the tree node block is forced to be divided until all pixel points of each coded CU are within the image boundary.

[0128] For example, the above intra sub - partitions (ISP) tool can divide the luma intra - prediction block vertically or horizontally into two or four sub - parts according to the block size.

[0129] In one example, the mode selection unit 260 of the video encoder 20 can be used to perform any combination of the segmentation techniques described above.

[0130] As described above, the video encoder 20 is used to determine or select the best or optimal prediction mode from a (predetermined) set of prediction modes. The set of prediction modes may include, for example, intra - prediction modes and / or inter - prediction modes.

[0131] Intra - prediction

[0132] The set of intra - prediction modes may include 35 different intra - prediction modes. For example, non - directional modes such as the DC (or mean) mode and the planar mode, or directional modes defined as in HEVC. Or it may include 67 different intra - prediction modes. For example, non - directional modes such as the DC (or mean) mode and the planar mode, or directional modes defined in VVC. For example, several traditional angular intra - prediction modes are adaptively replaced by wide - angle intra - prediction modes for non - square blocks defined in VVC. Also, for example, to avoid the division operation in DC prediction, only the longer side is used to calculate the average value of non - square blocks. And the intra - prediction result of the planar mode can also be modified using the position - dependent intra - prediction combination (PDPC) method.

[0133] The intra - prediction unit 254 is used to generate an intra - prediction block 265 by reconstructing pixel points using adjacent blocks of the same current image according to the intra - prediction modes in the set of intra - prediction modes.

[0134] The intra-frame prediction unit 254 (or generally the mode selection unit 260) is also used to output intra-frame prediction parameters (or generally information indicating the selected intra-frame prediction mode of the block) in the form of syntax elements 266 to the entropy coding unit 270 for inclusion in the encoded image data 21, so that the video decoder 30 can perform operations, such as receiving and using the prediction parameters for decoding.

[0135] The intra prediction modes in HEVC include DC prediction mode, plane prediction mode and 33 angle prediction modes, with a total of 35 candidate prediction modes. The current block can use the pixels of the reconstructed image blocks on the left and above as references for intra prediction. The image blocks in the surrounding area of the current block used for intra prediction of the current block become reference blocks, and the pixels in the reference blocks are called reference pixels. Among the 35 candidate prediction modes, the DC prediction mode is applicable to the area with flat texture in the current block, and all pixels in this area use the average value of the reference pixels in the reference block as prediction; the plane prediction mode is applicable to image blocks with smoothly changing textures. The current block that meets this condition uses the reference pixels in the reference block for bilinear interpolation as the prediction of all pixels in the current block; the angle prediction mode uses the characteristics that the texture of the current block is highly correlated with the texture of the adjacent reconstructed image blocks, and copies the values of the reference pixels in the corresponding reference block along a certain angle as the prediction of all pixels in the current block.

[0136] The HEVC encoder selects an optimal intra-frame prediction mode for the current block from 35 candidate prediction modes and writes the optimal intra-frame prediction mode into the video bitstream. To improve the coding efficiency of intra-frame prediction, the encoder / decoder derives three most likely modes from the optimal intra-frame prediction modes of the reconstructed image blocks in the surrounding area using intra-frame prediction. If the optimal intra-frame prediction mode selected for the current block is one of the three most likely modes, a first index is encoded to indicate that the selected optimal intra-frame prediction mode is one of the three most likely modes; if the selected optimal intra-frame prediction mode is not one of the three most likely modes, a second index is encoded to indicate that the selected optimal intra-frame prediction mode is one of the other 32 modes (other modes among the 35 candidate prediction modes except the aforementioned three most likely modes). The HEVC standard uses a 5-bit fixed-length code as the aforementioned second index.

[0137] The methods for the HEVC encoder to derive the three most probable modes include: selecting the optimal intra prediction modes of the left adjacent picture block and the upper adjacent picture block of the current block and putting them into a set. If these two optimal intra prediction modes are the same, only one of them needs to be retained in the set. If these two optimal intra prediction modes are the same and both are angular prediction modes, then select two angular prediction modes adjacent to this angular direction and add them to the set; otherwise, sequentially select the planar prediction mode, the DC mode, and the vertical prediction mode and add them to the set until the number of modes in the set reaches 3.

[0138] After the HEVC decoder performs entropy decoding on the bitstream, it obtains the mode information of the current block. This mode information includes an indication flag indicating whether the optimal intra prediction mode of the current block is among the three most probable modes, and the index of the optimal intra prediction mode of the current block among the three most probable modes or the index of the optimal intra prediction mode of the current block among the other 32 modes.

[0139] Inter-frame prediction

[0140] In a possible implementation, the inter-frame prediction mode set depends on the available reference images (i.e., for example, at least some of the previously decoded images stored in the DBP 230 as described above) and other inter-frame prediction parameters. For example, it depends on whether to use the entire reference image or only a part of the reference image, such as the search window area near the region of the current block, to search for the best matching reference block, and / or for example, it depends on whether to perform pixel interpolation of half pixels, quarter pixels, and / or sixteenth pixels.

[0141] In addition to the above prediction modes, skip mode and / or direct mode can also be adopted.

[0142] For example, for extended merge prediction, the merge candidate list for this mode consists of the following five candidate types in order: spatial MVP from spatially adjacent CUs, temporal MVP from collocated CUs, history-based MVP from the FIFO table, pairwise average MVP, and zero MV. A decoder side motion vector refinement (DMVR) based on bilateral matching can be used to increase the accuracy of the MVs of the merge mode. The merge mode with MVD (MMVD) comes from the merge mode with motion vector difference. The MMVD flag is sent immediately after the skip flag and the merge flag to specify whether the CU uses the MMVD mode. A CU-level adaptive motion vector resolution (AMVR) scheme can be used. AMVR supports encoding the MVD of the CU with different precisions. The MVD of the current CU is adaptively selected according to the prediction mode of the current CU. When the CU is encoded in the merge mode, the combined inter / intra prediction (CIIP) mode can be applied to the current CU. The inter and intra prediction signals are weighted and averaged to obtain the CIIP prediction. For affine motion compensation prediction, the affine motion field of the block is described by the motion information of the motion vectors of 2 control points (4 parameters) or 3 control points (6 parameters). The subblock-based temporal motion vector prediction (SbTMVP) is similar to the temporal motion vector prediction (TMVP) in HEVC, but predicts the motion vectors of the sub-CUs within the current CU. The bi-directional optical flow (BDOF), formerly known as BIO, is a simplified version that reduces calculations, especially in terms of the number of multiplications and the size of the multipliers. In the triangular split mode, the CU is evenly split into two triangular parts in two split ways: diagonal split and anti-diagonal split. In addition, the bi-directional prediction mode is extended based on simple averaging to support weighted averaging of two prediction signals.

[0143] The inter prediction unit 244 may include a motion estimation (ME) unit and a motion compensation (MC) unit (both in Figure 2(not shown in the figure). The motion estimation unit can be used to receive or obtain the image block 203 (the current image block 203 of the current image 17) and the decoded image 231, or at least one or more previously reconstructed blocks, for example, the reconstructed blocks of one or more other / different previously decoded images 231, to perform motion estimation. For example, the video sequence can include the current image and the previously decoded image 231, or in other words, the current image and the previously decoded image 231 can be part of the image sequence forming the video sequence or form the image sequence.

[0144] For example, the encoder 20 can be used to select a reference block from multiple reference blocks of the same or different images in multiple other images, and provide the offset (spatial offset) between the reference image (or reference image index) and / or the position (x, y coordinates) of the reference block and the position of the current block as an inter-frame prediction parameter to the motion estimation unit. This offset is also called a motion vector (MV).

[0145] The motion compensation unit is used to obtain, for example, receive, the inter-frame prediction parameter, and perform inter-frame prediction according to or using the inter-frame prediction parameter to obtain the inter-frame prediction block 246. The motion compensation performed by the motion compensation unit may include extracting or generating a prediction block according to the motion / block vector determined by motion estimation, and may also include performing interpolation with sub-pixel accuracy. The interpolation filter can generate pixel points of other pixels from the pixel points of known pixels, thereby potentially increasing the number of candidate prediction blocks available for encoding the image block. Once the motion vector corresponding to the PU of the current image block is received, the motion compensation unit can locate the prediction block pointed to by the motion vector in one of the reference image lists.

[0146] The motion compensation unit can also generate syntax elements related to the block and the video slice for the video decoder 30 to use when decoding the image blocks of the video slice. In addition, or as an alternative to the slice and the corresponding syntax elements, coded block groups and / or coded blocks and the corresponding syntax elements can be generated or used.

[0147] In the process of obtaining the candidate motion vector list in the advanced motion vector prediction (AMVP) mode, the motion vectors (MVs) that can be added to the candidate motion vector list as an alternative include the MVs of the spatially adjacent and temporally adjacent image blocks of the current block, where the MVs of the spatially adjacent image blocks can include the MVs of the left candidate image block located on the left side of the current block and the MVs of the upper candidate image block located above the current block. Exemplarily, please refer to Figure 4 , Figure 4 which is an exemplary schematic diagram of the candidate image block provided by the embodiment of the present application, such as Figure 4As shown, the set of left candidate image blocks includes {A0, A1}, the set of upper candidate image blocks includes {B0, B1, B2}, and the set of temporally adjacent candidate image blocks includes {C, T}. All three sets can be added as alternatives to the candidate motion vector list. However, according to the existing coding standard, the maximum length of the candidate motion vector list of AMVP is 2. Therefore, it is necessary to determine at most two MVs of image blocks to be added to the candidate motion vector list from the three sets according to the specified order. This order can be to first consider the set of left candidate image blocks {A0, A1} of the current block (first consider A0, and if A0 is not available, then consider A1), secondly consider the set of upper candidate image blocks {B0, B1, B2} of the current block (first consider B0, if B0 is not available, then consider B1, and if B1 is not available, then consider B2), and finally consider the set of temporally adjacent candidate image blocks {C, T} of the current block (first consider T, and if T is not available, then consider C).

[0148] After obtaining the above candidate motion vector list, the optimal MV is determined from the candidate motion vector list through the rate distortion cost (RDcost), and the candidate motion vector with the minimum RD cost is used as the motion vector predictor (MVP) of the current block. The rate distortion cost is calculated by the following formula:

[0149] J = SAD + λR

[0150] where J represents the RD cost, SAD is the sum of absolute differences (SAD) between the pixel values of the predicted block obtained by motion estimation using the candidate motion vector and the pixel values of the current block, R represents the bit rate, and λ represents the Lagrange multiplier.

[0151] The encoder transmits the index of the determined MVP in the candidate motion vector list to the decoder. Further, motion search can be performed within the neighborhood centered on the MVP to obtain the actual motion vector of the current block. The encoder calculates the motion vector difference (MVD) between the MVP and the actual motion vector, and also transmits the MVD to the decoder. The decoder parses the index, finds the corresponding MVP in the candidate motion vector list according to the index, parses the MVD, and adds the MVD to the MVP to obtain the actual motion vector of the current block.

[0152] In the process of obtaining the candidate motion information list in the Merge mode, the motion information that can be added to the candidate motion information list as an alternative includes the motion information of the spatially or temporally adjacent image blocks of the current block, where the spatially adjacent image blocks and the temporally adjacent image blocks can be referred to Figure 4 , the candidate motion information corresponding to the spatial domain in the candidate motion information list comes from 5 spatially adjacent blocks (A0, A1, B0, B1, and B2). If the spatially adjacent blocks are not available or are intra-frame predicted, their motion information is not added to the candidate motion information list. The candidate motion information in the temporal domain of the current block is obtained by scaling the MV of the corresponding block in the reference frame according to the picture order count (POC) of the reference frame and the current frame. First, it is judged whether the block at position T in the reference frame is available. If it is not available, the block at position C is selected. After obtaining the above candidate motion information list, the optimal motion information is determined from the candidate motion information list through the RD cost as the motion information of the current block. The encoding end transmits the index value of the position of the optimal motion information in the candidate motion information list (denoted as mergeindex) to the decoding end.

[0153] Entropy coding

[0154] The entropy coding unit 270 is used to apply an entropy coding algorithm or scheme (for example, variable length coding (VLC) scheme, context adaptive VLC (CALVC), arithmetic coding scheme, binarization algorithm, context adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or other entropy coding methods or techniques) to the quantized residual coefficients 209, inter-frame prediction parameters, intra-frame prediction parameters, loop filter parameters, and / or other syntax elements, to obtain encoded image data 21 that can be output in the form of an encoded bitstream 21, etc. through the output end 272, so that a video decoder 30, etc. can receive and use the parameters for decoding. The encoded bitstream 21 can be transmitted to the video decoder 30, or saved in a memory for later transmission or retrieval by the video decoder 30.

[0155] Other structural variants of the video encoder 20 can be used to encode a video stream. For example, a non-transform-based encoder 20 can directly quantize the residual signal in the case where some blocks or frames do not have a transform processing unit 206. In another implementation, the encoder 20 can have a quantization unit 208 and an inverse quantization unit 210 combined into a single unit.

[0156] Decoder and decoding method

[0157] As Figure 3 shown, the video decoder 30 is used to receive, for example, encoded image data 21 (e.g., an encoded bitstream 21) encoded by the encoder 20 to obtain a decoded image 331. The encoded image data or bitstream includes information for decoding the above-mentioned encoded image data, such as data representing image blocks of an encoded video slice (and / or an encoded group of blocks or an encoded block) and associated syntax elements.

[0158] In Figure 3 the example of, the decoder 30 includes an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (e.g., an adder 314), a loop filter 320, a decoded picture buffer (DBP) 330, a mode application unit 360, an inter prediction unit 344, and an intra prediction unit 354. The inter prediction unit 344 can be or include a motion compensation unit. In some examples, the video decoder 30 can perform a decoding process that is generally opposite to the encoding process described with reference to Figure 2 the video encoder 100.

[0159] As with the encoder 20 above, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter 220, the decoded picture buffer DPB 230, the inter prediction unit 344, and the intra prediction unit 354 also form the "built-in decoder" of the video encoder 20. Correspondingly, the inverse quantization unit 310 can be functionally the same as the inverse quantization unit 110, the inverse transform processing unit 312 can be functionally the same as the inverse transform processing unit 122, the reconstruction unit 314 can be functionally the same as the reconstruction unit 214, the loop filter 320 can be functionally the same as the loop filter 220, and the decoded picture buffer 330 can be functionally the same as the decoded picture buffer 230. Therefore, the explanations of the corresponding units and functions of the video encoder 20 correspondingly apply to the corresponding units and functions of the video decoder 30.

[0160] Entropy decoding

[0161] The entropy decoding unit 304 is used to parse the bitstream 21 (or generally the encoded image data 21) and perform entropy decoding on the encoded image data 21 to obtain quantization coefficients 309 and / or decoded encoding parameters ( Figure 3etc. (not shown in the figure), such as any one or all of inter - frame prediction parameters (e.g., reference image index and motion vector), intra - frame prediction parameters (e.g., intra - frame prediction mode or index), transform parameters, quantization parameters, loop filter parameters, and / or other syntax elements. The entropy decoding unit 304 can be used to apply a decoding algorithm or scheme corresponding to the encoding scheme of the entropy encoding unit 270 of the encoder 20. The entropy decoding unit 304 can also be used to provide inter - frame prediction parameters, intra - frame prediction parameters, and / or other syntax elements to the mode application unit 360, and provide other parameters to other units of the decoder 30. The video decoder 30 can receive syntax elements at the video slice and / or video block level. Additionally, or as an alternative to the slice and the corresponding syntax elements, coded block groups and / or coded blocks and the corresponding syntax elements can be received or used.

[0162] In some implementations, the video decoder 30 can include multiple entropy decoding units 304. For example, in a privacy - protection scenario, the bitstream obtained by encoding video images includes a privacy bitstream and a non - privacy bitstream. Therefore, the video decoder 30 can include two entropy decoding units 304. One entropy decoding unit 304 is used to parse the privacy bitstream in the bitstream, and the other entropy decoding unit 304 is used to parse the non - privacy bitstream in the bitstream.

[0163] Inverse quantization

[0164] The inverse quantization unit 310 can be used to receive a quantization parameter (QP) (or generally information related to inverse quantization) and quantized coefficients from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304), and inverse - quantize the decoded quantized coefficients 309 based on the above quantization parameter to obtain inverse - quantized coefficients 311. The inverse - quantized coefficients 311 can also be referred to as transform coefficients 311. The inverse - quantization process can include using the quantization parameter calculated by the video encoder 20 for each video block in the video slice to determine the quantization degree, and also determine the degree of inverse quantization to be performed.

[0165] Inverse transform

[0166] The inverse transform processing unit 312 can be used to receive the de - quantized coefficients 311, also referred to as transform coefficients 311, and apply a transform to the de - quantized coefficients 311 to obtain a reconstructed residual block 213 in the pixel domain. The reconstructed residual block 213 can also be referred to as a transform block 313. The transform can be an inverse transform, such as an inverse DCT, inverse DST, inverse integer transform, or a conceptually similar inverse - transform process. The inverse transform processing unit 312 can also be used to receive transform parameters or corresponding information from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304) to determine the transform to be applied to the de - quantized coefficients 311.

[0167] Reconstruction

[0168] The reconstruction unit 314 (e.g., the adder 314) is used to add the reconstruction residual block 313 to the prediction block 365 to obtain the reconstruction block 315 in the pixel domain. For example, the pixel values of the reconstruction residual block 313 and the pixel values of the prediction block 365 are added together.

[0169] Filtering

[0170] The loop filter unit 320 (in or after the encoding loop) is used to filter the reconstruction block 315 to obtain the filtered block 321, so as to smoothly perform pixel conversion or improve video quality, etc. The loop filter unit 320 may include one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or one or more other filters, such as an adaptive loop filter (ALF), a noise suppression filter (NSF), or any combination. For example, the loop filter unit 220 may include a deblocking filter, an SAO filter, and an ALF filter. The order of the filtering process may be the deblocking filter, the SAO filter, and the ALF filter. For another example, a process called luma mapping with chroma scaling (LMCS) (i.e., an adaptive in-loop shaper) is added. This process is performed before deblocking. For another example, the deblocking filtering process may also be applied to internal sub-block edges, such as affine sub-block edges, ATMVP sub-block edges, sub-block transform (SBT) edges, and intra sub-partition (ISP) edges. Although the loop filter unit 320 is shown as a loop filter in Figure 3 it may be implemented as a post-loop filter in other configurations.

[0171] Decoded picture buffer

[0172] Subsequently, the decoded video block 321 in an image is stored in the decoded picture buffer 330. The decoded picture buffer 330 stores the decoded picture 331 as a reference picture, and the reference picture is used for subsequent motion compensation of other pictures and / or output display respectively.

[0173] The decoder 30 is used to output the decoded picture 311 through the output terminal 312, etc., for display to the user or for the user to view.

[0174] Prediction

[0175] The inter-frame prediction unit 344 may be functionally the same as the inter-frame prediction unit 244 (specifically, the motion compensation unit), and the intra-frame prediction unit 354 may be functionally the same as the inter-frame prediction unit 254, and determines the division or segmentation and performs prediction based on the segmentation and / or prediction parameters or corresponding information received from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304). The mode application unit 360 may be used to perform prediction (intra-frame or inter-frame prediction) for each block according to the reconstructed image, block, or corresponding pixel points (filtered or unfiltered), resulting in a predicted block 365.

[0176] When encoding a video slice as an intra-coded (I) slice, the intra-frame prediction unit 354 in the mode application unit 360 is used to generate a predicted block 365 for the image block of the current video slice according to the indicated intra-frame prediction mode and data from the previously decoded blocks of the current image. When the video image is encoded as an inter-coded (i.e., B or P) slice, the inter-frame prediction unit 344 (e.g., the motion compensation unit) in the mode application unit 360 is used to generate a predicted block 365 for the video block of the current video slice according to the motion vector and other syntax elements received from the entropy decoding unit 304. For inter-frame prediction, these predicted blocks may be generated from one of the reference images in one of the reference image lists. The video decoder 30 may use the default construction technique to construct reference frame list 0 and list 1 according to the reference images stored in the DPB 330. In addition to slices (e.g., video slices) or as an alternative to slices, the same or similar process may be applied to embodiments of coded block groups (e.g., video coded block groups) and / or coded blocks (e.g., video coded blocks), e.g., video may be encoded using I, P, or B coded block groups and / or coded blocks.

[0177] The mode application unit 360 is used to determine the prediction information for the video block of the current video slice by parsing the motion vector and other syntax elements, and uses the prediction information to generate a predicted block for the current video block being decoded. For example, the mode application unit 360 uses some received syntax elements to determine the prediction mode (e.g., intra-frame prediction or inter-frame prediction) for the video block of the encoded video slice, the inter-frame prediction slice type (e.g., B slice, P slice, or GPB slice), the construction information for one or more reference image lists for the slice, the motion vector for each inter-frame coded video block of the slice, the inter-frame prediction state for each inter-frame coded video block of the slice, and other information to decode the video block within the current video slice. In addition to slices (e.g., video slices) or as an alternative to slices, the same or similar process may be applied to embodiments of coded block groups (e.g., video coded block groups) and / or coded blocks (e.g., video coded blocks), e.g., video may be encoded using I, P, or B coded block groups and / or coded blocks.

[0178] In one embodiment, Figure 3The video decoder 30 can also be used to segment and / or decode an image using slices (also referred to as video slices), where the image can be segmented or decoded using one or more slices (usually non-overlapping). Each slice can include one or more blocks (e.g., CTUs) or one or more block groups (e.g., coding tree units in the H.265 / HEVC / VVC standards and tiles in the VVC standard).

[0179] In one embodiment, Figure 3 the illustrated video decoder 30 can also be used to segment and / or decode an image using slice / coding tree unit groups (also referred to as video coding tree unit groups) and / or coding tree units (also referred to as video coding tree units), where the image can be segmented or decoded using one or more slice / coding tree unit groups (usually non-overlapping), each slice / coding tree unit group can include one or more blocks (e.g., CTUs) or one or more coding tree units, etc., where each coding tree unit can be in a shape such as a rectangle and can include one or more whole or partial blocks (e.g., CTUs).

[0180] Other variants of the video decoder 30 can be used to decode the encoded image data 21. For example, the decoder 30 can produce an output video stream without the loop filter unit 320. For example, a non-transform-based decoder 30 can directly dequantize the residual signal without the inverse transform processing unit 312 for certain blocks or frames. In another implementation, the video decoder 30 can have the dequantization unit 310 and the inverse transform processing unit 312 combined into a single unit.

[0181] It should be understood that in the encoder 20 and the decoder 30, the processing result of the current step can be further processed and then output to the next step. For example, after interpolation filtering, motion vector derivation, or loop filtering, further operations such as clip or shift operations can be performed on the processing result of interpolation filtering, motion vector derivation, or loop filtering.

[0182] It should be noted that further operations can be performed on the derived motion vectors of the current block (including but not limited to the control point motion vectors in the affine mode, the sub-block motion vectors in the affine, planar, and ATMVP modes, the temporal motion vectors, etc.). For example, the value of the motion vector can be restricted to a predefined range according to the representation bits of the motion vector. If the representation bits of the motion vector are bitDepth, the range is from -2^(bitDepth - 1) to 2^(bitDepth - 1) - 1, where "^" represents exponentiation. For example, if bitDepth is set to 16, the range is from -32768 to 32767; if bitDepth is set to 18, the range is from -131072 to 131071. For example, the values of the derived motion vectors (such as the MVs of 4 4×4 sub-blocks in an 8×8 block) are restricted such that the maximum difference between the integer parts of the above 4 4×4 sub-block MVs does not exceed N pixels, for example, does not exceed 1 pixel. Two methods for restricting the motion vector according to bitDepth are provided here.

[0183] Although the above embodiments mainly describe video coding and decoding, it should be noted that the embodiments of the decoding system 10, the encoder 20, and the decoder 30, as well as other embodiments described herein, can also be used for still image processing or coding and decoding, that is, the processing or coding and decoding of a single image independent of any previous or consecutive images in video coding and decoding. Generally, if the image processing is limited to a single image 17, the inter-frame prediction units 244 (encoder) and 344 (decoder) may not be available. All other functions (also referred to as tools or techniques) of the video encoder 20 and the video decoder 30 can equally be used for static image processing, such as residual calculation 204 / 304, transformation 206, quantization 208, dequantization 210 / 310, (inverse) transformation 212 / 312, segmentation 262 / 362, intra-frame prediction 254 / 354, and / or loop filtering 220 / 320, entropy coding 270, and entropy decoding 304.

[0184] Please refer to Figure 5 , Figure 5 which is an exemplary block diagram of the video decoding device 500 provided by the embodiments of the present application. The video decoding device 500 is suitable for implementing the disclosed embodiments described herein. In one embodiment, the video decoding device 500 can be a decoder, such as Figure 1a the video decoder 30 in Figure 1a or an encoder, such as

[0185] The video decoding device 500 includes: an input port 510 (or input port 510) for receiving data and a receiver unit (Rx) 520; a processor, logic unit, or central processing unit (CPU) 530 for processing data; for example, the processor 530 here may be a neural network processor 530; a transmitter unit (Tx) 540 and an output port 550 (or output port 550) for transmitting data; and a memory 560 for storing data. The video decoding device 500 may further include optical-to-electrical (OE) components and electrical-to-optical (EO) components coupled to the input port 510, the receiving unit 520, the transmitting unit 540, and the output port 550 for the exit or entry of optical or electrical signals.

[0186] The processor 530 is implemented by hardware and software. The processor 530 can be implemented as one or more processor chips, cores (e.g., multi-core processors), FPGAs, ASICs, and DSPs. The processor 530 communicates with the input port 510, the receiving unit 520, the transmitting unit 540, the output port 550, and the memory 560. The processor 530 includes a decoding module 570 (e.g., a neural network-based decoding module 570). The decoding module 570 implements the embodiments disclosed above. For example, the decoding module 570 performs, processes, prepares, or provides various encoding operations. Thus, the decoding module 570 provides a substantial improvement to the functions of the video decoding device 500 and affects the switching of the video decoding device 500 to different states. Alternatively, the decoding module 570 is implemented by instructions stored in the memory 560 and executed by the processor 530.

[0187] The memory 560 includes one or more disks, tape drives, and solid-state drives and can be used as an overflow data storage device for storing such programs when a selected program is to be executed and for storing instructions and data read during the execution of the program. The memory 560 can be volatile and / or non-volatile and can be read-only memory (ROM), random access memory (RAM), ternary content-addressable memory (TCAM), and / or static random-access memory (SRAM).

[0188] Please refer to Figure 6 , Figure 6An exemplary block diagram of the apparatus 600 provided by an embodiment of the present application. The apparatus 600 can be used as Figure 1a either or both of the source device 12 and the destination device 14 in

[0189] The processor 602 in the apparatus 600 can be a central processing unit. Alternatively, the processor 602 can be any other type of device or multiple devices that can manipulate or process information, existing or to be developed in the future. Although a single processor such as Figure 6 the processor 602 shown can be used to implement the disclosed implementations, using more than one processor is faster and more efficient.

[0190] In one implementation, the memory 604 in the apparatus 600 can be a read-only memory (ROM) device or a random access memory (RAM) device. Any other suitable type of storage device can be used as the memory 604. The memory 604 can include code and data 606 that the processor 602 accesses via the bus 612. The memory 604 can also include an operating system 608 and application programs 610, and the application programs 610 include at least one program that allows the processor 602 to execute the methods described above in this document. For example, the application programs 610 can include applications 1 to N, and also include a video decoding application that executes the methods described above in this document.

[0191] The apparatus 600 can also include one or more output devices, such as a display 618. In one example, the display 618 can be a touch-sensitive display that combines a display with a touch-sensitive element that can be used to sense touch inputs. The display 618 can be coupled to the processor 602 via the bus 612.

[0192] Although the bus 612 in the apparatus 600 is described as a single bus in this document, the bus 612 can include multiple buses. In addition, the auxiliary storage can be directly coupled to other components of the apparatus 600 or accessed via a network, and can include a single integrated unit such as a memory card or multiple units such as multiple memory cards. Therefore, the apparatus 600 can have various configurations.

[0193] Combined with the above content, the embodiments of the present application relate to processing a bitstream (which can also be referred to as a code stream) obtained by encoding a video / image. Specifically, it relates to bitstream extraction, that is, extracting a bitstream of a specific layer from the bitstream to obtain a sub-bitstream (or referred to as a sub-stream). It can be understood that during the encoding process, the images in the video sequence can be hierarchically processed, and the hierarchically processed images are encoded to obtain a bitstream. That is to say, the bitstream includes multiple hierarchically structured bitstreams.

[0194] First, an introduction to the relevant content of the hierarchical structure is given. Hierarchical processing of a video sequence can include spatial hierarchical processing and temporal hierarchical processing.

[0195] Among them, spatial domain layering means that within the spatial domain, an image includes multiple images with different resolutions, that is, an image within the spatial domain includes multiple layered images (or multiple layers). Each layer is set with a layer identifier (layer id). For example, if an image includes 4 layers in the spatial domain, the values of the layer identifiers (layer_id[i], where i represents the i-th layer) of the 4 layers can be 0, 1, 2, and 3 respectively, that is, layer_id[0]=0, layer_id[1]=1, layer_id[2]=2, layer_id[3]=3.

[0196] Temporal domain layering means that within the temporal domain, in order to effectively reflect the dependency relationship between images, images are divided into multiple temporal layers. Each image has a temporal layer identifier number (which can also be simply referred to as the temporal layer number, that is, temporal_id) indicating the temporal layer to which it belongs. A temporal layer can include one or multiple images. It should be noted that low-layer images (with a small temporal layer identifier number) do not use images with a higher temporal layer identifier number as references, that is, low-layer images do not depend on high-layer images for encoding and decoding. Based on the principle that low-layer images do not depend on high-layer images, for example, for images with a picture order count (POC) of 0 - 8, the images with POC of 0, 4, and 8 are divided into one temporal layer, and the temporal_id is 0, so it can be known that the temporal_id of the images with POC of 0, 4, and 8 is the same; the images with POC of 2 and 6 are divided into one temporal layer, and the temporal_id is 1; the images with POC of 1, 3, 5, and 7 are divided into one temporal layer, and the temporal_id is 2.

[0197] Currently, during the video / image encoding process, layer-related information, including the number of layers and inter-layer dependency information, is transmitted through the sequence parameter set (SPS), and it supports extracting the bitstream of a specific layer for independent decoding. However, after the extraction of the sub-stream (which can also be called the sub-bitstream, and the sub-bitstream refers to the bitstream of a specific layer extracted from the complete bitstream), the layer information of the bitstream has changed, and there is currently no information indicating the layer information of the extracted sub-stream.

[0198] Referring to Table 1 below, Table 1 shows the layer-related information transmitted by the raw byte sequence payload (RBSP) of the SPS in the current layer encoding scenario.

[0199] Table 1. Definition of the sequence parameter set RBSP

[0200]

[0201] "..." in Table 1 above represents the omitted content, and Table 1 only shows several syntax elements related to hierarchical coding.

[0202] Among them, num_of_layers_minus1 represents the number of spatial layers, which is an unsigned integer of 2 bits. Adding 1 indicates the number of layers of the spatial layer structure. num_of_layers_minus1 is only transmitted in the bitstream when the profile is 0xXX. The value of NumOfLayers (number of layers) is equal to num_of_layers_minus1 + 1. If num_of_layers_minus1 does not exist in the bitstream, the value of NumOfLayers is equal to 1. The value range of NumOfLayers should be 1 to MAX_LAYER.

[0203] sps_all_independent_layers_flag represents the total flag for independent coding of spatial layers, which is a binary variable. A value of '1' indicates that all spatial layers are independently coded and inter-layer dependent coding is not used. A value of '0' indicates that there is inter-layer dependent coding. The value of SpsAllIndependentLayersFlag is equal to the value of sps_all_independent_layers_flag. If sps_all_independent_layers_flag does not exist in the bitstream, the value of SpsAllIndependentLayersFlag is equal to 1.

[0204] sps_independent_layer_flag[i] represents the independent coding flag of the i-th spatial layer, which is a binary variable. A value of '1' indicates that the spatial layer with LayerId (layer identification) equal to i is independently coded and inter-layer dependent coding is not used. A value of '0' indicates that the spatial layer with LayerId equal to i can use inter-layer dependent coding. The value of SpsIndependentLayerFlag[i] is equal to the value of sps_independent_layer_flag[i]. If sps_independent_layer_flag[i] does not exist in the bitstream, the value of SpsIndependentLayerFlag[i] is equal to 1.

[0205] ref_layer_id[i] represents the dependency layer number of the i-th layer in the spatial domain, which is an unsigned integer with 2 digits. It is stipulated that the value of LayerId of the reference layer of the inter-layer dependency coding of the spatial layer with LayerId equal to i, that is, the reference layer identifier of the spatial layer with LayerId equal to i. The value range of ref_layer_id[i] is 0 to NumOfLayers - 1. The value of RefLayerId[i] is equal to ref_layer_id[i].

[0206] Regarding the problem of how to extract the bitstream of a specific layer in the bitstream for independent decoding during the above-mentioned hierarchical coding scenario, and how to handle the change of hierarchical information, the embodiments of the present application provide a bitstream processing method, which can realize bitstream extraction and can indicate new hierarchical information in the sub-bitstream.

[0207] During the video / image coding process, the bitstream received by the bitstream processing device (such as the decoding end) may be the bitstream that has not been processed (or edited) by the coding end after video / image coding (which can be understood as the original bitstream), or the bitstream received by the decoding end can also be the bitstream processed by the coding end on the original bitstream, or the bitstream processed by other devices. The bitstream processing device can extract the sub-bitstream from the bitstream according to the bitstream processing method provided by the embodiments of the present application. It should be understood that the bitstream contains syntax elements that act on the coded video sequence or image, such as syntax elements related to hierarchical coding, such as num_of_layers_minus1, sps_all_independent_layers_flag, sps_independent_layer_flag[i], ref_layer_id[i], etc. mentioned above.

[0208] Combined with the above content, the bitstream processing method provided by the embodiments of the present application will be described in detail below taking the bitstream processing device as the decoding end as an example. The bitstream processing method provided by the embodiments of the present application can be applied to the above Figure 1a 、 Figure 1b or Figure 3 in the decoder 30 (or video decoder 30).

[0209] As Figure 7 shown, the embodiments of the present application provide a bitstream processing method, which can be applied to the decoding end or other devices that can edit or process the bitstream. The method includes S701 - S703.

[0210] S701. Obtain the bitstream (inBitStream) of the target image. This bitstream includes the bitstreams of at least one layer after hierarchical encoding of the target image. The bitstream includes first layer information, and the first layer information contains first indication information for indicating the number of layers included in the bitstream and second indication information for indicating the layer identifier of the layers included in the bitstream.

[0211] In the embodiments of the present application, the bitstream obtained by the decoding end may be the original bitstream. Then the obtained bitstream is the bitstream obtained by hierarchical encoding of the target image. It is possible that the bitstream obtained by the decoding end is the processed bitstream, such as the bitstream after bitstream extraction performed by other devices.

[0212] Optionally, the first layer information (including the first indication information and the second indication information) is carried in the supplement enhancement information (SEI) in the bitstream. Refer to Table 2 and Table 3 below. Among them, Table 2 is the supplement enhancement payload syntax definition, and Table 3 is the layer information payload syntax definition.

[0213] Table 2

[0214]

[0215]

[0216] Table 3

[0217]

[0218] In the embodiments of the present application, the first indication information and the second indication information are added to the supplement enhancement information. According to Table 2, in the payload of the supplement enhancement information, the payload with the payload type (i.e., PayloadType) of 25 contains layer information (such as layer_info). According to Table 3, the layer_info includes the first indication information for indicating the number of layers and the second indication information for indicating the layer identifier. Combining Table 2 and Table 3, among them, the first indication information may be the layer number flag bit (sei_num_of_layers_minus1 in Table 3), and the second indication information may be the LayerID of the i-th layer in the target image in the bitstream (sei_layer_id[i] in Table 3).

[0219] The above sei_num_of_layers_minus1 is an unsigned integer of 2 bits. Adding 1 identifies the number of layers of the hierarchical structure. The value of sei_num_of_layers_minus1 should be less than NumOfLayers.

[0220] sei_layer_id[i], an unsigned integer of 2 bits. It represents the LayerID (layer identification) of the i-th layer. sei_layer_id[i] should be less than NumOfLayers. For any unsigned integers k and m, when k is less than m, sei_layer_id[k] should be less than sei_layer_id[m].

[0221] For example, the bitstream of the target image contains 4 layers, and the layer_ids are 0 - 3 respectively. If the bitstream obtained by the decoding end contains all the layers of the target image, then the number of layers in this bitstream is 4, and sei_num_of_layers_minus1 is 3. sei_layer_id[0] = 0, sei_layer_id[1] = 1, sei_layer_id[2] = 2, sei_layer_id[3] = 3.

[0222] It can be understood that after encoding a video / or an image, a bitstream is obtained. The bitstream includes one or more consecutive access units (AU). Usually, an AU includes the encoded data of one or more images. An access unit AU includes a set of network abstract layer units (NAL unit), that is, NAL units, which are associated with each other according to specified rules.

[0223] Optionally, if the bitstream obtained (such as received) by the decoding end is the bitstream of a video sequence (including multiple images), the decoding end extracts the bitstream of the target image from the bitstream according to a preset target temporal layer number (which can be called the target highest temporal layer number, targetTId), that is, extracts a partial bitstream from the bitstream of the video sequence to obtain the bitstream of the target image.

[0224] For example, all NAL units with temporal_id greater than targetTId are removed from the bitstream of the video sequence (which can be understood as the input bitstream inBitStream of the encoder) to obtain the bitstream of the target image. It can be understood that for the temporal layer, since the low-layer images do not depend on the high-layer images for encoding and decoding, therefore, for a given target highest temporal layer number targetTId, the data of the temporal layer with temporal_id greater than targetTId is removed, and the data of the temporal layer with temporal_id less than or equal to targetTId is retained. targetTId can be understood as the maximum value of the temporal layer numbers in the bitstream during the process of extracting the sub-bitstream. The above targetTId can be set by the user according to requirements.

[0225] According to the targetTId input by the user, the bitstream of the target image can be obtained from the bitstream of the video sequence. It can be understood that the target image includes the images in the temporal layer with temporal_id less than or equal to targetTId, and each image in the target image includes multiple layers in the spatial layer. Thus, the bitstream of the target image obtained through S701 includes the bitstreams of at least one layer after hierarchical coding of the target image (the target image includes one or more images in the time domain).

[0226] S702. Construct a target layer list (targetLayerList) corresponding to the target layer (targetLayer). The target layer is the layer to be extracted from the target image, and the target layer list includes the target layer. When there are inter-layer reference layers in at least one layer of the target layer, the target layer list also includes at least one inter-layer reference layer.

[0227] The bitstream processing method provided by the embodiments of the present application can be used to extract the bitstream of the layers in the spatial domain of the target image. The above-mentioned target layer can also be referred to as the target spatial layer, and the target layer list can be referred to as the target spatial layer list or the target spatial layer list.

[0228] The process of constructing the target layer list corresponding to the target layer includes S1 - S2:

[0229] S1. Analyze the bitstream of the target image to obtain the hierarchical independent coding identifier of at least one layer of the target image and the reference layer identifier of at least one layer.

[0230] The hierarchical independent coding identifier of a layer is used to indicate independent coding or inter-layer dependent coding of the layer. Specifically, first, analyze the NAL unit with the first NAL unit type (nal_unit_type) of 7 in the bitstream of the target image to obtain the number of layers (NumOfLayers), the spatial layer i independent coding flag (SpsIndependentLayerFlag[i]), and the spatial layer i dependent layer number (ref_layer_id[i] or RefLayerId[i]), where i = 0 to (NumOfLayers - 1). It can be understood that the NAL unit with the first NAL unit type of 7 in the bitstream includes the sequence parameter set (see Table 4 below), and the sequence parameter set contains a flag bit indicating the number of layers. Therefore, the number of layers can be parsed from the first nal_unit_type of 7 in the bitstream.

[0231] It should be understood that the NAL unit type flag (nal_unit_type) is a 5-bit unsigned integer, which represents the type of the RBSP data structure in the NAL unit. Referring to Table 4 below, the NAL unit type flag and the type of the RBSP data structure in the NAL unit are shown.

[0232] Table 4, NAL unit type table

[0233]

[0234]

[0235] S2. Add the layer identifier of the target layer to the target layer list, and if the layer independent coding identifier of the target layer indicates inter-layer dependent coding for the target layer, add the reference layer identifier of the target layer to the target layer list.

[0236] After obtaining the number of layers (NumOfLayers), the spatial domain layer independent coding flag (SpsIndependentLayerFlag[i]) and the spatial domain layer dependent layer number (ref_layer_id[i] or RefLayerId[i]) from bitstream parsing as described above, a target spatial domain layer list (targetLayerList) can be constructed based on this information and the target layer. Among them, targetLayerList[k] represents the LayerId of the k-th layer in the target spatial domain layer list. Initialize the number of layers numTargetLayers in the spatial domain layer list to 0, and the following operations can be performed to obtain the layers to be added to the target spatial domain layer list:

[0237] for(k = targetLayer; k >= 0;){

[0238] targetLayerList[numTargetLayers] = k

[0239] numTargetLayers += 1

[0240] if(SpsIndependentLayerFlag[k] == 0)

[0241] k = RefLayerId[k]

[0242] else

[0243] break

[0244] }

[0245] The above operation process is actually as follows: when the target layer is independently coded (the layer independent coding identifier indicates independent coding), the target layer is added to the target spatial layer list (specifically, the layer identifier of the target layer is added to the target spatial layer list); when the target layer has an inter-layer reference layer, the inter-layer reference layer of the target layer is determined according to ref_layer_id[i], and the inter-layer reference layer is added to the target spatial layer list (specifically, the layer identifier of the inter-layer reference layer of the target layer is added to the target spatial layer list), and if the inter-layer reference frame also has an inter-layer reference, the reference frame of the inter-layer reference frame also needs to be added to the target spatial layer list (specifically, the layer identifier of the reference layer of the inter-layer reference layer is added to the target spatial layer list).

[0246] S703. Process the bitstream of the target image based on the target layer list to output a sub-bitstream; the sub-bitstream includes the bitstreams of the layers in the target layer list and second layer information, and the second layer information includes third indication information for indicating the number of layers included in the sub-bitstream and fourth indication information for indicating the layer identifiers of the layers included in the sub-bitstream.

[0247] In the embodiment of the present application, processing the bitstream of the target image based on the target layer list to output a sub-bitstream includes: taking the bitstream inBitStream (the bitstream of a video sequence), the spatial layer list targetLayerList, the number of layers numTargetLayers in the spatial layer list, and the target highest temporal layer number targetTId as inputs, and calling the following sub-bitstream extraction method to obtain the sub-bitstream outBitStream.

[0248] Obtain the qualified sub-bitstream (that is, perform sub-bitstream extraction) according to the following steps:

[0249] Step 1. The decoding end copies the received bitstream (that is, the input bitstream inBitStream, the bitstream of a video sequence), and extracts the sub-bitstream based on the copied bitstream (outBitStream).

[0250] It can be understood that in the embodiment of the present application, the decoding end copies the received bitstream, records the copied bitstream as outBitStream, and removes the unnecessary bitstreams (or bitstreams that do not meet the specified conditions) from the copied bitstream outBitStream through subsequent steps, so as to obtain the final outBitStream, and the finally obtained outBitStream is the extracted sub-bitstream.

[0251] Step 2. Remove all NAL units in outBitStream whose temporal_id is greater than targetTId.

[0252] The targetTId is the temporal layer number of the target image contained in the bitstream to be extracted and layered. In step 2, the bitstream of the image after the bitstream of the target image in the bitstream is removed, that is, the bitstream of the image with a temporal layer number less than or equal to targetTId is retained.

[0253] The bitstream (outBitStream) input in step 2 is the bitstream obtained through step 1.

[0254] Step 3: Remove all NAL units in outBitStream (the bitstream of the target image) whose LayerId values are not included in targetLayerList and whose nal_unit_type is not 5, 6, 7, 8, 9, 10, 11, or 16. It can also be described as: Remove the NAL units whose nal_unit_type is not 5, 6, 7, 8, 9, 10, 11, or 16 from the bitstream of the layers that do not exist in the target layer list in the bitstream of the target image.

[0255] For step 3, it can be understood as: It is necessary to retain the NAL units in outBitStream whose LayerId is included in targetLayerList, and for the NAL units in outBitStream with LayerId not included in targetLayerList, retain the NAL units whose nal_unit_type is 5, 6, 7, 8, 9, 10, 11, or 16. Understandably, referring to Table 4 above, since the NAL units with nal_unit_type of 5, 6, 7, 8, 9, 10, 11, or 16 contain the common information for decoding the bitstream, they need to be retained (that is, extracted into the sub-bitstream).

[0256] The bitstream input in step 3 is the bitstream obtained through step 2.

[0257] Step 4: Remove all NAL units of nal_unit_type 6 in outBitStream whose LayerId values are not included in targetLayerList and do not include PayloadType of 19, 25, 26, or 127.

[0258] Step 4 can be understood as follows: For the NAL units with nal_unit_type of 6 in the outBitStream obtained in Step 3 where the LayerId is not included in the targetLayerList, retain the NAL units with PayloadType of 19, 25, 26, or 127 in the NAL units with nal_unit_type of 6. The payload with PayloadType of 19 represents the sequence-level privacy protection area (seq_privacy_parameters), and the sequence-level privacy protection area payload contains some sequence-level privacy protection parameters; the payload with PayloadType of 25 represents the supplementary enhancement information carrying layer information; the payload with PayloadType of 26 represents the display indication information carrying whether to indicate the display of the knowledge image; the payload with PayloadType of 127 represents the version information parameter. The information in the NAL units with PayloadType of 19, 25, 26, or 127 is some information related to the video sequence and cannot be removed and needs to be retained in the sub-bitstream.

[0259] Step 5: If there is a NAL unit with nal_unit_type of 6 containing PayloadType of 25 in the outBitStream, update the layer SEI payload in this NAL unit, set sei_num_layers_minus1 to numTargetLayers - 1, and delete the sei_layer_id not in the targetLayerList; otherwise (that is, there is no NAL unit with nal_unit_type of 6 containing PayloadType of 25 in the outBitStream), insert a NAL unit with nal_unit_type of 6 containing PayloadType of 25 before the first coded slice NAl unit of the access unit where each sequence start image and random access point image are located. Among them, sei_num_layers_minus1 is set to numTargetLayers - 1, and sei_layer_id[i] is set to targetLayerList[numTargetLayers - 1 - i] (i = 0 to numTargetLayers - 1). It can be understood that in the targetLayerList, the LayerId is arranged in descending order. By setting sei_layer_id[i] to targetLayerList[numTargetLayers - 1 - i] (i = 0 to numTargetLayers - 1), sei_layer_id is arranged in ascending order.

[0260] As can be seen from step 5 above, after the sub-bitstream extraction is completed, the first layer information in the original bitstream is updated to the second layer information to indicate the number of layers and layer identifiers in the sub-bitstream.

[0261] Optionally, there may be layer units in the access units of the sub-bitstream outBitStream that do not contain coded slice NAL units.

[0262] The bitstream of the layers in the target spatial layer list is extracted from the bitstream through steps 1 to 4 above to obtain the sub-bitstream. Through step 5, the layer information that has changed after the sub-bitstream extraction is written or updated to the sub-bitstream (i.e., the second layer information is the layer information after updating the first layer information) to indicate the layer situation in the subsequent decoding or transmission process of the sub-bitstream.

[0263] According to the above description, step 5 adds layer information, that is, adds layer supplementary enhancement syntax, to the supplementary enhancement information of the sub-bitstream to indicate the second layer information. The third indication information (layer number flag sei_num_of_layers_minus1) and the fourth indication information (layer identifier sei_layer_id[i]) are carried in the supplementary enhancement information. Combining Tables 3 and 4, the first indication information can be updated to the third indication information, and the second indication information can be updated to the fourth indication information.

[0264] Exemplarily, taking the bitstream of an image in the target image as an example, assuming that the bitstream of the target image contains 4 layers with layer_id being 0, 1, 2, and 3 respectively. After the sub-bitstream extraction, layers 1 and 2 of the target image are extracted. Then the number of layers in the sub-bitstream is 2, and sei_num_of_layers_minus1 is 1. sei_layer_id[0] = 1 (i.e., the 0th layer in the sub-stream is the 1st layer of the target image), and sei_layer_id[1] = 2 (i.e., the 1st layer in the sub-stream is the 2nd layer of the target image).

[0265] In one implementation, the above layer information (including the first layer information or the second layer information) is carried in the supplementary enhancement information. Correspondingly, the constraints between the access unit and the NAL unit are as follows:

[0266] 1) If there is a NAL unit with nal_unit_type equal to 15 (indicating the coded picture boundary), it must be the starting NAL unit of the access unit, and there is at most one NAL unit with nal_unit_type equal to 15 in one access unit.

[0267] 2) If there is a NAL unit with nal_unit_type equal to 16 (indicating the end of the coded video sequence) and the NAL unit is not followed by a NAL unit with nal_unit_type equal to 11, then the NAL unit shall be the last NAL unit of the access unit.

[0268] 3) If there is a NAL unit with nal_unit_type equal to 11 (indicating the end of the stream), then the NAL unit shall be the last NAL unit of the access unit.

[0269] 4) If there is a NAL unit with nal_unit_type equal to 19 (indicating the coded slice of a private picture), then the access order of the NAL unit shall be after the access units with nal_unit_type equal to 0, 1, 2, 12, 14, 17.

[0270] 5) If there is a NAL unit with nal_unit_type equal to 6 (indicating supplementary enhancement information) and PayloadType equal to 127, it shall be transmitted in each access unit where the first picture of the sequence and the random access point picture are located, and before the first coded slice NAL unit (FirstCrrCpNalUnit) of the access unit.

[0271] 6) If there is a NAL unit with nal_unit_type equal to 6 (indicating supplementary enhancement information) and PayloadType equal to 25 (indicating that the NAL unit carries layer information), it shall be transmitted in each access unit where the first picture of the sequence and the random access point picture are located, and before the first coded slice NAL unit (FirstCrrCpNalUnit) of the access unit.

[0272] In one implementation, the above layer information (including the first layer information or the second layer information) is carried in the supplementary enhancement information, and the encryption method of the layer information can be indicated by an encryption flag (encryption_idc).

[0273] It should be understood that the encryption flag (encryption_idc) is a binary variable, indicating whether the NAL unit is encrypted. A value of '0' indicates that the RBSP in the NAL unit is not encrypted, and a value of '1' indicates that the RBSP in the NAL unit is encrypted according to the encryption method specified in the security parameter set with the RBSP as the basic data unit. The last byte of the RBSP is not encrypted.

[0274] When the nal_unit_type of a NAL unit is 11 (indicating the end of the stream), 15 (indicating the boundary of the coded picture), or 16 (indicating the end of the coded video sequence), the encryption_idc shall be 0 (indicating that the RBSP in this NAL unit is not encrypted).

[0275] When the nal_unit_type of a NAL unit is 6 and the payload with PayloadType equal to 25 (carrying hierarchical information) is included, the encryption_idc shall be 0. That is to say, the encryption flag of the NAL unit containing the first hierarchical information or the second hierarchical information is the second value (i.e., 0), and the second value is used to indicate that the NAL unit containing the first hierarchical information or the second hierarchical information is not encrypted. Specifically, the second value is used to indicate to the decoding end that the encoding end has not encrypted the NAL unit containing the first hierarchical information or the second hierarchical information. In this way, the decoding end does not need to decrypt the NAL unit containing the first hierarchical information or the second hierarchical information.

[0276] In one implementation, the above hierarchical information (including the first hierarchical information or the second hierarchical information) is carried in the supplementary enhancement information, and the authentication method of this hierarchical information can be indicated by the authentication flag (authentication_idc).

[0277] It should be understood that the authentication flag (authentication_idc) is a binary variable, indicating whether the NAL unit is authenticated. The value '0' indicates that the NAL unit is not authenticated, and the value '1' indicates that the NAL unit is authenticated by the authentication method specified in the security parameter set, and the absolute time extension information must be carried in the coded bitstream to identify the authentication time.

[0278] When the nal_unit_type of a NAL unit is 11, 15, or 16, the authentication_idc shall be 0 (indicating that the RSRP in these NAL units is not authenticated).

[0279] When the nal_unit_type of a NAL unit is 6 and the payload with PayloadType equal to 25 (carrying hierarchical information) is included, the authentication_idc shall be 0. That is to say, the authentication flag of the NAL unit containing the first hierarchical information or the second hierarchical information is the first value (i.e., 0), and the first value is used to indicate that the NAL unit containing the first hierarchical information or the second hierarchical information is not authenticated. Specifically, the first value is used to indicate to the decoding end that the NAL unit containing the first hierarchical information or the second hierarchical information is not authenticated. In this way, the decoding end does not need to authenticate the NAL unit containing the first hierarchical information or the second hierarchical information.

[0280] In one implementation, the above hierarchical information (including the first hierarchical information or the second hierarchical information) is carried in the supplementary enhancement information, and the layer where the hierarchical information is located can be restricted by a layer identifier.

[0281] It should be understood that the layer identifier (layer_id) is a 2-bit unsigned integer, which indicates the layer identifier of the current image. The value range of the layer identifier is 0 to MAX_LAYERS. The layer_id of the sequence parameter set and the picture parameter set NALU (NALU represents the NAL unit) is 0. The layer_id of the picture header NAL unit and all coded slice NAL units of a coded picture should be the same. The value of LayerId is equal to the value of layer_id. Note: MAX_LAYERS is specified by the profile.

[0282] When the nal_unit_type of a NAL unit is 6 and it contains a payload with PayloadType equal to 25, the layer_id should be 0 (that is, the Layer_id corresponding to the NAL unit where the hierarchical information is located is 0).

[0283] In summary, in the bitstream processing method provided by the embodiments of the present application, a target layer list can be created according to the layer to be extracted, and then the bitstream of the layers in the target layer list can be extracted to obtain a sub-bitstream, and the hierarchical information after bitstream extraction can be carried in the sub-bitstream, so that the extraction of the sub-bitstream can be successfully realized and the indication method of the hierarchical information can be clarified.

[0284] It can be understood that in order to implement the above functions, the bitstream processing device includes corresponding hardware and / or software modules for executing each function. Combining the algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0285] The embodiments of the present application can divide the functional modules of the bitstream processing device according to the above method examples. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is illustrative, only a logical function division, and there may be other division methods in actual implementation.

[0286] In the case of dividing each functional module corresponding to each function, Figure 8Shows a possible schematic diagram of the composition of the bitstream processing device involved in the above embodiments, as Figure 8 shown. The bitstream processing device 800 may include: an acquisition module 801, a construction module 802, and a processing module 803.

[0287] The acquisition module 801, the construction module 802, and the processing module 803 cooperate to execute the steps of S701 - S703 in the above method embodiments.

[0288] The embodiments of the present application also provide a chip. Figure 9 Shows a schematic diagram of the structure of a chip 900. The chip 900 includes one or more processors 901 and an interface circuit 902. Optionally, the above chip 900 may further include a bus 903.

[0289] The processor 901 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above bitstream processing method may be completed by the integrated logic circuit in hardware or instructions in software form in the processor 901.

[0290] Optionally, the above - mentioned processor 901 may be a general - purpose processor, a digital signal processing (DSP) processor, an application specific integrated circuit (ASIC), a field - programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute the various methods and steps disclosed in the embodiments of the present application. The general - purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0291] The interface circuit 902 can be used for sending or receiving data, instructions, or information. The processor 901 can utilize the data, instructions, or other information received by the interface circuit 902 for processing, and can send the processed information through the interface circuit 902.

[0292] Optionally, the chip further includes a memory. The memory may include a read - only memory and a random access memory, and provide operation instructions and data to the processor. A part of the memory may also include a non - volatile random access memory (NVRAM).

[0293] Optionally, the memory stores executable software modules or data structures, and the processor can execute corresponding operations by calling the operation instructions stored in the memory (the operation instructions can be stored in the operating system).

[0294] Optionally, the chip can be used in the encoding device involved in the embodiments of the present application. Optionally, the interface circuit 902 can be used to output the execution result of the processor 901. For the bitstream processing method provided by one or more embodiments of the present application, reference can be made to the foregoing respective embodiments, and details are not described herein again.

[0295] It should be noted that the respective functions corresponding to the processor 901 and the interface circuit 902 can be implemented through hardware design, can also be implemented through software design, or can be implemented through a combination of software and hardware, and are not limited herein.

[0296] Figure 10 FIG. is a schematic structural diagram of an electronic device provided by an embodiment of the present application. The electronic device 1000 can be a processor, a chip, or a functional module in a processor. As Figure 10 shown, the electronic device 1000 includes a processor 1001, a transceiver 1002, and a communication line 1003.

[0297] Among them, the processor 1001 is used to execute any step in the bitstream processing method provided by the embodiment of the present application, and in the process of executing any step in the bitstream processing method provided by the embodiment of the present application, the transceiver 1002 and the communication line 1003 can be selectively called to complete corresponding operations.

[0298] Further, the electronic device 1000 may further include a memory 1004. Among them, the processor 1001, the memory 1004, and the transceiver 1002 can be connected through the communication line 1003.

[0299] Among them, the processor 1001 is a processor, a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 1001 can also be other devices with processing functions, such as circuits, devices, or software modules, without limitation.

[0300] A transceiver 1002 is used to communicate with other devices or other communication networks, and the other communication networks can be an Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. The transceiver 1002 can be a module, a circuit, a transceiver, or any device capable of implementing communication.

[0301] The transceiver 1002 is mainly used for transmitting and receiving commands, information, etc., and can include a transmitter and a receiver for respectively transmitting and receiving commands, information, etc.; operations other than the transmission and reception of commands, information, etc. are implemented by the processor.

[0302] A communication line 1003 is used to transmit information between the components included in the electronic device 1000.

[0303] In one design, the processor can be regarded as a logic circuit and the transceiver as an interface circuit.

[0304] A memory 1004 is used to store instructions. Among them, the instructions can be computer programs.

[0305] Among them, the memory 1004 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DRRAM). The memory 1004 can also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, etc. It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0306] It should be pointed out that the memory 1004 can exist independently of the processor 1001 or can be integrated with the processor 1001. The memory 1004 can be used to store instructions, program codes, or some data, etc. The memory 1004 can be located inside the electronic device 1000 or outside the electronic device 1000, without limitation. The processor 1001 is used to execute the instructions stored in the memory 1004 to implement the method provided in the foregoing embodiments of the present application.

[0307] In one example, the processor 1001 can include one or more processors, such as Figure 10 the processor 0 (CPU0) and the processor 1 (CPU1) in

[0308] As an alternative implementation, the electronic device 1000 includes multiple processors. For example, in addition to Figure 10 the processor 1001 therein, the processor 1007 may also be included.

[0309] As an alternative implementation, the electronic device 1000 further includes an output device 1005 and an input device 1006. Exemplarily, the input device 1006 is a device such as a keyboard, a mouse, a microphone, or a joystick, and the output device 1005 is a device such as a display screen or a speaker.

[0310] It should be noted that the electronic device 1000 may be a chip system or a device with a Figure 10 similar structure therein. Among them, the chip system may be composed of chips or may include chips and other discrete devices. Actions, terms, etc. involved between the embodiments of the present application can be referred to each other without limitation. The message names or parameter names in the messages exchanged between the devices in the embodiments of the present application are only examples, and other names may also be adopted in specific implementations without limitation. In addition, Figure 10 the composition structure shown therein does not constitute a limitation on the electronic device 1000. Except Figure 10 for the components shown, the electronic device 1000 may include more or fewer components than Figure 10 shown, or combine certain components, or have different component arrangements.

[0311] The processors and transceivers described in the present application can be implemented on an integrated circuit (IC), an analog IC, a radio frequency integrated circuit, a mixed-signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processors and transceivers can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (PMOS), bipolar junction transistor (BJT), BiCMOS, silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0312] Figure 11The figure is a schematic structural diagram of a bitstream processing device provided by an embodiment of the present application. The bitstream processing device can be applied to the scenarios shown in the above method embodiments. For the sake of convenience of description, Figure 11 only the main components of the bitstream processing device are shown, including a processor 1101, a memory 1102, a control circuit 1103, and an input / output device 1104. The processor 1101 is mainly used for processing communication protocols and communication data, executing software programs, and processing data of software programs. The memory 1102 is mainly used for storing software programs and data. The control circuit 1103 is mainly used for power supply and transmission of various electrical signals. The input / output device 1104 is mainly used for receiving data input by the user and outputting data to the user.

[0313] When the bitstream processing device is the processor 1101, the control circuit 1103 can be a main board, the memory 1102 includes storage media with storage functions such as hard disks, RAM, and ROM, the processor 1101 can include a baseband processor 1101 and a central processor. The baseband processor is mainly used for processing communication protocols and communication data, and the central processor is mainly used for controlling the entire bitstream processing device, executing software programs, and processing data of software programs. The input / output device 1104 includes a display screen, a keyboard, a mouse, etc.; the control circuit 1103 can further include or be connected to a transceiver circuit or a transceiver, for example: a network cable interface, etc., for sending or receiving data or signals, for example, for data transmission and communication with other devices. Further, an antenna can also be included for wireless signal transceiver for data / signal transmission with other devices.

[0314] An embodiment of the present application further provides a bitstream processing device, which includes: at least one processor, when the at least one processor executes program codes or instructions, the above-related method steps are implemented to implement the bitstream processing method in the above embodiment.

[0315] Optionally, the device can further include at least one memory for storing the program codes or instructions.

[0316] An embodiment of the present application further provides a computer storage medium, in which computer instructions are stored. When the computer instructions run on the bitstream processing device, the bitstream processing device is enabled to execute the above-related method steps to implement the bitstream processing method in the above embodiment.

[0317] An embodiment of the present application further provides a computer program product. When the computer program product runs on a computer, the computer is enabled to execute the above-related steps to implement the bitstream processing method in the above embodiment.

[0318] The embodiments of the present application further provide a bitstream processing device, which may specifically be a chip, an integrated circuit, a component or a module. Specifically, the device may include a processor connected to a memory for storing instructions, or the device includes at least one processor for obtaining instructions from an external memory. When the device runs, the processor can execute the instructions to cause the chip to execute the bitstream processing method in each of the above method embodiments.

[0319] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server or data center to another website, computer, server or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that the computer can access or a data storage device such as a server, data center, etc. that includes one or more available media integrated. The available medium may be a magnetic medium (such as a floppy disk, a magnetic disk, a magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium (such as a solid state drive (SSD)), etc.

[0320] Through the description of the above embodiments, those skilled in the art can clearly understand that for the convenience and brevity of description, only the above division of each functional module is used as an example. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working processes of the systems, devices and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0321] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0322] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0323] In addition, in each embodiment of the present application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0324] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes: various media that can store program codes such as flash memory, mobile hard disk, read-only memory, random access memory, magnetic disk, or optical disc.

[0325] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A bitstream processing method, characterized in that, Including: Obtain a bitstream of a target image, where the bitstream includes bitstreams of at least one layer after hierarchical coding of the target image; the bitstream includes first layer information, and the first layer information includes first indication information and second indication information. The first indication information is used to indicate the number of layers included in the bitstream, and the second indication information is used to indicate the layer identifier of the layer included in the bitstream. Construct a target layer list corresponding to the target layer; the target layer is the layer to be extracted in the target image, and the target layer list includes the target layer. When there is an inter-layer reference layer in at least one layer of the target layer, the target layer list further includes at least one inter-layer reference layer. Based on the target layer list, process the bitstream of the target image to output a sub-bitstream; the sub-bitstream includes the bitstreams of the layers in the target layer list and second layer information, and the second layer information includes third indication information and fourth indication information; wherein, the third indication information is used to indicate the number of layers included in the sub-bitstream, and the fourth indication information is used to indicate the layer identifier of the layer included in the sub-bitstream.

2. The method according to claim 1, wherein the first layer information is included in the supplementary enhancement information in the bitstream of the target image; and / or the second layer information is included in the supplementary enhancement information in the sub-bitstream.

3. The method according to claim 1 or 2, wherein the second layer information is the layer information updated from the first layer information.

4. The method according to any one of claims 1 to 3, characterized in that, The constructing a target layer list corresponding to the target layer includes: Parse the bitstream of the target image to obtain the layer independent coding identifier of the at least one layer and the reference layer identifier of the at least one layer; the layer independent coding identifier of a layer is used to indicate independent coding or inter-layer dependent coding of the layer. Add the layer identifier of the target layer to the target layer list. If the layer independent coding identifier of the target layer indicates inter-layer dependent coding of the target layer, add the reference layer identifier of the target layer to the target layer list.

5. The method according to any one of claims 1 to 4, characterized in that, The processing the bitstream of the target image based on the target layer list includes: Remove from the bitstream of the target image the NAL units whose NAL unit types are not 5, 6, 7, 8, 9, 10, 11, or 16 in the bitstreams of the layers that do not exist in the target layer list.

6. The method according to any one of claims 1 to 5, wherein the authentication flag of the network abstraction layer (NAL) unit including the first layer information or the second layer information is a first value, and the first value is used to indicate that the NAL unit including the first layer information or the second layer information is not authenticated.

7. The method according to any one of claims 1 to 6, wherein The encryption flag of the network abstraction layer (NAL) unit containing the first layer information or the second layer information is a second value, and the second value is used to indicate that the NAL unit containing the first layer information or the second layer information is not encrypted.

8. The method according to any one of claims 1 to 7, characterized in that The NAL unit containing the first layer information or the second layer information is carried in the bitstream of the first layer of the target image.

9. The method according to claim 6, characterized in that The first value is specifically used to indicate to the decoding end that the NAL unit containing the first layer information or the second layer information is not authenticated.

10. The method according to claim 7, characterized in that The second value is specifically used to indicate to the decoding end that the encoding end has not encrypted the NAL unit containing the first layer information or the second layer information.

11. A bitstream processing device, comprising at least one processor and a memory, characterized in that, The at least one processor executes the program or instruction stored in the memory, so that the device implements the method according to any one of claims 1 to 10 above.

12. A computer-readable storage medium for storing a computer program, characterized in that, When the computer program runs on a computer or a processor, the computer or the processor implements the method according to any one of claims 1 to 10 above.

13. A computer program product comprising instructions, characterized in that, When the instruction runs on a computer or a processor, the computer or the processor implements the method according to any one of claims 1 to 10 above.

14. A chip, comprising at least one processor and a memory, characterized in that, The at least one processor executes the program or instruction stored in the memory, so that the chip implements the method according to any one of claims 1 to 10 above.

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