Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the technical field of semiconductors, and the semiconductor device comprises a plurality of transistors which are distributed on a substrate in an array manner along a first direction and a second direction, and each transistor comprises a semiconductor column; the plurality of word lines extend along the second direction, the word lines at least partially surround a row of semiconductor columns of the transistors distributed along the second direction, and each word line comprises surrounding parts at least partially surrounding the semiconductor columns and connecting parts connecting two adjacent surrounding parts, and the distance between the adjacent connecting parts of the two adjacent word lines is smaller than the distance between the adjacent surrounding parts. According to the semiconductor device provided by the embodiment of the invention, parasitic capacitance between adjacent word lines can be reduced, and higher integration density can be realized.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, minor differences in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the needs of current products. Summary of the Invention

[0004] Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device. The parasitic capacitance between adjacent word lines of the semiconductor device is small, enabling a higher integration density and better performance.

[0005] Embodiments of the present application provide a semiconductor device, including:

[0006] A plurality of transistors, which are arrayed on a substrate in a first direction and a second direction. The transistors include semiconductor columns;

[0007] A plurality of word lines, extending along the second direction. At least part of the word line surrounds the semiconductor columns of a column of the transistors distributed along the second direction. The word line includes a surrounding part that at least partially surrounds the semiconductor column and a connecting part that connects two adjacent surrounding parts. The distance between adjacent connecting parts of two adjacent word lines is less than the distance between adjacent surrounding parts.

[0008] In some embodiments, the connecting part on the same word line is recessed relative to the surrounding part toward the geometric center line of the word line.

[0009] In some embodiments, the region surrounding the semiconductor column in the outer contour of the word line extending along the second direction is a curve, and the region between two semiconductor columns is a straight line.

[0010] In some embodiments, the surrounding part is annular.

[0011] In some embodiments, the distance between the outer contours of the surrounding parts in the first direction is d1, and the distance between the outer contours of the connecting parts in the first direction is d2;

[0012] 0.5d1 ≤ d2 < d1.

[0013] In some embodiments, an insulating layer is provided between two adjacent word lines, and the insulating layer contains air gaps.

[0014] An embodiment of the present application provides a method for manufacturing a semiconductor device, including:

[0015] Forming a plurality of semiconductor pillars extending in a direction perpendicular to the substrate on the substrate, and the plurality of semiconductor pillars are arrayed in a first direction and a second direction;

[0016] Filling a first insulating layer between two adjacent semiconductor pillars distributed in the second direction, and exposing two opposite sidewalls of the semiconductor pillars in the first direction;

[0017] Thinning the first insulating layer by etching so that the thickness of the first insulating layer in the first direction is less than the thickness of the semiconductor pillar in the first direction;

[0018] Depositing the first insulating layer again on the semiconductor pillar and the first insulating layer;

[0019] Filling a second insulating layer in contact with the first insulating layer between two adjacent columns of semiconductor pillars distributed in the first direction;

[0020] Removing the first insulating layer in the channel region of the semiconductor pillar and the first insulating layer between any two adjacent semiconductor pillars in a column of semiconductor pillars distributed in the second direction, to form a plurality of word line grooves extending in the second direction corresponding to each column of semiconductor pillars;

[0021] Forming a plurality of word lines in each of the word line grooves.

[0022] In some embodiments, the forming a plurality of semiconductor pillars extending in a direction perpendicular to the substrate on the substrate, and the plurality of semiconductor pillars are arrayed in a first direction and a second direction, filling a first insulating layer between two adjacent semiconductor pillars distributed in the second direction, and exposing two opposite sidewalls of the semiconductor pillars in the first direction includes:

[0023] Forming a semiconductor layer on the substrate;

[0024] Forming a plurality of first trenches extending in the first direction and spaced apart in the second direction and a plurality of second trenches extending in the second direction and spaced apart in the first direction on the semiconductor layer, and the first trenches and the second trenches divide the semiconductor layer into the plurality of semiconductor pillars;

[0025] Filling the first insulating layer in the first trenches and the second trenches;

[0026] Etch away the first insulating layer within the second trench, where the second trench exposes the sidewall of the semiconductor pillar in the first direction, and the thickness of the remaining first insulating layer within the first trench in the first direction is equal to the thickness of the semiconductor pillar in the first direction;

[0027] Thin down the remaining first insulating layer within the first trench so that the thickness of the first insulating layer within the first trench in the first direction is less than the thickness of the semiconductor pillar in the first direction.

[0028] In some embodiments, the manufacturing method further includes: after forming the semiconductor pillar, before thinning the first insulating layer by etching,

[0029] Etch the exposed substrate within the second trench to form a bit line groove extending beneath a row of the semiconductor pillars distributed along the first direction;

[0030] Form a bit line within the bit line groove that extends along the first direction and is connected to the semiconductor pillar;

[0031] Form the second insulating layer on the sidewall of the second trench and fill the first insulating layer within the second trench.

[0032] In some embodiments, removing the first insulating layer of the channel region of the semiconductor pillar and the first insulating layer between any adjacent semiconductor pillars in a column of semiconductor pillars distributed along the second direction to form a plurality of word line grooves extending along the second direction corresponding to each column of semiconductor pillars:

[0033] The semiconductor pillar includes a first electrode region close to the substrate, a second electrode region far from the substrate, and a channel region located between the first electrode region and the second electrode region. Remove the first insulating layer of the second electrode region of the semiconductor pillar, and fill the second insulating layer within the space after removing the first insulating layer;

[0034] Remove the first insulating layer of the channel region of the semiconductor pillar and the first insulating layer between any adjacent semiconductor pillars in a column of semiconductor pillars distributed along the second direction to form a plurality of word line grooves extending along the second direction corresponding to each column of semiconductor pillars.

[0035] In some embodiments, the semiconductor pillar is a silicon pillar, the material of the first insulating layer is silicon oxide, the material of the second insulating layer is silicon nitride, and the silicon nitride of the second insulating layer contains air gaps.

[0036] In some embodiments, the word line includes a surrounding portion that at least partially surrounds the semiconductor pillar and a connecting portion that connects two adjacent surrounding portions, and the distance between adjacent connecting portions of two adjacent word lines is less than the distance between adjacent surrounding portions.

[0037] In some embodiments, the distance between the outer contours of the surrounding portions in the first direction is d1, and the distance between the outer contours of the connecting portions in the first direction is d2;

[0038] 0.5d1 ≤ d2 < d1.

[0039] An embodiment of the present application provides an electronic device, including: a semiconductor device fabricated by the above semiconductor device or the above manufacturing method.

[0040] Other features and advantages of the present application will be described in the subsequent specification, and, in part, will become clearer from the specification, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the specification and the drawings. Description of the Drawings

[0041] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application, and do not constitute a limitation to the technical solutions of the present application.

[0042] Figure 1 It is a schematic structural diagram of a word line of a VCT structure semiconductor device in some embodiments;

[0043] Figure 2A It is a top view structural diagram of a semiconductor device according to an exemplary embodiment of the present application;

[0044] Figure 2B For Figure 2A It is a cross-sectional view of the semiconductor device shown in the a-a' direction perpendicular to the substrate;

[0045] Figure 2C For Figure 2A It is a cross-sectional view of the semiconductor device shown in the b-b' direction perpendicular to the substrate;

[0046] Figure 2D For Figure 2A It is a schematic structural diagram of a word line of the semiconductor device shown;

[0047] Figure 3 It is a schematic structural diagram of a word line of another semiconductor device according to an exemplary embodiment of the present application;

[0048] Figure 4 It is a process flow diagram of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present disclosure;

[0049] Figure 5A A cross-sectional view in the a-a' direction perpendicular to the substrate after forming bit lines for a method of manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;

[0050] Figure 5B is Figure 5A A cross-sectional view in the b-b' direction perpendicular to the substrate of the structure shown;

[0051] Figure 6 A cross-sectional view in the b-b' direction perpendicular to the substrate after thinning the first insulating layer for a method of manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;

[0052] Figure 7A A top view after filling a second insulating layer in a second trench for a method of manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;

[0053] Figure 7B is Figure 7A A cross-sectional view in the a-a' direction perpendicular to the substrate of the structure shown;

[0054] Figure 7C is Figure 7A A cross-sectional view in the b-b' direction perpendicular to the substrate of the structure shown;

[0055] Figure 8A A cross-sectional view in the a-a' direction perpendicular to the substrate after removing the first insulating layer in the region corresponding to the second electrode region for a method of manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;

[0056] Figure 8B is Figure 8A A cross-sectional view in the b-b' direction perpendicular to the substrate of the structure shown;

[0057] Figure 9A A cross-sectional view in the a-a' direction perpendicular to the substrate after forming a word line groove for a method of manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure;

[0058] Figure 9B is Figure 9A A cross-sectional view in the b-b' direction perpendicular to the substrate of the structure shown.

[0059] The meanings of the reference symbols in the drawings are as follows:

[0060] 10 - Substrate; 11 - First insulating layer; 12 - Second insulating layer; 13 - Semiconductor layer; 20 - Transistor; 21 - Semiconductor pillar; 211 - First electrode region; 212 - Channel region; 213 - Second electrode region; 30 - Word line; 31 - Recess; 32 - Surrounding portion; 33 - Connection portion; 34 - Word line groove; 40 - Bit line; 51 - First trench; 52 - Second trench. Detailed implementation manners

[0061] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0062] The implementation manners of the present application do not necessarily limit the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the implementation manners of the present application are not limited to the shapes or values shown in the drawings.

[0063] The size and proportional relationships between the various film layers or components in the drawings of the present application can be used as a reference in actual processes, which belong to implementation manners with better technical effects, but are not limited thereto. For example: the aspect ratio of the semiconductor pillar, the thickness and spacing of each film layer can be adjusted according to actual needs.

[0064] The ordinal numbers such as "first" and "second" in the present application are set to avoid confusion of the components and do not represent any order, quantity or importance.

[0065] In the present application, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the components with reference to the drawings, which are only for facilitating the description of this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation on the present application. The positional relationships of the components are appropriately changed according to the directions for describing the components. Therefore, it is not limited to the terms described in the disclosure and can be appropriately replaced according to the situation.

[0066] In the present application, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0067] In the present application, a transistor refers to an element having at least three terminals including a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present application, the channel region refers to the region through which current mainly flows.

[0068] In the present application, it may be that the first electrode is the drain electrode and the second electrode is the source electrode, or it may be that the first electrode is the source electrode and the second electrode is the drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, etc., the functions of the "source electrode" and the "drain electrode" sometimes swap with each other. Therefore, in the present application, unless otherwise specified, the "source electrode" and the "drain electrode" can swap with each other.

[0069] In the present application, "electrically connected" or "connected" includes cases where components are connected together through an element having a certain electrical effect. For example, electrical signal connection (coupled connection, such as coupled to), or physical direct connection. The "element having a certain electrical effect" is not particularly limited as long as it can transfer electrical signals between the components to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0070] In the present application, "parallel" means approximately parallel or almost parallel. For example, the state where the angle formed by two straight lines is -10° or more and 10° or less, and thus, it also includes the state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular. For example, the state where the angle formed by two straight lines is 80° or more and 100° or less, and thus, it also includes the state where the angle is 85° or more and 95° or less.

[0071] In the present application, the distance between A and B refers to the average value or the maximum value of the distances between A and B measured at multiple positions multiple times.

[0072] In the present application, "film" and "layer" can be swapped with each other. For example, sometimes "insulating layer" can be replaced with "insulating film".

[0073] The statement "A and B are an integral structure" in the embodiments of the present application may mean that there is no obvious fault or gap, etc., as an obvious boundary interface at the microscopic structure. Generally, a film layer patterned and formed on another film layer is integral. For example, A and B are formed of the same material to form a film layer and have a connected structure formed simultaneously through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be exactly the same.

[0074] In the present application, the spaced-apart distribution can be understood as a separated and independent distribution, which can be achieved by physical disconnection or electrical disconnection. For example, the semiconductor layer between the effective channels corresponding to two transistors is modified to achieve insulation, so as to realize the electrical spacing between the two channels.

[0075] Figure 1 It is a schematic structural diagram of the word line of the VCT structure semiconductor device in some embodiments. As Figure 1 shown, it is a structure in which the gate surrounds the semiconductor pillar. The word lines are generally parallel straight lines, and the distances between adjacent two word lines (Word Line, WL) are basically the same everywhere. As the storage unit density increases, the distance between adjacent two word lines gets closer and closer. This structure is likely to form a capacitive coupling effect between adjacent two word lines, forming a parasitic capacitance and resulting in a reduction in device performance.

[0076] The embodiment of the present application provides a semiconductor device. Figure 2A It is a top view structural diagram of a semiconductor device according to an exemplary embodiment of the present application; Figure 2B is Figure 2A a cross-sectional view of the semiconductor device shown in the a-a' direction perpendicular to the substrate;

[0077] Figure 2C is Figure 2A a cross-sectional view of the semiconductor device shown in the b-b' direction perpendicular to the substrate; Figure 2D is Figure 2A a schematic structural diagram of the word line of the semiconductor device shown.

[0078] As Figures 2A to 2D shown, the semiconductor device includes: a plurality of transistors 20 and a plurality of word lines 30 located on the substrate 10;

[0079] The plurality of transistors 20 are arranged in an array on the substrate 10 along a first direction and a second direction, the first direction intersects with the second direction, and the transistor 20 includes a semiconductor pillar 21, and the semiconductor pillar 21 can extend along a direction perpendicular to the substrate 10;

[0080] A plurality of word lines 30 extend along the second direction. The word lines 30 at least partially surround the semiconductor pillars 21 of a column of transistors 20 distributed along the second direction. The word lines 30 include a surrounding portion 32 that at least partially surrounds the semiconductor pillar 21 and a connecting portion 33 that connects two adjacent surrounding portions 32. The distance between adjacent connecting portions of adjacent word lines is less than the distance between adjacent surrounding portions. In this way, the average distance between adjacent word lines is reduced as a whole, and the average distance of the word lines is less than the distance between the gates of adjacent transistors in the first direction. The average distance refers to the average value of the distance between the gates and the distance between the connecting portions, and this average value can be the average value or the maximum value of multiple measurement values. Exemplarily, when measuring the distance, it can be the distance between adjacent outer contours.

[0081] In some embodiments, at least a portion of the connecting portions 33 on the same word line are recessed with respect to the surrounding portion 32 toward the geometric center line of the word line 30 to form a recess 31.

[0082] In the semiconductor device according to the embodiment of the present application, the connecting portion of the word line between the transistors is recessed with respect to the surrounding portion surrounding the semiconductor pillar toward the geometric center line of the word line, so that the distance between adjacent word lines at the position of the connecting portion is greater than the distance at the position of the surrounding portion, increasing the average distance between adjacent word lines, thereby reducing the coupling capacitance between adjacent word lines. The smaller coupling capacitance can not only improve the performance of the device, but also allow the trenches between adjacent word lines to be further narrowed, improving the integration density of the device.

[0083] In the present application, the first direction may be parallel to the substrate, the second direction may be parallel to the substrate, and the first direction and the second direction may be perpendicular to each other. For example, the first direction may be the Figure 2A X direction (or called the row direction) as shown, and the second direction may be the Figure 2A Y direction (or called the column direction) as shown.

[0084] In an exemplary embodiment of the present application, the connecting portion 33 on the same word line 30 is recessed with respect to the surrounding portion 32 toward the geometric center line of the word line 30.

[0085] In an exemplary embodiment of the present application, as Figure 2D shown, each connecting portion 33 on the same word line 30 is recessed with respect to the surrounding portion 32 toward the geometric center line of the word line 30, that is, the word line 30 has a recess 31 between each adjacent two semiconductor pillars 21 it surrounds.

[0086] In an exemplary embodiment of the present application, as Figure 2DAs shown, the word line 30 may have a pair of recesses 31 with opposite openings between each adjacent two semiconductor pillars 21 it surrounds.

[0087] In an exemplary embodiment of the present application, the surrounding portion may partially surround or completely surround the transistor. For a single transistor, the surrounding of the single transistor by the surrounding portion may be partial surrounding or complete surrounding.

[0088] In some embodiments, the surrounding of a single semiconductor pillar by the surrounding portion may be complete surrounding, that is, the entire sidewall of the channel region of the transistor is surrounded by the surrounding portion, and the cross-section of the surrounding portion after surrounding is a closed ring in a plane parallel to the substrate. In some embodiments, the surrounding of a single semiconductor pillar by the surrounding portion may be partial surrounding, that is, a part of the sidewall of the channel region of the transistor is surrounded by the surrounding portion, and the cross-section of the surrounding portion after surrounding is not closed, but presents a ring shape. For example, a ring with an opening or a U shape. In the semiconductor device as Figures 2A to 2D shown, all the semiconductor pillars 21 of the transistors 20 are surrounded by the surrounding portion 32, and the surrounding of each semiconductor pillar 21 by the surrounding portion 32 is complete surrounding, that is, the entire sidewall of the channel region of each transistor 20 is surrounded by the surrounding portion 32. As Figure 3 shown, the word line structure shows a case where the surrounding of a single semiconductor pillar 21 by the surrounding portion 32 is partial surrounding.

[0089] In an exemplary embodiment of the present application, the word line completely surrounds the semiconductor pillar, and the widths of different regions of the word line are different in the first direction.

[0090] In an exemplary embodiment of the present application, as Figure 2D shown, the surrounding portion 32 completely surrounds the semiconductor pillar 21; the average width of each surrounding portion 32 on the same word line 30 in the first direction is greater than the average width of each connecting portion 33 in the first direction.

[0091] In an exemplary embodiment of the present application, as Figure 2D shown, the surrounding portion 32 completely surrounds the semiconductor pillar 21; the distance between the outer contours of the surrounding portions on the same word line in the first direction is d1, and the distance between the outer contours of the connecting portions in the first direction is d2, d2 ≤ d1, and d2 only needs to satisfy that the connecting portion can connect the surrounding portion. For example, d2 = (0.1 to 0.9)d1.

[0092] In an exemplary embodiment of the present application, 0.5d1 ≤ d2 < d1. When the width of d2 is greater than or equal to half of the width of d1, the risk of too small resistance or wire breakage is reduced.

[0093] In an exemplary embodiment of the present application, the minimum width of all the surrounding portions located on the same word line in the first direction is greater than the maximum width of the connecting portion in the first direction.

[0094] In an exemplary embodiment of the present application, as Figure 2D shown, the orthographic projection of the connecting portion 33 located on the same word line 30 in a cross-section perpendicular to the substrate and extending in the first direction falls within the range of the orthographic projection of the surrounding portion 32 in a cross-section perpendicular to the substrate and extending in the first direction.

[0095] In an exemplary embodiment of the present application, as Figure 2A and Figure 2B shown, the transistor 20 may include a semiconductor column 21 extending in a direction perpendicular to the substrate 10. Along the direction away from the substrate 10, the semiconductor column 21 may sequentially include a first electrode region 211, a channel region 212, and a second electrode region 213.

[0096] In an exemplary embodiment of the present application, as Figure 2B shown, the first electrode region 211, the channel region 212, and the second electrode region 213 may be of an integral structure.

[0097] In an exemplary embodiment of the present application, as Figure 2A shown, the orthographic projection of the connecting portion 33 in a cross-section perpendicular to the substrate and extending in the first direction falls within the range of the orthographic projection of the semiconductor column 21 of the transistor 20 surrounded by the word line 30 where the connecting portion 33 is located in a cross-section perpendicular to the substrate and extending in the first direction.

[0098] In an exemplary embodiment of the present application, the transistor may further include a gate electrode. The gate electrode may surround the channel region of the semiconductor column, and the gate electrode may be a part of the word line. For example, the surrounding portion of the word line may be used as the gate electrode. There is a gate insulating layer for insulation between the gate electrode and the channel region.

[0099] In an exemplary embodiment of the present application, there may be an insulating layer between two adjacent word lines 30. The material of the insulating layer may include silicon nitride (SiN), a Low-K insulating material different from the first insulating layer, or an insulating layer containing an air gap. The Low-K insulating layer may use a dielectric material with a dielectric constant K < 3.9, including but not limited to oxides of silicon, such as silicon dioxide (SiO2) or other silicon-containing materials, etc., but it is required to have an etching selectivity ratio with the first insulating layer.

[0100] Using an insulating layer containing an air gap can further reduce the coupling capacitance between two adjacent word lines.

[0101] In an exemplary embodiment of the present application, as Figure 2A and Figure 2B shown, the semiconductor device may further include bit lines 40 extending in the first direction, and the bit lines 40 may be connected to one ends (first electrode regions 211) of a plurality of transistors 20 distributed in the first direction and close to the substrate 10.

[0102] In an exemplary embodiment of the present application, as Figure 2A shown, there is a first trench 51 between two adjacent rows of transistors 20 in the second direction, and there is a second trench 52 between two adjacent columns of transistors 20 in the first direction. The first trench 51 and the second trench 52 may be filled with an insulating layer to realize insulation of the plurality of transistors 20 in the first direction and the second direction.

[0103] In an exemplary embodiment of the present application, the depth of the first trench 51 is greater than the depth of the second trench 52. For example, the first trench 51 may extend to the surface or inside of the substrate 10, and the second trench 52 extends to the surface of the bit line 30.

[0104] In the present application, the semiconductor layer can be understood as semiconductor material, and its shape and structure are not emphasized here, only its function is emphasized.

[0105] Exemplarily, the material of the substrate may be silicon or the like.

[0106] Exemplarily, the material of the semiconductor layer may be single-crystalline silicon or polycrystalline silicon and other materials with a band gap less than 1.65 eV, or may also be a wide-band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0107] For example, the material of the metal oxide semiconductor layer or the channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium and other materials. Of course, compounds containing other elements are not excluded in the metal oxide, such as elements N, Si, etc.; and other minor doping elements are not excluded either.

[0108] In some embodiments, the material of the metal oxide semiconductor layer may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. As long as the leakage current of the transistor can meet the requirements, it can be specifically adjusted according to the actual situation.

[0109] These materials have a wide bandgap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the operating performance of the dynamic memory.

[0110] The materials of the above-mentioned metal oxide semiconductor layer or channel only emphasize the element type of the material, not the atomic ratio in the material and the film quality of the material.

[0111] Exemplarily, the material of the bit line may include any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, titanium, etc. The bit line can be a single-layer or multi-layer structure. For example, it can be a multi-layer structure formed by titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0112] In the exemplary embodiments of the present application, the electrode material of the gate electrode can be any one or more of the following different types of materials:

[0113] For example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it can be a metal alloy containing these metals mentioned above;

[0114] It can also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.

[0115] Of course, it can also be polysilicon material; it can also be a conductive material doped with a semiconductor material, for example, silicon after conductive doping, germanium after conductive doping, silicon-germanium after conductive doping, etc.; other materials that exhibit conductivity, etc.

[0116] In an exemplary embodiment of the present application, the material of the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0117] Low-K material, such as silicon oxide.

[0118] High-K material, such as a dielectric material with a dielectric constant K≥3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc. high-K materials.

[0119] Exemplarily, the semiconductor device may be a semiconductor device including a transistor such as a memory, a logic circuit, or a discrete device, for example, a memory such as a dynamic random access memory (DRAM). The storage unit of the memory may be a 1T or 2T storage unit, such as structures such as 1T1C, 2T1C, 1T0C, or 2T0C.

[0120] The embodiment of the present application also provides a manufacturing method of a semiconductor device. The semiconductor device provided by the embodiment of the present application can be obtained through this manufacturing method.

[0121] Figure 4 It is a process flow chart of a manufacturing method of a semiconductor device provided for an exemplary embodiment of the present disclosure. As Figure 4 shown, the manufacturing method of the semiconductor device includes:

[0122] Form a plurality of semiconductor pillars extending in a direction perpendicular to the substrate on the substrate, and the plurality of semiconductor pillars are arrayed in a first direction and a second direction; the semiconductor pillars can be single-crystalline silicon, polysilicon, or metal oxide semiconductor pillars, etc.

[0123] A first insulating layer is filled between two adjacent semiconductor columns distributed along the second direction, and two opposite sidewalls of the semiconductor columns located in the first direction are exposed;

[0124] The first insulating layer is thinned by etching so that the thickness of the first insulating layer in the first direction is less than the thickness of the semiconductor column in the first direction;

[0125] A first insulating layer is deposited again on the semiconductor column and the first insulating layer;

[0126] A second insulating layer in contact with the first insulating layer is filled between two adjacent columns of semiconductor columns distributed along the first direction;

[0127] The first insulating layer in the channel region of the semiconductor column and the first insulating layer between any two adjacent semiconductor columns in a column of semiconductor columns distributed along the second direction are removed to form a plurality of word grooves extending along the second direction corresponding to each column of semiconductor columns;

[0128] A plurality of word lines are formed in each of the word grooves.

[0129] In the manufacturing method of the semiconductor device according to the embodiment of the present application, by etching the first insulating layer filled between two adjacent semiconductor columns to thin it, the surface of the first insulating layer between two adjacent semiconductor columns can form a depression relative to the surface of the semiconductor column, and the first insulating layer formed on the exposed sidewalls of the semiconductor column subsequently forms a protrusion. Therefore, the surface of the obtained first insulating layer in the second direction is uneven. Subsequently, the first insulating layer in the corresponding region of the channel region is replaced with a word line. Therefore, the surface of the formed word line in the second direction is also uneven, and the word line faces the depression between the transistors, so that the distance between two adjacent word lines is larger at the depression, thereby increasing the average distance between two adjacent word lines and reducing the coupling capacitance between the word lines.

[0130] Moreover, the manufacturing process of the semiconductor device according to the embodiment of the present application is simple, can be realized by adjusting the manufacturing process of the existing VCT structure device, and does not require an additional mask.

[0131] In an exemplary embodiment of the present application, forming a plurality of semiconductor columns extending in a direction perpendicular to the substrate on the substrate, the plurality of semiconductor columns being arrayed and distributed in a first direction and a second direction, filling a first insulating layer between two adjacent semiconductor columns distributed along the second direction, and exposing two opposite sidewalls of the semiconductor columns located in the first direction includes:

[0132] Forming a semiconductor layer on the substrate;

[0133] Form a plurality of first trenches extending in the first direction and spaced apart in the second direction and a plurality of second trenches extending in the second direction and spaced apart in the first direction on the semiconductor layer, and the first trenches and the second trenches divide the semiconductor layer into the plurality of semiconductor pillars;

[0134] Fill the first trenches and the second trenches with a first insulating layer;

[0135] Etch and remove the first insulating layer in the second trenches, and the second trenches expose the sidewalls of the semiconductor pillars in the first direction, and the thickness of the remaining first insulating layer in the first trenches in the first direction is equal to the thickness of the semiconductor pillars in the first direction;

[0136] Thin the remaining first insulating layer in the first trenches so that the thickness of the first insulating layer in the first trenches in the first direction is less than the thickness of the semiconductor pillars in the first direction.

[0137] In an exemplary embodiment of the present application, the manufacturing method may further include: after forming the semiconductor pillars and before thinning the first insulating layer by etching,

[0138] Etch the exposed substrate in the second trenches to form bit line grooves extending under a row of the semiconductor pillars distributed in the first direction;

[0139] Form bit lines extending in the first direction and connected to the semiconductor pillars in the bit line grooves;

[0140] Form the second insulating layer on the sidewalls of the second trenches and fill the first insulating layer in the second trenches.

[0141] In an exemplary embodiment of the present application, remove the first insulating layer in the channel regions of the semiconductor pillars and the first insulating layer between any adjacent semiconductor pillars in a column of semiconductor pillars distributed in the second direction to form a plurality of word line grooves extending in the second direction corresponding to each column of semiconductor pillars:

[0142] The semiconductor pillars include a first electrode region close to the substrate, a second electrode region far from the substrate, and a channel region located between the first electrode region and the second electrode region. Remove the first insulating layer in the second electrode regions of the semiconductor pillars and fill the second insulating layer in the vacated space;

[0143] Remove the first insulating layer in the channel region of the semiconductor pillar and the first insulating layer between any adjacent semiconductor pillars in a column of semiconductor pillars distributed along the second direction, to form a plurality of word line grooves extending along the second direction corresponding to each column of semiconductor pillars.

[0144] The technical solution of the embodiment of the present application will be further described below through the manufacturing process of a semiconductor device in an exemplary embodiment. The deposition mentioned in this embodiment can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., and the etching can adopt known methods, which will not be specifically limited here.

[0145] Figure 5A A cross-sectional view in the a-a' direction perpendicular to the substrate after forming the bit line for a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present disclosure; Figure 5B is Figure 5A A cross-sectional view in the b-b' direction perpendicular to the substrate of the structure shown in FIG. 6; A cross-sectional view in the b-b' direction perpendicular to the substrate after thinning the first insulating layer for a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present disclosure; Figure 7A A top view of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present disclosure after filling the second insulating layer in the second trench; Figure 7B is Figure 7A A cross-sectional view in the a-a' direction perpendicular to the substrate of the structure shown in FIG. Figure 7C is Figure 7A A cross-sectional view in the b-b' direction perpendicular to the substrate of the structure shown in FIG. Figure 8A A cross-sectional view in the a-a' direction perpendicular to the substrate of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present disclosure after removing the first insulating layer in the region corresponding to the second electrode region; 8B is Figure 8A A cross-sectional view in the b-b' direction perpendicular to the substrate of the structure shown in FIG. Figure 9A A cross-sectional view in the a-a' direction perpendicular to the substrate of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present disclosure after forming the word line groove; Figure 9B is Figure 9A A cross-sectional view in the b-b' direction perpendicular to the substrate of the structure shown in FIG.

[0146] As Figures 5A to 9B shown, in an exemplary embodiment of the present disclosure, the manufacturing method of the semiconductor device may include:

[0147] S10: Form a plurality of semiconductor pillars 21 extending in a direction perpendicular to the substrate 10 on the substrate 10. The plurality of semiconductor pillars 21 are distributed in an array in a first direction and a second direction, and a first insulating layer 11 is filled between two adjacent semiconductor pillars 21 distributed in the second direction, and two opposite sidewalls of the semiconductor pillar 21 located in the first direction are exposed, as Figure 5A and Figure 5B shown.

[0148] Exemplarily, step S10 may include:

[0149] S11: Form a semiconductor layer 13 on the substrate 10. The semiconductor layer 13 and the substrate 10 may be of an integral structure. For example, a semiconductor layer 13 may be formed by epitaxy on a silicon substrate;

[0150] S12: Etch on the semiconductor layer 13 to form a plurality of first trenches 51 extending in the first direction and spaced apart in the second direction, and make the first trenches 51 extend into the substrate 10. The first trenches 51 divide the semiconductor layer 13 into a plurality of semiconductor walls; fill the first insulating layer 11 in the first trenches 51; etch on the semiconductor walls to form a plurality of second trenches 52 extending in the second direction and spaced apart in the first direction. The plurality of second trenches 52 divide the semiconductor walls into a plurality of semiconductor pillars 21 distributed in an array in the first direction and the second direction. The second trenches 52 expose the sidewalls of the semiconductor pillars 21 located in the first direction and expose the substrate 10; along the direction away from the substrate 10, the semiconductor pillar 21 sequentially includes a first electrode region 211, a channel region 212, and a second electrode region 213;

[0151] S13: Etch the exposed substrate 10 in the second trenches 52 and the substrate under the semiconductor pillars 21 to form bit line grooves extending under a row of semiconductor pillars 21 distributed in the first direction; form bit lines 40 extending in the first direction and connected to the semiconductor pillars 21 in the bit line grooves;

[0152] S14: Deposit a second insulating layer 12 on the sidewalls of the second trenches 52, fill the first insulating layer 11 in the first trenches 51 and the second trenches 52, and perform a back-etch on the first insulating layer 11 and the second insulating layer 12 in the second trenches 52, only retaining the first insulating layer 11 and the second insulating layer 12 at the lower part of the second trenches 52. The first insulating layer 11 and the second insulating layer 12 in the second trenches 52 cover the exposed bit lines 40. At this time, the thickness of the remaining first insulating layer 11 in the first trenches 51 in the first direction is equal to the thickness of the semiconductor pillars 21 in the first direction, as Figure 5A and Figure 5B shown.

[0153] As Figure 5Aand Figure 5B As shown, the width of the semiconductor column 21 obtained in step S10 in the first direction is the same as the width of the first insulating layer 11 in the first trench 51 in the first direction, both being W.

[0154] As Figure 5A and Figure 5B shown, the depth of the first trench 51 is greater than the depth of the second trench 52.

[0155] In this embodiment, the first trench 51 is formed first and then the second trench 52 is formed. In other embodiments, the second trench 52 may also be formed first and then the first trench 51 is formed.

[0156] Exemplarily, the materials of the first insulating layer and the second insulating layer may be any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN), but the materials of the first insulating layer and the second insulating layer are different. For example, the material of the first insulating layer may be silicon oxide, and the material of the second insulating layer may be silicon nitride.

[0157] S20: Thinning the first insulating layer 11 between two adjacent semiconductor columns 21 along the second direction so as to expose at least a part of the side walls of the semiconductor columns 21 in the second direction. At this time, the thickness of the first insulating layer 11 in the first trench 51 in the first direction is less than the thickness of the semiconductor column 21 in the first direction, as Figure 6 shown.

[0158] Exemplarily, step S20 may include:

[0159] Thinning the first insulating layer 11 between two adjacent semiconductor columns 21 along the second direction by using an isotropic etching method, reducing the width of the first insulating layer 11 in the first direction to W0, and W0 is less than the width W of the semiconductor column 21 in the first direction, so as to form at least one depression between two adjacent semiconductor columns 21 distributed along the second direction.

[0160] S30: Forming the first insulating layer 11 on the exposed side walls of the semiconductor columns 21 and filling the second insulating layer 12 between two adjacent rows of semiconductor columns 21 distributed along the first direction, and performing planarization by using a Chemical Mechanical Polishing (CMP) process until the end face of the semiconductor column 21 far from the substrate 10 is exposed, as Figures 7A to 7C shown.

[0161] S40: Remove the first insulating layer 11 in the area corresponding to the second electrode region 213 of the semiconductor pillar 21. For example, the first insulating layer 11 can be removed by an isotropic etching method, and a second insulating layer 12 is filled in the vacated space, as Figure 8A and Figure 8B shown.

[0162] S50: Remove the first insulating layer 11 in the area corresponding to the channel region 212 of the semiconductor pillar 21 and the first insulating layer 11 between any adjacent semiconductor pillars 21 in a column of semiconductor pillars 21 distributed along the second direction. For example, the first insulating layer 11 can be removed by an isotropic etching method to form a word line groove 34 extending along the second direction, as Figure 9A and Figure 9B shown.

[0163] S60: Form a word line 30 in the word line groove.

[0164] The embodiment of the present application further provides an electronic device, which includes the semiconductor device provided by the embodiment of the present application, or a semiconductor device manufactured by the manufacturing method.

[0165] In an exemplary embodiment of the present application, the electronic device can be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device can include the memory in a computer, etc., which is not limited herein.

[0166] Although the disclosed embodiments of the present application are as above, the above content is only an embodiment adopted for the convenience of understanding the present application, and is not used to limit the present application. Any person skilled in the art within the scope of the present application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present application. However, the protection scope of the present application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that, Including: A plurality of transistors are arrayed on a substrate in a first direction and a second direction. The transistors include semiconductor columns. A plurality of word lines extend along the second direction. The word lines at least partially surround the semiconductor columns of a column of the transistors distributed along the second direction. The word lines include a surrounding portion that at least partially surrounds the semiconductor column and a connecting portion that connects two adjacent surrounding portions. The distance between adjacent connecting portions of adjacent two word lines is less than the distance between adjacent surrounding portions.

2. The semiconductor device according to claim 1, wherein The connecting portions located on the same word line are recessed relative to the surrounding portions toward the geometric center line of the word line.

3. The semiconductor device according to claim 1, wherein The region surrounding the semiconductor column in the outer contour of the word line extending along the second direction is a curve, and the region between two semiconductor columns is a straight line.

4. The semiconductor device according to claim 2, characterized in that, The surrounding portion is annular.

5. The semiconductor device according to claim 4, characterized in that, The distance between the outer contours of the surrounding portions in the first direction is d1, and the distance between the outer contours of the connecting portions in the first direction is d2. 0.5d1 ≤ d2 < d1.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, There is an insulating layer between adjacent two word lines, and the insulating layer contains air gaps.

7. A method for manufacturing a semiconductor device, characterized in that, Including: Forming a plurality of semiconductor columns extending in a direction perpendicular to the substrate on the substrate. The plurality of semiconductor columns are arrayed in a first direction and a second direction. Filling a first insulating layer between two adjacent semiconductor columns distributed along the second direction and exposing two opposite sidewalls of the semiconductor columns in the first direction. Thinning the first insulating layer by etching so that the thickness of the first insulating layer in the first direction is less than the thickness of the semiconductor column in the first direction. Redepositing the first insulating layer on the semiconductor column and the first insulating layer. Filling a second insulating layer in contact with the first insulating layer between two adjacent columns of semiconductor columns distributed along the first direction. Removing the first insulating layer in the channel region of the semiconductor column and the first insulating layer between any adjacent semiconductor columns in a column of semiconductor columns distributed along the second direction to form a plurality of word line grooves extending along the second direction corresponding to each column of semiconductor columns. Forming a plurality of word lines in each of the word line grooves.

8. The manufacturing method according to claim 7, characterized in that The forming a plurality of semiconductor columns extending in a direction perpendicular to the substrate on the substrate. The plurality of semiconductor columns are arrayed in a first direction and a second direction. Filling a first insulating layer between two adjacent semiconductor columns distributed along the second direction and exposing two opposite sidewalls of the semiconductor columns in the first direction includes: Forming a semiconductor layer on the substrate. Forming a plurality of first grooves extending along the first direction and spaced apart in the second direction and a plurality of second grooves extending along the second direction and spaced apart in the first direction on the semiconductor layer. The first grooves and the second grooves divide the semiconductor layer into the plurality of semiconductor columns. Filling the first insulating layer in the first grooves and the second grooves. Etch away the first insulating layer in the second trench, the second trench exposing the sidewall of the semiconductor pillar in the first direction, the thickness of the remaining first insulating layer in the first trench in the first direction being equal to the thickness of the semiconductor pillar in the first direction; Thin down the remaining first insulating layer in the first trench so that the thickness of the first insulating layer in the first trench in the first direction is less than the thickness of the semiconductor pillar in the first direction.

9. The manufacturing method according to claim 8, characterized in that, Further included are: After forming the semiconductor pillar and before thinning the first insulating layer by etching, Etch the exposed substrate in the second trench to form a bit line groove extending under a row of the semiconductor pillars distributed along the first direction; Form a bit line extending along the first direction and connected to the semiconductor pillars in the bit line groove; Form the second insulating layer on the sidewall of the second trench and fill the first insulating layer in the second trench.

10. The manufacturing method according to claim 7, characterized in that, Remove the first insulating layer in the channel region of the semiconductor pillar and the first insulating layer between any adjacent semiconductor pillars in a column of semiconductor pillars distributed along the second direction, forming a plurality of word line grooves extending along the second direction corresponding to each column of semiconductor pillars: The semiconductor pillar includes a first electrode region close to the substrate, a second electrode region far from the substrate, and a channel region between the first electrode region and the second electrode region. Remove the first insulating layer in the second electrode region of the semiconductor pillar, and fill the second insulating layer in the space after removing the first insulating layer; Remove the first insulating layer in the channel region of the semiconductor pillar and the first insulating layer between any adjacent semiconductor pillars in a column of semiconductor pillars distributed along the second direction, forming a plurality of word line grooves extending along the second direction corresponding to each column of semiconductor pillars.

11. The manufacturing method according to any one of claims 7 to 10, characterized in that, The semiconductor pillar is a silicon pillar, the material of the first insulating layer is silicon oxide, the material of the second insulating layer is silicon nitride, and the silicon nitride of the second insulating layer contains air gaps.

12. The manufacturing method according to any one of claims 7 to 10, characterized in that, The word line includes a surrounding portion at least partially surrounding the semiconductor pillar and a connecting portion connecting two adjacent surrounding portions, the distance between adjacent connecting portions of two adjacent word lines being less than the distance between adjacent surrounding portions.

13. The manufacturing method according to claim 12, characterized in that, The distance between the outer contours of the surrounding portions in the first direction is d1, and the distance between the outer contours of the connecting portions in the first direction is d2; 0.5d1 ≤ d2 < d1.

14. An electronic device, characterized in that, Including the semiconductor device according to any one of claims 1 to 6, or including the semiconductor device manufactured by the manufacturing method according to any one of claims 7 to 13.

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