Semiconductor device and preparation method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method and a memory system. The semiconductor device comprises a semiconductor column extending in the first direction, the semiconductor column comprises a first part and a second part located on one side of the first part, and the first end of the first part is connected with the second end of the second part in the first direction; in the direction perpendicular to the first direction, the size D1 of the first end and the size D2 of the second end meet the condition that D1 is larger than D2.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and fabrication, and more particularly, to semiconductor devices, methods for fabricating semiconductor devices, and memory systems. Background Art

[0002] Memory is one of the important storage components in an electronic system. Taking a Dynamic Random Access Memory (DRAM) as an example, a semiconductor device may include memory cells composed of capacitors and transistors, where multiple memory cells may be arranged in the form of a two-dimensional array. To further reduce the size of the two-dimensional array, the transistors may include a Vertical Gate Transistor (VGT) array. In this structure, a transistor may include a vertically extending semiconductor pillar, a source electrode and a drain electrode respectively located at two ends of the semiconductor pillar in the extending direction, and a gate structure formed on at least one side of the semiconductor pillar.

[0003] With the rapid development of semiconductor technology, how to optimize the comprehensive performance of semiconductor devices, simplify the fabrication process, and reduce the process cost is one of the important research directions in the industry. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above problems or other problems in this field.

[0005] On the one hand, this application provides a semiconductor device, where the semiconductor device includes a semiconductor pillar extending along a first direction, the semiconductor pillar includes a first portion and a second portion located on one side of the first portion, wherein a first end of the first portion is connected to a second end of the second portion along the first direction; and in a direction perpendicular to the first direction, a size D1 of the first end and a size D2 of the second end satisfy: D1 > D2.

[0006] In an embodiment of this application, the second portion further includes a third end opposite to the second end in the first direction, wherein in a direction perpendicular to the first direction, a size D3 of the third end and a size D2 of the second end satisfy: D3 > D2.

[0007] In an embodiment of this application, the second portion further includes a third end opposite to the second end in the first direction, wherein in a direction perpendicular to the first direction, a size D3 of the third end and a size D1 of the first end satisfy: D3 ≥ D1.

[0008] In an embodiment of this application, the first portion and the second portion include different semiconductor material layers.

[0009] In one embodiment of the present application, the first part and the second part are formed by different manufacturing processes.

[0010] In one embodiment of the present application, the second part includes a plurality of sub-parts arranged in sequence along the first direction. Among them, at least one of the plurality of sub-parts includes a first sub-end and a second sub-end opposite to each other in the first direction. The first sub-end is closer to the first part than the second sub-end. In a direction perpendicular to the first direction, the dimension D5 of the first sub-end and the dimension D6 of the second sub-end satisfy: D5 ≤ D6; and the first sub-end of the sub-part closest to the first part among the plurality of sub-parts is the second end of the second part, and the second sub-end of the sub-part farthest from the first part among the plurality of sub-parts is the third end of the second part.

[0011] In one embodiment of the present application, the cross-sectional shape of at least one of the plurality of sub-parts in a plane parallel to the first direction includes a trapezoidal shape.

[0012] In one embodiment of the present application, at least two of the plurality of sub-parts include different semiconductor material layers.

[0013] In one embodiment of the present application, the dimension D6 of the second sub-end of at least one of the plurality of sub-parts in a direction perpendicular to the first direction and the extension length H1 of at least one of the plurality of sub-parts in the first direction satisfy: 1 / 8 ≤ D6 / H1 ≤ 1 / 7.

[0014] In one embodiment of the present application, the semiconductor device further includes a gate structure. Among them, the semiconductor column includes a plurality of side walls, and the gate structure is located on at least one of the side walls.

[0015] In one embodiment of the present application, the cross-section of the semiconductor column in a plane perpendicular to the first direction includes at least one of a square shape, a rectangular shape, a trapezoidal shape, a circular shape, and an elliptical shape.

[0016] On the other hand, the present application provides a method for manufacturing a semiconductor device, the method comprising: forming an initial first part extending along a first direction, wherein the bottoms of a plurality of the initial first parts arranged along a second direction perpendicular to the first direction are connected to each other; forming an initial second part extending along the first direction and connected to the initial first part; and forming a first opening extending along the second direction, wherein the plurality of first openings divide the initial first part and the initial second part into a plurality of first parts and a plurality of second parts respectively, wherein a first end of the first part is connected to a second end of the second part to form a semiconductor column; and in a direction perpendicular to the first direction, a dimension D1 of the first end and a dimension D2 of the second end satisfy: D1 > D2.

[0017] In an embodiment of the present application, forming the initial second part extending along the first direction and connected to the initial first part includes: forming the initial second part by using at least one of an epitaxial process and a deposition process.

[0018] In an embodiment of the present application, forming the initial second part extending along the first direction and connected to the initial first part includes: forming a first dielectric layer covering at least the initial first part, and forming a second opening in the first dielectric layer extending along the first direction to the initial first part; and filling the second opening to form the initial second part.

[0019] In an embodiment of the present application, the method further includes: forming the first opening from a first side of the initial second part; and before forming the first opening, processing a top surface of the first dielectric layer on the first side and a top surface of the initial second part on the first side by using a planarization process.

[0020] In an embodiment of the present application, the initial second part includes a plurality of sub-parts arranged in sequence along the first direction, and forming the initial second part extending along the first direction and connected to the initial first part includes: forming a first dielectric layer covering at least the initial first part, and forming a first sub-opening in the first dielectric layer extending along the first direction to the initial first part; filling the first sub-opening to form a first sub-part of the initial second part; forming a second dielectric layer covering at least the first sub-part, and forming a second sub-opening in the second dielectric layer extending along the first direction to the first sub-part; and filling the second sub-opening to form a second sub-part of the initial second part, wherein the second sub-part is the next sub-part connected to the first sub-part among the plurality of sub-parts.

[0021] In one embodiment of the present application, forming an initial second part that extends along the first direction and is connected to the initial first part includes: forming the plurality of sub-parts respectively by using different filling processes, where the filling process includes at least one of an epitaxial process and a deposition process.

[0022] In one embodiment of the present application, the initial second part includes a plurality of sub-parts arranged in sequence along the first direction, and the method further includes: forming the initial first part and the initial second part respectively by using different semiconductor materials; and / or forming the plurality of sub-parts respectively by using different semiconductor materials.

[0023] Another aspect of the present application provides a memory system, which includes the semiconductor device provided in one aspect of the present application and a controller coupled to the semiconductor device, and the controller is used to store data in the semiconductor device.

[0024] According to the semiconductor device, preparation method, and memory system provided by at least one embodiment of the present application, the semiconductor device may include a semiconductor column extending along a first direction, where a first end of a first part of the semiconductor column is connected to a second end of a second part of the semiconductor column along the first direction, and in a direction perpendicular to the first direction, the size of the first end is larger than that of the second end. By forming the first part and the second part of the semiconductor column step by step, the situation of bending and tilting of the semiconductor column can be effectively reduced, and the process window of other structures of the semiconductor device formed on the semiconductor column subsequently can be increased. While optimizing the preparation process of the semiconductor device, the comprehensive performance of the semiconductor device is improved. Description of the Drawings

[0025] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes, and advantages of the present application will become more obvious. Among them:

[0026] Figure 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present application;

[0027] Figure 2 is a perspective view of a semiconductor device according to one embodiment of the present application;

[0028] Figure 3 is a cross-sectional view of a semiconductor device according to another embodiment of the present application;

[0029] Figures 4 - 11 are respectively process schematic diagrams of a method for preparing a semiconductor device in an embodiment;

[0030] Figure 12 is a cross-sectional view of a semiconductor device in an embodiment;

[0031] Figure 13 Is a perspective view of a semiconductor device of an embodiment;

[0032] Figure 14 Is a scanning electron microscope image of the semiconductor device 1 of an embodiment;

[0033] Figure 15 Is a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application;

[0034] Figures 16 - 25 Are respectively process schematic diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present application; and

[0035] Figure 26 Is a schematic diagram of a storage system structure according to an embodiment of the present application. Detailed Embodiments

[0036] To better understand the present application, more detailed descriptions of various aspects of the present application will be made with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of the exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to separate one feature from another feature region and do not represent any limitation on the feature, especially not any order. Therefore, without departing from the teachings of the present application, the first end discussed in the present application may also be referred to as the second end, and vice versa.

[0038] In the accompanying drawings, for the sake of convenience of illustration, the thickness, size, and shape of the components have been slightly adjusted. The drawings are only examples and are not drawn strictly to scale. As used herein, the terms "substantially", "about" and similar terms are used as approximate terms and not as terms of degree, and are intended to illustrate the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0039] It should also be understood that expressions such as "comprising", "including", "having", "containing" and / or "including" are open-ended rather than closed-ended expressions in this specification, which means that the stated features, elements and / or components exist, but do not exclude the existence of one or more other features, elements, components and / or their combinations. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than just an individual element in the list. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0040] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as the ordinary understanding of those of ordinary skill in the art to which this application belongs. It should also be understood that unless clearly stated in this application, words defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0041] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. In addition, unless clearly defined or in contradiction with the context, the specific steps included in the methods described in this application do not have to be limited to the recorded order, but can be executed in any order or executed in parallel.

[0042] In addition, in this application, when using "connected" or "coupled", it may mean direct contact or indirect contact between the corresponding components, unless there are clear other definitions or can be deduced from the context.

[0043] The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0044] Some embodiments of the present application provide a semiconductor device. Figure 1 is a cross-sectional view of a semiconductor device 1000 according to an embodiment of the present application. Figure 2 is a perspective view of a semiconductor device 1000 according to an embodiment of the present application. Figure 3 is a cross-sectional view of a semiconductor device 1000 according to another embodiment of the present application.

[0045] As Figures 1 - 3As shown, the semiconductor device 1000 includes a semiconductor pillar 100 extending along a first direction (z direction). The semiconductor pillar 100 includes a first portion 100-1 and a second portion 100-2 located on one side of the first portion 100-1. The first end 101 of the first portion 100-1 is connected to the second end 102 of the second portion 100-2 along the z direction. In a direction perpendicular to the z direction (e.g., x direction or y direction), the size D1 of the first end 101 and the size D2 of the second end 102 satisfy: D1 > D2.

[0046] According to at least one embodiment of the present application, the semiconductor device may include a semiconductor pillar extending along a first direction, wherein the first end of the first portion of the semiconductor pillar is connected to the second end of the second portion of the semiconductor pillar along the first direction. In a direction perpendicular to the first direction, the size of the first end is greater than the size of the second end. By forming the first portion and the second portion of the semiconductor pillar step by step, the situation of the semiconductor pillar bending and tilting can be effectively reduced, and the process window of other structures of the semiconductor device formed on the semiconductor pillar subsequently can be increased. While optimizing the manufacturing process of the semiconductor device, the comprehensive performance of the semiconductor device is improved.

[0047] Specifically, the second portion 102 further includes a third end 103 opposite to the second end 102 in the z direction. In a direction perpendicular to the z direction (e.g., x direction or y direction), the size D3 of the third end 103 and the size D2 of the second end 102 satisfy: D3 > D2.

[0048] In addition, as an option, in a direction perpendicular to the z direction (e.g., x direction or y direction), the size D3 of the third end 103 and the size D1 of the first end 101 may satisfy: D3 ≥ D1. As another option, in a direction perpendicular to the z direction (e.g., x direction or y direction), the size D3 of the third end 103 and the size D1 of the first end 101 may also satisfy: D3 < D1.

[0049] In some embodiments described in detail below, by performing "deep trench" etching on the substrate, a plurality of semiconductor pillars arranged in an array can be obtained. However, due to the limitations of the etching process, the deep trench extends along the z direction, and the width dimension of the bottom of the trench often becomes smaller as the deep trench becomes deeper. The deeper the trench, the smaller the width dimension of the bottom of the trench usually is. Therefore, in order to ensure that the width dimension of the bottom of the deep trench meets the preset value, the width dimension of the top of the deep trench is often relatively large. Correspondingly, the size of the portion reserved at the top of the substrate becomes relatively smaller, and the size of the top end of the semiconductor pillar formed by this method subsequently is also smaller. The process window of other structures of the semiconductor device formed on the semiconductor pillar is also relatively smaller, which is not conducive to improving the comprehensive performance and integration degree of the semiconductor device.

[0050] In some embodiments of the present application, different "parts" of the semiconductor column distributed along the z-direction can be formed step by step. For example, the first part of the semiconductor column, the second part located on one side of the first part, etc. can be formed step by step. In addition, the "parts" of the semiconductor column can also be formed step by step through different manufacturing processes. For example, one "section" of the semiconductor column can be formed by etching the substrate; and another "section" of the semiconductor column can be formed by filling a semiconductor material in a groove connected to one "section". Among the "parts" of the semiconductor column formed step by step, since the depth of the groove is shallower compared with the "deep groove" above, when ensuring that the groove width dimension at the bottom of the groove meets the preset value, the dimension at the top of the groove becomes relatively smaller, and the dimension of the part reserved at the top of the substrate becomes relatively larger. In addition, by selecting different manufacturing processes to form the "parts" of the semiconductor column, the end dimension of the semiconductor column can be effectively controlled. For example, a relatively large-size top dimension of the semiconductor column can be obtained, so as to facilitate the formation of other structures of the semiconductor device on the relatively large-size top subsequently, effectively improving the comprehensive performance and integration degree of the semiconductor device.

[0051] Optionally, the first part 100-1 and the second part 100-2 of the semiconductor column 100 can include different semiconductor material layers. For example, the first part 100-1 of the semiconductor column 100 can be prepared using single-crystalline silicon (Si) material, and the second part 100-2 of the semiconductor column 100 can be prepared using a material different from the single-crystalline silicon material, such as single-crystalline germanium (Ge), germanium-silicon (GeSi), silicon carbide (SiC), or gallium arsenide, etc. The present application does not limit the materials of the first part 100-1 and the second part 100-2 of the semiconductor column 100. In addition, the first part 100-1 and the second part 100-2 of the semiconductor column 100 can also include the same semiconductor material layer. Additionally, at least one of the first part 100-1 and the second part 100-2 of the semiconductor column 100 can also be a composite structure, for example, including a composite layer composed of different semiconductor materials. The present application does not limit this.

[0052] As an option, the first part 100-1 and the second part 100-2 of the semiconductor column 100 can be formed by different manufacturing processes. For example, the process for forming the first part 100-1 of the semiconductor column 100 can include a dry etching process. Multiple initial first parts are formed by dry etching an intermediate body, and then the first part is formed by continuing to dry etch the initial first parts. The process for forming the second part 100-2 of the semiconductor column 100 can include a dry etching process for forming a groove connected to the initial first part in the intermediate body and a process for filling the groove with a semiconductor material layer. Specifically, the process for filling the groove with a semiconductor material layer can include at least one of a deposition process and an epitaxial growth process. The manufacturing processes of the first part 100-1 and the second part 100-2 of the semiconductor column 100 will be described in detail below.

[0053] Reference Figure 1and Figure 3 The second part 100-2 may include a plurality of sub-parts arranged in sequence along the z direction, such as a first sub-part 11, a second sub-part 12, and so on. At least one of the plurality of sub-parts includes a first sub-end and a second sub-end that are opposite to each other in the z direction. The first sub-end is closer to the first part 101 than the second sub-end. In a direction perpendicular to the z direction (for example, the x direction or the y direction), the dimension D5 of the first sub-end and the dimension D6 of the second sub-end satisfy: D5 ≤ D6. Taking the second sub-part 12 as an example, the second sub-part 12 includes a first sub-end 105 and a second sub-end 106 that are opposite to each other in the z direction. The first sub-end 105 is closer to the first part 101 than the second sub-end 106. In a direction perpendicular to the z direction (for example, the x direction or the y direction), the dimension D5 of the first sub-end 105 and the dimension D6 of the second sub-end 106 satisfy: D5 ≤ D6.

[0054] In addition, the first sub-end of the sub-part closest to the first part 100-1 among the plurality of sub-parts of the second part 100-2 is the second end 102 of the second part 100-2; the second sub-end of the sub-part farthest from the first part 100-1 among the plurality of sub-parts of the second part 100-2 is the third end 103 of the second part 100-2. For example, when the second part 100-2 includes two sub-parts, namely the first sub-part 11 and the second sub-part 12, the first sub-part 11 is the sub-part closest to the first part 100-1 among the plurality of sub-parts of the second part 100-2, and the first sub-end of the first sub-part 11 is the second end 102 of the second part 100-2; the second sub-part 12 is the sub-part farthest from the first part 100-1 among the plurality of sub-parts of the second part 100-2, and the second sub-end 106 of the second sub-part 12 is the third end 103 of the second part 100-2.

[0055] Optionally, the cross-sectional shape of at least one of the plurality of sub-parts in a plane parallel to the z direction includes a trapezoidal shape. For example, in the z-x or z-y plane, the cross-sectional shapes of the first sub-part 11 and the second sub-part 12 are both trapezoidal shapes. In addition, the cross-sectional shape of at least one of the plurality of sub-parts in a plane parallel to the z direction may also include a rectangular shape, etc.

[0056] Optionally, at least two of the multiple sub - parts include different semiconductor material layers. For example, at least one sub - part in the second part 100 - 2 of the semiconductor column 100 can be prepared using single - crystal silicon (Si) material, and the remaining sub - parts in the second part 100 - 2 of the semiconductor column 100 can be prepared using materials different from single - crystal silicon material, such as single - crystal germanium, silicon germanium, silicon carbide, or gallium arsenide, etc. This application does not limit the materials of the multiple sub - parts of the second part 100 - 2 of the semiconductor column 100. In addition, the multiple sub - parts of the second part 100 - 2 of the semiconductor column 100 can also include the same semiconductor material layer. Additionally, at least one of the multiple sub - parts of the second part 100 - 2 of the semiconductor column 100 can also be a composite structure, for example, including a composite layer composed of different semiconductor materials, and this application does not limit this.

[0057] In some embodiments of this application, for at least one of the multiple sub - parts, the dimension D6 of the second sub - end in a direction perpendicular to the z - direction (for example, the x - direction or the y - direction) and the extension length H1 of at least one of the multiple sub - parts in the z - direction satisfy: 1 / 8 ≤ D6 / H1 ≤ 1 / 7. Taking the second sub - part 12 as an example, the dimension D6 of the second sub - end 106 of the second sub - part 12 in a direction perpendicular to the z - direction (for example, the x - direction or the y - direction) and the extension length H1 of the second sub - part 12 in the z - direction satisfy: 1 / 8 ≤ D6 / H1 ≤ 1 / 7. The groove where the second sub - part 12 is located can be formed by a dry etching process. By defining the ratio of the end dimension of the second sub - part to the extension dimension of the second sub - part, the ratio of the depth to the width of the above - mentioned groove can be kept within a certain range, so as to optimize the semiconductor device manufacturing process while setting the number of sub - parts of the second part and the end dimension of the semiconductor column according to the specific parameters of the semiconductor device, and improve the comprehensive performance of the semiconductor device.

[0058] Optionally, the multiple sub - parts in the second part 100 - 2 of the semiconductor column 100 can also be formed by different manufacturing processes. For example, the first sub - part 11 of the second part 100 - 2 can be formed by a deposition process; the second sub - part 12 of the second part 100 - 2 can be formed by an epitaxial growth process. However, this application does not limit the manufacturing processes of the multiple sub - parts in the second part 100 - 2.

[0059] In some embodiments of this application, the first part 100 - 1 of the semiconductor column 100 further includes a fourth end 104 opposite to the first end 101. The fourth end 104 of the first part 100 - 1 can also be understood as the bottom end of the semiconductor column 100, and the third end 103 of the second part 100 - 2 can also be understood as the top end of the semiconductor column 100, where the top end and the bottom end of the semiconductor column 100 are opposite in the z - direction. In addition, the semiconductor column 100 further includes at least one side wall 34 located between the top end and the bottom end.

[0060] Optionally, the semiconductor pillar 100 may have a cubic shape to expose its four sidewalls 34. However, those skilled in the art should understand that the semiconductor pillar 100 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. In other words, the cross-section of the semiconductor pillar 100 in a plane intersecting the z-direction (e.g., the x-y plane) may have a square shape, a rectangular shape, a trapezoidal shape, a circular shape, an elliptical shape, or any other suitable shape, where the x-direction, the y-direction, and the z-direction intersect each other. It should be understood that, consistent with the scope of the present application, for a semiconductor pillar 100 having a circular or elliptical cross-section in the above-mentioned plane, the semiconductor pillar 100 can still be considered to have a plurality of sidewalls 34.

[0061] Optionally, the surface of the sidewall 34 of the semiconductor pillar 100 is a curved surface.

[0062] Taking DRAM as an example, the semiconductor device 1000 may include memory cells composed of capacitors and transistors, and multiple memory cells may be arranged in the form of a two-dimensional array. To further reduce the size of the two-dimensional array, the transistor may include a vertical gate transistor array (Vertical Gate Transistor, VGT).

[0063] Optionally, in this structure, the semiconductor device 1000 may include a vertically extending semiconductor pillar, a source electrode (not shown) and a drain electrode (not shown) respectively located at both ends of the extending direction of the semiconductor pillar 100, and a gate structure (not shown) formed on at least one sidewall of the semiconductor pillar.

[0064] In one embodiment of the present application, a vertical transistor such as a vertical metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) may replace a conventional planar transistor as a transfer transistor of a memory cell to reduce the area occupied by the transfer transistor, the coupling capacitance, and the complexity of the interconnect wiring. In some embodiments, different from a planar transistor formed in a substrate, the vertical transistor may include a semiconductor pillar 100 vertically extending along the z-direction above a substrate (not shown). The semiconductor pillar 100 may extend above the top surface of the substrate, exposing not only the top end of the semiconductor pillar 100 but also one or more sidewalls 34 of the semiconductor pillar 100.

[0065] Optionally, the semiconductor device further includes a back gate structure (not shown), where the gate structure and the back gate structure can be respectively located on different sidewalls of the semiconductor pillar 100. The gate structure can be located on one of the two opposite sidewalls of the semiconductor pillar 100 in the x direction. In addition, on this basis, the gate structure can also be located on the remaining sidewalls of the semiconductor pillar 100 other than the two opposite sidewalls in the x direction, and this application does not limit this. Optionally, the back gate structure can be located on the other of the two opposite sidewalls of the semiconductor pillar 100 in the x direction.

[0066] By applying a reference voltage (e.g., ground voltage) to the back gate structure of the semiconductor device 1000, interference between adjacent gate structures in the semiconductor device 1000 can be reduced. The back gate structure 300 can include a back gate dielectric layer (not shown) located on one sidewall of the semiconductor pillar 100, and a back gate conductive layer (not shown) above and in contact with the back gate dielectric layer.

[0067] In one embodiment of the present application, the gate structure can include a gate dielectric (not shown) on one or more sidewalls of the semiconductor pillar 100. In addition, the gate structure can also include a gate conductive layer (not shown) above and in contact with the gate dielectric.

[0068] In some embodiments, the semiconductor device 1000 can further include a source and a drain respectively formed at two ends (top end and bottom end) of the semiconductor pillar 100 in the z direction, which can be understood as doped regions of the semiconductor pillar 100 and can also be referred to as source electrodes and drain electrodes. As an option, the source and the drain can be doped with any suitable P-type dopant, and the P-type dopant can include any one or combination of boron (B) or gallium (Ga). As another option, the source and the drain can be doped with any suitable N-type dopant, and the N-type dopant can include any one or combination of phosphorus (P), arsenic (As), and antimony (Sb). The source and the drain can be separated by the gate structure in the z direction.

[0069] According to the semiconductor device provided by at least one embodiment of the present application, the first end of the first part of the semiconductor pillar is connected to the second end of the second part of the semiconductor pillar along the first direction, and in the direction perpendicular to the first direction, the size of the first end is larger than the size of the second end. By forming the first part and the second part of the semiconductor pillar step by step, the situations of bending and tilting of the semiconductor pillar can be effectively reduced, and the process window of other structures of the semiconductor device formed subsequently on the semiconductor pillar can be increased. While optimizing the manufacturing process of the semiconductor device, the comprehensive performance of the semiconductor device is improved.

[0070] Figure 4 It is a cross-sectional schematic diagram of the structure formed after forming the first trench 110 in an embodiment of the manufacturing method. Figure 5It is a three-dimensional schematic diagram of the structure formed after forming the first trench 110 in an embodiment of the manufacturing method. Figure 6 It is a cross-sectional schematic diagram of the structure formed after forming the initial filling dielectric layer 210 in an embodiment of the manufacturing method. Figure 7 It is a three-dimensional schematic diagram of the structure formed after forming the initial filling dielectric layer 210 in an embodiment of the manufacturing method. Figure 8 It is a cross-sectional schematic diagram of the structure formed after forming the filling dielectric layer 210' in an embodiment of the manufacturing method. Figure 9 It is a three-dimensional schematic diagram of the structure formed after forming the initial filling dielectric layer 210' in an embodiment of the manufacturing method. Figure 10 It is a cross-sectional schematic diagram of the structure formed after removing a part of the hard mask layer in an embodiment of the manufacturing method. Figure 11 It is a three-dimensional schematic diagram of the structure formed after removing a part of the hard mask layer in an embodiment of the manufacturing method. Figure 12 It is a cross-sectional view of the semiconductor device 1 in an embodiment. Figure 13 It is a three-dimensional view of the semiconductor device 1 in an embodiment.

[0071] As Figures 4 - 13 shown, in one embodiment, the method for obtaining a semiconductor device may include: providing a substrate 100'; forming a patterned hard mask layer 300 on the top surface of the substrate 100'; based on the patterned hard mask layer 300, forming first trenches 110 extending in the substrate 100' along the z direction, and a plurality of first trenches 110 are arranged at intervals along a second direction (y direction) intersecting the z direction; filling the first trenches 110 with an initial filling dielectric layer 210; removing a part of the initial filling dielectric layer 210 to form a filling dielectric layer 210'; removing the hard mask layer 300 and performing a planarization process; forming second trenches 01' extending along the y direction to divide the first semiconductor layer structure 111' into a plurality of semiconductor columns 111, and the plurality of semiconductor columns 111 are formed into the semiconductor device 1.

[0072] Specifically, as Figures 4 - 5 shown, the substrate 100' can be formed of any suitable semiconductor material. The material for preparing the substrate 100' can be selected from any suitable semiconductor material, for example, it can be single crystal silicon, single crystal germanium, silicon germanium, silicon carbide, silicon on insulator, germanium on insulator, or group III-V compounds such as gallium arsenide.

[0073] The hard mask layer 300 can be formed on the top surface of the substrate 100' by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0074] Optionally, the hard mask layer 300 may be a composite structure. For example, the hard mask layer 300 includes a first mask layer 301 and a second mask layer 302. For example, both the first mask layer 301 and the second mask layer 302 may include a silicon oxide layer, a silicon nitride layer, a polysilicon layer, etc. The present application does not limit the materials of the first mask layer 301 and the second mask layer 302. Through, for example, photolithography, a patterned hard mask layer 300 can be formed, where the pattern of the hard mask layer 300 includes the pattern of the first trench 110 formed subsequently in the substrate 100'.

[0075] It is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc. By removing part of the substrate 100', a first trench 110 extending in the substrate 100' along the z direction can be formed. A plurality of first trenches 110 are arranged at intervals in the y direction, thereby dividing the substrate 100' into a plurality of first semiconductor layer structures 111', and the plurality of first semiconductor layer structures 111' are also arranged at intervals in the y direction. In other words, the plurality of first trenches 110 and the plurality of first semiconductor layer structures 111' are arranged alternately in the y direction. In addition, since the first trench 110 does not penetrate the substrate 100' along the z direction, the bottoms of the plurality of first semiconductor layer structures 111' are connected to each other.

[0076] As Figures 4 - 7 shown, through one or more thin film deposition processes, an initial filling dielectric layer 210 can be filled in the first trench 110. The thin film deposition process may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin film deposition processes or any combination thereof. As an option, the initial filling dielectric layer 210 may include any suitable dielectric material, for example, silicon oxide, silicon nitride, and silicon oxynitride, etc.

[0077] As Figures 6 - 9 shown, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc. By removing part of the initial filling dielectric layer 210, a filling dielectric layer 210' is formed. The filling dielectric layer 210' may have a top surface flush with the hard mask layer 300. It should be noted that limited by the process, the error range between the top surface of the filling dielectric layer 210' and the top surface of the hard mask layer 300 relative to the same reference plane may be between -10% and 10%.

[0078] As Figures 8 - 13As shown, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove the hard mask layer 300 and expose the top surface of the first semiconductor layer structure 111'. As an option, the first mask layer 301 and the second mask layer 302 of the hard mask layer 300 can be removed in different processes and at different steps.

[0079] After removing the hard mask layer 300, or during the process of removing the hard mask layer 300, a planarization process can be performed on the top surface of the filling dielectric layer 210' and the top surface of the first semiconductor layer structure 111', where the planarization process can include any suitable technique for planarization, such as grinding and / or chemical mechanical polishing, etc. After the planarization treatment, the filling dielectric layer 210' and the first semiconductor layer structure 111' have a flush top surface to facilitate the subsequent formation of the second trench 01' extending in the z direction through this flat and flush top surface. It should be noted that limited by the process, the error range of the top surface of the filling dielectric layer 210' and the top surface of the first semiconductor layer structure 111' relative to the same reference plane can be between -10% and 10%.

[0080] In addition, as an option, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to form the second trench 01'. The second trench 01' extends in the y direction and divides the first semiconductor layer structure 111' into multiple semiconductor columns 111.

[0081] The multiple semiconductor columns 111 are arranged in the x direction and in the y direction to form a semiconductor device 1. Since the second trench 01' does not penetrate the first semiconductor layer structure 111' in the z direction, the bottoms of the multiple semiconductor columns 111 are connected to each other.

[0082] As Figure 12 As shown, in the semiconductor device 1, the semiconductor columns 111 extend in the z direction and include a first end 111-1 and a second end 111-2 that are opposite to each other in the z direction. The multiple semiconductor columns 111 are arranged in the x direction, and a spacer dielectric layer 220 is filled between adjacent semiconductor columns 111. However, in the direction intersecting with the z direction, the size d1 of the first end 111-1 is smaller than the size d2 of the second end 111-2, which is not conducive to the subsequent formation of other structures of the semiconductor device at the first end 111-1 of the semiconductor column 111.

[0083] Figure 14 is a scanning electron microscope image of the semiconductor device 1 of an embodiment.

[0084] Combined with Figure 12And Figure 14 In an ideal state, the cross-section of the semiconductor pillar 111 formed through the above embodiments in the y-z plane can be as shown in Figure 12 As shown, the semiconductor pillar 111 extends in the z direction and presents an approximately straight columnar structure. However, generally, the cross-section of the semiconductor pillar 111 formed through the above embodiments in the y-z plane is as shown in Figure 14 As shown, the semiconductor pillar 111 has a curved and inclined situation, which has an adverse impact on subsequent processes such as filling and ion implantation, and reduces the process window for forming other structures of semiconductor devices at the top of the conductor pillar subsequently, affecting the overall performance of the finally formed semiconductor devices.

[0085] To at least solve the above problems, the present application provides a semiconductor device 1000 and a manufacturing method 2000 of a semiconductor device.

[0086] Figure 15 is a flowchart of a method 2000 for manufacturing a semiconductor device according to an exemplary embodiment of the present application. Figures 16 - 25 are process schematic diagrams of a manufacturing method 2000 of a semiconductor device according to an embodiment of the present application, respectively.

[0087] As shown in Figure 15 As shown, some embodiments of the present application provide a manufacturing method of a semiconductor device. The manufacturing method 2000 of the semiconductor device includes:

[0088] S1, forming an initial first part extending in a first direction, wherein the bottoms of a plurality of initial first parts arranged in a second direction perpendicular to the first direction are connected to each other.

[0089] S2, forming an initial second part extending in the first direction and connected to the initial first part.

[0090] S3, forming a first opening extending in the second direction, wherein the plurality of first openings divide the initial first part and the initial second part into a plurality of first parts and a plurality of second parts respectively, and the first end of the first part is connected to the second end of the second part to form a semiconductor pillar. In a direction perpendicular to the first direction, the size D1 of the first end and the size D2 of the second end satisfy: D1 > D2.

[0091] Next, the specific processes of each step of the above manufacturing method 2000 in Embodiment 1 will be described in detail with reference to Figures 15 - 25 is a cross-sectional schematic diagram of the structure formed after forming the initial first part 100-1' according to an embodiment of the manufacturing method of the present application.

[0092] Step S1

[0093] Figure 16 is a cross-sectional schematic diagram of the structure formed after forming the initial first part 100-1' according to an embodiment of the manufacturing method of the present application. Figure 17It is a three-dimensional schematic diagram of the structure formed after forming the initial first part 100-1' according to the preparation method of an embodiment of the present application.

[0094] As Figures 15 - 17 shown, as an option, step S1 forms an initial first part extending in the first direction, and the bottom ends of a plurality of initial first parts arranged in a second direction perpendicular to the first direction being connected to each other may, for example, include: providing a substrate 100'; forming initial openings 120-1 extending in the substrate 100' in the z direction, the plurality of initial openings 120-1 being spaced apart in a second direction (y direction) intersecting the z direction, and dividing the substrate 100' into a plurality of initial first parts 100-1' spaced apart in the y direction. In addition, since the initial openings 120-1 do not penetrate the substrate 100' in the z direction, the bottom ends 104' of the plurality of initial first parts 100-1' are connected to each other.

[0095] Specifically, the substrate 100' can be formed of any suitable semiconductor material. The material for preparing the substrate 100' can be selected from any suitable semiconductor material, such as single crystal silicon, single crystal germanium, silicon germanium, silicon carbide, silicon on insulator, germanium on insulator, or group III-V compounds such as gallium arsenide.

[0096] Through one or more thin film deposition processes, a hard mask layer (not shown) can be formed on the top surface of the substrate 100'. The thin film deposition process can include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin film deposition processes or any combination thereof. Optionally, the hard mask layer can be a composite structure. For example, the hard mask layer includes a silicon oxide layer, a silicon nitride layer, a polysilicon layer, etc. Through, for example, photolithography, a patterned hard mask layer can be formed, and the pattern of the hard mask layer includes the pattern of the initial openings 120-1 subsequently formed in the substrate 100'. It is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to remove part of the substrate 100', and the initial openings 120-1 extending in the substrate 100' in the z direction can be formed.

[0097] Referring again to Figures 15 - 17 , as another option, step S1 forms an initial first part extending in the first direction, and the bottom ends of a plurality of initial first parts arranged in a second direction perpendicular to the first direction being connected to each other may also, for example, include: providing a substrate 100'; forming initial first parts 100-1' extending on the substrate 100' in the z direction, where the plurality of initial first parts 100-1' are spaced apart in the y direction. The bottom ends 104' of the plurality of initial first parts 100-1' are all connected to the substrate 100' and are connected to each other through the substrate 100'.

[0098] Optionally, an initial first layer (not shown) is formed on the substrate 100' by an epitaxial growth process, which includes but is not limited to: Vapor Phase Epitaxy (VPE), Liquid Phase Epitaxy (LPE), Molecular Beam Epitaxy (MPE), or any combination thereof. The material of the initial first layer can be at least one of silicon, silicon germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials.

[0099] In addition, the initial first layer can also be formed on the substrate 100' by one or more thin film deposition processes, which can include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination of thin film deposition processes or any combination thereof.

[0100] After that, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove part of the initial first layer, and the initial first part 100-1' extending along the z direction on the substrate 100'.

[0101] Step S2

[0102] Figure 18 is a cross-sectional schematic view of the structure formed after forming the first dielectric layer 240 according to the preparation method of an embodiment of the present application. Figure 19 is a three-dimensional schematic view of the structure formed after forming the first dielectric layer 240 according to the preparation method of an embodiment of the present application. Figure 20 is a cross-sectional schematic view of the structure formed after forming the second opening 120-2 according to the preparation method of an embodiment of the present application. Figure 21 is a three-dimensional schematic view of the structure formed after forming the second opening 120-2 according to the preparation method of an embodiment of the present application. Figure 22 is a cross-sectional schematic view of the structure formed after forming the initial second part 100-2' according to the preparation method of an embodiment of the present application. Figure 23 is a three-dimensional schematic view of the structure formed after forming the initial second part 100-2' according to the preparation method of an embodiment of the present application.

[0103] As Figures 18 - 23As shown, step S2 of forming an initial second part extending along a first direction and connected to the initial first part may include, for example: forming a first dielectric layer 240 covering at least the initial first part 100-1'; forming a second opening 120-2 extending in the z direction into the initial first part 100-1' in the first dielectric layer 240; and filling the second opening 120-2 to form the initial second part 100-2'.

[0104] Specifically, as Figures 16 - 19 shown, a first dielectric layer 240 covering at least the initial first part 100-1' is formed by one or more thin film deposition processes, and the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the first dielectric layer 240 fills a plurality of initial openings 120-1 and covers at least the top surface of the initial first part 100-1' away from the substrate 100'. In addition, the first dielectric layer 240 may include any suitable dielectric material, such as silicon oxide, silicon nitride, and silicon oxynitride, etc.

[0105] As Figures 18 - 21 shown, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove a part of the first dielectric layer 240, and a second opening 120-2 extending in the z direction into the initial first part 100-1' can be formed.

[0106] As Figures 20 - 23 shown, optionally, at least one of an epitaxial process and a deposition process may be used to form the initial second part 100-2'. As an option, an initial second part 100-2' filling the second opening 120-2 is formed by one or more thin film deposition processes, and the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; as another option, an initial first layer (not shown) is formed on the substrate 100' by an epitaxial growth process, and the epitaxial growth processes include, but are not limited to: VPE, LPE, MPE, etc., or any combination thereof. The material of the initial second part 100-2' may be at least one of silicon, silicon germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials.

[0107] Optionally, different semiconductor materials are used to form the initial first part 100-1' and the initial second part 100-2' respectively; in addition, the same semiconductor materials may also be used to form the initial first part 100-1' and the initial second part 100-2' respectively, and this application does not make any limitation thereto.

[0108] In addition, in some embodiments of the present application, the initial second part 100-2' may include a plurality of initial sub-parts (not shown) arranged in sequence along the z direction, so as to form Figure 3 the semiconductor device 1000 shown including a plurality of sub-parts.

[0109] Specifically, as Figures 18 - 23 shown, the initial second part 100-2' formed to extend along the z direction and connected to the initial first part 100-1' includes: forming a first dielectric layer 240 that at least covers the initial first part 100-1', and forming a first sub-opening (not shown) that extends along the z direction to the initial first part 100-1' in the first dielectric layer 240; filling the first sub-opening to form a first initial sub-part (not shown) of the initial second part 100-2'; forming a second dielectric layer (not shown) that at least covers the first initial sub-part, and forming a second sub-opening (not shown) that extends along the z direction to the first initial sub-part in the second dielectric layer; and filling the second sub-opening to form a second initial sub-part (not shown) of the initial second part 100-2', where the second initial sub-part is the next initial sub-part connected to the first initial sub-part among the plurality of initial sub-parts. According to the above method, a plurality of initial sub-parts of the initial second part 100-2' can be formed in sequence.

[0110] Optionally, different filling processes are used to form the above-mentioned plurality of initial sub-parts respectively, and the filling process may include at least one of an epitaxial process and a deposition process. For example, the epitaxial growth process includes but is not limited to: VPE, LPE, MPE, etc. or any combination thereof. The thin film deposition process may include but is not limited to CVD, PVD, ALD or any combination of thin film deposition processes or any combination thereof.

[0111] In addition, the material of the initial sub-part may be at least one of silicon, silicon germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials. Optionally, different semiconductor materials are used to form the plurality of initial sub-parts respectively; in addition, the same semiconductor material may also be used to form the plurality of initial sub-parts respectively, and the present application does not limit this.

[0112] Step S3

[0113] Figure 24 is a schematic cross-sectional view of the structure formed after planarizing the first dielectric layer 240 according to the preparation method of an embodiment of the present application. Figure 25 is a schematic three-dimensional view of the structure formed after planarizing the first dielectric layer 240 according to the preparation method of an embodiment of the present application.

[0114] Combined with Figures 1 - 3 、 Figures 24 - 25, in step S3, a first opening 130 extending in the y direction is formed, and a plurality of first openings 130 divide the initial first part 100-1' and the initial second part 100-2' into a plurality of first parts 100-1 and a plurality of second parts 100-2 respectively.

[0115] Specifically, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., to form the first opening 130. The first opening 130 extends through the initial second part 100-2' in the z direction and the initial first part 100-1' corresponding to the initial second part 100-2'; in addition, the first opening 130 extends in the y direction, passing through a plurality of initial second parts 100-2' and a plurality of initial first parts 100-1', thereby dividing the initial first part 100-1' and the initial second part 100-2' into a plurality of first parts 100-1 and a plurality of second parts 100-2 respectively. A plurality of first parts 100-1 and a plurality of second parts 100-2 connected to the plurality of first parts 100-1 are formed into a semiconductor device 1000.

[0116] In addition, as Figures 22 - 25 shown, before forming the first opening 130, a planarization process can be performed on the top surface of the first dielectric layer 240 and the top surface of the initial second part 100-2', and the planarization process can include any suitable technical planarization, such as grinding and / or chemical mechanical polishing, etc. The first dielectric layer 240 after planarization is formed into a second dielectric layer 200, which has a flush top surface with the initial second part 100-2', so as to facilitate the subsequent formation of the first opening 130 via this flat and flush top surface. It should be noted that limited by the process, the error range of the top surface of the first dielectric layer 240 and the top surface of the initial second part 100-2' relative to the same reference plane can be between -10% and 10%.

[0117] In the semiconductor device 1000, in a direction perpendicular to the z direction (x direction or y direction), the dimension D1 of the first end 101 of the first part 100-1 satisfies: D1 > D2 with the dimension D2 of the second end 102 of the second part 100-2.

[0118] According to the semiconductor device manufacturing method provided by at least one embodiment of the present application, the semiconductor device may include a semiconductor pillar extending in a first direction, wherein a first end of a first part of the semiconductor pillar is connected to a second end of a second part of the semiconductor pillar in the first direction, and in a direction perpendicular to the first direction, the size of the first end is larger than the size of the second end. By forming the first part and the second part of the semiconductor pillar step by step, the situations of bending and tilting of the semiconductor pillar can be effectively reduced, and the process window of other structures of the semiconductor device formed on the semiconductor pillar subsequently can be increased. While optimizing the semiconductor device manufacturing process, the comprehensive performance of the semiconductor device is improved.

[0119] In addition, Figure 26 FIG. 30000 is a schematic structural diagram of a storage system 30000 according to an embodiment of the present application.

[0120] As Figure 26 shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and the present application will not elaborate on this. The semiconductor device 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. Hereinafter, a three-dimensional semiconductor device will be taken as an example for illustration.

[0121] As an option, the three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0122] The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and the present application will not elaborate on this. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations in response to requests from a host 31000 based on the control of the controller 32000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access a region selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 may perform an internal operation corresponding to the command on the region selected by the address.

[0123] In some embodiments, the three-dimensional storage system may be implemented as, for example, a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of an MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of an SD, mini SD, and micro SD, a storage device of the personal computer memory card international association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card, or a memory stick, etc. The storage system provided in this application has the same beneficial effects as the semiconductor device due to the provision of the semiconductor device provided in this application, which will not be elaborated here.

[0124] Although exemplary preparation methods and structures of the semiconductor device are described herein, it can be understood that one or more features may be omitted, substituted, or added to the structure of the semiconductor device. In addition, the materials of the exemplified layers are merely exemplary.

[0125] The above description is only a preferred embodiment of this application and an explanation of the applied technical principles. Those skilled in the art should understand that the protection scope involved in this application is not limited to the technical solution formed by the selected combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solution formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that, including a semiconductor column extending along a first direction, the semiconductor column including a first portion and a second portion located on one side of the first portion, wherein a first end of the first portion is connected to a second end of the second portion along the first direction; and in a direction perpendicular to the first direction, a dimension D1 of the first end and a dimension D2 of the second end satisfy: D1 > D2.

2. The semiconductor device according to claim 1, wherein, The second portion further includes a third end opposite to the second end in the first direction, wherein, in a direction perpendicular to the first direction, a dimension D3 of the third end and a dimension D2 of the second end satisfy: D3 > D2.

3. The semiconductor device according to claim 1, wherein, The second portion further includes a third end opposite to the second end in the first direction, wherein, in a direction perpendicular to the first direction, a dimension D3 of the third end and a dimension D1 of the first end satisfy: D3 ≥ D1.

4. The semiconductor device according to claim 1, wherein, the first portion and the second portion include different semiconductor material layers.

5. The semiconductor device according to claim 1, wherein, the first portion and the second portion are formed by different manufacturing processes.

6. The semiconductor device according to any one of claims 1-5, wherein, The second portion includes a plurality of sub-portions arranged in sequence along the first direction, the second portion further includes a third end opposite to the second end in the first direction, wherein at least one of the plurality of sub-portions includes a first sub-end and a second sub-end opposite to each other in the first direction, the first sub-end is closer to the first portion than the second sub-end, in a direction perpendicular to the first direction, a dimension D5 of the first sub-end and a dimension D6 of the second sub-end satisfy: D5 ≤ D6; and the first sub-end of the sub-portion closest to the first portion among the plurality of sub-portions is the second end of the second portion, and the second sub-end of the sub-portion farthest from the first portion among the plurality of sub-portions is the third end of the second portion.

7. The semiconductor device according to claim 6, wherein, a cross-sectional shape of at least one of the plurality of sub-portions in a plane parallel to the first direction includes a trapezoidal shape.

8. The semiconductor device according to claim 6, wherein, at least two of the plurality of sub-portions include different semiconductor material layers.

9. The semiconductor device according to claim 6, wherein, A dimension D6 of the second sub-end of at least one of the plurality of sub-portions in a direction perpendicular to the first direction and an extension length H1 of at least one of the plurality of sub-portions in the first direction satisfy: 1 / 8 ≤ D6 / H1 ≤ 1 / 7.

10. The semiconductor device according to any one of claims 2-5, wherein, The semiconductor device further includes a gate structure, wherein the semiconductor column includes a plurality of sidewalls, and the gate structure is located on at least one of the sidewalls.

11. The semiconductor device according to any one of claims 2-5, wherein, A cross-section of the semiconductor column in a plane perpendicular to the first direction includes at least one of a square shape, a rectangular shape, a trapezoidal shape, a circular shape, and an elliptical shape.

12. A method for manufacturing a semiconductor device, characterized in that, including: forming an initial first portion extending along a first direction, wherein bottoms of a plurality of the initial first portions arranged along a second direction perpendicular to the first direction are connected to each other; forming an initial second portion extending along the first direction and connected to the initial first portion; and Form a first opening extending along the second direction, wherein a plurality of the first openings divide the initial first part and the initial second part into a plurality of first parts and a plurality of second parts respectively, wherein, a first end of the first part is connected to a second end of the second part to form a semiconductor column; and in a direction perpendicular to the first direction, a dimension D1 of the first end and a dimension D2 of the second end satisfy: D1 > D2.

13. The method according to claim 12, wherein, Forming an initial second part extending along the first direction and connected to the initial first part includes: Forming the initial second part by using at least one of an epitaxial process and a deposition process.

14. The method according to claim 12, wherein, Forming an initial second part extending along the first direction and connected to the initial first part includes: Forming a first dielectric layer covering at least the initial first part, and forming a second opening in the first dielectric layer extending along the first direction to the initial first part; and Filling the second opening to form the initial second part.

15. The method according to claim 14, wherein, The method further includes: Forming the first opening from a first side of the initial second part; and Before forming the first opening, processing a top surface of the first dielectric layer on the first side and a top surface of the initial second part on the first side by using a planarization process.

16. The method according to claim 12, wherein, The initial second part includes a plurality of initial sub-parts arranged in sequence along the first direction. Forming an initial second part extending along the first direction and connected to the initial first part includes: Forming a first dielectric layer covering at least the initial first part, and forming a first sub-opening in the first dielectric layer extending along the first direction to the initial first part; Filling the first sub-opening to form a first initial sub-part of the initial second part; Forming a second dielectric layer covering at least the first initial sub-part, and forming a second sub-opening in the second dielectric layer extending along the first direction to the first initial sub-part; and Filling the second sub-opening to form a second initial sub-part of the initial second part, wherein, the second initial sub-part is the next initial sub-part connected to the first initial sub-part among the plurality of initial sub-parts.

17. The method according to claim 16, wherein, Forming an initial second part extending along the first direction and connected to the initial first part includes: Forming the plurality of initial sub-parts by using different filling processes respectively, wherein, the filling process includes at least one of an epitaxial process and a deposition process.

18. The method according to claim 12, wherein, The initial second part includes a plurality of initial sub-parts arranged in sequence along the first direction. The method further includes: Forming the initial first part and the initial second part by using different semiconductor materials respectively; and / or Forming the plurality of initial sub-parts by using different semiconductor materials respectively.

19. A memory system, characterized in that, Includes: At least one semiconductor device according to any one of claims 1 - 11; And A controller, coupled to the semiconductor device and configured to control the semiconductor device to store data.

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