Storage array and preparation method thereof, memory and electronic equipment

Abstract

The invention provides a memory array and a preparation method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and aims to improve the arrangement density of the memory array. The storage array comprises a plurality of storage units arranged in an array mode, and each storage unit comprises a capacitor and a transistor. The capacitor comprises a first electrode, a dielectric layer and a second electrode, the first electrode is arranged around the second electrode, and the dielectric layer is located between the first electrode and the second electrode. The transistor is arranged on the capacitor and comprises a channel layer, a gate dielectric layer and a gate layer, the gate layer surrounds the side face of the channel layer, and the gate dielectric layer is located between the channel layer and the gate layer. The channel layer is in contact with the second electrode, the channel layer comprises a first surface in contact with the second electrode, the second electrode comprises a second surface in contact with the channel layer, and the boundary of the first surface coincides with the boundary of the second surface. The memory array can be applied to a memory to realize reading and writing of data.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a storage array, a preparation method thereof, a memory, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) has become one of the mainstream memories due to its advantages such as high speed, high density, and low latency.

[0003] Currently, the size reduction of DRAM has reached a bottleneck. How to improve the layout density of the storage array in the memory to achieve the size reduction of the device has become an urgent problem in the field. Summary of the Invention

[0004] Embodiments of this application provide a storage array, a preparation method thereof, a memory, and an electronic device, aiming to improve the layout density of the storage array.

[0005] To achieve the above object, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a storage array is provided. The storage array includes a plurality of storage units arranged in an array. Each storage unit includes a capacitor and a transistor. Among them, the capacitor includes a first electrode, a dielectric layer, and a second electrode. The first electrode is arranged around the second electrode, and the dielectric layer is located between the first electrode and the second electrode. The transistor is disposed on the capacitor. The transistor includes a channel layer, a gate dielectric layer, and a gate layer. The gate layer surrounds the side surface of the channel layer, and the gate dielectric layer is located between the channel layer and the gate layer. The channel layer is in contact with the second electrode. The channel layer includes a first surface in contact with the second electrode, and the second electrode includes a second surface in contact with the channel layer. The boundary of the first surface coincides with the boundary of the second surface.

[0007] In the storage array provided by the above embodiments of this application, the storage array includes a plurality of storage units arranged in an array. In the capacitor of each storage unit, the first electrode is arranged around the second electrode, and the dielectric layer is located between the first electrode and the second electrode, so that the capacitor has a "columnar capacitor structure". The transistor is disposed on the capacitor. The transistor includes a channel layer, a gate dielectric layer, and a gate layer. The gate layer surrounds the side surface of the channel layer, which is beneficial to improving the control ability of the gate layer over the channel layer and increasing the window of the operating voltage of the transistor. The gate dielectric layer is located between the channel layer and the gate layer, and the transistor has a "vertical transistor structure".

[0008] The planar size of the columnar capacitor structure is smaller than that of the planar capacitor structure, and the planar size of the vertical transistor structure is smaller than that of the planar transistor structure, which is beneficial to reducing the planar size of the memory cell, increasing the number of memory cells arranged per unit area, and thus improving the layout density of the memory array.

[0009] The channel layer of the transistor contacts the second electrode of the capacitor. The channel layer includes a first surface that contacts the second electrode, and the second electrode includes a second surface that contacts the channel layer. The boundary of the first surface coincides with the boundary of the second surface, that is, the positions and sizes of the ends where the channel layer and the second electrode contact are the same. The channel layer and the second electrode are aligned with a high alignment accuracy, ensuring a stable connection between the transistor and the capacitor and being beneficial to improving the layout density of the memory array.

[0010] In some embodiments, the memory array further includes a plurality of word lines. The multiple memory cells arranged in an array include multiple rows and multiple columns. The gate layers of the multiple transistors in one row of memory cells are connected together to form a word line. The word line includes a conductive connection layer located between the gate layers of two adjacent transistors. The surface of the conductive connection layer far from the capacitor is recessed towards the direction close to the capacitor, so that the cross-sectional area of the conductive connection layer is smaller, which can save the materials used for preparing the word line.

[0011] Alternatively, the conductive connection layer fills the gap region between the gate layers of two adjacent transistors, so that the cross-sectional area of the word line is larger, which is beneficial to reducing the resistance of the word line and thus reducing the voltage drop of the voltage signal transmitted on the word line.

[0012] In some embodiments, the memory array further includes a plurality of bit lines. Each bit line is disposed on the side of the transistor far from the capacitor, and each bit line is electrically connected to the channel layers of the multiple transistors in one column of memory cells. The end of the channel layer connected to the bit line is the source electrode of the transistor.

[0013] In some embodiments, the memory array further includes a plate line disposed on the side of the capacitor far from the transistor. The first electrodes of the multiple capacitors in the multiple memory cells are electrically connected to the plate line.

[0014] In some embodiments, the memory cell includes a plurality of capacitors and a transistor. Along the direction from the capacitor to the transistor, the first electrode layers of the plurality of capacitors are stacked and spaced apart, and the second electrodes of the plurality of capacitors are connected together to form a columnar electrode. The channel layer of the transistor is connected to one end of the columnar electrode.

[0015] In some embodiments, along the direction from the capacitor to the transistor, the memory array includes a plurality of memory structures stacked. Each memory structure includes a plurality of memory cells arranged in an array. Through the three-dimensional stacking of the plurality of memory structures, it is beneficial to improve the layout density of the memory array.

[0016] In some embodiments, the material of the dielectric layer includes a ferroelectric material. In this case, the capacitor formed by the first electrode, the dielectric layer, and the second electrode is a ferroelectric capacitor.

[0017] In a second aspect, a method for manufacturing a memory array is provided. The manufacturing method includes: forming an insulating layer having a plurality of vias on a substrate, and the plurality of vias are arranged in an array. Forming a first electrode, a dielectric layer, and a second electrode in the vias, the first electrode is located on the surface of the via, the dielectric layer is located inside the first electrode, and the second electrode is located inside the dielectric layer. Relative to the substrate, the surface of the second electrode on the side away from the substrate is lower than the surface of the insulating layer on the side away from the substrate. Forming a barrier layer in the via, the barrier layer is located inside the dielectric layer and on the side of the second electrode away from the substrate. Removing the insulating layer, the part of the first electrode and the dielectric layer outside the barrier layer to expose the barrier layer. Forming a gate dielectric layer and a gate layer on the side surface of the barrier layer.

[0018] In the manufacturing method provided by the above embodiments of the present application, by forming an insulating layer having a plurality of vias on a substrate and forming a first electrode, a dielectric layer, and a second electrode in the vias, the first electrode is located on the surface of the via, and the dielectric layer and the second electrode are sequentially located inside the first electrode. The first electrode, the dielectric layer, and the second electrode form a "columnar capacitor structure". Moreover, the top surface of the second electrode is lower than the top surface of the insulating layer, that is, during the process of manufacturing the columnar capacitor structure, a chamber is synchronously formed in the via.

[0019] Then, a barrier layer is formed in the chamber in the via. The barrier layer is also located inside the dielectric layer and above the second electrode. Finally, the insulating layer, the part of the first electrode and the dielectric layer outside the barrier layer are removed to expose the barrier layer, and a gate dielectric layer and a gate layer are formed on the side surface of the barrier layer. The barrier layer can be used as the channel layer of the transistor, and the barrier layer, the gate dielectric layer, and the gate layer form a transistor. Or, the barrier layer is used as a sacrificial layer, and the barrier layer is replaced with a channel layer, and the channel layer, the gate dielectric layer, and the gate layer form a transistor.

[0020] It can be seen that both the barrier layer and the second electrode are located inside the dielectric layer, and the barrier layer is located above the second electrode. Therefore, in the direction parallel to the substrate, the positions and sizes of the barrier layer and the second electrode are defined by the same dielectric layer, that is, the positions and sizes of the channel layer and the second electrode are defined by the same dielectric layer, so that the positions of the channel layer and the second electrode are the same and the sizes are the same, realizing the "automatic alignment" of the channel layer and the second electrode.

[0021] Compared with the process of exposure and development, etching channel holes on the gate layer to form the channel layer requires aligning the channel holes with the second electrode. In the above preparation method of the present application, the process of "automatic alignment" between the channel layer and the second electrode does not require the exposure and development process, and the preparation process is relatively simple and controllable, which is beneficial to reducing the process difficulty and cost.

[0022] In some embodiments, forming the first electrode, dielectric layer, and second electrode in the via includes: forming the first electrode on the surface of the via. Forming the dielectric layer on the inner side of the first electrode. Depositing a conductive material to form a filling layer on the inner side of the dielectric layer. Removing the part of the filling layer away from the substrate to form a first chamber in the via, and the remaining part of the filling layer forms the second electrode, realizing the formation of the first chamber in the via synchronously during the preparation of the columnar capacitor structure.

[0023] Forming the barrier layer in the via includes: forming the barrier layer in the first chamber, the barrier layer is in contact with the second electrode, the position of the barrier layer is the same as that of the second electrode, and the sizes of the ends of the barrier layer and the second electrode in contact are the same.

[0024] In some embodiments, forming the gate dielectric layer and gate layer on the side of the barrier layer includes: forming a gate dielectric thin film and a gate thin film on the outer side of the barrier layer. The gate dielectric thin film at least includes a first part located on the side of the barrier layer away from the substrate and a second part located on the side of the barrier layer. The gate thin film at least includes a third part located on the side of the barrier layer away from the substrate and a fourth part located on the side of the barrier layer. Removing the third part of the gate thin film and removing the first part of the gate dielectric thin film, and the remaining second part serves as the gate dielectric layer, and the fourth part serves as the gate layer, and the surface of the barrier layer away from the substrate is exposed, so as to form a bit line on the surface of the barrier layer subsequently or replace the barrier layer with a channel layer.

[0025] In some embodiments, the plurality of vias include multiple rows and multiple columns, and the multiple barrier layers in the plurality of vias include multiple rows and multiple columns. After forming the gate dielectric layer and gate layer on the side of the barrier layer, a first mask layer is formed. The first mask layer has a plurality of first openings, and each first opening exposes the gate layer on the side of a row of barrier layers. Depositing a conductive material, through the first openings, a conductive connection layer is formed between the multiple barrier layers in the same row, and the conductive connection layer is connected to the gate layers on the sides of the multiple barrier layers to form a word line.

[0026] In some embodiments, the gate thin film further includes a fifth part located on the surface of the insulating layer, and the fifth part is connected to the gate layers on the sides of the multiple barrier layers. After forming the gate dielectric layer and gate layer on the side of the barrier layer, a second mask layer is formed. The second mask layer has a plurality of second openings, and each second opening exposes the region between adjacent two rows of barrier layers. Through the second openings, a part of the fifth part of the gate thin film is removed, and the remaining part of the fifth part and the gate layers on the sides of the barrier layers in the same row jointly form a word line.

[0027] In some embodiments, the barrier layer is directly used as the channel layer of the transistor. The transistor includes a barrier layer, a gate dielectric layer, and a gate layer. A bit line can be directly formed on the surface of the barrier layer, simplifying the process steps for preparing the channel layer.

[0028] In some embodiments, the barrier layer is used as a sacrificial layer. After forming the gate dielectric layer and the gate layer on the side of the barrier layer, the barrier layer is removed to form a second chamber. A channel layer of the transistor is formed in the second chamber. The transistor includes a channel layer, a gate dielectric layer, and a gate layer, realizing the replacement of the barrier layer with the channel layer, which can avoid etching damage to the channel layer during the process of forming the gate dielectric layer and the gate layer, thus being beneficial to improving the film quality of the channel layer and the electrical performance of the transistor.

[0029] In a third aspect, a memory is provided. The memory includes the storage array in any of the above embodiments, and a controller electrically connected to the storage array.

[0030] In a fourth aspect, an electronic device is provided. The electronic device is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. The electronic device includes a circuit board and the memory in the above embodiments, and the memory is electrically connected to the circuit board.

[0031] It can be understood that for the memory and the electronic device provided in the above embodiments of the present application, the beneficial effects that can be achieved can refer to the beneficial effects of the storage array in the foregoing text, which will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present application, the drawings required for use in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products and the actual processes of the methods involved in the embodiments of the present application.

[0033] Figure 1 It is the architecture diagram of the electronic device provided by the embodiment of the present application;

[0034] Figure 2 It is the exploded view of the electronic device provided by the embodiment of the present application;

[0035] Figure 3 It is the architecture diagram of the memory provided by the embodiment of the present application;

[0036] Figure 4The circuit diagram of the storage array provided by the embodiment of the present application;

[0037] Figure 5A and Figure 5B The flowcharts for preparing the storage array provided by the embodiment of the present application;

[0038] Figures 6A to 6S The structure diagrams corresponding to the steps of a preparation method of the storage array provided by the embodiment of the present application;

[0039] Figures 7A to 7D The structure diagrams corresponding to the steps of another preparation method of the storage array provided by the embodiment of the present application;

[0040] Figures 8A to 8F The structure diagrams corresponding to the steps of yet another preparation method of the storage array provided by the embodiment of the present application;

[0041] Figure 9 The cross-sectional view of a storage array along the plane X-Z provided by the embodiment of the present application;

[0042] Figure 10 The cross-sectional view of a storage array along the plane Y-Z provided by the embodiment of the present application;

[0043] Figure 11 The structure diagram of another storage array provided by the embodiment of the present application. Detailed implementation manners

[0044] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0045] Some embodiments of the present application provide an electronic device, which can be, for example, different types of user devices or terminal devices such as mobile phones, tablet computers, personal digital assistants (PDAs), televisions, smart wearable products (such as smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, small household appliances for charging (such as soybean milk machines, floor sweeping robots), drones, radars, aerospace equipment, and vehicle-mounted equipment; the electronic device can also be a network device such as a base station. The embodiments of the present application do not impose special restrictions on the specific form of the electronic device.

[0046] Figure 1It is an architecture diagram of the electronic device provided by the embodiments of this application.

[0047] Refer to Figure 1 , the electronic device 1 includes components such as a storage device 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art can understand that Figure 1 the architecture of the electronic device 1 shown in Figure 1 does not limit the electronic device 1. The electronic device 1 may include more or fewer components than those shown in Figure 1 , or may combine some of the components shown in Figure 1 , or may be arranged differently from the components shown in

[0048] Among them, the storage device 11 is used to store software programs and modules. The storage device 11 mainly includes a program storage area and a data storage area. Among them, the program storage area can store and back up an operating system, application programs required for at least one function (such as a sound playback function, an image playback function, etc.); the data storage area can store data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.). In addition, the storage device 11 includes an external memory 111 and an internal memory 112. The data stored in the external memory 111 and the internal memory 112 can be transmitted to each other.

[0049] The external memory 111 may include, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 112 may include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a resistive random access memory (RRAM), a phase change random access memory (PCRAM), a ferroelectric random access memory (FeRAM), a ferroelectric field-effect transistor (FeFET) memory, a ferroelectric tunnel junction (FTJ) memory, a NAND flash memory (NAND Flash), etc.

[0050] The processor 12 is the control center of the electronic device 1, connecting various parts of the entire electronic device 1 through various interfaces and circuits. By running or executing software programs and / or modules stored in the storage device 11, and calling data stored in the storage device 11, it performs various functions of the electronic device 1 and processes data. Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), etc. Among them, different processing units may be independent devices or integrated in one or more processors. For example, the processor 12 may integrate an application processor and a modem processor. Among them, the application processor mainly processes the operating system, user interface, application programs, etc., and the modem processor mainly processes wireless communication. It can be understood that the above modem processor may not be integrated into the processor 12. The above application processor may be a Central Processing Unit (CPU) for example. Figure 1 Taking the processor 12 as a CPU as an example, the CPU may include an arithmetic unit 121 and a controller 122. The arithmetic unit 121 obtains the data stored in the internal memory 112 and processes the data stored in the internal memory 112. The processed result is usually sent back to the internal memory 112. The controller 122 can control the arithmetic unit 121 to process data, and the controller 122 can also control the external storage device 111 and the internal memory 112 to read or write data.

[0051] The input device 13 is used to receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the electronic device. Exemplarily, the input device 13 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect touch operations of the user on or near the touch screen (such as operations of the user using a finger, a stylus, or any suitable object or accessory on or near the touch screen), and drive the corresponding connection device according to a preset program. The controller 122 in the above processor 12 can also control the input device 13 to receive or not receive input signals. In addition, the input digital or character information received by the input device 13, and the key signal inputs related to the user settings and function controls of the electronic device can be stored in the internal memory 112.

[0052] The output device 14 is used to output the input of the input device 13 and the signals corresponding to the data stored in the internal memory 112. For example, the output device 14 outputs sound signals or video signals. The controller 122 in the above processor 12 can also control the output device 14 to output or not output signals.

[0053] It should be noted that Figure 1 the thick arrows in are used to indicate the transmission of data, and the direction of the thick arrows indicates the direction of data transmission. For example, the single arrow between the input device 13 and the internal memory 112 indicates that the data received by the input device 13 is transmitted to the internal memory 112. Another example is that the double arrows between the arithmetic unit 121 and the internal memory 112 indicate that the data stored in the internal memory 112 can be transmitted to the arithmetic unit 121, and the data processed by the arithmetic unit 121 can be transmitted to the internal memory 112. Figure 1 The thin arrows in indicate the components that the controller 122 can control. Exemplarily, the controller 122 can control the external memory bank 111, the internal memory 112, the arithmetic unit 121, the input device 13, the output device 14, etc.

[0054] Figure 2 is an exploded view of the electronic device provided by the embodiment of the present application.

[0055] See Figure 2 , taking the electronic device 1 as a mobile phone as an example, the electronic device 1 includes a middle frame 15, a rear shell 16 and a display screen 17. The rear shell 16 and the display screen 17 are respectively located on opposite sides of the middle frame 15. The middle frame 15 includes a carrier plate 150 and a frame 151 surrounding the carrier plate 150 for one week. The carrier plate 150 is used to carry the display screen 17.

[0056] Continue to see Figure 2 , the electronic device 1 may further include a circuit board 18, which is arranged on the side of the carrier plate 150 close to the rear shell 16. The internal memory 112 in the electronic device 1 may be arranged on the circuit board 18, and the internal memory 112 is electrically connected to the circuit board 18.

[0057] Currently, DRAM is one of the mainstream memories and can be used as the internal memory 112. Figure 3 is an architecture diagram of the memory provided by the embodiment of the present application.

[0058] See Figure 3 , the internal memory 112 includes a memory array 21, a row decoding circuit 22, a column decoding circuit 23, a timing control circuit 24, a read / write control circuit 25 and a sense amplifier 26.

[0059] Among them, the memory array 21 includes a plurality of memory cells 210 arranged in an array. The plurality of memory cells 210 include multiple rows arranged along the first direction X and multiple columns arranged along the second direction Y. The first direction X intersects with the second direction Y. For example, the two are perpendicular to each other.

[0060] The timing control circuit 24 is electrically connected to the row decoding circuit 22, the column decoding circuit 23, the memory array 21, the read / write control circuit 25, and the sense amplifier 26 respectively, and the timing control circuit 24 is configured to perform timing control on each circuit.

[0061] The row decoding circuit 22 is electrically connected to the memory array 21, and the row decoding circuit 22 is configured to select the memory cells 210 of the corresponding row according to the row address for addressing the memory cells 210 of the corresponding row.

[0062] The column decoding circuit 23 is electrically connected to the memory array 21. After the memory cells 210 of the corresponding row are selected, the column decoding circuit 23 is configured to address the memory cells 210 of the corresponding column according to the column address, so as to select the memory cells 210 that need to perform read operations or write operations.

[0063] The read / write control circuit 25 is electrically connected to the memory array 21, and the read / write control circuit 25 is configured to control the selected memory cells 210 to perform read operations or write operations.

[0064] The sense amplifier 26 is electrically connected to the memory array 21, and the sense amplifier 26 is configured to read, amplify, and output the data information stored in the selected memory cells 210 to implement the data read operation; or, input data signals to the selected memory cells 210 to implement the data write operation.

[0065] Figure 4 It is a circuit diagram of the memory array provided by the embodiment of the present application.

[0066] See Figure 4 , the memory array 21 further includes a plurality of word lines (WL) extending along the direction X, a plurality of bit lines (BL) extending along the direction Y, and a plurality of plate lines (PL) extending along the direction Y. Each row of memory cells 210 is electrically connected to one word line WL, and each column of memory cells 210 is electrically connected to one bit line BL and one plate line PL.

[0067] Continue to see Figure 4 , the memory cell 210 may have a 1T1C (1-Transistor-1-Capacitor) structure, that is, the memory cell 210 includes a transistor T and a capacitor C. The gate of the transistor T is electrically connected to the word line WL, the source is electrically connected to the bit line BL, the drain is electrically connected to one electrode of the capacitor C, and the other electrode of the capacitor C is electrically connected to the plate line PL. The circuit architecture of the memory cell 210 in the embodiment of the present application is not limited to this.

[0068] The embodiment of the present application provides a method for manufacturing a memory array, Figure 5A andFigure 5B Flowcharts for preparing a storage array provided by embodiments of the present application; Figures 6A to 6S Structural diagrams corresponding to the steps of a method for preparing a storage array provided by embodiments of the present application.

[0069] Refer to Figure 5A , the method for preparing a storage array includes the following S1 to S5:

[0070] Figure 6A In, (b) is a cross-sectional view of (a) along the section line A-A'; Figure 6B In, (b) is a cross-sectional view of (a) along the section line B-B'.

[0071] S1: Refer to Figure 6A and Figure 6B , form a first insulating layer 31 having a plurality of vias H on a substrate 30. The plurality of vias H are arranged in an array. For example, the plurality of vias H include multiple rows and multiple columns. Each row of vias H is arranged along the direction X, and each column of vias H is arranged along the direction Y.

[0072] Exemplarily, refer to Figure 6A , first form a board line PL on the substrate 30, and form a first insulating layer 31 above the board line PL. Then, refer to Figure 6B , use a lithography process to etch the first insulating layer 31 to form a plurality of vias H on the first insulating layer 31. The bottom of the via H exposes the board line PL.

[0073] Exemplarily, the plurality of vias H arranged in an array include multiple rows and multiple columns. Each row of vias H is arranged along the direction X, and each column of vias H is arranged along the direction Y.

[0074] S2: Refer to Figure 6C and Figure 6D , form a first electrode 32, a dielectric layer 33, and a second electrode 34 in the via H. The first electrode 32 is located on the surface of the via H, the dielectric layer 33 is located inside the first electrode 32, and the second electrode 34 is located inside the dielectric layer 33. The first electrode 32, the dielectric layer 33, and the second electrode 34 form a capacitor C. The second electrode 34 is surrounded by the first electrode 32. The first electrode 32 can be referred to as the "bottom electrode", and the second electrode 34 can be referred to as the "top electrode". The capacitor C has a "columnar capacitive structure".

[0075] Relative to the substrate 30, the surface P1 of the second electrode 34 on the side away from the substrate 30 is lower than the surface P2 of the first insulating layer 31 on the side away from the substrate 30. That is, relative to the substrate 30, the height of the surface P1 of the second electrode 34 is less than the height of the surface P2 of the first insulating layer 31 to form a first chamber C1 in the via H.

[0076] In some examples, refer to Figure 5B, the above S2 may include the following S21 to S24:

[0077] S21: Refer to Figure 6C , form a first electrode 32 on the surface of the via hole H, and the first electrode 32 is connected to the board line PL located at the bottom of the via hole H.

[0078] Exemplarily, the electrode material may be deposited over the entire surface to form the first electrode 32, and the first electrode 32 may cover the surface of the via hole H and also cover the surface P2 of the first insulating layer 31 on the side away from the substrate 30.

[0079] S22: Refer to Figure 6C , form a dielectric layer 33 inside the first electrode 32.

[0080] Exemplarily, the dielectric material may be deposited over the entire surface to form the dielectric layer 33, and the dielectric layer 33 covers the first electrode 32, and inside the via hole H, the dielectric layer 33 is located inside the first electrode 32.

[0081] Exemplarily, the material of the dielectric layer 33 may include a dielectric material.

[0082] Exemplarily, the material of the dielectric layer 33 may include a ferroelectric material. In this case, the capacitor C formed by the first electrode 32, the dielectric layer 33, and the second electrode 34 is a ferroelectric capacitor.

[0083] S23: Continue to refer to Figure 6C , deposit a conductive material to form a filling layer 340 inside the dielectric layer 33 to fill the via hole H.

[0084] S24: Refer to Figure 6C and Figure 6D , remove the part of the filling layer 340 away from the substrate 30 to form a first chamber C1 inside the via hole H, and the remaining part of the filling layer 340 forms the second electrode 34, achieving the formation of the first chamber C1 inside the via hole H during the process of fabricating the capacitor C.

[0085] Exemplarily, a recess process may be used to etch the filling layer 340 downward to form the first chamber C1. The first chamber C1 is subsequently used to form a blocking layer (the channel layer of the transistor T), and the first chamber C1 defines the size of the channel layer. Or rather, the etching depth of the filling layer 340 depends on the height of the channel layer.

[0086] S3: Refer to Figure 6E and Figure 6F , form a blocking layer 35 inside the via hole H. The blocking layer 35 is located inside the dielectric layer 33 and on the side of the second electrode 34 away from the substrate 30.

[0087] It can be understood that the multiple vias H include multiple rows and columns, such that the multiple barrier layers 35 within the multiple vias H include multiple rows and columns, each row of barrier layers 35 is arranged along the direction X, and each column of barrier layers 35 is arranged along the direction Y.

[0088] Exemplarily, referring to Figure 6E and Figure 6F , a sacrificial material or a channel material can be deposited over the entire surface to form a barrier film 350 within the first chamber C1. Then, a Chemical Mechanical Polishing (CMP) process is employed to grind the upper surface of the barrier film 350 until the surface P2 of the first insulating layer 31, the first electrode 32, and the dielectric layer 33 are exposed, and the remaining portion of the barrier film 350 forms the barrier layer 35.

[0089] Continuing to refer to Figure 6F , the barrier layer 35 is in contact with the second electrode 34. The barrier layer 35 includes a first surface M1 in contact with the second electrode 34, and the second electrode 34 includes a second surface M2 in contact with the barrier layer 35. The boundary of the first surface M1 coincides with the boundary of the second surface M2, that is, the dimensions of the ends of the barrier layer 35 and the second electrode 34 in contact are the same.

[0090] It can be understood that within the same via H, the barrier layer 35 is located inside the dielectric layer 33, and the second electrode 34 is also located inside the dielectric layer 33, and the barrier layer 35 is located above the second electrode 34. In the X - Y plane, the positions and dimensions of the barrier layer 35 and the second electrode 34 are defined by the dielectric layer 33 within the same via H, such that the positions and dimensions of the barrier layer 35 and the second electrode 34 are the same, achieving "automatic alignment" of the barrier layer 35 and the second electrode 34.

[0091] S4: Referring to Figure 6F and Figure 6G , the portion of the first insulating layer 31 located outside the barrier layer 35 is removed, the portion of the first electrode 32 located outside the barrier layer 35 is removed, and the portion of the dielectric layer 33 located outside the barrier layer 35 is removed to expose the barrier layer 35.

[0092] Exemplarily, first, the first insulating layer 31 is etched to remove the portion of the first insulating layer 31 located outside the barrier layer 35 to expose the portion of the first electrode 32 located outside the barrier layer 35. Then, the first electrode 32 is etched to remove the portion of the first electrode 32 located outside the barrier layer 35 to expose the portion of the dielectric layer 33 located outside the barrier layer 35. Finally, the dielectric layer 33 is etched to remove the portion of the dielectric layer 33 located outside the barrier layer 35 to expose the side surface of the barrier layer 35.

[0093] It can be understood that the material of the barrier layer 35 has a large etching selectivity ratio with respect to the materials of the first insulating layer 31, the first electrode 32, and the dielectric layer 33. Therefore, during the etching process of the first insulating layer 31, the first electrode 32, and the dielectric layer 33, the barrier layer 35 will not be etched and damaged, so as to retain the barrier layer 35.

[0094] S5: Refer to Figures 6H to 6L , a gate dielectric layer 36 and a gate layer 37 are formed on the side surface of the barrier layer 35.

[0095] Exemplarily, refer to Figure 6H , by using the Atomic Layer Deposition process, the gate dielectric material is deposited over the entire surface to form a gate dielectric film 360 on the outside of the barrier layer 35.

[0096] Refer to Figure 6I , the conductive material is deposited over the entire surface to form a gate film 370 on the surface of the gate dielectric film 360. Among them, the gate dielectric film 360 includes a first part a1 on the side of the barrier layer 35 away from the substrate 30, and a second part a2 on the side surface of the barrier layer 35. The gate film 370 includes a third part a3 on the side of the barrier layer 35 away from the substrate 30, and a fourth part a4 on the side surface of the barrier layer 35.

[0097] Refer to Figure 6I and Figure 6J , the third part a3 of the gate film 370 is removed, and the fourth part a4 of the gate film 370 forms the gate layer 37. The gate layer 37 surrounds the side surface of the barrier layer 35. After the channel layer of the transistor T is formed subsequently, it is beneficial to improve the control ability of the gate layer 37 over the channel layer and increase the window of the operating voltage of the transistor T.

[0098] For example, a dry etching process can be used to etch the gate film 370 downward. During the process of removing the third part a3 of the gate film 370, the part of the gate film 370 located on the surface of the first insulating layer 31 is also removed, so that the connection between the gate layers 37 located on the side surfaces of multiple barrier layers 35 is disconnected.

[0099] Refer to Figure 6K , the dielectric material is deposited over the entire surface to form a second insulating layer 38 on the outside of the barrier layer 35. The second insulating layer 38 plays a role in filling in, so as to facilitate subsequent grinding.

[0100] Refer to Figure 6K and Figure 6L, a chemical mechanical polishing process is adopted to grind the upper surface of the second insulating layer 38 and the first part a1 of the gate dielectric film 360, and the first part a1 of the gate dielectric film 360 is removed to expose the surface of the barrier layer 35 on the side away from the substrate 30. The second part a2 of the gate dielectric film 360 serves as the gate dielectric layer 36. Moreover, the remaining part of the second insulating layer 38 covers the gate layer 37.

[0101] Figure 6M In (b), it is a cross-sectional view of (a) along the section line C-C'.

[0102] After S5, refer to Figure 6M , a first mask layer 39 is formed on the second insulating layer 38. For example, the first mask layer 39 can be a photoresist. The first mask layer 39 can be exposed and developed, and a plurality of first openings K1 are formed on the first mask layer 39. Each first opening K1 extends along the direction X, and each first opening K1 exposes a row of the barrier layer 35 in the direction X and exposes the part of the second insulating layer 38 between the plurality of barrier layers 35 in the same row.

[0103] Figure 6N In (b), it is a cross-sectional view of (a) along the section line D-D'.

[0104] Refer to Figure 6M and Figure 6N , through the first opening K1 of the first mask layer 39, the part of the second insulating layer 38 between the plurality of barrier layers 35 in the same row is etched, and the part of the second insulating layer 38 between the plurality of barrier layers 35 in the same row is removed, so that each first opening K1 exposes the side surface of the gate layer 37 of a row of the barrier layer 35.

[0105] Figure 6O In (b), it is a cross-sectional view of (a) along the section line E-E'.

[0106] Refer to Figure 6O , a conductive material is deposited over the entire surface. Through the first opening K1 of the first mask layer 39, the conductive material fills the gap region G between the plurality of barrier layers 35 in the same row to form a conductive connection layer 40, and the conductive connection layer 40 is connected to the gate layer 37 on the side surfaces of the plurality of barrier layers 35.

[0107] Figure 6P In (b), it is a cross-sectional view of (a) along the section line F-F'.

[0108] Refer to Figure 6P, an etch-back process is adopted to etch the conductive connection layer 40 downward, and the part of the conductive connection layer 40 filled between two adjacent barrier layers 35 is reserved. The conductive connection layer 40 is connected in series with the gate layer 37 on the side of the same row of barrier layers 35 to form a word line WL extending along the direction X. The width W of the word line WL depends on the width of the first opening K1. In the direction Y, the width of the first opening K1 can be greater than the size of the barrier layer 35, can be equal to the size of the barrier layer 35, or can be less than the size of the barrier layer 35, so that the width W of the word line WL can be greater than, equal to, or less than the size of the barrier layer 35.

[0109] Since the conductive connection layer 40 fills the gap region G between multiple barrier layers 35, the surface P3 of the word line WL far from the capacitor C is flush. The cross-sectional area of the word line WL in the Y direction is large, which is beneficial to reducing the resistance of the word line WL, thereby reducing the voltage drop of the voltage signal transmitted on the word line WL.

[0110] Figure 6Q In, (b) is a cross-sectional view of (a) along the section line G-G'; (c) is a cross-sectional view of (a) along the section line H-H'.

[0111] See Figure 6Q , a dielectric material is deposited over the entire surface to form a third insulating layer 41, and the third insulating layer 41 covers multiple word lines WL.

[0112] Figure 6R In, (b) is a cross-sectional view of (a) along the section line I-I'; (c) is a cross-sectional view of (a) along the section line J-J'.

[0113] See Figure 6Q and Figure 6R , a chemical mechanical polishing process is adopted to polish the upper surface of the third insulating layer 41 until the upper surface of the barrier layer 35 is exposed.

[0114] Figure 6S In, (b) is a cross-sectional view of (a) along the section line K-K'; (c) is a cross-sectional view of (a) along the section line L-L'.

[0115] See Figure 6S , multiple bit lines BL are formed. Each bit line BL extends along the direction Y, and each bit line BL is connected to the barrier layer 35 in the same column.

[0116] Exemplarily, a dielectric material is first deposited over the entire surface to form a fourth insulating layer 42. Then, a photolithography and development process is adopted to etch the fourth insulating layer 42 to form vias, and the vias expose the barrier layer 35. Finally, bit lines BL are formed in the vias of the fourth insulating layer 42.

[0117] It can be understood that by selecting a suitable channel material for the material of the blocking layer 35, the blocking layer 35 can be directly used as the channel layer of the transistor T, which can simplify the process steps of preparing the channel layer.

[0118] The transistor T includes a blocking layer 35, a gate dielectric layer 36, and a gate layer 37. The blocking layer 35 is a vertical channel structure extending in the Z direction. The gate layer 37 is located on the side of the blocking layer 35, and the gate dielectric layer 36 is located between the blocking layer 35 and the gate layer 37. The transistor T has a "vertical transistor structure".

[0119] The gate layer 37 serves as the gate of the transistor T. The gate layer 37 is part of the word line WL, that is, the gate of the transistor T is electrically connected to the word line WL. One end of the blocking layer 35 connected to the bit line BL is the source electrode of the transistor T. The blocking layer 35 is connected to the second electrode 34, and one end of the blocking layer 35 connected to the second electrode 34 is the drain electrode of the transistor T. The transistor T is connected to the capacitor C to form a storage unit 210.

[0120] According to the foregoing, the blocking layer 35 and the second electrode 34 have the same position and the same size, and the blocking layer 35 and the second electrode 34 are "automatically aligned". Since the blocking layer 35 can be directly used as the channel layer of the transistor T, the channel layer and the second electrode 34 have the same position and the same size, realizing the "automatic alignment" of the channel layer and the second electrode 34, and the alignment accuracy between the channel layer and the second electrode 34 is relatively high, ensuring the stable connection between the transistor T and the capacitor C.

[0121] Compared with the method of etching a channel hole on the gate layer to form a channel layer by using a photolithography process, which requires aligning the channel hole with the second electrode, in the above preparation method of the present application, the capacitor C has a columnar capacitor structure. The columnar capacitor structure occupies a smaller area on the X-Y plane compared with the planar capacitor structure. The transistor T has a vertical transistor structure, and the vertical transistor structure occupies a smaller area on the X-Y plane compared with the planar transistor structure, which is beneficial to reducing the area occupied by the storage unit 210 on the X-Y plane. Moreover, the alignment accuracy of the channel layer of the transistor T and the second electrode 34 is relatively high, which is beneficial to increasing the number of storage units 210 arranged per unit area on the X-Y plane, improving the layout density of the storage array 21, and enabling the storage array 21 to reach a 4F2 cell size, where "F" is the minimum feature size of the chip manufacturing process (Feature Size), and the "4F2 cell size" means the square of twice the minimum feature size (4F2 = 2F × 2F).

[0122] Moreover, the process of "automatically aligning" the channel layer and the second electrode 34 does not require a photolithography process. Only two photolithography processes are used in total during the preparation of the word line WL and the bit line BL. The preparation process is relatively simple and controllable, which is beneficial to reducing the process difficulty and cost.

[0123] Another manufacturing method of the storage array is also provided in an embodiment of the present application. Figures 7A to 7D It is a structural diagram corresponding to each step of another manufacturing method of the storage array provided in the embodiment of the present application.

[0124] Figure 7A In (b), it is a cross-sectional view of (a) along the section line A-A'; in (c), it is a cross-sectional view of (a) along the section line B-B'. Figure 7B In (b), it is a cross-sectional view of (a) along the section line C-C'; in (c), it is a cross-sectional view of (a) along the section line D-D'.

[0125] Referring to Figure 7A , the manufacturing steps in the foregoing manufacturing method can be adopted to form the structure in Figures 6A to 6R , and the upper surface of the barrier layer 35 is exposed. Figure 7A Different from the manufacturing method shown in

[0126] and Figures 6A to 6S , in the manufacturing method of this embodiment, the material of the barrier layer 35 is not a material that can be used as a channel layer, but a sacrificial material. For example, the material of the barrier layer 35 may include silicon nitride. Therefore, referring to Figure 7A and Figure 7B , using the barrier layer 35 as a sacrificial layer, the barrier layer 35 is removed to form a second chamber C2, and the second chamber C2 exposes the second electrode 34 below it.

[0127] It can be understood that the material of the barrier layer 35 has a large etching selectivity ratio with the materials of the second insulating layer 38 and the third insulating layer 41. Therefore, during the etching process of the barrier layer 35, the second insulating layer 38 and the third insulating layer 41 will not be etched and damaged.

[0128] Figure 7C In (b), it is a cross-sectional view of (a) along the section line E-E'; in (c), it is a cross-sectional view of (a) along the section line F-F'.

[0129] Referring to Figure 7C , a channel layer 43 of the transistor T is formed in the second chamber C2. The channel layer 43 is connected to the second electrode 34, and the channel layer 43, the gate dielectric layer 36, and the gate layer 37 form the transistor T.

[0130] Figure 7D In (b), it is a cross-sectional view of (a) along the section line G-G'; in (c), it is a cross-sectional view of (a) along the section line H-H'.

[0131] Referring to Figure 7D , a plurality of bit lines BL are formed. Each bit line BL extends along the direction Y, and each bit line BL is connected to the channel layer 43 in the same column.

[0132] It is understandable that the film quality of the channel layer 43 affects the electrical performance of the transistor T. The better the film quality of the channel layer 43, the better the electrical performance of the transistor T.

[0133] By using the barrier layer 35 as a sacrificial layer, after forming the gate dielectric layer 36 and the gate layer 37 on the side of the barrier layer 35, the barrier layer 35 is removed to form the second chamber C2, and the channel layer 43 is formed in the second chamber C2, realizing the replacement of the barrier layer 35 with the channel layer 43, which can avoid etching damage to the channel layer 43 during the process of forming the gate dielectric layer 36 and the gate layer 37, thus facilitating the improvement of the film quality of the channel layer 43 and the electrical performance of the transistor T.

[0134] An embodiment of the present application also provides another manufacturing method of a storage array. Figures 8A to 8F For the structural diagrams corresponding to the steps of another manufacturing method of the storage array provided by the embodiment of the present application, different from Figures 6A to 6S the manufacturing method shown, this embodiment provides another manufacturing method of the word line WL.

[0135] Referring to Figure 8A , the manufacturing steps in the foregoing manufacturing method can be adopted to form Figures 6A to 6I the structure in Figure 8A . A gate dielectric thin film 360 and a gate thin film 370 are formed on the outer side of the barrier layer 35. The gate dielectric thin film 360 includes a first part a1 on the side of the barrier layer 35 away from the substrate 30 and a second part a2 on the side of the barrier layer 35. The gate thin film 370 includes a third part a3 on the side of the barrier layer 35 away from the substrate 30, a fourth part a4 on the side of the barrier layer 35, and a fifth part a5 on the surface of the first insulating layer 31, and the fifth part a5 is connected to the fourth part a4.

[0136] Referring to Figure 8B , a dielectric material is deposited over the entire surface to form a fifth insulating layer 44 covering the gate thin film 370. The fifth insulating layer 44 serves a leveling function to facilitate subsequent polishing.

[0137] Referring to Figure 8B and Figure 8C , a chemical mechanical polishing process is used to polish the upper surface of the fifth insulating layer 44, the third part a3 of the gate thin film 370, and the first part a1 of the gate dielectric thin film 360, removing the third part a3 of the gate thin film 370 and the first part a1 of the gate dielectric thin film 360 to expose the upper surface of the barrier layer 35. The fourth part a4 of the gate thin film 370 serves as the gate layer 37, and the second part a2 of the gate dielectric thin film 360 serves as the gate dielectric layer 36.

[0138] Figure 8DIn (b), it is a sectional view of (a) along the section line A-A'.

[0139] See Figure 8D , a second mask layer 45 is formed. For example, the second mask layer 45 can be a photoresist. The second mask layer 45 can be exposed and developed to form a plurality of second openings K2 on the second mask layer 45. Each second opening K2 extends in the direction X, and each second opening K2 exposes the region (the fifth insulating layer 44) between two adjacent rows of the barrier layer 35.

[0140] Figure 8E In (b), it is a sectional view of (a) along the section line B-B'; in (c), it is a sectional view of (a) along the section line C-C'.

[0141] See Figure 8D and Figure 8E , through the second opening K2 of the second mask layer 45, the fifth insulating layer 44 is etched to expose the fourth part a4 and the fifth part a5 of the gate film 370. Then, through the second opening K2 of the second mask layer 45, the fifth part a5 of the gate film 370 is etched, and a part of the fifth part a5 of the gate film 370 is removed, so that the gate film 370 is disconnected in the direction Y. The remaining part of the fifth part a5 forms a plurality of word lines WL extending in the direction X together with the fourth part a4 (the gate layer 37 on the side of the same row of the barrier layer 35). The surface P3 of the fifth part a5 far from the capacitor C is recessed in the direction V close to the capacitor C, so that the cross-sectional area of the word line WL in the Y direction is small, and the material used for preparing the word line can be saved.

[0142] Figure 8F In (b), it is a sectional view of (a) along the section line D-D'; in (c), it is a sectional view of (a) along the section line E-E'.

[0143] See Figure 8F , first, a dielectric material is deposited over the entire surface to form a sixth insulating layer 46 covering the barrier layer 35 and the gate layer 37. Then, a plurality of vias 47 are formed on the sixth insulating layer 46, and the vias 47 expose the upper surface of the barrier layer 35. Finally, a plurality of bit lines BL are formed. Each bit line BL extends in the direction Y, and each bit line BL is connected to the same column of the barrier layer 35.

[0144] The preparation method provided by the above embodiments of the present application adopts a chemical mechanical polishing process to grind the gate film 370 to form the gate layer 37, and the gate layer 37 is disconnected in the direction Y through etching to form a plurality of word lines WL, which simplifies the preparation process of the word lines WL and is beneficial to reducing the process cost.

[0145] The embodiments of the present application also provide a memory array. Figure 9A cross-sectional view of a storage array along the X-Z plane provided by an embodiment of the present application; Figure 10 A cross-sectional view of a storage array along the Y-Z plane provided by an embodiment of the present application.

[0146] Referring to Figure 9 and Figure 10 , along the direction Z, the storage array 21 includes a plurality of storage structures 211 stacked, and any one or more of the plurality of storage structures 211 can be prepared by the preparation method described above.

[0147] The storage array 21 is a three-dimensional storage array. Each storage structure 211 includes a plurality of storage cells 210 arranged in an array. Through three-dimensional stacking, it is beneficial to increase the number of storage cells 210 arranged per unit area on the X-Y plane and improve the arrangement density of the storage array 21.

[0148] Exemplarily, referring to Figure 9 , the storage array 21 further includes a word line connection structure 48, and the word line connection structure 48 penetrates through the plurality of stacked storage structures 211. Along the direction Z, multiple word lines WL in the plurality of storage structures 211 correspond to each other, and the corresponding multiple word lines WL are connected by the word line connection structure 48.

[0149] Similarly, referring to Figure 10 , the storage array 21 further includes a bit line connection structure 49, and the bit line connection structure 49 penetrates through the plurality of stacked storage structures 211. Along the direction Z, multiple bit lines BL in the plurality of storage structures 211 correspond to each other, and the corresponding multiple bit lines BL are connected by the bit line connection structure 49.

[0150] An embodiment of the present application further provides a storage array, Figure 11 A structural diagram of another storage array provided by an embodiment of the present application.

[0151] Referring to Figure 11 , the storage array 21 includes a plurality of storage cells 210 arranged in an array. The storage cell 210 can have a 1TnC (1-Transistor-n-Capacitor) structure, where n is an integer greater than 1, that is, the storage cell 210 includes one transistor T and multiple capacitors C.

[0152] Along the direction Z, the first electrodes 32 of the multiple capacitors C are stacked and spaced apart. The second electrode 34 of each capacitor C penetrates through its first electrode 32, and the second electrodes 34 of the multiple capacitors C are connected. For example, the second electrodes 34 of the multiple capacitors C are integrally provided to form a columnar electrode 50. The channel layer 43 of the transistor T is connected to the second electrodes 34 (the top of the columnar electrode 50) of the multiple capacitors C.

[0153] It can be understood that the above storage array 21 can also be prepared by the preparation method described above. On the plane X-Y, the positions and sizes of the channel layer 43 and the columnar electrode 50 are defined by the same dielectric layer 33, so that the positions and sizes of the channel layer 43 and the columnar electrode 50 are the same, realizing the "automatic alignment" of the channel layer 43 and the columnar electrode 50.

[0154] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A storage array, characterized in that, The storage array includes a plurality of storage cells arranged in an array, and the storage cells include a capacitor and a transistor; The capacitor includes a first electrode, a dielectric layer, and a second electrode. The first electrode is disposed around the second electrode, and the dielectric layer is located between the first electrode and the second electrode; The transistor is disposed on the capacitor. The transistor includes a channel layer, a gate dielectric layer, and a gate electrode layer. The gate electrode layer surrounds the side surface of the channel layer, and the gate dielectric layer is located between the channel layer and the gate electrode layer; Wherein, the channel layer is in contact with the second electrode. The channel layer includes a first surface in contact with the second electrode, and the second electrode includes a second surface in contact with the channel layer. The boundary of the first surface coincides with the boundary of the second surface.

2. The storage array according to claim 1, wherein The storage array further includes a plurality of word lines; The plurality of storage cells arranged in an array include multiple rows and multiple columns. The gate electrode layers of the multiple transistors in one row of storage cells are connected together to form one of the word lines; The word line includes a conductive connection layer located between the gate electrode layers of two adjacent transistors. The surface of the conductive connection layer away from the capacitor is recessed in a direction close to the capacitor, or the conductive connection layer fills the gap region between the gate electrode layers of two adjacent transistors.

3. The storage array according to claim 1 or 2, wherein The storage array further includes a plurality of bit lines, and the bit lines are disposed on a side of the transistor away from the capacitor; The plurality of storage cells arranged in an array include multiple rows and multiple columns. Each bit line is electrically connected to the channel layers of multiple transistors in one column of storage cells.

4. The storage array according to any one of claims 1 to 3, characterized in that The storage array further includes a plate line, and the plate line is disposed on a side of the capacitor away from the transistor; The first electrodes of the multiple capacitors in the multiple storage cells are electrically connected to the plate line.

5. The storage array according to any one of claims 1 to 4, characterized in that, The storage cell includes a plurality of the capacitors and one transistor; Along the direction from the capacitor to the transistor, the first electrodes of the plurality of capacitors are stacked and spaced apart, and the second electrodes of the plurality of capacitors are connected together to form a columnar electrode; The channel layer of the transistor is connected to one end of the columnar electrode.

6. The storage array according to any one of claims 1 to 5, characterized in that Along the direction from the capacitor to the transistor, the storage array includes a plurality of storage structures stacked. Each storage structure includes a plurality of the storage cells arranged in an array.

7. The storage array according to any one of claims 1 to 6, characterized in that, The material of the dielectric layer includes a ferroelectric material.

8. A method for preparing a storage array, characterized in that, Including: Forming an insulating layer having a plurality of vias on a substrate, and the plurality of vias are arranged in an array; Forming a first electrode, a dielectric layer, and a second electrode in the via. The first electrode is located on the surface of the via, the dielectric layer is located inside the first electrode, and the second electrode is located inside the dielectric layer; Relative to the substrate, the surface of the second electrode away from the substrate is lower than the surface of the insulating layer away from the substrate; Forming a barrier layer in the via. The barrier layer is located inside the dielectric layer and on a side of the second electrode away from the substrate; Remove the part of the insulating layer outside the barrier layer, remove the part of the first electrode outside the barrier layer, and remove the part of the dielectric layer outside the barrier layer to expose the barrier layer; Form a gate dielectric layer and a gate layer on the side surface of the barrier layer.

9. The preparation method according to claim 8, wherein Form a first electrode, a dielectric layer, and a second electrode in the via, including: Form the first electrode on the surface of the via; Form the dielectric layer inside the first electrode; Deposit a conductive material to form a filling layer inside the dielectric layer; Remove the part of the filling layer away from the substrate to form a first chamber in the via, and the remaining part of the filling layer forms the second electrode; Form a barrier layer in the via, including: Form the barrier layer in the first chamber.

10. The preparation method according to claim 8 or 9, characterized in that, Form a gate dielectric layer and a gate layer on the side surface of the barrier layer, including: Form a gate dielectric thin film and a gate thin film on the outside of the barrier layer. The gate dielectric thin film at least includes a first part on the side of the barrier layer away from the substrate and a second part on the side surface of the barrier layer; the gate thin film at least includes a third part on the side of the barrier layer away from the substrate and a fourth part on the side surface of the barrier layer; Remove the third part of the gate thin film and remove the first part of the gate dielectric thin film to expose the surface of the barrier layer away from the substrate; Wherein, the second part serves as the gate dielectric layer, and the fourth part serves as the gate layer.

11. The preparation method according to claim 10, wherein The multiple vias include multiple rows and multiple columns, and the multiple barrier layers in the multiple vias include multiple rows and multiple columns; After forming a gate dielectric layer and a gate layer on the side surface of the barrier layer, the manufacturing method further includes: Form a first mask layer, the first mask layer having a plurality of first openings, each first opening exposing the gate layer on the side surface of a row of barrier layers; Deposit a conductive material, and through the first opening, form a conductive connection layer between the multiple barrier layers in the same row. The conductive connection layer is connected to the gate layer on the side surface of the multiple barrier layers to form a word line.

12. The preparation method according to claim 10, wherein The multiple vias include multiple rows and multiple columns, and the multiple barrier layers in the multiple vias include multiple rows and multiple columns; The gate thin film further includes a fifth part on the surface of the insulating layer, and the fifth part is connected to the gate layers on the side surfaces of the multiple barrier layers; After forming a gate dielectric layer and a gate layer on the side surface of the barrier layer, the manufacturing method further includes: Form a second mask layer, the second mask layer having a plurality of second openings, each second opening exposing the area between two adjacent rows of barrier layers; Through the second opening, remove a part of the fifth part of the gate thin film, and the remaining part of the fifth part and the gate layers on the side surfaces of the barrier layers in the same row together form a word line.

13. The preparation method according to any one of claims 8 to 12, characterized in that, The barrier layer serves as the channel layer of the transistor, and the transistor includes the barrier layer, the gate dielectric layer, and the gate layer.

14. The preparation method according to any one of claims 8 to 12, characterized in that, The barrier layer serves as a sacrificial layer. After forming a gate dielectric layer and a gate layer on the side surface of the barrier layer, the manufacturing method further includes: Remove the barrier layer to form a second chamber; A channel layer of a transistor is formed in the second chamber. The transistor includes the channel layer, the gate dielectric layer, and the gate layer.

15. A memory, characterized in that, Comprising: The memory array according to any one of claims 1 to 7; A controller, the memory array being electrically connected to the controller.

16. An electronic device, characterized in that, Comprising: The memory according to claim 15; A circuit board, the memory being electrically connected to the circuit board.

Images