Semiconductor device and forming method thereof

Abstract

The invention relates to a semiconductor device and a forming method thereof. A semiconductor device includes an N-well between a first P-well and a second P-well. An N-type active region including a first N-type active region and a second N-type active region is disposed in the N well. The shortest distance between the boundary of the second P well and the N well and the second N-type active region is larger than the shortest distance between the boundary of the first P well and the N well and the first N-type active region. A first P-gate dielectric layer including a first modulation layer is disposed on the first N-type active region. The first modulation layer includes a first intermediate modulation layer between the lower modulation layer and the upper modulation layer. A second P gate dielectric layer including a second modulation layer is disposed on the second N-type active region. The second modulation layer includes a second intermediate modulation layer between the lower modulation layer and the upper modulation layer. The first intermediate modulation layer is thicker than the second intermediate modulation layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0010088, filed on January 23, 2024, which is incorporated herein by reference in its entirety. Technical field

[0003] Various embodiments of the present disclosure generally relate to a semiconductor device including a sub - word line driver and a method of forming the same. Background art

[0004] Semiconductor devices include transistors configured in a memory cell array and peripheral circuits. With the high integration of semiconductor devices, the size and pitch of transistors are gradually reduced. Reducing the size and pitch of transistors causes various problems in the manufacturing process, such as well proximity effect (WPE). Therefore, the dispersion of the electrical characteristics of transistors may increase. Summary of the invention

[0005] Multiple embodiments of the present disclosure aim to provide a semiconductor device and a method of forming the same that reduce the dispersion of electrical characteristics and facilitate high integration.

[0006] In some embodiments of the present disclosure, a semiconductor device may include a first P - well, a second P - well in a substrate, and an N - well located between the first P - well and the second P - well. A plurality of N - type active regions defined within the N - well may be provided. The plurality of N - type active regions may include a first N - type active region adjacent to the first P - well and a second N - type active region adjacent to the second P - well. The shortest distance between the boundary of the second P - well and the N - well and the second N - type active region may be greater than the shortest distance between the boundary of the first P - well and the N - well and the first N - type active region. A first P - gate dielectric layer may be provided, the first P - gate dielectric layer being disposed on the first N - type active region and including a first modulation layer. The first modulation layer may include a first intermediate modulation layer located between a lower modulation layer and an upper modulation layer. A second P - gate dielectric layer may be provided, the second P - gate dielectric layer being disposed on the second N - type active region and including a second modulation layer. The second modulation layer may include a second intermediate modulation layer located between a lower modulation layer and an upper modulation layer. The first intermediate modulation layer may be thicker than the second intermediate modulation layer. A first P - gate electrode may be disposed on the first P - gate dielectric layer. A second P - gate electrode may be disposed on the second P - gate dielectric layer.

[0007] In some embodiments of the present disclosure, a semiconductor device may include a first P-well, a second P-well, and an N-well in a substrate. The N-well includes a first N-well and a second N-well located between the first P-well and the second P-well. The first N-well may be adjacent to the first P-well, and the second N-well may be adjacent to the second P-well. A plurality of N-type active regions defined within the first N-well may be provided. The plurality of N-type active regions may include a first N-type active region adjacent to the first P-well and a second N-type active region adjacent to the second N-well. The shortest distance between the boundary of the first P-well and the first N-well and the first N-type active region may be substantially the same as the shortest distance between the boundary of the first N-well and the second N-well and the second N-type active region. A first P-gate dielectric layer provided on the first N-type active region and including a first modulation layer may be provided. A second P-gate dielectric layer provided on the second N-type active region and including a second modulation layer may be provided. The first modulation layer may be thicker than the second modulation layer. A first P-gate electrode including a first P-work function metal layer on the first P-gate dielectric layer may be provided. A second P-gate electrode including a second P-work function metal layer on the second P-gate dielectric layer may be provided. The first P-work function metal layer may be thicker than the second P-work function metal layer.

[0008] In some embodiments of the present disclosure, a semiconductor device may include a first P-well, a second P-well, and an N-well in a substrate, where the N-well is located between the first P-well and the second P-well. A plurality of N-type active regions defined within the N-well may be provided. The plurality of N-type active regions may include a first N-type active region adjacent to the first P-well and a second N-type active region adjacent to the second P-well. The shortest distance between the boundary of the second P-well and the N-well and the second N-type active region may be greater than the shortest distance between the boundary of the first P-well and the N-well and the first N-type active region. A first P-gate electrode including a first P-work function metal layer on the first N-type active region may be provided. A second P-gate electrode including a second P-work function metal layer on the second N-type active region may be provided. The first P-work function metal layer may be thicker than the second P-work function metal layer. A P-gate dielectric layer may be provided between the first N-type active region and the first P-gate electrode and between the second N-type active region and the second P-gate electrode.

[0009] In some embodiments of the present disclosure, a semiconductor device may include a first P-well, a second P-well in a substrate, and an N-well located between the first P-well and the second P-well, where the N-well includes a first N-well and a second N-well. The first N-well may be adjacent to the first P-well, and the second N-well may be adjacent to the second P-well. A plurality of N-type active regions defined within the first N-well may be provided. The plurality of N-type active regions may include a first N-type active region adjacent to the first P-well and a second N-type active region adjacent to the second N-well. The shortest distance between the boundary of the first P-well and the first N-well and the first N-type active region may be substantially the same as the shortest distance between the boundary of the first N-well and the second N-well and the second N-type active region. A P-gate dielectric layer may be provided on the first N-type active region and the second N-type active region. A P-gate electrode may be provided on the P-gate dielectric layer.

[0010] In some embodiments of the present disclosure, a semiconductor device may include a first P-well, a second P-well in a substrate, and an N-well located between the first P-well and the second P-well, where the N-well includes a first N-well and a second N-well. The first N-well may be adjacent to the first P-well, and the second N-well may be adjacent to the second P-well. A plurality of N-type active regions defined within the N-well may be provided. The plurality of N-type active regions may include: a first N-type active region that is adjacent to the first P-well and is defined within the first N-well; and a second N-type active region that is adjacent to the second P-well and is defined within the second N-well. The shortest distance between the boundary of the second P-well and the second N-well and the second N-type active region may be greater than the shortest distance between the boundary of the first P-well and the first N-well and the first N-type active region. A P-gate dielectric layer may be provided on the first N-type active region and the second N-type active region. A P-gate electrode may be provided on the P-gate dielectric layer.

[0011] In some embodiments of the present disclosure, a semiconductor device may include a first P-well, a second P-well in a substrate, and an N-well located between the first P-well and the second P-well, where the N-well includes a first N-well and a second N-well. The first N-well may be adjacent to the first P-well, and the second N-well may be adjacent to the second P-well. A plurality of N-type active regions defined within the N-well may be provided. The plurality of N-type active regions may include: a first N-type active region adjacent to the first P-well and defined within the first N-well, and a second N-type active region adjacent to the second P-well and defined within the second N-well. The shortest distance between the boundary of the second P-well and the second N-well and the second N-type active region may be greater than the shortest distance between the boundary of the first P-well and the first N-well and the first N-type active region. A first P-gate dielectric layer may be provided, which is disposed on the first N-type active region and includes a first modulation layer. A second P-gate dielectric layer may be provided, which is disposed on the second N-type active region and includes a second modulation layer. The first modulation layer may be thicker than the second modulation layer. A first P-gate electrode may be provided, which includes a first P-work function metal layer on the first P-gate dielectric layer. A second P-gate electrode may be provided, which includes a second P-work function metal layer on the second P-gate dielectric layer. The first P-work function metal layer may be thicker than the second P-work function metal layer.

[0012] According to the embodiments of the present disclosure, a semiconductor device that reduces the dispersion of transistor electrical characteristics and is conducive to high integration can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a cross-sectional view for describing a semiconductor device based on some embodiments of the present disclosure.

[0014] Figure 2 is a layout view for describing a semiconductor device based on some embodiments of the present disclosure.

[0015] Figures 3 to 17 is a cross-sectional view for describing a semiconductor device based on some embodiments of the present disclosure.

[0016] Figure 18 and Figure 19 is a flowchart for describing a method of forming a semiconductor device based on some embodiments of the present disclosure.

[0017] Figures 20 to 30 is a cross-sectional view for describing a method of forming a semiconductor device based on some embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] Figure 1 is a cross-sectional view for describing a semiconductor device, Figure 2 is a layout view based on some embodiments of the present disclosure. Figures 3 to 17is a cross-sectional view for describing a semiconductor device according to an embodiment of the present disclosure. Figure 1 and Figures 3 to 14 is a cross-sectional view taken along line I-I' of Figure 2 , Figure 15 is a cross-sectional view taken along line II-II' of Figure 2 , Figure 16 is a cross-sectional view taken along line III-III' of Figure 2 , Figure 17 is a cross-sectional view taken along line IV-IV' of Figure 2 .

[0019] Referring to Figure 1 , a semiconductor device according to some embodiments of the present disclosure may include a substrate 21, an N-well 25, a first P-well 27, a second P-well 28, active regions 31, 32, 33, 34, 41, 42, and 48, isolation patterns 51, 52, 53, and 54, gate dielectric layers 69, 69A, and 79, and gate electrodes 85, 85A, and 95. The substrate 21 may include a cell region CA (see Figure 2 ), a boundary region BR, a P-type sub-word line driving region SWDP, and an N-type sub-word line driving region SWDN. The N-well 25 may include a first N-well 25A and a second N-well 25B.

[0020] The active regions 31, 32, 33, 34, 41, 42, and 48 may include N-type active regions 31, 32, 33, and 34, P-type active regions 41 and 42, and a dummy active region 48. The N-type active regions 31, 32, 33, and 34 include a first N-type active region 31, a second N-type active region 32, a third N-type active region 33, and a fourth N-type active region 34. The P-type active regions 41 and 42 may include a first P-type active region 41 and a second P-type active region 42. For ease of description, the first N-type active region 31 to the fourth N-type active region 34 are assigned serial numbers in this order, and may be assigned different serial numbers in some embodiments. For example, in some embodiments, the fourth N-type active region 34 may be referred to as the second N-type active region, the second N-type active region 32 may be referred to as the third N-type active region, and the third N-type active region 33 may be referred to as the fourth N-type active region.

[0021] The N-type active regions 31, 32, 33, 34 may be disposed in the P-type sub-word line driving region SWDP, the P-type active regions 41, 42 may be disposed in the N-type sub-word line driving region SWDN, and the dummy active region 48 may be disposed in the boundary region BR. The isolation patterns 51, 52, 53, and 54 may include a first isolation pattern 51, a second isolation pattern 52, a third isolation pattern 53, and a fourth isolation pattern 54.

[0022] The gate dielectric layers 69, 69A, and 79 may include a first P gate dielectric layer 69A, a second P gate dielectric layer 69, and an N gate dielectric layer 79. The first P gate dielectric layer 69A may include a P interface layer 61, a P dielectric layer 62, a first modulation layer 67A, and a P capping layer 68 stacked in sequence. The first modulation layer 67A may include a lower modulation layer 63, a first intermediate modulation layer 64A, and an upper modulation layer 65 stacked in sequence. The second P gate dielectric layer 69 may include a P interface layer 61, a P dielectric layer 62, a second modulation layer 67, and a P capping layer 68 stacked in sequence. The second modulation layer 67 may include a lower modulation layer 63, a second intermediate modulation layer 64, and an upper modulation layer 65 stacked in sequence. The N gate dielectric layer 79 may include an N interface layer 71, an N dielectric layer 72, and an N capping layer 78 stacked in sequence.

[0023] In Figure 1 embodiments, the gate electrodes 85, 85A, and 95 may include a first P gate electrode 85A, a second P gate electrode 85, and an N gate electrode 95. The first P gate electrode 85A may include a first P work function metal layer 82A and a P gate conductive layer 84 stacked in sequence. The second P gate electrode 85 may include a second P work function metal layer 82 and a P gate conductive layer 84 stacked in sequence. The N gate electrode 95 may include an N work function metal layer 92 and an N gate conductive layer 94 stacked in sequence on top of the N gate dielectric layer 79. The N work function metal layer 92 may be located on the N capping layer 78 of the N gate dielectric layer 79.

[0024] In some embodiments, the P interface layer 61 and the N interface layer 71 may include an insulating material such as silicon oxide, silicon oxynitride, or a combination thereof. The P dielectric layer 62 and the N dielectric layer 72 may include HfSiON, HfO2, HfON, SiON, ZrSiO4, Y2O3, Ta2O5, BaO, HfSiO, MgO, Al2O3, Si3N4, CaO, LaLuO2, or a combination thereof. The lower modulation layer 63 may include TiN, TiCN, TaN, WN, TiAl, MoN, or a combination thereof. The first intermediate modulation layer 64A and the second intermediate modulation layer 64 may include Al2O3, HfO2, or a combination thereof. The upper modulation layer 65 may include TiN, TiCN, TaN, WN, TiAl, MoN, or a combination thereof. The P capping layer 68 and the N capping layer 78 may include LaO, La2O3, Y2O3, ScO2, or a combination thereof. The first P work function metal layer 82A, the second P work function metal layer 82, and the N work function metal layer 92 may include TiN, TiCN, TaN, WN, TiAl, MoN, or a combination thereof. The P gate conductive layer 84 and the N gate conductive layer 94 may include doped polysilicon, SiGe, SiC, Si, or a combination thereof.

[0025] See Figure 2, a semiconductor device according to some embodiments of the present disclosure may include a cell region CA, a boundary region BR, and sub - word line driving regions SWDP and SWDN. The boundary region BR may be continuous with one side of the cell region CA. The boundary region BR may be disposed between the cell region CA and the sub - word line driving regions SWDP and SWDN. The sub - word line driving regions SWDP and SWDN may include a P - type sub - word line driving region SWDP and an N - type sub - word line driving region SWDN. The P - type sub - word line driving region SWDP may be disposed between the boundary region BR and the N - type sub - word line driving region SWDN.

[0026] Memory cells MC may be disposed in the cell region CA. dummy memory cells DMC and a dummy active region 48 may be disposed in the boundary region BR. P - type transistors pTr1, pTr2, pTr3, and pTr4 may be disposed in the P - type sub - word line driving region SWDP, and N - type transistors nTr1, nTr2, nTr3, and nTr4 may be disposed in the N - type sub - word line driving region SWDN.

[0027] The P - type transistors pTr1, pTr2, pTr3, and pTr4 may include a first P - type transistor pTr1, a second P - type transistor pTr2, a third P - type transistor pTr3, and a fourth P - type transistor pTr4. The first P - type transistor pTr1 may be disposed adjacent to the boundary between the P - type sub - word line driving region SWDP and the N - type sub - word line driving region SWDN. The fourth P - type transistor pTr4 may be disposed at a position relatively far from the boundary between the P - type sub - word line driving region SWDP and the N - type sub - word line driving region SWDN. The fourth P - type transistor pTr4 may be disposed at a position relatively close to the boundary between the P - type sub - word line driving region SWDP and the boundary region BR. The second P - type transistor pTr2 may be disposed between the first P - type transistor pTr1 and the fourth P - type transistor pTr4. The third P - type transistor pTr3 may be disposed between the second P - type transistor pTr2 and the fourth P - type transistor pTr4. The gaps between the P - type transistors pTr1, pTr2, pTr3, and pTr4 may be substantially the same.

[0028] For ease of description, the first P - type transistor pTr1 to the fourth P - type transistor pTr4 are assigned serial numbers in this order, and in some embodiments, different serial numbers may be assigned. In some embodiments, the fourth P - type transistor pTr4 may be referred to as the second P - type transistor, the second P - type transistor pTr2 may be referred to as the third P - type transistor, and the third P - type transistor pTr3 may be referred to as the fourth P - type transistor.

[0029] The N-type transistors nTr1, nTr2, nTr3, and nTr4 may include a first N-type transistor nTr1, a second N-type transistor nTr2, a third N-type transistor nTr3, and a fourth N-type transistor nTr4. The first N-type transistor nTr1 may be disposed adjacent to the boundary between the P-type sub-word line driving region SWDP and the N-type sub-word line driving region SWDN. The fourth N-type transistor nTr4 may be disposed at a position relatively far from the boundary between the P-type sub-word line driving region SWDP and the N-type sub-word line driving region SWDN. The second N-type transistor nTr2 may be disposed between the first N-type transistor nTr1 and the fourth N-type transistor nTr4. The third N-type transistor nTr3 may be disposed between the second N-type transistor nTr2 and the fourth N-type transistor nTr4. The gaps between the N-type transistors nTr1, nTr2, nTr3, and nTr4 may be substantially the same.

[0030] The P-type transistors pTr1, pTr2, pTr3, and pTr4 may include respective N-type active regions 31, 32, 33, and 34 and P gate electrodes 85 and 85A. The N-type transistors nTr1, nTr2, nTr3, and nTr4 may include respective P-type active regions 41, 42, 43, and 44 and N gate electrodes 95. The P-type active regions 41, 42, 43, and 44 may include a first P-type active region 41, a second P-type active region 42, a third P-type active region 43, and a fourth P-type active region 44.

[0031] The memory cell MC may include a volatile memory, a non-volatile memory, or a combination thereof. The memory cell MC may include a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, a magnetoresistive random access memory (MRAM), a phase change random access memory (PRAM), a ferroelectric random access memory (FRAM), a resistive random access memory (RRAM), or a combination thereof.

[0032] Reference Figure 1 and Figure 2 , in the substrate 21, the N-well 25 may be disposed in the P-type sub-word line driving region SWDP, the first P-well 27 may be disposed in the N-type sub-word line driving region SWDN, and the second P-well 28 may be disposed in the cell region CA and the boundary region BR. The N-type active regions 31, 32, 33, and 34 may be disposed in the first N-well 25A, the P-type active regions 41, 42, 43, and 44 may be disposed in the first P-well 27, and the dummy active region 48 may be disposed in the second P-well 28. Regarding the configuration of the first N-well 25A and the second N-well 25B, it will be described later with reference to Figure 4 for description.

[0033] The first N-type active region 31 can be set adjacent to the boundary between the P-type sub-word line driving region SWDP and the N-type sub-word line driving region SWDN. The first N-type active region 31 can be set adjacent to the boundary between the first N-well 25A and the first P-well 27. The fourth N-type active region 34 can be set relatively far from the boundary between the P-type sub-word line driving region SWDP and the N-type sub-word line driving region SWDN. The fourth N-type active region 34 can be set relatively close to the boundary between the P-type sub-word line driving region SWDP and the boundary region BR. The fourth N-type active region 34 can be set adjacent to the boundary between the first N-well 25A and the second N-well 25B. The shortest distance between the fourth N-type active region 34 and the boundary between the first N-well 25A and the second N-well 25B can be substantially the same as the shortest distance between the first N-type active region 31 and the boundary between the first N-well 25A and the first P-well 27. The second N-type active region 32 can be set between the first N-type active region 31 and the fourth N-type active region 34. The third N-type active region 33 can be set between the second N-type active region 32 and the fourth N-type active region 34.

[0034] The first P-type active region 41 can be set adjacent to the boundary between the P-type sub-word line driving region SWDP and the N-type sub-word line driving region SWDN. The first P-type active region 41 can be set adjacent to the boundary between the first N-well 25A and the first P-well 27. The fourth P-type active region 44 can be set relatively far from the boundary between the P-type sub-word line driving region SWDP and the N-type sub-word line driving region SWDN. The second P-type active region 42 can be set between the first P-type active region 41 and the fourth P-type active region 44. The third P-type active region 43 can be set between the second P-type active region 42 and the fourth P-type active region 44. The first P-type active region 41 can be set between the second P-type active region 42 and the first N-type active region 31.

[0035] The first isolation pattern 51 can be set in the P-type sub-word line driving region SWDP. The first isolation pattern 51 can be set between the N-type active regions 31, 32, 33, and 34. The N-type active regions 31, 32, 33, and 34 can have similar sizes and shapes. The horizontal widths of the respective N-type active regions 31, 32, 33, and 34 can be substantially the same. The gaps between the N-type active regions 31, 32, 33, and 34 can be substantially the same. The respective first isolation patterns 51 can have substantially the same horizontal width.

[0036] The second isolation pattern 52 can be set adjacent to the boundary between the P-type sub-word line driving region SWDP and the N-type sub-word line driving region SWDN. The second isolation pattern 52 can be disposed between the first N-type active region 31 and the first P-type active region 41. The boundary between the first N-well 25A and the first P-well 27 can be aligned with or located below the second isolation pattern 52. The gap between the first N-type active region 31 and the first P-type active region 41 can be greater than the gap between the first N-type active region 31 and the second N-type active region 32. The horizontal width of the second isolation pattern 52 can be greater than the horizontal width of each of the first isolation patterns 51.

[0037] The third isolation pattern 53 can be set adjacent to the boundary between the P-type sub-word line driving region SWDP and the boundary region BR. The third isolation pattern 53 can be disposed between the fourth N-type active region 34 and the dummy active region 48. The second N-well 25B can be defined below the third isolation pattern 53. The boundary between the second N-well 25B and the second P-well 28 can be aligned with or located below the third isolation pattern 53. The gap between the fourth N-type active region 34 and the dummy active region 48 can be greater than the gap between the first N-type active region 31 and the first P-type active region 41. The horizontal width of the third isolation pattern 53 can be greater than the horizontal width of the second isolation pattern 52.

[0038] The fourth isolation pattern 54 can be formed in the N-type sub-word line driving region SWDN. The P-type active regions 41, 42, 43, and 44 can have similar sizes and shapes. The horizontal widths of the P-type active regions 41, 42, 43, and 44 can be substantially the same. The gaps between the P-type active regions 41, 42, 43, and 44 can be substantially the same. The fourth isolation pattern 54 can be formed between the P-type active regions 41, 42, 43, and 44 (only 41 and 42 are shown for avoiding drawing congestion). The gaps between the P-type active regions 41, 42, 43, and 44 can be smaller than the gap between the first N-type active region 31 and the first P-type active region 41. The horizontal width of each of the fourth isolation patterns 54 can be smaller than the horizontal width of the second isolation pattern 52.

[0039] The first P gate dielectric layer 69A and the first P gate electrode 85A can be sequentially stacked on the first N-type active region 31 or stacked on the first N-type active region 31 as shown in the figure. The second P gate dielectric layer 69 and the second P gate electrode 85 can be sequentially stacked on each of the second to fourth N-type active regions 32, 33, and 34 or stacked on each of the second to fourth N-type active regions 32, 33, and 34 as shown in the figure. The N gate dielectric layer 79 and the N gate electrode 95 can be sequentially stacked on each of the P-type active regions 41, 42, 43, and 44, or stacked on each of the P-type active regions 41, 42, 43, and 44 as shown in the figure (only 41 and 42 are shown for avoiding drawing congestion).

[0040] The first intermediate modulation layer 64A in the first P gate dielectric layer 69A may be thicker than the second intermediate modulation layer 64 in the second P gate dielectric layer 69. Regarding the configurations of the first intermediate modulation layer 64A and the second intermediate modulation layer 64, further description will be made below with reference to Figure 3 As Figure 1 shown in the embodiment of Figure 8 the first P work function metal layer 82A in the first P gate electrode 85A may be thicker than the second P work function metal layer 82 in the second P gate electrode 85. Regarding the configurations of the first P work function metal layer 82A and the second P work function metal layer 82, further description will be made later with reference to

[0041] Reference Figure 3 , the boundary between the N well 25 and the first P well 27 may be aligned with or located below the second isolation pattern 52. The boundary between the N well 25 and the second P well 28 may be aligned with or located below the third isolation pattern 53. The shortest distance between the boundary of the N well 25 and the first P well 27 and the first N-type active region 31 may be less than the shortest distance between the boundary of the N well 25 and the second P well 28 and the fourth N-type active region 34.

[0042] The first P gate dielectric layer 69A and the second P gate electrode 85 may be sequentially stacked on the first N-type active region 31 or stacked on the first N-type active region 31 as shown. The second P gate dielectric layer 69 and the second P gate electrode 85 may be sequentially stacked on each of the second to fourth N-type active regions 32, 33, and 34 or stacked on each of the second to fourth N-type active regions 32, 33, and 34 as shown. The N gate dielectric layer 79 and the N gate electrode 95 may be sequentially stacked on each P-type active region (such as 41, 42, 43, and 44) or stacked on each P-type active region (such as 41, 42, 43, and 44) as shown. It should be noted that Figure 3 only two P-type active regions are shown in Figure 2 but all four P-type active regions may be shown in

[0043] The first P gate dielectric layer 69A may include a P interface layer 61, a P dielectric layer 62, a first modulation layer 67A, and a P capping layer 68 stacked in sequence. The first modulation layer 67A may include a lower modulation layer 63, a first intermediate modulation layer 64A, and an upper modulation layer 65 stacked in sequence. The second P gate dielectric layer 69 may include a P interface layer 61, a P dielectric layer 62, a second modulation layer 67, and a P capping layer 68 stacked in sequence. The second modulation layer 67 may include a lower modulation layer 63, a second intermediate modulation layer 64, and an upper modulation layer 65 stacked in sequence. The N gate dielectric layer 79 may include an N interface layer 71, an N dielectric layer 72, and an N capping layer 78 stacked in sequence.

[0044] In an embodiment, the first modulation layer 67A and the second modulation layer 67 may include a dipole structure. The first intermediate modulation layer 64A and the second intermediate modulation layer 64 may include Al2O3. The lower modulation layer 63 and the upper modulation layer 65 may include TiN. The first intermediate modulation layer 64A may be thicker than the second intermediate modulation layer 64. The first modulation layer 67A may be thicker than the second modulation layer 67. The first P-gate dielectric layer 69A may be thicker than the second P-gate dielectric layer 69.

[0045] Due to the well proximity effect (WPE), the N-type impurity concentration of the first N-type active region 31 may be higher than the N-type impurity concentrations of the second to fourth N-type active regions 32, 33, and 34. By modulating the thickness of the first intermediate modulation layer 64A, the threshold voltage of the first P-type transistor pTr1 can be controlled. By modulating the thickness of the first intermediate modulation layer 64A, the threshold voltage of the first P-type transistor pTr1 can be controlled to be similar to the threshold voltages of the second to fourth P-type transistors pTr2, pTr3, and pTr4. By modulating the thickness of the first intermediate modulation layer 64A, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0046] The second P-gate electrode 85 may include a second P-work function metal layer 82 and a P-gate conductive layer 84 stacked in sequence. The N-gate electrode 95 may include an N-work function metal layer 92 and an N-gate conductive layer 94. Refer to Figure 4 , the N-well 25 may include a first N-well 25A and a second N-well 25B. The first N-well 25A and the second N-well 25B may be formed using different ion implantation masks and / or the first N-well 25A and the second N-well 25B may be formed using different ion implantation processes. The boundary between the first N-well 25A and the second N-well 25B may be aligned with or located below the third isolation pattern 53. The second N-well 25B may be defined below the third isolation pattern 53. The second N-well 25B may be entirely located below the third isolation pattern 53.

[0047] The second P-gate dielectric layer 69 and the second P-gate electrode 85 may be stacked in sequence on each of the N-type active regions 31, 32, 33, and 34 or stacked on each of the N-type active regions 31, 32, 33, and 34 as shown. The N-gate dielectric layer 79 and the N-gate electrode 95 may be stacked in sequence on each of the P-type active regions 41, 42, 43, and 44 or stacked on each of the P-type active regions 41, 42, 43, and 44 as shown. In Figure 4 only two of the four P-type active regions are shown.

[0048] The shortest distance between the boundary of the first N-well 25A and the second N-well 25B and the fourth N-type active region 34 can be substantially the same as the shortest distance between the boundary of the first N-well 25A and the first P-well 27 and the first N-type active region 31. Due to the reduction of the well proximity effect (WPE), the N-type impurity concentrations of the N-type active regions 31, 32, 33, and 34 can be controlled similarly. Therefore, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0049] Reference Figure 5 , the N-well 25 may include a third N-well 25C and a fourth N-well 25D. The third N-well 25C and the fourth N-well 25D may be formed using different ion implantation masks. The third N-well 25C and the fourth N-well 25D may be formed using different ion implantation processes. The first N-type active region 31 may be defined within the third N-well 25C, while the second to fourth N-type active regions 32, 33, and 34 may be defined within the fourth N-well 25D. The boundary between the third N-well 25C and the fourth N-well 25D may be aligned between the first N-type active region 31 and the second N-type active region 32. The boundary between the third N-well 25C and the first P-well 27 may be aligned with or located below the second isolation pattern 52. The boundary between the fourth N-well 25D and the second P-well 28 may be aligned with or located below the third isolation pattern 53.

[0050] By using different ion implantation masks and different ion implantation processes, the dispersion of the N-type impurity concentrations of the N-type active regions 31, 32, 33, and 34 (i.e., the non-uniformity of the N-type impurity concentrations) can be reduced. According to this configuration, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0051] Reference Figure 6, the N-well 25 may include a first N-well 25A and a second N-well 25B. The dispersion of the N-type impurity concentration (i.e., the non-uniformity of the N-type impurity concentration) in the N-type active regions 31, 32, 33, and 34 can be reduced. The first P-gate dielectric layer 69A and the second P-gate electrode 85 may be sequentially stacked on the first N-type active region 31 or stacked on the first N-type active region 31 as shown in the figure. The second P-gate dielectric layer 69 and the second P-gate electrode 85 may be sequentially stacked on each of the second to fourth N-type active regions 32, 33, and 34 or stacked on each of the second to fourth N-type active regions 32, 33, and 34 as shown in the figure. The first intermediate modulation layer 64A in the first P-gate dielectric layer 69A may be thicker than the second intermediate modulation layer 64 in the second P-gate dielectric layer 69. The threshold voltage of the first P-type transistor pTr1 can be controlled to be similar to the threshold voltages of the second to fourth P-type transistors pTr2, pTr3, and pTr4. According to this configuration, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0052] Reference Figure 7 , the N-well 25 may include a third N-well 25C and a fourth N-well 25D. The dispersion of the N-type impurity concentration (i.e., the non-uniformity of the N-type impurity concentration) in the N-type active regions 31, 32, 33, and 34 can be reduced. The first P-gate dielectric layer 69A and the second P-gate electrode 85 may be sequentially stacked on the first N-type active region 31 or stacked on the first N-type active region 31 as shown in the figure. The second P-gate dielectric layer 69 and the second P-gate electrode 85 may be sequentially stacked on each of the second to fourth N-type active regions 32, 33, and 34 or stacked on each of the second to fourth N-type active regions 32, 33, and 34 as shown in the figure. The threshold voltage of the first P-type transistor pTr1 can be controlled to be similar to the threshold voltages of the second to fourth P-type transistors pTr2, pTr3, and pTr4. According to this configuration, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0053] Reference Figure 8 , the second P-gate dielectric layer 69 and the first P-gate electrode 85A may be sequentially stacked on the first N-type active region 31 or stacked on the first N-type active region 31 as shown in the figure. The second P-gate dielectric layer 69 and the second P-gate electrode 85 may be sequentially stacked on each of the second to fourth N-type active regions 32, 33, and 34 or stacked on each of the second to fourth N-type active regions 32, 33, and 34 as shown in the figure. The N-gate dielectric layer 79 and the N-gate electrode 95 may be sequentially stacked on each of the P-type active regions 41, 42, 43, and 44 or stacked on each of the P-type active regions 41, 42, 43, and 44 as shown in the figure (only 41 and 42 are shown to avoid overcrowding the figure).

[0054] The second P gate dielectric layer 69 may include a sequentially stacked P interface layer 61 and a P dielectric layer 62. The N gate dielectric layer 79 may include an N interface layer 71, an N dielectric layer 72, and an N capping layer 78, and the N interface layer 71, the N dielectric layer 72, and the N capping layer 78 are sequentially stacked on each of the P-type active regions 41, 42, 43, and 44 or are stacked on each of the P-type active regions 41, 42, 43, and 44 as shown in the figure.

[0055] The first P gate electrode 85A may include a first P work function metal layer 82A and a P gate conductive layer 84. The second P gate electrode 85 may include a second P work function metal layer 82 and a P gate conductive layer 84. The N gate electrode 95 may include an N work function metal layer 92 and an N gate conductive layer 94.

[0056] In some embodiments, the first P work function metal layer 82A, the second P work function metal layer 82, and the N work function metal layer 92 may include TiN. The first P work function metal layer 82A may be thicker than the second P work function metal layer 82.

[0057] The N-type impurity concentration of the first N-type active region 31 may be higher than the N-type impurity concentrations of the second to fourth N-type active regions 32, 33, and 34. By modulating the thickness of the first P work function metal layer 82A, the threshold voltage of the first P-type transistor pTr1 can be controlled. By modulating the thickness of the first P work function metal layer 82A, the threshold voltage of the first P-type transistor pTr1 can be controlled to be similar to the threshold voltages of the second to fourth P-type transistors pTr2, pTr3, and pTr4. By modulating the thickness of the first P work function metal layer 82A, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0058] Reference Figure 9 , the N well 25 may include a first N well 25A and a second N well 25B. The dispersion (i.e., the non-uniformity of the N-type impurity concentration) of the N-type impurity concentrations of the N-type active regions 31, 32, 33, and 34 can be reduced. The second P gate dielectric layer 69 and the second P gate electrode 85 may be stacked sequentially on each of the N-type active regions 31, 32, 33, and 34 or are stacked on each of the N-type active regions 31, 32, 33, and 34 as shown in the figure. The N gate dielectric layer 79 and the N gate electrode 95 may be sequentially stacked on each of the P-type active regions 41, 42, 43, and 44 or are stacked on each of the P-type active regions 41, 42, 43, and 44 as shown in the figure (only 41 and 42 are shown to avoid overcrowding of the figure). According to this configuration, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0059] Reference Figure 10, the N-well 25 may include a third N-well 25C and a fourth N-well 25D. The dispersion of the N-type impurity concentration (i.e., the non-uniformity of the N-type impurity concentration) in the N-type active regions 31, 32, 33, and 34 can be reduced. The second P-gate dielectric layer 69 and the second P-gate electrode 85 may be sequentially stacked on each of the N-type active regions 31, 32, 33, and 34 or stacked on each of the N-type active regions 31, 32, 33, and 34 as shown in the figure. The N-gate dielectric layer 79 and the N-gate electrode 95 may be sequentially stacked on each of the P-type active regions 41, 42, 43, and 44 or stacked on each of the P-type active regions 41, 42, 43, and 44 as shown in the figure (only 41 and 42 are shown to avoid overcrowding the figure). According to this configuration, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0060] Reference Figure 11 , the N-well 25 may include a first N-well 25A and a second N-well 25B. The dispersion of the N-type impurity concentration (i.e., the non-uniformity of the N-type impurity concentration) in the N-type active regions 31, 32, 33, and 34 can be reduced. The second P-gate dielectric layer 69 and the first P-gate electrode 85A may be sequentially stacked on the first N-type active region 31 or stacked on the first N-type active region 31 as shown in the figure. The second P-gate dielectric layer 69 and the second P-gate electrode 85 may be sequentially stacked on each of the second to fourth N-type active regions 32, 33, and 34 or stacked on each of the second to fourth N-type active regions 32, 33, and 34 as shown in the figure. The N-gate dielectric layer 79 and the N-gate electrode 95 may be sequentially stacked on each of the P-type active regions 41, 42, 43, and 44 or stacked on each of the P-type active regions 41, 42, 43, and 44 as shown in the figure (only 41 and 42 are shown to avoid overcrowding the figure). According to this configuration, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0061] Reference Figure 12 , the N-well 25 may include a third N-well 25C and a fourth N-well 25D. The dispersion of the N-type impurity concentration (i.e., the non-uniformity of the N-type impurity concentration) in the N-type active regions 31, 32, 33, and 34 can be reduced. The second P-gate dielectric layer 69 and the first P-gate electrode 85A may be sequentially stacked on the first N-type active region 31 or stacked on the first N-type active region 31 as shown in the figure. The second P-gate dielectric layer 69 and the second P-gate electrode 85 may be sequentially stacked on each of the second to fourth N-type active regions 32, 33, and 34 or stacked on each of the second to fourth N-type active regions 32, 33, and 34 as shown in the figure. According to this configuration, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0062] ReferenceFigure 13 , the N-type impurity concentration of the first N-type active region 31 can be higher than that of the second to fourth N-type active regions 32, 33, and 34. The first P-gate dielectric layer 69A and the first P-gate electrode 85A can be sequentially stacked on the first N-type active region 31 or stacked on the first N-type active region 31 as shown in the figure. The second P-gate dielectric layer 69 and the second P-gate electrode 85 can be sequentially stacked on each of the second to fourth N-type active regions 32, 33, and 34 or stacked on each of the second to fourth N-type active regions 32, 33, and 34 as shown in the figure. The N-gate dielectric layer 79 and the N-gate electrode 95 can be sequentially stacked on each of the P-type active regions 41, 42, 43, and 44, or stacked on each of the P-type active regions 41, 42, 43, and 44 as shown in the figure (only 41 and 42 are shown to avoid overcrowding the figure). According to this configuration, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0063] Reference Figure 14 , the N-well 25 can include a third N-well 25C and a fourth N-well 25D. The dispersion of the N-type impurity concentration of the N-type active regions 31, 32, 33, and 34 (i.e., the non-uniformity of the N-type impurity concentration) can be reduced. The first P-gate dielectric layer 69A and the first P-gate electrode 85A can be sequentially stacked on the first N-type active region 31 or stacked on the first N-type active region 31 as shown in the figure. The second P-gate dielectric layer 69 and the second P-gate electrode 85 can be sequentially stacked on each of the second to fourth N-type active regions 32, 33, and 34 or stacked on each of the second to fourth N-type active regions 32, 33, and 34 as shown in the figure. The N-gate dielectric layer 79 and the N-gate electrode 95 can be sequentially stacked on each of the P-type active regions 41, 42, 43, and 44, or stacked on each of the P-type active regions 41, 42, 43, and 44 as shown in the figure (only 41 and 42 are shown to avoid overcrowding the figure). According to this configuration, the dispersion of the electrical characteristics of the P-type transistors pTr1, pTr2, pTr3, and pTr4 can be reduced.

[0064] Reference Figure 15 , a pair of P source / drain regions 122 can be disposed adjacent to both sides of the first P-gate electrode 85A in the first N-type active region 31. The pair of P source / drain regions 122 can include P-type impurities. The first P-type transistor pTr1 (see Figure 2 ) can include the first N-type active region 31, the first P-gate dielectric layer 69A, the first P-gate electrode 85A, and a pair of P source / drain regions 122. Each of the P-type transistors pTr1, pTr2, pTr3, and pTr4 (see Figure 2 ) can include a configuration similar to that of the pair of P source / drain regions 122.

[0065] See Figure 16 , a pair of N source / drain regions 124 can be disposed in the first P-type active region 41 adjacent to both sides of the N gate electrode 95. The pair of N source / drain regions 124 may include N-type impurities. The first N-type transistor nTr1 (see Figure 2 ) may include the first P-type active region 41, an N gate dielectric layer 79, an N gate electrode 95, and a pair of N source / drain regions 124. Each of the N-type transistors nTr1, nTr2, nTr3, and nTr4 (see Figure 2 ) may include a configuration similar to that of the pair of N source / drain regions 124.

[0066] See Figure 17 , in some embodiments, a memory cell MC (see Figure 2 ) based on some embodiments of the present disclosure may include a DRAM. According to some embodiments of the present disclosure, a semiconductor device may include a substrate 21, a second P-well 28, a cell active region 148, a cell isolation pattern 155, a cell source / drain region 174, a gate overlay 176, a cell gate dielectric layer 179, a word line WL, an interlayer insulating layer 181, a bit plug 182, a bit line BL, a storage contact plug SNC, a landing pad LP, an etch stop layer ES, a lower electrode 191, a support SP, a capacitor dielectric layer 193, and an upper electrode 195. The lower electrode 191, the capacitor dielectric layer 193, and the upper electrode 195 may configure a cell capacitor 197. The word line WL may be electrically connected to P-type transistors pTr1, pTr2, pTr3, and pTr4 (see Figure 2 ) and / or N-type transistors nTr1, nTr2, nTr3, and nTr4 (see Figure 2 ).

[0067] The cell active region 148 may be defined within the second P-well 28 by the cell isolation pattern 155. The cell active region 148 may include P-type impurities. The cell source / drain region 174 may include N-type impurities.

[0068] The cell isolation pattern 155, the gate overlay 176, the cell gate dielectric layer 179, the interlayer insulating layer 181, the etch stop layer ES, the support SP, and the capacitor dielectric layer 193 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0069] The word line WL, the bit plug 182, the bit line BL, the storage contact plug SNC, the landing pad LP, the lower electrode 191, and the upper electrode 195 may include a conductive material, such as a metal, a metal oxide, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof.

[0070] Figure 18 and Figure 19is a flowchart for describing a method of forming a semiconductor device according to some embodiments of the present disclosure, Figures 20 to 30 is a cross-sectional view for describing a method of forming a semiconductor device according to some embodiments of the present disclosure. Figures 20 to 30 is a cross-sectional view taken along the I-I′ line of Figure 2 For example, a cross-sectional view taken along the I-I′ line of

[0071] Referring to Figure 18 , a method of forming a semiconductor device according to some embodiments of the present disclosure may include forming an isolation pattern (B20), forming an N-well (B40), forming a P-well (B60), and forming a gate dielectric layer and a gate electrode (B80).

[0072] Referring to Figure 19 , in some embodiments, forming an N-well (B40) may include forming a first N-well mask (B41), performing a first N-well ion implantation process (B43), forming a second N-well mask (B45), and performing a second N-well ion implantation process (B47).

[0073] Referring to Figure 18 and Figure 20 , isolation patterns 51, 52, 53, and 54 (B20) defining active regions 31, 32, 33, 34, 41, 42, and 48 may be formed on a substrate 21.

[0074] The substrate 21 may include a semiconductor substrate, such as a silicon wafer or an SOI (silicon-on-insulator) wafer. The substrate 21 may include a III-V semiconductor substrate, such as a compound semiconductor substrate such as GaAs. The substrate 21 may include single-crystalline silicon, polycrystalline silicon, amorphous silicon, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof. In some embodiments, the substrate 21 may be a single-crystalline silicon wafer having P-type impurities.

[0075] The active regions 31, 32, 33, 34, 41, 42, and 48 may be defined by the isolation patterns 51, 52, 53, and 54 within the substrate 21. The isolation patterns 51, 52, 53, and 54 may be formed using a trench isolation method. Each of the isolation patterns 51, 52, 53, and 54 may include a single layer or multiple layers. The isolation patterns 51, 52, 53, and 54 may include at least two selected from the group consisting of Si, O, N, C, and B. The isolation patterns 51, 52, 53, and 54 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. For simplicity of description, the isolation patterns 51, 52, 53, and 54 are shown to have the same depth, but may also be formed to have different depths.

[0076] Referring to Figure 18 and 21, an N-well mask NM can be formed on the substrate 21, and the N-well mask NM covers the cell area CA (see Figure 2 ), the boundary area BR, and the N-type sub-word line driving area SWDN and exposes the P-type sub-word line driving area SWDP. The N-well mask NM can completely cover the P-type active regions 41 and 42, the dummy active region 48, and the fourth isolation pattern 54. The N-well mask NM can be formed to cover a part of the second isolation pattern 52 and a part of the third isolation pattern 53.

[0077] Refer to Figure 18 and Figure 22 , the N-well mask NM can be used as an ion implantation mask to form an N-well 25 (B40). The N-well 25 can include N-type impurities, such as phosphorus, arsenic, or a combination thereof. The N-well 25 can be formed at a predetermined depth from the surface of the substrate 21. The lowermost end of the N-well 25 can be formed at a level lower than the lowermost ends of the first isolation pattern 51, the second isolation pattern 52, and the third isolation pattern 53. The N-well 25 can be formed in the P-type sub-word line driving area SWDP of the substrate 21. The N-type active regions 31, 32, 33, and 34 can be defined within the N-well 25. The N-type active regions 31, 32, 33, and 34 can include N-type impurities.

[0078] In some embodiments, the shortest distance between the N-well mask NM and the first N-type active region 31 can be less than the shortest distance between the N-well mask NM and the fourth N-type active region 34. Due to the well proximity effect (WPE), the N-type impurity concentration of the first N-type active region 31 can be different from the N-type impurity concentrations of the second to fourth N-type active regions 32, 33, and 34. For example, the N-type impurity concentration of the first N-type active region 31 can be higher than the N-type impurity concentrations of the second to fourth N-type active regions 32, 33, and 34.

[0079] Refer to Figure 18 and Figure 23 , the N-well mask NM can be removed, and a P-well mask PM that covers the P-type sub-word line driving area SWDP and exposes the cell area CA (see Figure 2 ) can be formed on the substrate 21, the boundary area BR, and the N-type sub-word line driving area SWDN. The P-well mask PM can cover the N-well 25. The P-well mask PM can completely cover the N-type active regions 31, 32, 33, and 34 and the first isolation pattern 51. The P-well mask PM can be formed to cover a part of the second isolation pattern 52 and a part of the third isolation pattern 53.

[0080] Refer to Figure 18 and Figure 24, a P-well mask PM can be used as an ion implantation mask to form a first P-well 27 and a second P-well 28 (B60). The first P-well 27 and the second P-well 28 may include P-type impurities, such as boron. The first P-well 27 and the second P-well 28 can be formed to a predetermined depth from the surface of the substrate 21. In some embodiments, the N-well 25, the first P-well 27, and the second P-well 28 can be formed to have different depths.

[0081] The lowermost end of the first P-well 27 can be formed at a level lower than the lowermost ends of the second isolation pattern 52 and the fourth isolation pattern 54. The first P-well 27 can be formed in the N-type sub-word line driving region SWDN of the substrate 21. The P-type active regions 41 and 42 can be defined within the first P-well 27. The boundary between the N-well 25 and the first P-well 27 can be located below the second isolation pattern 52. The lowermost end of the second P-well 28 can be formed at a level lower than the lowermost end of the third isolation pattern 53. The second P-well 28 can be formed in the cell region CA (see Figure 2 ) and the boundary region BR of the substrate 21. The dummy active region 48 can be defined within the second P-well 28. The boundary between the N-well 25 and the first P-well 28 can be formed below the third isolation pattern 53. The P-type active regions 41 and 42 and the dummy active region 48 may include P-type impurities.

[0082] Reference Figure 18 and Figure 25 , the P-well mask PM can be removed. In some embodiments, the N-type impurity concentration of the first N-type active region 31 can be different from the N-type impurity concentrations of the second to fourth N-type active regions 32, 33, and 34. The N-type impurity concentration of the first N-type active region 31 can be higher than the N-type impurity concentrations of the second to fourth N-type active regions 32, 33, and 34.

[0083] Reference Figure 18 and Figure 3 , a gate dielectric layer 69, 69A, and 79 and gate electrodes 85 and 95 (B80) can be formed on the substrate 21 on which the N-well 25, the first P-well 27, the second P-well 28, the active regions 31, 32, 33, 34, 41, 42, and 48, and the isolation patterns 51, 52, 53, and 54 are formed.

[0084] The gate dielectric layers 69, 69A, and 79 may include a first P gate dielectric layer 69A, a second P gate dielectric layer 69, and an N gate dielectric layer 79. The first P gate dielectric layer 69A may include a P interface layer 61, a P dielectric layer 62, a first modulation layer 67A, and a P capping layer 68. The first modulation layer 67A may include a lower modulation layer 63, a first intermediate modulation layer 64A, and an upper modulation layer 65. The second P gate dielectric layer 69 may include a P interface layer 61, a P dielectric layer 62, a second modulation layer 67, and a P capping layer 68. The second modulation layer 67 may include a lower modulation layer 63, a second intermediate modulation layer 64, and an upper modulation layer 65. The N gate dielectric layer 79 may include an N interface layer 71, an N dielectric layer 72, and an N capping layer 78.

[0085] The gate electrodes 85 and 95 may include a second P gate electrode 85 and an N gate electrode 95. The second P gate electrode 85 may include a second P work function metal layer 82 and a P gate conductive layer 84. The N gate electrode 95 may include an N work function metal layer 92 and an N gate conductive layer 94.

[0086] Reference Figure 18 and Figure 8 and, the gate dielectric layers 69 and 79 and the gate electrodes 85, 85A, and 95 may be formed on a substrate 21 in which an N well 25, a first P well 27, a second P well 28, active regions 31, 32, 33, 34, 41, 42, and 48, and isolation patterns 51, 52, 53, and 54 are formed (B80).

[0087] The gate dielectric layers 69 and 79 may include a second P gate dielectric layer 69 and an N gate dielectric layer 79. The second P gate dielectric layer 69 may include a P interface layer 61 and a P dielectric layer 62. The N gate dielectric layer 79 may include an N interface layer 71, an N dielectric layer 72, and an N capping layer 78.

[0088] The gate electrodes 85, 85A, and 95 may include a first P gate electrode 85A, a second P gate electrode 85, and an N gate electrode 95. The first P gate electrode 85A may include a first P work function metal layer 82A and a P gate conductive layer 84. The second P gate electrode 85 may include a second P work function metal layer 82 and a P gate conductive layer 84. The N gate electrode 95 may include an N work function metal layer 92 and an N gate conductive layer 94.

[0089] Reference Figure 18 , Figure 19 and Figure 26 and, a first N well mask NM1 may be formed on the substrate 21, and the first N well mask NM1 covers a cell region CA (see Figure 2) a boundary region BR and an N-type sub-word line driving region SWDN, and expose a part (B41) of the P-type sub-word line driving region SWDP. The remaining part of the substrate 21 except for the exposed part of the P-type sub-word line driving region SWDP can be covered by the first N-well mask NM1. The first N-well 25A can be formed by performing a first N-well ion implantation process using the first N-well mask NM1 as an ion implantation mask (B43).

[0090] In some embodiments, the shortest distance between the first N-well mask NM1 and the first N-type active region 31 can be substantially the same as the shortest distance between the first N-well mask NM1 and the fourth N-type active region 34. Due to the reduction of the well proximity effect (WPE), the dispersion of the N-type impurity concentration (i.e., the non-uniformity of the N-type impurity concentration) in the N-type active regions 31, 32, 33, and 34 can be reduced.

[0091] Reference Figure 18 、 Figure 19 and Figure 27 ,a second N-well mask NM2 can be formed on the substrate 21, and the second N-well mask NM2 only exposes the part of the P-type sub-word line driving region SWDP covered by the first N-well mask NM1 (B45). The second N-well mask NM2 can cover the first N-well 25A. The second N-well 25B can be formed by performing a second N-well ion implantation process using the second N-well mask NM2 as an ion implantation mask (B47). The second N-well mask NM2 can be removed. The first N-well 25A and the second N-well 25B can configure the N-well 25.

[0092] In some embodiments, the boundary between the first N-well 25A and the second N-well 25B can be aligned with or located below the third isolation pattern 53. The second N-well 25B can be defined below the third isolation pattern 53. The N-type impurity concentration in the second N-well 25B can be different from the N-type impurity concentration in the first N-well 25A. The lower surfaces of the first N-well 25A and the second N-well 25B are shown to be formed at similar levels, but can also be formed at different levels.

[0093] Reference Figure 18 、 Figure 19 and Figure 28 ,the first P-well 27 and the second P-well 28 can be formed by a method similar to the method described above with reference to Figure 24 and 25 (B60).

[0094] Reference Figure 18 、 Figure 19 and Figure 4, the gate dielectric layers 69 and 79 and the gate electrodes 85 and 95 (B80) can be formed. The gate dielectric layers 69 and 79 can include a second P gate dielectric layer 69 and an N gate dielectric layer 79. The second P gate dielectric layer 69 can include a P interface layer 61, a P dielectric layer 62, a second modulation layer 67, and a P capping layer 68. The second modulation layer 67 can include a lower modulation layer 63, a second intermediate modulation layer 64, and an upper modulation layer 65. The N gate dielectric layer 79 can include an N interface layer 71, an N dielectric layer 72, and an N capping layer 78. The gate electrodes 85 and 95 can include a second P gate electrode 85 and an N gate electrode 95. The second P gate electrode 85 can include a second P work function metal layer 82 and a P gate conductive layer 84. The N gate electrode 95 can include an N work function metal layer 92 and an N gate conductive layer 94.

[0095] Reference Figure 18 、 Figure 19 and Figure 9 , the gate dielectric layers 69 and 79 and the gate electrodes 85 and 95 (B80) can be formed. The gate dielectric layers 69 and 79 can include a second P gate dielectric layer 69 and an N gate dielectric layer 79. The second P gate dielectric layer 69 can include a P interface layer 61 and a P dielectric layer 62. The N gate dielectric layer 79 can include an N interface layer 71, an N dielectric layer 72, and an N capping layer 78. The gate electrodes 85 and 95 can include a second P gate electrode 85 and an N gate electrode 95. The second P gate electrode 85 can include a second P work function metal layer 82 and a P gate conductive layer 84. The N gate electrode 95 can include an N work function metal layer 92 and an N gate conductive layer 94.

[0096] Reference Figure 18 、 Figure 19 and Figure 29 , it can be formed in a method similar to that described in the above reference Figure 21 and Figure 22 by performing a third N-well ion implantation process using an N-well mask NM (see Figure 20 ) as an ion implantation mask to form a third N-well 25C. The third N-well 25C can be formed to have a size similar to that of the N-well 25 of Figure 22 . The amount of N-type impurities implanted in the third N-well ion implantation process can be less than the amount of N-type impurities used when forming the N-well 25 of Figure 22 .

[0097] A third N-well mask NM3 for forming a P-type sub-word line driving region SWDP that partially exposes the substrate 21 can be formed. The third N-well mask NM3 can cover a part of the third N-well 25C and expose the remaining part. The third N-well mask NM3 can cover the first N-type active region 31.

[0098] By performing a fourth N-well ion implantation process using a third N-well mask NM3 as an ion implantation mask, a fourth N-well 25D can be formed. The remaining portion of the third N-well 25C not covered by the third N-well mask NM3 can be converted into the fourth N-well 25D. The first N-type active region 31 can be defined within the third N-well 25C, and the second to fourth N-type active regions 32, 33, and 34 can be defined within the fourth N-well 25D.

[0099] The third N-well mask NM3 can be removed. The third N-well 25C and the fourth N-well 25D can configure the N-well 25. The lower surfaces of the third N-well 25C and the fourth N-well 25D are shown as being formed at similar levels, but they can also be formed at different levels.

[0100] By applying different ion implantation masks (such as the N-well mask NM (see Figure 20 )) and the third N-well mask NM3 (see Figure 29 )) and by applying different ion implantation processes (such as the third N-well ion implantation process and the fourth N-well ion implantation process performed in sequence), the dispersion of the N-type impurity concentration (i.e., the non-uniformity of the N-type impurity concentration) in the N-type active regions 31, 32, 33, and 34 can be reduced.

[0101] Refer to Figure 18 、 Figure 19 and Figure 30 , a method similar to the method described above with reference to Figure 24 and Figure 25 can be used to form the first P-well 27 and the second P-well 28 (B60).

[0102] Refer to Figure 18 、 Figure 19 and Figure 5 , the gate dielectric layers 69 and 79 and the gate electrodes 85 and 95 (B80) can be formed. The gate dielectric layers 69 and 79 can include a second P-gate dielectric layer 69 and an N-gate dielectric layer 79. The second P-gate dielectric layer 69 can include a P interface layer 61, a P dielectric layer 62, a second modulation layer 67, and a P capping layer 68. The second modulation layer 67 can include a lower modulation layer 63, a second intermediate modulation layer 64, and an upper modulation layer 65. The N-gate dielectric layer 79 can include an N interface layer 71, an N dielectric layer 72, and an N capping layer 78. The gate electrodes 85 and 95 can include a second P-gate electrode 85 and an N-gate electrode 95. The second P-gate electrode 85 can include a second P work function metal layer 82 and a P-gate conductive layer 84. The N-gate electrode 95 can include an N work function metal layer 92 and an N-gate conductive layer 94.

[0103] Refer to Figure 18 、 Figure 19 and Figure 10, the gate dielectric layers 69 and 79 and the gate electrodes 85 and 95 (B80) can be formed. The gate dielectric layers 69 and 79 can include a second P gate dielectric layer 69 and an N gate dielectric layer 79. The second P gate dielectric layer 69 can include a P interface layer 61 and a P dielectric layer 62. The N gate dielectric layer 79 can include an N interface layer 71, an N dielectric layer 72, and an N capping layer 78. The gate electrodes 85 and 95 can include a second P gate electrode 85 and an N gate electrode 95. The second P gate electrode 85 can include a second P work function metal layer 82 and a P gate conductive layer 84. The N gate electrode 95 can include an N work function metal layer 92 and an N gate conductive layer 94.

[0104] Although various embodiments of the present disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the drawings should be considered merely descriptive and not for limiting the technical scope of the present disclosure. The technical scope of the present disclosure is not limited by the embodiments and the drawings. The scope of the present disclosure should be interpreted in conjunction with the appended claims and cover all equivalents falling within the scope of the appended claims. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A first P-well, a second P-well, and an N-well, which are formed in a substrate, wherein the N-well is located between the first P-well and the second P-well; A plurality of N-type active regions, which are defined within the N-well, the plurality of N-type active regions including a first N-type active region adjacent to the first P-well and a second N-type active region adjacent to the second P-well, and the shortest distance between the boundary of the second P-well and the N-well and the second N-type active region is greater than the shortest distance between the boundary of the first P-well and the N-well and the first N-type active region; A first P-gate dielectric layer, which is disposed on the first N-type active region and includes a first modulation layer; A second P-gate dielectric layer, which is disposed on the second N-type active region and includes a second modulation layer; A first P-gate electrode, which is located on the first P-gate dielectric layer; And A second P-gate electrode, which is located on the second P-gate dielectric layer.

2. The semiconductor device according to claim 1, Among them, The first modulation layer includes a first intermediate modulation layer located between a lower modulation layer and an upper modulation layer, Wherein, the second modulation layer includes a second intermediate modulation layer located between the lower modulation layer and the upper modulation layer, and the first intermediate modulation layer is thicker than the second intermediate modulation layer, Wherein, each of the first intermediate modulation layer and the second intermediate modulation layer includes Al2O3, HfO2, or a combination thereof.

3. The semiconductor device according to claim 2, wherein, Each of the lower modulation layer and the upper modulation layer includes TiN, TiCN, TaN, WN, TiAl, MoN, or a combination thereof.

4. The semiconductor device according to claim 1, wherein, The N-type impurity concentration of the first N-type active region is higher than the N-type impurity concentration of the second N-type active region.

5. The semiconductor device according to claim 1, further comprising: A P-type active region, which is defined within the first P-well; A plurality of first isolation patterns, which are located between the plurality of N-type active regions; A second isolation pattern, which is located between the P-type active region and the first N-type active region; And A third isolation pattern, which is adjacent to the boundary between the second P-well and the N-well, and the horizontal width of the third isolation pattern is greater than that of the second isolation pattern.

6. The semiconductor device according to claim 5, wherein: The boundary between the N-well and the first P-well is aligned below the second isolation pattern, and The boundary between the N-well and the second P-well is aligned below the third isolation pattern.

7. The semiconductor device according to claim 5, further comprising: An N-gate dielectric layer on the P-type active region; And An N-gate electrode on the N-gate dielectric layer, Wherein, the N-gate dielectric layer includes an N interface layer, an N dielectric layer, and an N capping layer stacked in sequence.

8. The semiconductor device according to claim 7, wherein: The N interface layer includes silicon oxide, silicon oxynitride, or a combination thereof, The N dielectric layer includes HfSiON, HfO2, HfON, SiON, ZrSiO4, Y2O3, Ta2O5, BaO, HfSiO, MgO, Al2O3, Si3N4, CaO, LaLuO2, or a combination thereof, and The N capping layer includes LaO, La2O3, Y2O3, ScO2, or a combination thereof.

9. The semiconductor device according to claim 1, Among them, The first P gate dielectric layer further includes: A P dielectric layer located between the first modulation layer and the first N-type active region; and A P interface layer located between the P dielectric layer and the first N-type active region, and wherein, the second P gate dielectric layer further includes: The P dielectric layer located between the second modulation layer and the second N-type active region; and The P interface layer located between the P dielectric layer and the second N-type active region.

10. The semiconductor device according to claim 9, wherein: The P dielectric layer includes HfSiON, HfO2, HfON, SiON, ZrSiO4, Y2O3, Ta2O5, BaO, HfSiO, MgO, Al2O3, Si3N4, CaO, LaLuO2, or a combination thereof, and The P interface layer includes silicon oxide, silicon oxynitride, or a combination thereof.

11. The semiconductor device according to claim 1, wherein: The first P gate dielectric layer further includes a P capping layer located between the first modulation layer and the first P gate electrode, and The second P gate dielectric layer further includes the P capping layer located between the second modulation layer and the second P gate electrode.

12. The semiconductor device according to claim 11, wherein, The P capping layer includes LaO, La2O3, Y2O3, ScO2, or a combination thereof.

13. The semiconductor device according to claim 1, wherein: The first P gate electrode includes a first P work function metal layer located on the first P gate dielectric layer, The second P gate electrode includes a second P work function metal layer located on the second P gate dielectric layer, and The first P work function metal layer is thicker than the second P work function metal layer.

14. The semiconductor device according to claim 13, wherein, The first P work function metal layer and the second P work function metal layer include TiN, TiCN, TaN, WN, TiAl, MoN, or a combination thereof.

15. The semiconductor device according to claim 1, wherein: The N well includes a first N well adjacent to the first P well and a second N well adjacent to the second P well, and The plurality of N-type active regions are defined within the first N well.

16. The semiconductor device according to claim 15, wherein, The shortest distance between the boundary of the first P well and the first N well and the first N-type active region is substantially the same as the shortest distance between the boundary of the first N well and the second N well and the second N-type active region.

17. The semiconductor device according to claim 15, wherein The N-type impurity concentration in the second N well is different from the N-type impurity concentration in the first N well.

18. The semiconductor device according to claim 1, wherein: The N well includes a first N well adjacent to the first P well and a second N well adjacent to the second P well, The first N-type active region is defined within the first N well, and The second N-type active region is defined within the second N well.

19. The semiconductor device according to claim 18, wherein, The shortest distance between the boundary of the second P well and the second N well and the second N-type active region is greater than the shortest distance between the boundary of the first P well and the first N well and the first N-type active region.

20. A semiconductor device, comprising: A first P-well, a second P-well, and an N-well in a substrate, wherein the N-well includes a first N-well and a second N-well located between the first P-well and the second P-well, the first N-well is adjacent to the first P-well, and the second N-well is adjacent to the second P-well; A plurality of N-type active regions defined within the first N-well, the plurality of N-type active regions including a first N-type active region adjacent to the first P-well and a second N-type active region adjacent to the second N-well, and a shortest distance between a boundary of the first P-well and the first N-well and the first N-type active region is substantially the same as a shortest distance between a boundary of the first N-well and the second N-well and the second N-type active region; A first P-gate dielectric layer disposed on the first N-type active region and including a first modulation layer; A second P-gate dielectric layer disposed on the second N-type active region and including a second modulation layer, the first modulation layer being thicker than the second modulation layer; A first P-gate electrode including a first P-work function metal layer on the first P-gate dielectric layer; And A second P-gate electrode including a second P-work function metal layer on the second P-gate dielectric layer, Wherein the first P-work function metal layer is thicker than the second P-work function metal layer.

21. A semiconductor device, comprising: A first P-well, a second P-well, and an N-well in a substrate located between the first P-well and the second P-well; A plurality of N-type active regions defined within the N-well, the plurality of N-type active regions including a first N-type active region adjacent to the first P-well and a second N-type active region adjacent to the second P-well, and a shortest distance between a boundary of the second P-well and the N-well and the second N-type active region is greater than a shortest distance between a boundary of the first P-well and the N-well and the first N-type active region; A first P-gate electrode including a first P-work function metal layer on the first N-type active region; A second P-gate electrode including a second P-work function metal layer on the second N-type active region, the first P-work function metal layer being thicker than the second P-work function metal layer; And A P-gate dielectric layer located between the first N-type active region and the first P-gate electrode and between the second N-type active region and the second P-gate electrode.

22. The semiconductor device according to claim 21, wherein, Each of the first P-work function metal layer and the second P-work function metal layer includes TiN, TiCN, TaN, WN, TiAl, MoN, or a combination thereof.

23. The semiconductor device according to claim 21, wherein, An N-type impurity concentration of the first N-type active region is higher than an N-type impurity concentration of the second N-type active region.

24. The semiconductor device according to claim 21, further comprising: A P-type active region defined within the first P-well; A plurality of first isolation patterns located between the plurality of N-type active regions; A second isolation pattern located between the P-type active region and the first N-type active region; And A third isolation pattern adjacent to a boundary between the second P-well and the N-well and having a horizontal width greater than the second isolation pattern.

25. The semiconductor device according to claim 24, wherein: The boundary between the N-well and the first P-well is aligned under the second isolation pattern, and the boundary between the N-well and the second P-well is aligned under the third isolation pattern.

26. The semiconductor device according to claim 24, further comprising: An N gate dielectric layer located on the P-type active region; And An N gate electrode located on the N gate dielectric layer, wherein the N gate dielectric layer includes an N interface layer, an N dielectric layer, and an N capping layer stacked in sequence.

27. The semiconductor device according to claim 26, wherein: The N interface layer includes silicon oxide, silicon oxynitride, or a combination thereof, The N dielectric layer includes HfSiON, HfO2, HfON, SiON, ZrSiO4, Y2O3, Ta2O5, BaO, HfSiO, MgO, Al2O3, Si3N4, CaO, LaLuO2, or a combination thereof, and The N capping layer includes LaO, La2O3, Y2O3, ScO2, or a combination thereof.

28. The semiconductor device according to claim 21, wherein, Each of the P gate dielectric layers includes a P interface layer and a P dielectric layer stacked in sequence.

29. The semiconductor device according to claim 28, wherein: The P dielectric layer includes HfSiON, HfO2, HfON, SiON, ZrSiO4, Y2O3, Ta2O5, BaO, HfSiO, MgO, Al2O3, Si3N4, CaO, LaLuO2, or a combination thereof, and The P interface layer includes silicon oxide, silicon oxynitride, or a combination thereof.

30. The semiconductor device according to claim 21, wherein: The N-well includes a first N-well adjacent to the first P-well and a second N-well adjacent to the second P-well, and The plurality of N-type active regions are defined within the first N-well.

31. The semiconductor device according to claim 30, wherein, The shortest distance between the boundary of the first P-well and the first N-well and the first N-type active region is substantially the same as the shortest distance between the boundary of the first N-well and the second N-well and the second N-type active region.

32. The semiconductor device according to claim 30, wherein, The N-type impurity concentration in the second N-well is different from the N-type impurity concentration in the first N-well.

33. The semiconductor device according to claim 21, wherein: The N-well includes a first N-well adjacent to the first P-well and a second N-well adjacent to the second P-well, The first N-type active region is defined within the first N-well, and The second N-type active region is defined within the second N-well.

34. The semiconductor device according to claim 33, wherein, The shortest distance between the boundary of the second P-well and the second N-well and the second N-type active region is greater than the shortest distance between the boundary of the first P-well and the first N-well and the first N-type active region.

35. A semiconductor device, comprising: A first P-well, a second P-well in a substrate, and an N-well located between the first P-well and the second P-well, the N-well including a first N-well and a second N-well, the first N-well being adjacent to the first P-well, and the second N-well being adjacent to the second P-well; A plurality of N-type active regions defined within the first N-well, the plurality of N-type active regions including a first N-type active region adjacent to the first P-well and a second N-type active region adjacent to the second N-well, and a shortest distance between a boundary between the first P-well and the first N-well and the first N-type active region being substantially the same as a shortest distance between a boundary between the first N-well and the second N-well and the second N-type active region; A P-gate dielectric layer thereon over the first N-type active region and the second N-type active region; and A P-gate electrode thereon over the P-gate dielectric layer.

36. The semiconductor device according to claim 35, wherein, An N-type impurity concentration in the second N-well is different from an N-type impurity concentration in the first N-well.

37. The semiconductor device according to claim 35, wherein, Each of the P-gate dielectric layers includes a P interface layer and a P dielectric layer stacked in sequence.

38. The semiconductor device according to claim 37, wherein, The P dielectric layer includes HfSiON, HfO2, HfON, SiON, ZrSiO4, Y2O3, Ta2O5, BaO, HfSiO, MgO, Al2O3, Si3N4, CaO, LaLuO2, or a combination thereof, and The P interface layer includes silicon oxide, silicon oxynitride, or a combination thereof.

39. The semiconductor device according to claim 37, wherein, Each of the P-gate dielectric layers further includes a modulation layer disposed on the P dielectric layer and including a lower modulation layer, an intermediate modulation layer, and an upper modulation layer stacked in sequence.

40. The semiconductor device according to claim 39, wherein: Each of the lower modulation layer and the upper modulation layer includes TiN, TiCN, TaN, WN, TiAl, MoN, or a combination thereof, and The intermediate modulation layer includes Al2O3, HfO2, or a combination thereof.

41. The semiconductor device according to claim 39, wherein, Each of the P-gate dielectric layers further includes a P capping layer disposed on the modulation layer.

42. The semiconductor device according to claim 41, wherein, The P capping layer includes LaO, La2O3, Y2O3, ScO2, or a combination thereof.

43. The semiconductor device according to claim 35, further comprising: A P-type active region defined within the first P-well; A plurality of first isolation patterns located between the plurality of N-type active regions; A second isolation pattern located between the P-type active region and the first N-type active region; and A third isolation pattern adjacent to a boundary between the second P-well and the N-well and having a horizontal width greater than that of the second isolation pattern.

44. The semiconductor device according to claim 43, wherein: A boundary between the first N-well and the first P-well is aligned below the second isolation pattern, and A boundary between the second N-well and the second P-well is aligned below the third isolation pattern.

45. The semiconductor device according to claim 44, wherein, A boundary between the first N-well and the second N-well is aligned below the third isolation pattern.

46. The semiconductor device according to claim 43, further comprising: An N-gate dielectric layer on the P-type active region; and An N-gate electrode on the N-gate dielectric layer, wherein the N-gate dielectric layer includes an N interface layer, an N dielectric layer, and an N capping layer stacked in sequence.

47. The semiconductor device according to claim 46, wherein: The N interface layer includes silicon oxide, silicon oxynitride, or a combination thereof, The N dielectric layer includes HfSiON, HfO2, HfON, SiON, ZrSiO4, Y2O3, Ta2O5, BaO, HfSiO, MgO, Al2O3, Si3N4, CaO, LaLuO2, or a combination thereof, and The N capping layer includes LaO, La2O3, Y2O3, ScO2, or a combination thereof.

48. A semiconductor device, comprising: a first P well, a second P well in a substrate, and an N well located between the first P well and the second P well, the N well including a first N well and a second N well, the first N well adjacent to the first P well, and the second N well adjacent to the second P well; a plurality of N-type active regions defined within the N well, the plurality of N-type active regions including: a first N-type active region adjacent to the first P well and defined within the first N well; and a second N-type active region adjacent to the second P well and defined within the second N well; a shortest distance between a boundary of the second P well and the second N well and the second N-type active region is greater than a shortest distance between a boundary of the first P well and the first N well and the first N-type active region; a P gate dielectric layer located on the first N-type active region and the second N-type active region; and a P gate electrode located on the P gate dielectric layer.

49. The semiconductor device according to claim 48, further comprising: a P-type active region defined within the first P well; a plurality of first isolation patterns located between the plurality of N-type active regions; a second isolation pattern located between the P-type active region and the first N-type active region; and a third isolation pattern adjacent to a boundary between the second P well and the N well and having a horizontal width greater than that of the second isolation pattern.

50. The semiconductor device according to claim 49, wherein: a boundary between the first N well and the first P well is aligned below the second isolation pattern, and a boundary between the second N well and the second P well is aligned below the third isolation pattern.

51. The semiconductor device according to claim 49, Among them, the plurality of N-type active regions further includes: a third N-type active region located between the first N-type active region and the second N-type active region; and a fourth N-type active region located between the second N-type active region and the third N-type active region, and wherein a boundary between the first N well and the second N well is aligned below the first isolation pattern between the first N-type active region and the third N-type active region.

52. The semiconductor device according to claim 49, further comprising: an N gate dielectric layer located on the P-type active region; and an N gate electrode located on the N gate dielectric layer, wherein the N gate dielectric layer includes an N interface layer, an N dielectric layer, and an N capping layer stacked in sequence.

53. The semiconductor device according to claim 52, wherein: the N interface layer includes silicon oxide, silicon oxynitride, or a combination thereof, The N dielectric layer includes HfSiON, HfO2, HfON, SiON, ZrSiO4, Y2O3, Ta2O5, BaO, HfSiO, MgO, Al2O3, Si3N4, CaO, LaLuO2, or a combination thereof, and The N capping layer includes LaO, La2O3, Y2O3, ScO2, or a combination thereof.

54. The semiconductor device according to claim 48, wherein, Each of the P gate dielectric layers includes a sequentially stacked P interface layer and a P dielectric layer.

55. The semiconductor device according to claim 54, wherein: The P dielectric layer includes HfSiON, HfO2, HfON, SiON, ZrSiO4, Y2O3, Ta2O5, BaO, HfSiO, MgO, Al2O3, Si3N4, CaO, LaLuO2, or a combination thereof, and The P interface layer includes silicon oxide, silicon oxynitride, or a combination thereof.

56. The semiconductor device according to claim 54, wherein, Each of the P gate dielectric layers further includes a modulation layer, which is located on the P dielectric layer and includes a sequentially stacked lower modulation layer, an intermediate modulation layer, and an upper modulation layer.

57. The semiconductor device according to claim 56, wherein: Each of the lower modulation layer and the upper modulation layer includes TiN, TiCN, TaN, WN, TiAl, MoN, or a combination thereof, and The intermediate modulation layer includes Al2O3, HfO2, or a combination thereof.

58. The semiconductor device according to claim 56, wherein, Each of the P gate dielectric layers further includes a P capping layer on the modulation layer.

59. The semiconductor device according to claim 58, wherein, The P capping layer includes LaO, La2O3, Y2O3, ScO2, or a combination thereof.

60. A semiconductor device, comprising: A first P well, a second P well in a substrate, and an N well located between the first P well and the second P well, the N well including a first N well and a second N well, the first N well being adjacent to the first P well, and the second N well being adjacent to the second P well; A plurality of N-type active regions defined within the N well, the plurality of N-type active regions including a first N-type active region adjacent to the first P well and defined within the first N well and a second N-type active region adjacent to the second P well and defined within the second N well, the shortest distance between the boundary of the second P well and the second N well and the second N-type active region being greater than the shortest distance between the boundary of the first P well and the first N well and the first N-type active region; A first P gate dielectric layer disposed on the first N-type active region and including a first modulation layer; A second P gate dielectric layer disposed on the second N-type active region and including a second modulation layer, the first modulation layer being thicker than the second modulation layer; A first P gate electrode including a first P work function metal layer on the first P gate dielectric layer; And A second P gate electrode including a second P work function metal layer on the second P gate dielectric layer, Wherein, the first P work function metal layer is thicker than the second P work function metal layer.

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