Two-dimensional flash memory / CMOS monolithic integrated cross-platform heterogeneous system

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a two-dimensional flash memory / CMOS monolithic integrated cross-platform heterogeneous system. The system is obtained by integrating a two-dimensional flash memory array and a CMOS (complementary metal oxide semiconductor) peripheral circuit monolithic, the CMOS monolithic serves as a peripheral circuit of the two-dimensional flash memory array, and the CMOS monolithic and the two-dimensional flash memory array are closely combined in device-level granularity; the upper layer is a two-dimensional flash memory array, the lower layer is a CMOS circuit, and the two layers are interconnected through a TGV; the two-dimensional flash memory array is effectively controlled by the CMOS in a modular communication mode; according to the invention, the technical problems of mismatching of technical nodes, process pollution caused by heterogeneous integration, conflict of circuit architecture recombination and the like when the two parts are tightly combined are solved. According to the invention, the CMOS utilizes the high-speed read-write characteristic of the two-dimensional flash memory, so that the clock speed of the CMOS is increased, and the working efficiency of a future chip is improved; the two-dimensional flash memory optimizes a peripheral reading circuit of the two-dimensional flash memory by utilizing a mature and efficient logic circuit of a CMOS (Complementary Metal Oxide Semiconductor); and the two-dimensional flash memory is promoted to the industrial circle.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration. Background Art

[0002] Semiconductor devices based on silicon materials have always been the core of past integrated circuit technologies. Recent research has shown that two-dimensional materials exhibit superior electronic properties at monolayer ultra-thin thicknesses and precise energy band regulation in van der Waals heterostructures. These properties enable the expansion ability of two-dimensional electronics to exceed that of silicon technology and have created new semiconductor devices based on two-dimensional materials. As one of the semiconductor memories of integrated circuits, two-dimensional flash memory has advantages such as ultra-fast programming speed and channel length scaling compared with silicon flash memory (the mainstream non-volatile memory technology).

[0003] In past research, extensive studies on two-dimensional electronics have discovered many new material properties and innovative device concepts. The next stage of two-dimensional electronics should demonstrate its superiority at the system level and accelerate the transition of viable emerging devices from the laboratory to the factory. In recent years, the integrated circuit (IC) industry and academic researchers have increasingly considered integrating two-dimensional semiconductors. For example, well-known enterprises in the semiconductor industry have listed two-dimensional materials as candidate materials for next-generation channel materials (Intel, TSMC, IMEC), and the academic community has also explored wafer-level three-dimensional integration of two-dimensional electronics. However, due to the hysteresis of two-dimensional PMOS, two-dimensional semiconductors currently cannot rival logic circuits based on the most advanced silicon technology, which is a fatal drawback for achieving high-performance systems. Combining two-dimensional electronic devices with mature silicon CMOS logic circuits is a feasible method to prove the superiority of two-dimensional electronic devices at the system level.

[0004] The cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration of the present invention combines high-performance two-dimensional flash memory prepared in the laboratory and commercial CMOS circuits, promoting the process of two-dimensional flash memory from the laboratory to the industrial community. Summary of the Invention

[0005] The purpose of the present invention is to provide a cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration with superior performance.

[0006] The cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration provided by the present invention involves the preparation of a two-dimensional flash memory array compatible with commercial CMOS circuits; the interconnection method for the monolithic integration of two-dimensional flash memory and CMOS circuits; and also involves a test method for this cross-platform heterogeneous system.

[0007] The cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration provided by the present invention is obtained by monolithically integrating a high-performance two-dimensional flash memory array and a mature CMOS peripheral circuit. By taking advantage of the merits of two material systems, the CMOS monolith serves as the peripheral circuit of the two-dimensional flash memory array and is tightly integrated at the device-level granularity, providing a new paradigm for the application of new memories. Specifically, the cross-platform heterogeneous system of the present invention mainly includes an upper and a lower layer structure. The upper layer is a two-dimensional flash memory array, and the lower layer is a CMOS circuit. The two are interconnected through TGV (Through Glass Via technology); and the CMOS circuit effectively controls the two-dimensional flash memory array through a modular communication method to realize the cross-platform heterogeneous system.

[0008] The cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration is obtained by the following steps:

[0009] (1) Determine the scale and structure of the two-dimensional flash memory array: including designing the device scale, device programming method, device performance, and circuit structure of the two-dimensional flash memory;

[0010] (2) Design the CMOS circuit and perform wafer processing: The CMOS serves as the peripheral circuit of the two-dimensional flash memory array and executes data reading, programming, and erasing operations applicable to the two-dimensional flash memory array;

[0011] (3) Monolithically integrate and interconnect the two-dimensional flash memory array and the CMOS circuit;

[0012] (4) Fabricate the on-chip two-dimensional flash memory array;

[0013] (5) Package the heterogeneous system and adopt a dedicated chip test system.

[0014] Furthermore:

[0015] The device programming method is one of FN tunneling programming / erasing, hot electron programming / erasing, and any combination thereof;

[0016] For the device programming, its voltage and programming speed are ±14V and 500ns respectively;

[0017] The device circuit structure is one of NOR and NAND;

[0018] The data reading operation of the two-dimensional flash memory array supports both parallel reading and single-device reading;

[0019] The data programming operation of the two-dimensional flash memory array supports both parallel programming and single-device programming;

[0020] The data erasing operation of the two-dimensional flash memory array supports full-chip erasing, parallel erasing, and single-device erasing.

[0021] The two-dimensional flash memory array device compatible with commercial CMOS circuits involved in the present invention, namely the cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration, has the following structure: a CMOS circuit; an isolation layer and vias located on the surface of the CMOS circuit; a gate electrode and a gate connection wire located on the surface of the isolation layer and connected to the vias; a first dielectric layer covering the gate electrode, the isolation layer and the vias as a barrier layer; a floating gate on the surface of the first dielectric layer corresponding to the position of the gate electrode; a second dielectric layer covering the floating gate and the first dielectric layer as a tunneling layer; a channel layer located on the surface of the second dielectric layer; a source electrode, a drain electrode and corresponding connection wires located on the channel layer and connected to the vias. For the gate electrode, the source electrode and the drain electrode connection wires, they need to be connected to the vias of the CMOS circuit, and at the same time, according to the structure of the two-dimensional flash memory array (such as NAND structure or NOR structure), the corresponding metal traces are arranged.

[0022] Further:

[0023] The gate electrode material is selected from one of Cr, Ti, Sb, Au, Pt and any combination thereof;

[0024] The material of the first dielectric layer is HfO2 with a thickness of 15-30 nanometers;

[0025] The floating gate material is Pt with a thickness of 1-5 nanometers;

[0026] The material of the second dielectric layer is HfO2 with a thickness of 8-15 nanometers;

[0027] The gate channel layer material is selected from one of MoS2, WS2, WSe2 and any combination thereof;

[0028] The source electrode and drain electrode materials are selected from one of Cr, Ti, Sb, Au, Pt and any combination thereof;

[0029] The interconnection method for the monolithic integration of two-dimensional flash memory and CMOS circuits involved in the present invention is specifically as follows: in the connection of the upper and lower layer systems, due to problems such as process, node and material mismatches, which lead to problems such as process pollution and wire delay affecting communication, system interconnection operations need to be carried out after the CMOS wafer is processed and before the two-dimensional flash memory array is grown; specifically including:

[0030] (1) Grow an isolation layer on the surface of the CMOS circuit and reserve vias through photolithography technology or hard mask technology;

[0031] (2) Perform surface planarization on the isolation layer; specifically, provide a relatively flat preparation substrate for the upper-layer two-dimensional flash memory to improve the growth quality of the two-dimensional flash memory;

[0032] (3) Before integrating the two-dimensional flash memory array, perform a pre-cleaning process on the CMOS substrate to further ensure the atomic-level flatness of the CMOS substrate;

[0033] (4) Perform metal filling on the vias between the CMOS and the two-dimensional flash memory array; the filling metal includes but is not limited to metal materials such as Au, Cr, and Cu.

[0034] Furthermore:

[0035] The isolation layer is one of silicon nitride, silicon oxide, and their combinations;

[0036] The surface planarization process is CMP;

[0037] The pre-cleaning process includes: an ultrasonic bath lifting process, soaking in a solution such as acetone for several hours, spin-coating photoresist and soaking in the solution to remove the photoresist, and any combination thereof.

[0038] The test method for the cross-platform heterogeneous system involved in the present invention specifically includes the following steps:

[0039] (1) Package the prepared heterogeneous system. The packaging method can be DIP packaging.

[0040] (2) Before testing, place the packaged heterogeneous system chip into a test socket compatible with the corresponding packaging.

[0041] (3) Turn on the power and connect the waveform generator and the DC power supply to the test system. The waveform generator provides the clock signal for the system, and the DC power supply provides the DC signal required for the test chip. The waveform generator and the DC power supply can also be built into the heterogeneous system using a phase-locked loop and a voltage pump.

[0042] (4) Connect the host to the field-programmable gate array (FPGA) in the test system. The FPGA transmits the commands of the host to the input port of the heterogeneous system.

[0043] The two-dimensional flash memory / CMOS monolithic integrated cross-platform heterogeneous system provided by the present invention realizes a good combination of heterogeneous architectures; the present invention solves technical problems such as the mismatch of technical nodes when the two parts are closely combined, process pollution caused by heterogeneous integration, and conflicts in circuit architecture reorganization. In the present invention, on the one hand, the CMOS circuit utilizes the high-speed read and write characteristics of the two-dimensional flash memory to increase the clock speed of the CMOS circuit and improve the working efficiency of future chips; on the other hand, the two-dimensional flash memory utilizes the mature and efficient logic circuit of the CMOS circuit to optimize the peripheral read circuit of the two-dimensional flash memory. This system combines the high-performance two-dimensional flash memory prepared in the laboratory with the commercial CMOS circuit, promoting the process of the two-dimensional flash memory from the laboratory to the industrial community. Brief Description of the Drawings

[0044] Figure 1 Design flow chart of a heterogeneous system for two-dimensional flash memory / CMOS monolithic integration.

[0045] Figure 2 Schematic diagram of the structure of a two-dimensional flash memory device.

[0046] Figure 3 Schematic diagram of the two-dimensional flash memory array structure.

[0047] Figure 4 Schematic diagram of the interconnection of two-dimensional flash memory and CMOS circuits for monolithic integration.

[0048] Figure 5 Testing system for a heterogeneous system of two-dimensional flash memory / CMOS monolithic integration.

[0049] Reference numerals in the figure: 1 is the via label, 2 is the gate label, 3 - 5 are the storage stack materials: 3 is HfO2, 4 is Pt, 5 is HfO2, 6 is MoS2, 8 is the isolation layer, 10 is the two-dimensional flash memory array, 11 is the DC power supply, 12 is the waveform generator, 13 is the host computer, 14 is the FPGA system, 15 is the cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration, and the reference numerals 16 - 18 represent data and supply current, respectively representing that 16 provides a DC voltage, 17 provides a clock signal, and 18 provides an operation instruction. Detailed implementation manners

[0050] The present invention will be further introduced below through embodiments in conjunction with the accompanying drawings.

[0051] In this embodiment, molybdenum disulfide material is selected as the 1Kb NOR array of the channel, which is a two-dimensional flash memory array.

[0052] Many specific details are provided in the following description, such as the structure, materials, dimensions, processing technology, etc. of the device. However, as those of ordinary skill in the art can understand, the present invention can be implemented without following these specific details. Unless specifically pointed out below, each part of the device can be composed of materials well-known to those skilled in the art.

[0053] Figure 1 Shows the design flow of a cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration. Specifically, it includes:

[0054] (1) Determine the scale and structure of the two-dimensional flash memory array: A 1Kb scale two-dimensional flash memory NOR array is adopted, and its basic programming / erasing voltage and pulse width are (±14V, 100ns) respectively. When reading, the voltages are: gate turn-on voltage 0V, turn-off voltage -2V, and source-drain voltage difference 1V.

[0055] (2) Design the CMOS circuit and perform a co-fabrication: The operations performed by the CMOS peripheral circuit are: parallel access of the two-dimensional flash memory array, single-device data reading; row-by-row data programming; full-chip data erasure function.

[0056] (3) Prepare the interconnection layer for the monolithic integration of the two-dimensional flash memory and the CMOS circuit.

[0057] (4) Fabricate the two-dimensional flash memory array on the chip.

[0058] (5) Package the heterogeneous system and test it using a dedicated chip test system.

[0059] Figure 2 and Figure 3 shows the structural schematic diagram and the array structure diagram of the two-dimensional flash memory array device compatible with commercial CMOS circuits.

[0060] The structure of the two-dimensional flash memory array device compatible with commercial CMOS circuits of the present invention is described as follows. Device structure: The gate electrode and the gate connection wire (a combination of Cr and Au metals) are located on the surface of the isolation layer and are connected to the via hole; the first dielectric layer (15-nanometer-thick HfO2) covers the gate electrode, the isolation layer, and the via hole and serves as a barrier layer; the floating gate (1-nanometer-thick Pt metal) is on the surface of the first dielectric layer and corresponds to the position of the gate electrode; the second dielectric layer (8-nanometer-thick HfO2) covers the floating gate and the first dielectric layer and serves as a tunneling layer; the channel layer is located on the surface of the second dielectric layer; the source electrode, the drain electrode, and the corresponding connection wires (a combination of Cr and Au metals) are located on the channel layer and are connected to the via hole. Device array structure: The 1Kb NOR flash memory structure is formed by connecting 32 * 32 single devices through wires.

[0061] Figure 4 shows the interconnection method for the monolithic integration of the two-dimensional flash memory and the CMOS circuit, specifically including:

[0062] (1) Grow a PA isolation layer on the surface of the CMOS circuit and retain the via hole through photolithography technology;

[0063] (2) Perform CMP (chemical mechanical polishing, a surface planarization process) on the isolation layer;

[0064] (3) Perform a pre-cleaning process on the CMOS substrate, including an ultrasonic bath lifting process (45 s), soaking in solutions such as acetone for 12 hours, spin-coating photoresist, and soaking in a solution to remove the photoresist;

[0065] (4) Fill the via hole between the CMOS and the two-dimensional flash memory array with metal (a combination of Cr and Au metals);

[0066] Figure 5 shows the test system for the cross-platform heterogeneous system. The specific test steps are as follows:

[0067] (1) Perform DIP packaging on the prepared heterogeneous system.

[0068] (2) Before testing, place the packaged heterogeneous system chip into a test socket compatible with DIP packaging.

[0069] (3) Turn on the power supply and connect the waveform generator and DC power supply to the test system. The waveform generator ((33120A, Agilent)) provides the clock signal for the system, and the DC power supply (DSOX1204A, Keysight) provides the DC signal required for testing the chip. The waveform generator and DC power supply can also be built into the heterogeneous system using a phase-locked loop and a voltage pump.

[0070] (4) Connect the host to the field-programmable gate array (FPGA) in the test system. The FPGA transmits the commands of the host to the input port of the heterogeneous system.

[0071] (5) The host sends instructions for reading, parallel programming, and full-chip erasure of the two-dimensional flash memory array, and counts the yield of the two-dimensional flash memory array.

[0072] Experiments show that the entire system can operate well, and the overall yield of the two-dimensional flash memory array reaches 94.34%.

[0073] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A two-dimensional flash memory / CMOS monolithic integrated cross-platform heterogeneous system, characterized in that It is monolithically integrated by a two-dimensional flash memory array and a CMOS peripheral circuit. The CMOS is used as the peripheral circuit of the two-dimensional flash memory array, and the two are tightly combined at the device-level granularity. Specifically, it is divided into upper and lower layers. The upper layer is the two-dimensional flash memory array, and the lower layer is the CMOS circuit. The two are interconnected through TGVs. And the CMOS circuit effectively controls the two-dimensional flash memory array through a modular communication method. It is specifically obtained through the following steps: (1) Determine the scale and structure of the two-dimensional flash memory array: including designing the device scale, device programming method, device performance, and circuit structure of the two-dimensional flash memory; (2) Design the CMOS circuit and perform a wafer run: The CMOS, as the peripheral circuit of the two-dimensional flash memory array, performs data reading, programming, and erasing operations applicable to the two-dimensional flash memory array; (3) Monolithically integrate and interconnect the two-dimensional flash memory array and the CMOS circuit; (4) Fabricate the on-chip two-dimensional flash memory array; (5) Package the heterogeneous system and use a dedicated chip test system.

2. The cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration according to claim 1, wherein: The device programming method is one of FN tunneling programming / erasing, hot electron programming / erasing, and any combination thereof; For the device programming, the voltage and programming speed are ±14V and 500 ns respectively; The device circuit structure is one of NOR and NAND; For the data reading operation of the two-dimensional flash memory array, it supports both parallel reading and single-device reading; For the data programming operation of the two-dimensional flash memory array, it supports both parallel programming and single-device programming; For the data erasing operation of the two-dimensional flash memory array, it supports full-chip erasing, parallel erasing, and single-device erasing.

3. The two-dimensional flash memory / CMOS monolithic integrated cross-platform heterogeneous system according to claim 1, characterized in that, Its structure includes: a CMOS circuit; an isolation layer and vias on the surface of the CMOS circuit; a gate electrode and a gate connection wire on the surface of the isolation layer, and connected to the vias; a first dielectric layer covering the gate electrode, isolation layer, and vias, serving as a barrier layer; a floating gate on the surface of the first dielectric layer corresponding to the position of the gate electrode; a second dielectric layer covering the floating gate and the first dielectric layer, serving as a tunneling layer; a channel layer on the surface of the second dielectric layer; a source electrode, a drain electrode, and corresponding connection wires on the channel layer, and connected to the vias; for the gate electrode, source electrode, and drain electrode connection wires, they are connected to the vias of the CMOS circuit, and at the same time, according to the structure of the two-dimensional flash memory array, there are corresponding metal traces.

4. The cross-platform heterogeneous system of two-dimensional flash memory / CMOS monolithic integration according to claim 3, wherein: The gate electrode material is selected from Cr, Ti, Sb, Au, Pt; The material of the first dielectric layer is HfO2, and the thickness is 15 - 30 nanometers; The material of the floating gate is Pt, and the thickness is 1 - 5 nanometers; The material of the second dielectric layer is HfO2, and the thickness is 8 - 15 nanometers; The material of the gate channel layer is selected from MoS2, WS2, WSe2; The source electrode and drain electrode materials are selected from Cr, Ti, Sb, Au, Pt.

5. The two-dimensional flash memory / CMOS monolithic integrated cross-platform heterogeneous system according to claim 4, characterized in that The interconnection method for monolithic integration of the two-dimensional flash memory and CMOS circuit is specifically as follows: After the CMOS is fabricated, system interconnection operations are performed before the two-dimensional flash memory array is grown; specifically including: (1) A isolation layer is grown on the surface of the CMOS circuit, and vias are reserved through photolithography technology or hard mask technology; (2) The surface of the isolation layer is planarized; to improve the growth quality of the two-dimensional flash memory; (3) Before integrating the two-dimensional flash memory array, the CMOS substrate is pre-cleaned to further ensure the atomic-level flatness of the CMOS substrate; (4) The vias between the CMOS and the two-dimensional flash memory array are filled with metal.

6. The cross-platform heterogeneous system for monolithic integration of two-dimensional flash memory / CMOS according to claim 5, wherein the isolation layer is one of silicon nitride, silicon oxide or a combination thereof; the surface planarization process is CMP; the pre-cleaning treatment includes: an ultrasonic bath lifting process, soaking in an acetone solution, spin-coating photoresist and soaking in a solution to remove the photoresist, or any combination thereof; the filling metal is selected from Au, Cr, Cu.

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