Semiconductor device, preparation method thereof and storage system
By dividing the connection structure into three sections and using two sections of deep hole etching, and using conductive pads as stop layer, the problem of difficult etching process in three-dimensional memory is solved, and the reliability and efficiency of the connection structure are improved.
Patent Information
- Application Number
- CN202410107790.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-24
- Publication Date
- 2025-07-25
Smart Images
Figure CN120379262A_ABST
Abstract
Description
Technical Field
[0001] This application generally relates to the field of electronic devices, and more specifically, to a semiconductor device, a method for manufacturing the same, and a storage system. Background Art
[0002] In three-dimensional memories, a control circuit is combined with a storage structure to control read and write operations of the storage structure. In order to lead out the control circuit and connect it to an external circuit, the configuration of the connection structure often causes difficulties in various processes. Therefore, how to design a better connection structure has always been a problem in the industry.
[0003] Summary of the Application
[0004] The purpose of this application is to provide a semiconductor device, a method for manufacturing the same, and a storage system, aiming to reduce the etching process difficulty of the connection structure.
[0005] In a first aspect, this application provides a semiconductor device, which includes:
[0006] A transistor array;
[0007] A storage array located on one side of the transistor array along a first direction;
[0008] A connection structure including a first connection structure, a conductive pad, and a second connection structure connected along the first direction, where the first connection structure is located at the periphery of the storage array, the second connection structure is located at the periphery of the transistor array, and the conductive pad is located between the first connection structure and the second connection structure.
[0009] In some embodiments, the semiconductor device further includes:
[0010] An internal lead contact located on a side of the transistor array away from the storage array;
[0011] Wherein, one end of the second connection structure away from the first connection structure is flush with one end of the internal lead contact away from the transistor array.
[0012] In some embodiments, the semiconductor device further includes:
[0013] Virtual semiconductor pillars spaced apart from each other at the periphery of the transistor array;
[0014] Wherein, the second connection structure is located in a space between the virtual semiconductor pillars.
[0015] In some embodiments, the storage array includes:
[0016] Capacitor structures arranged in an array;
[0017] A conductive layer covering the surface of the capacitive structure and the side of the dummy semiconductor pillar close to the capacitive structure, the conductive layer including a connected first conductive layer, a second conductive layer, and a third conductive layer, the first conductive layer being located on the side of the capacitive structure away from the transistor array, the second conductive layer being located on the side surface of the capacitive structure, and the third conductive layer being located on the side of the dummy semiconductor pillar close to the capacitive structure;
[0018] Wherein, the conductive pad is arranged at the same layer and spaced apart from the third conductive layer, and they are made of the same material.
[0019] In some embodiments, the semiconductor device further includes:
[0020] A dielectric layer located between the transistor array and the conductive pad, and between the transistor array and the third conductive layer, and the second connection structure passes through the dielectric layer and is connected to the conductive pad.
[0021] In some embodiments, the semiconductor device further includes:
[0022] An external lead contact connected to the side of the first conductive layer away from the transistor array;
[0023] Wherein, one end of the first connection structure away from the conductive pad is flush with one end of the external lead contact away from the first conductive layer.
[0024] In some embodiments, the transistor array includes:
[0025] Semiconductor pillars arranged in an array between the internal lead contact and the storage array, the semiconductor pillars being arranged in multiple rows along a second direction perpendicular to the first direction;
[0026] A gate line structure located between adjacent rows of the semiconductor pillars and extending along the second direction;
[0027] Wherein, the internal lead contact includes a gate line lead contact and a bit line lead contact, the gate line lead contact is connected to the end of the gate line structure along the second direction, and the bit line lead contact is connected to the end of the semiconductor pillar away from the storage array.
[0028] In some embodiments, the size of the gate line lead contact along the first direction is larger than the size of the bit line lead contact along the first direction.
[0029] In some embodiments, the size of the second connection structure along the first direction is larger than the size of the gate line lead contact along the first direction.
[0030] In some embodiments, the size of the first connection structure along the first direction is greater than the size of the second connection structure along the first direction; the size of the second connection structure along the first direction is greater than the size of the conductive pad along the first direction.
[0031] In some embodiments, the first connection structure includes a first end face close to the second connection structure and a second end face far from the second connection structure, and the size of the first end face is smaller than the size of the second end face; the second connection structure includes a third end face close to the first connection structure and a fourth end face far from the first connection structure, and the size of the third end face is smaller than the size of the fourth end face.
[0032] In some embodiments, the cross-sectional area of the conductive pad in the plane direction perpendicular to the first direction is greater than the size of the first end face and greater than the size of the third end face.
[0033] In some embodiments, the semiconductor device further includes:
[0034] A control circuit, bonded to a side of the transistor array away from the memory array and connected to the connection structure.
[0035] In some embodiments, the semiconductor device further includes:
[0036] A first bonding metal layer, connected to a side of the second connection structure away from the transistor array;
[0037] A second bonding metal layer, bonded to a side of the first bonding metal layer away from the second connection structure.
[0038] In some embodiments, the semiconductor device further includes:
[0039] A first pad, connecting one end of the external lead contact away from the memory array;
[0040] A second pad, connecting one end of the first connection structure away from the second connection structure.
[0041] In some embodiments, the capacitive structure includes:
[0042] A stacked layer, including a first dielectric layer and a second dielectric layer alternately stacked along the first direction, and the thickness of the first dielectric layer along the first direction is greater than the thickness of the second dielectric layer along the first direction;
[0043] A first electrode structure, penetrating the stacked layer along the first direction, and one end of the first electrode structure close to the transistor array is connected to the semiconductor column.
[0044] A second electrode structure is located between the first electrode structure and the stacked layer. One end of the second electrode structure away from the transistor array is connected to the first conductive layer;
[0045] A dielectric layer is located between the first electrode structure and the second electrode structure.
[0046] In a second aspect, the present application provides a method for manufacturing a semiconductor device, and the method for manufacturing the semiconductor device includes:
[0047] Providing a first substrate;
[0048] Forming a transistor array in the first substrate;
[0049] Forming a storage array and a conductive pad on one side of the transistor array along a first direction;
[0050] Thinning the first substrate to expose the transistor array;
[0051] Forming a second connection structure on a side of the transistor array away from the storage array, and the second connection structure connects the conductive pad;
[0052] Forming a first connection structure connecting the conductive pad on the periphery of the storage array.
[0053] In some embodiments, the step of forming a second connection structure on a side of the transistor array away from the storage array includes:
[0054] Forming an internal lead contact and a second connection structure on a side of the transistor array away from the storage array, the internal lead contact connects the transistor array, and the second connection structure connects the conductive pad.
[0055] In some embodiments, the step of forming a transistor array in the first substrate includes:
[0056] Etching the first substrate to form array - arranged semiconductor columns and dummy semiconductor columns. The dummy semiconductor columns are located on the periphery of the semiconductor columns. The semiconductor columns are arranged in multiple rows along a second direction, and the second direction is perpendicular to the first direction;
[0057] Forming a gate line structure between adjacent two rows of the semiconductor columns. The gate line structure extends along the second direction, and a dimension of the gate line structure along the first direction is smaller than a dimension of the semiconductor column along the first direction;
[0058] Wherein, the internal lead-out contacts include gate line lead-out contacts and bit line lead-out contacts. The gate line lead-out contacts are connected to the ends of the gate line structure along the second direction, and the bit line lead-out contacts are connected to one end of the semiconductor column away from the memory array.
[0059] In some embodiments, the step of forming a memory array and conductive pads on one side of the transistor array along the first direction includes:
[0060] Forming a capacitively coupled structure arranged in an array on one side of the transistor array along the first direction;
[0061] Forming an initial conductive layer on the surface of the capacitively coupled structure and on one side of the virtual semiconductor column close to the capacitively coupled structure;
[0062] Patterning the initial conductive layer to form spaced conductive layers and conductive pads. The conductive layers include a first conductive layer, a second conductive layer, and a third conductive layer connected to each other. The first conductive layer is located on the side of the capacitively coupled structure away from the transistor array, the second conductive layer is located on the side surface of the capacitively coupled structure, and the third conductive layer is located on the side of the virtual semiconductor column close to the capacitively coupled structure. The conductive pads are arranged corresponding to the spaces between the virtual semiconductor columns.
[0063] In some embodiments, the method for manufacturing the semiconductor device further includes:
[0064] Forming a dielectric layer between the transistor array and the conductive pads, and the second connection structure passes through the dielectric layer and is connected to the conductive pads.
[0065] In some embodiments, the step of forming a first connection structure connecting the conductive pads on the periphery of the memory array includes:
[0066] Connecting the control circuit to the internal lead-out contacts and the second connection structure through a bonding metal layer;
[0067] Forming an external lead-out contact and a first connection structure on the side of the memory array and the first connection structure away from the transistor array. The external lead-out contact is connected to the first conductive layer, and the first connection structure is connected to the conductive pads.
[0068] In some embodiments, the method for manufacturing the semiconductor device further includes:
[0069] Forming a first pad at one end of the external lead-out contact away from the memory array;
[0070] Forming a second pad at one end of the first connection structure away from the conductive pads.
[0071] In some embodiments, the step of forming an array - arranged capacitive structure on one side of the transistor array along a first direction includes:
[0072] Forming a stacked layer on one side of the transistor array along the first direction, the stacked layer includes a first dielectric layer and a second dielectric layer alternately stacked along the first direction, and the thickness of the first dielectric layer along the first direction is greater than the thickness of the second dielectric layer along the first direction;
[0073] Forming a first electrode structure penetrating the stacked layer along the first direction, and one end of the first electrode structure close to the transistor array is connected to the semiconductor column;
[0074] Forming a second electrode structure located between the first electrode structure and the stacked layer, and one end of the first conductive layer away from the transistor array is connected to the second electrode structure;
[0075] Forming a dielectric layer located between the first electrode structure and the second electrode structure.
[0076] In a third aspect, the present application provides a storage system, including:
[0077] The semiconductor device in any of the above - mentioned embodiments;
[0078] A controller, the controller is connected to the semiconductor device and is used to control the semiconductor device to store data.
[0079] The present application provides a semiconductor device, a preparation method thereof, and a storage system. The semiconductor device includes a transistor array, a storage array, and a connection structure. The storage array is located on one side of the transistor array along a first direction. The connection structure includes a first connection structure, a conductive pad, and a second connection structure connected along the first direction. The first connection structure is located on the periphery of the storage array, the second connection structure is located on the periphery of the transistor array, and the conductive pad is located between the first connection structure and the second connection structure. The present application divides the connection structure into three segments, and only two segments (the first connection structure and the second connection structure) require deep - hole etching, which can reduce the depth of one - time etching and the difficulty of the etching process. And the conductive pad can be used as a stop layer for forming the first connection structure and a stop layer for forming the second connection structure, further reducing the difficulty of the etching process and increasing the process window. BRIEF DESCRIPTION OF THE DRAWINGS
[0080] The following combines the drawings and details the specific implementation manners of the present application, and the technical solutions and other beneficial effects of the present application will be obvious.
[0081] Figure 1 is a schematic structural diagram of a semiconductor device provided by some embodiments of the present application;
[0082] Figure 2 is a schematic structural diagram of a storage array provided by some embodiments of the present application;
[0083] Figure 3 is a schematic flow diagram of a method for manufacturing a semiconductor device provided by some embodiments of the present application;
[0084] Figures 4a - 4h is a schematic structural diagram of a semiconductor device during the manufacturing process provided by some embodiments of the present application;
[0085] Figure 5 is a schematic structural diagram of a storage system provided by some embodiments of the present application. Detailed implementation manners
[0086] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present application.
[0087] It should be understood that although terms such as first and second can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. For example, the first component can be called the second component, and similarly, the second component can be called the first component without departing from the scope of the present application.
[0088] It should be understood that when a component is said to be "on" another component or "connected" to another component, it can be directly on the other component or connected to the other component, or there can also be an inserted component. Other words used to describe the relationship between components should be interpreted in a similar manner.
[0089] As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. A layer can extend over the entire underlying or overlying structure, or can have a range smaller than the range of the underlying or overlying structure. In addition, a layer can be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, which can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductive layers and contact layers (where contacts, interconnect lines, and / or vertical interconnections (VIAs) are formed) and one or more dielectric layers.
[0090] It should be noted that the diagrams provided in the embodiments of the present application only illustrate the basic concept of the present application in a schematic manner. Although only the components related to the present application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation, the types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0091] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a semiconductor device provided in some embodiments of the present application. The semiconductor device 100 can be a wafer or a 3D memory, or a part of a 3D memory. The 3D memory can be applied to communication products, consumer electronic products, automotive products, aerospace products, artificial intelligence products, or big data, etc. Among them, consumer electronic products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses, or gaming products, etc.
[0092] The semiconductor device 100 includes a transistor array 10, a memory array 20, and a connection structure 30. The memory array 20 is located on one side of the transistor array 10 along the first direction (X). The connection structure 30 includes a first connection structure 31, a conductive pad 32, and a second connection structure 33 connected along the first direction (X). The first connection structure 31 is located on the periphery of the memory array 20, the second connection structure 33 is located on the periphery of the transistor array 10, and the conductive pad 32 is located between the first connection structure 31 and the second connection structure 33.
[0093] In some embodiments, since the first connection structure 31 is located on the periphery of the memory array 20, the second connection structure 33 is located on the periphery of the transistor array 10, and the size of the memory array 20 along the first direction (X) is greater than the size of the transistor array 10 along the first direction (X), the size of the first connection structure 31 along the first direction (X) is greater than the size of the second connection structure 33 along the first direction (X).
[0094] In some embodiments, the conductive pad 32 can not only serve as a stop layer for forming the first connection structure 31 and the second connection structure 33, but also serve as a connection layer between the first connection structure 31 and the second connection structure 33. Among them, the size of the second connection structure 33 along the first direction (X) is greater than the size of the conductive pad 32 along the first direction (X).
[0095] In some embodiments, the first connection structure 31 includes a first end face (bottom face) close to the second connection structure 33 and a second end face (top face) far from the second connection structure 33, and the size of the first end face is smaller than that of the second end face. Specifically, the cross-sectional area of the first connection structure 31 gradually increases from the first end face to the second end face. Herein, the "cross-sectional area" refers to the cross-sectional area in the plane direction perpendicular to the first direction (X).
[0096] The second connection structure 33 includes a third end face (top face) close to the first connection structure 31 and a fourth end face (bottom face) far from the first connection structure 31, and the size of the third end face is smaller than that of the fourth end face. Specifically, the cross-sectional area of the second connection structure 33 gradually increases from the third end face to the fourth end face.
[0097] In some embodiments, the cross-sectional area of the conductive pad 32 in the plane direction perpendicular to the first direction (X) is larger than the size of the first end face and larger than the size of the third end face, so that the first connection structure 31 and the second connection structure 33 can be located on the conductive pad 32.
[0098] In some embodiments, the transistor array 10 includes semiconductor columns 11 and gate line structures 12. The semiconductor columns 11 extend along the first direction (X) and are arranged in multiple rows along the second direction (Y), and the second direction (Y) is perpendicular to the first direction (X). Specifically, the semiconductor columns 11 are arranged in an array along the second direction (Y) and the third direction (Z), and the third direction (Z) is perpendicular to the first direction (X) and the second direction (Y). Among them, multiple semiconductor columns 11 are arranged in rows along the second direction (Y), and multiple semiconductor columns 11 are arranged in columns along the third direction (Z).
[0099] The gate line structure 12 is located between two adjacent rows of the semiconductor columns 11 in the third direction (Z) and extends along the second direction (Y). Since Figure 1 it is a sectional view, the position of the gate line structure 12 is represented by a dashed line. In some embodiments, the size of the gate line structure 12 along the first direction (X) is smaller than the size of the semiconductor column 11 along the first direction (X).
[0100] Among them, the material of the semiconductor column 11 may include silicon or polysilicon. The gate line structure 12 may include a gate and a gate insulating layer, and the gate insulating layer is located between the semiconductor column 11 and the gate.
[0101] In some embodiments, the semiconductor device 100 may further include a virtual semiconductor pillar 13, which is disposed at intervals around the transistor array 10 or the semiconductor pillar 11 and is made of the same material as the semiconductor pillar 11. The difference between the semiconductor pillar 11 and the virtual semiconductor pillar 13 is that the semiconductor pillar 11 has electrical connections, while the virtual semiconductor pillar 13 has no electrical connections.
[0102] Wherein, the second connection structure 33 may be located in the interval between the virtual semiconductor pillars 13.
[0103] In some embodiments, the semiconductor device 100 further includes an internal lead contact 40, which is located on the side of the transistor array 10 away from the memory array 20. Specifically, the semiconductor pillar 11 is arranged in an array between the internal lead contact 40 and the memory array 20. Wherein, the internal lead contact 40 includes a gate line lead contact 41 and a bit line lead contact 42. The gate line lead contact 41 is connected to the end of the gate line structure 12 along the second direction (Y), and the bit line lead contact 42 is connected to one end of the semiconductor pillar 11 away from the memory array 20.
[0104] In some embodiments, one end of the gate line lead contact 41 away from the transistor array 10 may be flush with one end of the bit line lead contact 42 away from the transistor array 10, and the dimension of the gate line lead contact 41 along the first direction (X) is greater than the dimension of the bit line lead contact 42 along the first direction (X).
[0105] In some embodiments, the dimension of the second connection structure 33 along the first direction (X) is greater than the dimension of the gate line lead contact 41 along the first direction (X).
[0106] In some embodiments, one end of the second connection structure 33 away from the first connection structure 31 is flush with one end of the internal lead contact 40 away from the transistor array 10. It should be noted that in the case where the internal lead contact 40 and the second connection structure 33 are formed together and planarized, one end of the second connection structure 33 away from the first connection structure 31 may be flush with one end of the internal lead contact 40 away from the transistor array 10. Due to process influences, the above two ends may not be flush, and the present application does not limit this.
[0107] In some embodiments, the storage array 20 includes a capacitively structured array 21 and a conductive layer 22 covering the surface of the capacitive structure 21 and the side of the virtual semiconductor pillar 13 close to the capacitive structure 21. The conductive layer 22 includes a first conductive layer 221, a second conductive layer 222, and a third conductive layer 223 connected in sequence. The first conductive layer 221 is located on the side of the capacitive structure 21 away from the transistor array 10, the second conductive layer 222 is located on the side of the capacitive structure 21, and the third conductive layer 223 is located on the side of the virtual semiconductor pillar 13 close to the capacitive structure 21. Among them, the material of the conductive layer 22 may include tungsten.
[0108] In some embodiments, the conductive pad 32 is arranged at the same layer and spaced apart from the third conductive layer 223, and has the same material. Therefore, in the manufacturing process, the material can be patterned to form the conductive layer 22 and the conductive pad 32 together, that is, the preparation of the conductive pad 32 does not require adding new processes and masks.
[0109] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of a storage array provided by some embodiments of the present application.
[0110] The capacitive structure 21 may include a stacked layer 211, a first electrode structure 212, a second electrode structure 213, and a dielectric layer 214. In some embodiments, the stacked layer 211 includes a first dielectric layer 2111 and a second dielectric layer 2112 alternately stacked along the first direction (X). The thickness of the first dielectric layer 2111 along the first direction (X) is greater than the thickness of the second dielectric layer 2112 along the first direction (X). Among them, the first dielectric layer 2111 may be silicon oxide, and the second dielectric layer 2112 may be silicon nitride.
[0111] In some embodiments, the stacked layer 211 may only include the first dielectric layer 2111 in some regions, and the stacked layer 211 is alternately stacked with the first dielectric layer 2111 and the second dielectric layer 2112 in other regions. The second dielectric layer 2112 may act as a framework to provide support during the manufacturing process in the stacked layer 211.
[0112] The first electrode structure 212 penetrates through the stacked layer 211 along the first direction (X), and one end (the lower end) of the first electrode structure 212 close to the transistor array 10 is connected to the semiconductor column 11. The second electrode structure 213 is located between the first electrode structure 212 and the stacked layer 211, and one end (the upper end) of the second electrode structure 213 far from the transistor array 10 is connected to the first conductive layer 221. The dielectric layer 214 is located between the first electrode structure 212 and the second electrode structure 213 to play an insulating role. Therefore, the first electrode structure 212 and the second electrode structure 213 form two plates of a capacitor.
[0113] In some embodiments, the first electrode structure 212 may include a first filling layer 2121 and a first electrode 2122 surrounding the first filling layer 2121. The first filling layer 2121 may include polysilicon, and the first electrode 2122 may include tantalum carbide. The second electrode structure 213 may include a second electrode 2131. The second electrode 2131 may include tantalum carbide, and the dielectric layer 214 surrounds the second electrode 2131. The dielectric layer 214 may include a high-K dielectric layer (such as alumina). Among them, the first electrode 2122 is connected to the semiconductor column 11, and the second electrode 2131 is connected to the conductive layer 22.
[0114] Please continue to refer to Figure 1 , the semiconductor device 100 may further include a dielectric layer 50. The dielectric layer 50 is located between the transistor array 10 and the conductive pad 32, and between the transistor array 10 and the third conductive layer 223. And the second connection structure 33 passes through the dielectric layer 50 and is connected to the conductive pad 32. Among them, the dielectric layer 50 located between the transistor array 10 and the conductive pad 32 may also serve as a stop layer for the second connection structure 33, and this stop layer can be formed during the preparation process of the dielectric layer 50 without adding a new manufacturing process.
[0115] In some of these embodiments, the dielectric layer 50 is also located between the transistor array 10 and the capacitor structure 21. The semiconductor device 100 may further include a contact (not shown) in the dielectric layer 50 for connecting the semiconductor column 11 and the first electrode structure 212.
[0116] The semiconductor device 100 further includes an external lead contact 60. The external lead contact 60 is connected to a side of the first conductive layer 221 far from the transistor array 10 for leading out the second electrode structure 213.
[0117] In some embodiments, one end of the first connection structure 31 far from the conductive pad 32 is flush with one end of the external lead contact 60 far from the first conductive layer 221.
[0118] It should be noted that when the external lead contact 60 and the first connection structure 31 are formed together and planarized, the end of the first connection structure 31 away from the second connection structure 33 can be flush with the end of the external lead contact 60 away from the first conductive layer 221. Due to process effects, the above two ends in the semiconductor device 100 may not be flush, and the present application does not limit this.
[0119] In some embodiments, the semiconductor device 100 further includes a control circuit 70, which is bonded to the side of the transistor array 10 away from the storage array 20 and is connected to the connection structure 30.
[0120] Specifically, the semiconductor device 100 further includes a first bonding metal layer 81 and a second bonding metal layer 82. The first bonding metal layer 81 is connected to the side of the second connection structure 33 away from the transistor array 10, and the second bonding metal layer 82 is bonded to the side of the first bonding metal layer 81 away from the second connection structure 33. Therefore, the second connection structure 33 is connected to the control circuit 70 through the first bonding metal layer 81 and the second bonding metal layer 82.
[0121] In some embodiments, the semiconductor device 100 further includes a first pad 91 and a second pad 92. The first pad 91 is connected to the end of the external lead contact 60 away from the storage array 20, and the second pad 92 is connected to the end of the first connection structure 31 away from the second connection structure 33. The first pad 91 can connect the external lead contact 60 to an external circuit, and the second pad 92 can connect the first connection structure 31 to an external circuit, that is, connect the control circuit 70 to an external circuit.
[0122] The semiconductor device 100 provided by the embodiments of the present application includes a transistor array 10, a storage array 20, and a connection structure 30. The storage array 20 is located on one side of the transistor array 10 along the first direction (X). The connection structure 30 includes a first connection structure 31, a conductive pad 32, and a second connection structure 33 connected along the first direction (X). The first connection structure 31 is located on the periphery of the storage array 20, the second connection structure 33 is located on the periphery of the transistor array 10, and the conductive pad 32 is located between the first connection structure 31 and the second connection structure 33. The present application divides the connection structure 30 into three segments, and only two segments (the first connection structure 21 and the second connection structure 33) require deep hole etching, which can reduce the depth of a single etching and the difficulty of the etching process. And the conductive pad 32 can be used as a stop layer for forming the first connection structure 31 and a stop layer for forming the second connection structure 33, further reducing the difficulty of the etching process and increasing the process window.
[0123] Please refer to Figure 3, Figure 3 is a schematic flow chart of a method for manufacturing a semiconductor device provided in some embodiments of the present application. Please refer to Figures 4a - 4h , Figures 4a - 4h is a schematic structural diagram of a semiconductor device during manufacturing in some embodiments of the present application. In this embodiment, taking the manufacturing of the above semiconductor device 100 as an example, the method for manufacturing the semiconductor device will be described. Therefore, please refer to Figure 1 and Figure 2 , and the method for manufacturing the semiconductor device includes the following steps S1 - S6.
[0124] Step S1: Provide a first substrate 101.
[0125] As shown in Figure 4a , the first substrate 101 can be silicon or polysilicon, and the first substrate 101 has the same material as the subsequent formed semiconductor pillar 11.
[0126] Step S2: Form a transistor array 10 in the first substrate 101.
[0127] Specifically, step S2 may include the following steps.
[0128] 1) As shown in Figure 4a , etch the first substrate 101 to form array - arranged semiconductor pillars 11 and dummy semiconductor pillars 13. The dummy semiconductor pillars 13 are located on the periphery of the semiconductor pillars 11. The semiconductor pillars 11 are arranged in multiple rows along the second direction (Y), and the second direction (Y) is perpendicular to the first direction (X). Among them, the second direction (Y) is the row direction.
[0129] 2) As shown in Figure 4b , form a gate line structure 12 between two adjacent rows of the semiconductor pillars 11. The gate line structure 12 extends along the second direction (Y), and the dimension of the gate line structure 12 along the first direction (X) is smaller than the dimension of the semiconductor pillar 11 along the first direction (X).
[0130] Among them, an insulating layer is filled between the semiconductor pillars 11, between the dummy semiconductor pillars 13, and between the semiconductor pillars 11 and the dummy semiconductor pillars 13.
[0131] Step S3: Form a memory array 20 and a conductive pad 32 on one side of the transistor array 10 along the first direction (X).
[0132] Specifically, step S3 may include the following steps.
[0133] 1) As shown in Figure 4c , form array - arranged capacitor structures 21 on one side of the transistor array 10 along the first direction (X).
[0134] In some embodiments, it may be combined with Figure 2 , first form a stacked layer 211 on one side of the transistor array 10 along the first direction (X). The stacked layer 211 includes a first dielectric layer 2111 and a second dielectric layer 2112 that are alternately stacked along the first direction (X). The thickness of the first dielectric layer 2111 along the first direction (X) is greater than the thickness of the second dielectric layer 2112 along the first direction (X). Then, form a first electrode structure 212 that penetrates the stacked layer 211 along the first direction (X). One end of the first electrode structure 212 close to the transistor array 10 is connected to the semiconductor column 11. Next, form a second electrode structure 213 located between the first electrode structure 212 and the stacked layer 211. Finally, form a dielectric layer 214 located between the first electrode structure 212 and the second electrode structure 213.
[0135] Specifically, after forming the stacked layer 211, first form a first electrode hole 2122T through an etching process, and form a first electrode structure 212 in the first electrode hole 2122T (for example, sequentially deposit tantalum carbide and polysilicon). The bottom of the first electrode structure 212 is exposed for connection to the semiconductor column 11. Then, remove a part of the stacked layer 211 outside the first electrode structure 212 to form a cavity around the first electrode structure 212, and sequentially form a dielectric layer 214 and a second electrode structure 213 in the cavity (for example, sequentially deposit a high-K dielectric layer and tantalum carbide).
[0136] In some embodiments, in the process of removing a part of the stacked layer 211 outside the first electrode structure 212, the second dielectric layer 2112 can be spaced and perforated so that the etching solution can contact the first dielectric layer 2111 to remove the first dielectric layer 2111. The second dielectric layer 2112 remains at the unperforated positions, thereby playing a role in supporting the overall structure when the first dielectric layer 2111 is removed. After forming the second electrode structure 213, the first dielectric layer 2111 (such as silicon oxide) can be filled again. Therefore, in Figure 2 the displayed capacitor structure 21, the second electrode structure 213 can also be completely filled with the first dielectric layer 2111. That is to say, in the finally formed capacitor structure 21, there is no second dielectric layer 2112 in the area corresponding to the perforation of the stacked layer 211, and only includes the first dielectric layer 2111. The area corresponding to the unperforated part of the stacked layer 211 has the first dielectric layer 2111 and the second dielectric layer 2112.
[0137] In some embodiments, in the process of forming the first electrode structure 212, an insulating layer can be formed on the top of the first electrode structure 212 so that the subsequent formed conductive layer 22 will not be connected to the first electrode structure 212.
[0138] 2) Form an initial conductive layer on the surface of the capacitor structure 21 and on the side of the dummy semiconductor pillar 13 close to the capacitor structure 21.
[0139] 3) As Figure 4c shown, pattern the initial conductive layer to form spaced conductive layers 22 and conductive pads 32. The conductive layer 22 includes a connected first conductive layer 221, second conductive layer 222, and third conductive layer 223. The first conductive layer 221 is located on the side of the capacitor structure 21 away from the transistor array 10, the second conductive layer 222 is located on the side surface of the capacitor structure 21, and the third conductive layer 223 is located on the side of the dummy semiconductor pillar 13 close to the capacitor structure 21. The conductive pads 32 are disposed corresponding to the intervals between the dummy semiconductor pillars 13. Among them, the first conductive layer 221 is connected to the end of the second electrode structure 213 away from the transistor array 10 (in combination with Figure 2 ).
[0140] Specifically, as Figure 4c shown, an initial conductive layer (such as tungsten) can be first deposited on the surface of the capacitor structure 21 and on the side of the dummy semiconductor pillar 13 close to the capacitor structure 21, and then the initial conductive layer is patterned to form disconnected conductive layers 22 and conductive pads 32. The conductive pads 32 are located on the side of the dummy semiconductor pillar 13 close to the capacitor structure 21.
[0141] In some embodiments, the manufacturing method of the semiconductor device 100 may include: forming a dielectric layer 50 between the transistor array 10 and the conductive pads 32. When forming the second connection structure 33 subsequently, the second connection structure 33 passes through the dielectric layer 50 and is connected to the conductive pads 32.
[0142] Specifically, as Figure 4c shown, an initial dielectric layer is first formed on one side of the transistor array 10, and then the capacitor structure 21 is formed on the initial dielectric layer. During the process of patterning the initial conductive layer, the initial dielectric layer can be patterned to form a dielectric layer 50 between the conductive pads 32 and the transistor array 10.
[0143] In some embodiments, as Figure 4c shown, after forming the storage array 20, the conductive pads 32, and the dielectric layer 50, an insulating layer is covered on the storage array 20 and the conductive pads 32.
[0144] Step S4: Thin the first substrate 101 to expose the transistor array 10.
[0145] As Figure 4dAs shown, a second substrate 102 can be formed on the side of the storage array 20 away from the transistor array 10 first, and then the second substrate 102 is placed below and the first substrate 101 is placed above, and then the first substrate 101 is thinned to expose the transistor array 10.
[0146] In some embodiments, as Figure 4e shown, after the semiconductor pillar 11 is exposed, a bit line BL is formed at one end of the semiconductor pillar 11 away from the storage array 20.
[0147] Step S5: A second connection structure 33 is formed on the side of the transistor array 10 away from the storage array 20, and the second connection structure 33 connects the conductive pad 32.
[0148] In some embodiments, as Figure 4f shown, step S5 may include: forming an internal lead contact 40 and a second connection structure 33 on the side of the transistor array 10 away from the storage array 20, the internal lead contact 40 connecting the transistor array 10, and the second connection structure 33 connecting the conductive pad 32.
[0149] Specifically, an insulating layer is first formed on the bit line BL and the dummy semiconductor pillar 13, and then an etching process and a filling process are performed on the insulating layer to form the internal lead contact 40 and the second connection structure 33. The etching depth of the second connection structure 33 is greater than that of the internal lead contact 40, and the second connection structure 33 passes through the dielectric layer 50 and lands on the conductive pad 32, and the internal lead contact 40 lands on the bit line BL and the gate line structure 12.
[0150] In some embodiments, the internal lead contact 40 includes a gate line lead contact 41 and a bit line lead contact 42. The gate line lead contact 41 connects to the end of the gate line structure 12 along the second direction (Y), and the bit line lead contact 42 connects to one end of the semiconductor pillar 11 away from the storage array 20.
[0151] Step S6: A first connection structure 31 connecting the conductive pad 32 is formed around the storage array 20.
[0152] In some embodiments, step S6 may include the following steps.
[0153] 1) As Figure 4g shown, the control circuit 70 is connected to the internal lead contact 40 and the second connection structure 33 through a bonding metal layer 80. The bonding metal layer 80 includes a first bonding metal layer 81 and a second bonding metal layer 82.
[0154] The control circuit 70 can be a Complementary Metal Oxide Semiconductor (CMOS). Specifically, the CMOS is bonded to the internal lead contact 40 to control the transistor array 10, and the second connection structure 33 is bonded to the CMOS to lead out the CMOS and connect it to an external circuit.
[0155] As Figure 4g shown, after bonding, the control circuit 70 is placed below and the storage array 20 is placed above.
[0156] 2) Form an external lead contact 60 and a first connection structure 31 on the side of the storage array 20 and the first connection structure 31 away from the transistor array 10. The external lead contact 60 is connected to the first conductive layer 221, and the first connection structure 31 is connected to the conductive pad 32.
[0157] As Figure 4h shown, etch the insulating layer covering the storage array 20 to form the external lead contact 60 and the first connection structure 31. The etching depth of the first connection structure 31 is greater than that of the external lead contact 60, and the first connection structure 31 lands on the conductive pad 32, and the external lead contact 60 lands on the conductive layer 22.
[0158] The manufacturing method of the semiconductor device 100 further includes: as Figure 1 shown, form a first pad 91 at one end of the external lead contact 60 away from the storage array 20; form a second pad 92 at one end of the first connection structure 31 away from the conductive pad 32. Among them, the first pad 91 and the second pad 92 are respectively connected to different external circuits.
[0159] In the manufacturing method of the semiconductor device provided by the embodiments of the present application, the connection structure 30 is formed by two deep hole etching processes. The second connection structure 33 is formed in the etching process of forming the internal lead contact 40 for the first time, and the first connection structure 31 is formed in the etching process of forming the external lead contact 60 for the second time. This not only can reduce the etching depth of one etching to lower the etching difficulty, but also reduces the manufacturing process of the connection structure 30. The reduction of the etching depth of one etching means the reduction of the etched thickness of the film layer, then the marker recognition degree increases, and the process window is enlarged. In addition, in the etching processes of the first connection structure 31 and the second connection structure 33, the conductive pad 32 can also be used as a stop layer, further reducing the etching process difficulty.
[0160] Please refer to Figure 5 , Figure 5It is a schematic structural diagram of a storage system provided by some embodiments of the present application. The storage system 200 includes a semiconductor device 201 and a controller 202. The semiconductor device 201 can be the semiconductor device in any of the above embodiments, and the semiconductor device 201 can be prepared by the preparation method of the semiconductor device in the above embodiments. The controller 202 is connected to the semiconductor device 201 and is used to control the semiconductor device 201 to store data. The semiconductor device 201 can perform the operation of storing data based on the control of the controller 202.
[0161] In some embodiments, the storage system can be implemented as, for example, a universal flash storage (UFS) device, a solid-state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a storage device of the personal computer memory card international association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card, or a memory stick, etc.
[0162] The semiconductor device 201 includes: a transistor array; a storage array located on one side of the transistor array along a first direction; a connection structure including a first connection structure, a conductive pad, and a second connection structure connected along the first direction. The first connection structure is located on the periphery of the storage array, the second connection structure is located on the periphery of the transistor array, and the conductive pad is located between the first connection structure and the second connection structure.
[0163] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A semiconductor device, characterized in that, The semiconductor device includes: A transistor array; A memory array located on one side of the transistor array along a first direction; A connection structure including a first connection structure, a conductive pad, and a second connection structure connected along the first direction. The first connection structure is located on the periphery of the memory array, the second connection structure is located on the periphery of the transistor array, and the conductive pad is located between the first connection structure and the second connection structure.
2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: Internal lead contacts located on the side of the transistor array away from the memory array; Wherein, one end of the second connection structure away from the first connection structure is flush with one end of the internal lead contacts away from the transistor array.
3. The semiconductor device according to claim 2, wherein, The semiconductor device further includes: Virtual semiconductor columns spaced apart on the periphery of the transistor array; Wherein, the second connection structure is located in the space between the virtual semiconductor columns.
4. The semiconductor device according to claim 3, wherein, The memory array includes: Capacitor structures arranged in an array; A conductive layer covering the surface of the capacitor structures and the side of the virtual semiconductor columns close to the capacitor structures. The conductive layer includes a connected first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is located on the side of the capacitor structures away from the transistor array, the second conductive layer is located on the side of the capacitor structures, and the third conductive layer is located on the side of the virtual semiconductor columns close to the capacitor structures; Wherein, the conductive pad is arranged at the same layer and spaced apart from the third conductive layer, and they are made of the same material.
5. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: A dielectric layer located between the transistor array and the conductive pad, and between the transistor array and the third conductive layer, and the second connection structure passes through the dielectric layer to connect with the conductive pad.
6. The semiconductor device according to claim 4, wherein The semiconductor device further includes: External lead contacts connected to the side of the first conductive layer away from the transistor array; Wherein, one end of the first connection structure away from the conductive pad is flush with one end of the external lead contacts away from the first conductive layer.
7. The semiconductor device according to claim 4, wherein, The transistor array includes: Semiconductor columns arranged in an array between the internal lead contacts and the memory array. The semiconductor columns are arranged in multiple rows along a second direction, and the second direction is perpendicular to the first direction; Gate line structures located between adjacent rows of the semiconductor columns and extending along the second direction; Wherein, the internal lead contacts include gate line lead contacts and bit line lead contacts. The gate line lead contacts connect the ends of the gate line structures along the second direction, and the bit line lead contacts connect the ends of the semiconductor columns away from the memory array.
8. The semiconductor device according to claim 7, wherein The dimension of the gate line lead contacts along the first direction is larger than the dimension of the bit line lead contacts along the first direction.
9. The semiconductor device according to claim 8, wherein The dimension of the second connection structure along the first direction is larger than the dimension of the gate line lead contacts along the first direction.
10. The semiconductor device according to claim 1, wherein The dimension of the first connection structure along the first direction is larger than the dimension of the second connection structure along the first direction; the dimension of the second connection structure along the first direction is larger than the dimension of the conductive pad along the first direction.
11. The semiconductor device according to claim 1, characterized in that, The first connection structure includes a first end face close to the second connection structure and a second end face far from the second connection structure, and the size of the first end face is smaller than that of the second end face; the second connection structure includes a third end face close to the first connection structure and a fourth end face far from the first connection structure, and the size of the third end face is smaller than that of the fourth end face.
12. The semiconductor device according to claim 11, wherein, The cross-sectional area of the conductive pad in the plane direction perpendicular to the first direction is larger than the size of the first end face and larger than the size of the third end face.
13. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A control circuit, bonded to the side of the transistor array far from the memory array and connected to the connection structure.
14. The semiconductor device according to claim 13, wherein, The semiconductor device further includes: A first bonding metal layer, connected to the side of the second connection structure far from the transistor array; A second bonding metal layer, bonded to the side of the first bonding metal layer far from the second connection structure.
15. The semiconductor device according to claim 6, wherein The semiconductor device further includes: A first pad, connecting one end of the external lead contact far from the memory array; A second pad, connecting one end of the first connection structure far from the second connection structure.
16. The semiconductor device according to claim 7, characterized in that, The capacitive structure includes: A stacked layer, including a first dielectric layer and a second dielectric layer alternately stacked along the first direction, and the thickness of the first dielectric layer along the first direction is greater than that of the second dielectric layer along the first direction; A first electrode structure, penetrating the stacked layer along the first direction, and one end of the first electrode structure close to the transistor array is connected to the semiconductor column; A second electrode structure, located between the first electrode structure and the stacked layer, and one end of the second electrode structure far from the transistor array is connected to the first conductive layer; A dielectric layer, located between the first electrode structure and the second electrode structure.
17. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method of the semiconductor device includes: Providing a first substrate; Forming a transistor array in the first substrate; Forming a memory array and a conductive pad on one side of the transistor array along the first direction; Thinning the first substrate to expose the transistor array; Forming a second connection structure on the side of the transistor array far from the memory array, and the second connection structure connects the conductive pad; Forming a first connection structure connecting the conductive pad on the periphery of the memory array.
18. The method for manufacturing a semiconductor device according to claim 17, wherein, The step of forming the second connection structure on the side of the transistor array far from the memory array includes: Forming an internal lead contact and a second connection structure on the side of the transistor array far from the memory array, the internal lead contact connects the transistor array, and the second connection structure connects the conductive pad.
19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The step of forming the transistor array in the first substrate includes: Etching the first substrate to form semiconductor columns and dummy semiconductor columns arranged in an array, the dummy semiconductor columns are located on the periphery of the semiconductor columns, and the semiconductor columns are arranged in multiple rows along a second direction, and the second direction is perpendicular to the first direction; A gate line structure is formed between two adjacent rows of the semiconductor pillars. The gate line structure extends along the second direction, and the dimension of the gate line structure along the first direction is smaller than the dimension of the semiconductor pillar along the first direction. Wherein, the internal lead contacts include gate line lead contacts and bit line lead contacts. The gate line lead contacts are connected to the ends of the gate line structure along the second direction, and the bit line lead contacts are connected to one end of the semiconductor pillar away from the memory array.
20. The method for manufacturing a semiconductor device according to claim 19, wherein, The step of forming a memory array and conductive pads on one side of the transistor array along the first direction includes: Forming an array of capacitor structures on one side of the transistor array along the first direction; Forming an initial conductive layer on the surface of the capacitor structure and on one side of the virtual semiconductor pillar close to the capacitor structure; Patterning the initial conductive layer to form spaced conductive layers and conductive pads. The conductive layer includes a connected first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is located on the side of the capacitor structure away from the transistor array, the second conductive layer is located on the side surface of the capacitor structure, the third conductive layer is located on the side of the virtual semiconductor pillar close to the capacitor structure, and the conductive pads are arranged corresponding to the spaces between the virtual semiconductor pillars.
21. The method for manufacturing a semiconductor device according to claim 20, wherein, The method for manufacturing the semiconductor device further includes: Forming a dielectric layer between the transistor array and the conductive pads, and the second connection structure passes through the dielectric layer and is connected to the conductive pads.
22. The method for manufacturing a semiconductor device according to claim 20, wherein, The step of forming a first connection structure connecting the conductive pads on the periphery of the memory array includes: Connecting the control circuit to the internal lead contacts and the second connection structure through a bonding metal layer; Forming an external lead contact and a first connection structure on the side of the memory array and the first connection structure away from the transistor array. The external lead contact is connected to the first conductive layer, and the first connection structure is connected to the conductive pads.
23. The method for manufacturing a semiconductor device according to claim 22, wherein, The method for manufacturing the semiconductor device further includes: Forming a first pad at one end of the external lead contact away from the memory array; Forming a second pad at one end of the first connection structure away from the conductive pads.
24. The manufacturing method of the semiconductor device according to claim 20, characterized in that, The step of forming an array of capacitor structures on one side of the transistor array along the first direction includes: Forming a stacked layer on one side of the transistor array along the first direction. The stacked layer includes a first dielectric layer and a second dielectric layer alternately stacked along the first direction, and the thickness of the first dielectric layer along the first direction is greater than the thickness of the second dielectric layer along the first direction; Forming a first electrode structure penetrating the stacked layer along the first direction. One end of the first electrode structure close to the transistor array is connected to the semiconductor pillar; Forming a second electrode structure between the first electrode structure and the stacked layer. The first conductive layer is connected to one end of the second electrode structure away from the transistor array; Forming a dielectric layer between the first electrode structure and the second electrode structure.
25. A storage system, characterized in that, Including: The semiconductor device according to any one of claims 1-16; A controller, which is connected to the semiconductor device and is used to control the semiconductor device to store data.