Chip and electronic device

Abstract

The invention relates to a chip and electronic equipment, the chip comprises a first chip assembly and a second chip assembly, and the first chip assembly comprises at least one processor unit; the second chip assembly comprises at least one integrated passive device and at least one memory, the at least one integrated passive device is connected with the at least one processor unit, and the at least one memory is connected with the at least one processor unit. According to the chip disclosed by the invention, the integrated passive device of the second chip assembly is connected with the processor unit of the first chip assembly, and sufficient capacitance density of a decoupling capacitor and a relatively low equivalent inductance value are provided for the processor unit by utilizing the characteristic of relatively high accommodating density of the integrated passive device; the memory of the second chip assembly is connected with the processing unit of the first chip assembly, so that the memory can provide high-capacity and low-delay data reading and storage for the processor unit.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a chip and an electronic device. Background Art

[0002] The most typical feature of a mobile SoC (system on chip) is on-chip heterogeneity, which meets the complex and diverse mobile application requirements through different on-chip heterogeneous processors. With the improvement of application complexity and continuous progress of technology, there are different problems with on-chip heterogeneous processors. For example, the capacitance density of decap (de-coupling capacitors) is insufficient, the ESL (Equivalent Series Inductance) value is high, the capacity is low, and the latency of data storage and reading increases, etc. Summary of the Invention

[0003] The present disclosure proposes a chip to improve the capacitance density of the chip and reduce the equivalent inductance of the chip.

[0004] The chip of the present disclosure includes a first chip component and a second chip component. The first chip component includes at least one processor unit; the second chip component includes at least one integrated passive device and at least one memory. At least one of the integrated passive devices is connected to at least one of the processor units, and at least one of the memories is connected to at least one of the processor units.

[0005] Optionally, the first chip component and the second chip component are arranged in a stacked manner, and at least one of the integrated passive devices is arranged corresponding to at least one of the processor units.

[0006] Optionally, the second chip component includes a power gating unit. At least one of the processor units is a central processing unit, and the power gating unit is arranged corresponding to the central processing unit and connected to the central processing unit.

[0007] Optionally, the central processing unit includes a first part and a second part. The power gating unit is arranged corresponding to the first part and connected to the first part. At least one of the integrated passive devices is a first integrated passive device, and the first integrated passive device is arranged corresponding to the second part and connected to the second part; the first integrated passive device and the power gating unit are integrated into one body to form a first integrated unit.

[0008] Optionally, the number of the integrated passive devices is multiple. At least one of the integrated passive devices is a second integrated passive device. The first chip component includes at least one interface, and the second integrated passive device is arranged corresponding to the interface and connected to the interface.

[0009] Optionally, at least one of the processor units is a graphics processor, and at least one of the memories is a dynamic random access memory, the dynamic random access memory being provided corresponding to and connected to the graphics processor; and / or, at least one of the processor units is a neural network processor, and the second chip component further includes a memory-computation integrated module, the memory-computation integrated module being provided corresponding to and connected to the neural network processor.

[0010] Optionally, the first chip component and the second chip component are connected by hybrid bonding.

[0011] Optionally, the number of the second chip components is multiple, and the multiple second chip components are provided on the same side of the first chip component in the thickness direction of the chip, and the multiple second chip components are arranged in a stacked manner.

[0012] Optionally, at least one of the processor units is a graphics processor, and at least one of the memories is a dynamic random access memory, the dynamic random access memory being connected to the graphics processor.

[0013] Optionally, the chip includes a first chip layer, a second chip layer, and a third chip layer which are sequentially arranged in a stacked manner, the graphics processor is provided on the first chip layer, the dynamic random access memory includes a peripheral circuit and a memory cell array, the peripheral circuit is provided on the second chip layer, and the memory cell array and the integrated passive device are both provided on the third chip layer; the peripheral circuit is provided corresponding to the graphics processor and connected to the graphics processor, and the memory cell array is provided corresponding to the peripheral circuit and connected to the peripheral circuit.

[0014] Optionally, the number of the processor units is multiple, and at least one of the processor units is a central processing unit; the central processing unit includes a first cache portion and a second cache portion, the first cache portion is provided on the first chip layer, the second cache portion is provided on the second chip layer, the second cache portion is provided corresponding to the first cache portion and connected to the second cache portion.

[0015] Optionally, the second chip component includes a power gating unit, the power gating unit is provided on the third chip layer, the power gating unit is provided corresponding to the second cache portion and connected to the second cache portion.

[0016] Optionally, the second cache unit includes a first sub-unit and a second sub-unit. The power gating unit is disposed corresponding to the first sub-unit and connected to the first sub-unit. At least one of the integrated passive devices is a first integrated passive device. The first integrated passive device is disposed corresponding to the second sub-unit and connected to the second sub-unit. The first integrated passive device and the power gating unit are integrated into one body to form a second integrated unit.

[0017] Optionally, the first chip component includes at least one interface. The interface is disposed on the first chip layer. At least one of the integrated passive devices is a second integrated passive device. The second integrated passive device is disposed corresponding to the interface and connected to the interface.

[0018] Optionally, the number of the processor units is multiple. At least one of the processor units is a neural network processor. The neural network processor is disposed on the first chip layer. The second chip component further includes a memory-computation integrated module. The memory-computation integrated module is disposed on the second chip layer. The memory-computation integrated module is disposed corresponding to the neural network processor and connected to the neural network processor. The memory-computation integrated module and the peripheral circuit are integrated into one body to form a third integrated unit.

[0019] Optionally, the number of the third chip layers is multiple. The multiple third chip layers are disposed on the same side of the second chip layer in the thickness direction of the chip, and the multiple third chip layers are stacked.

[0020] Optionally, the first chip layer and the second chip layer are connected by hybrid bonding; the second chip layer and the third chip layer are connected by hybrid bonding.

[0021] Optionally, the integrated passive device is connected to the power ground of the first chip component, and the dynamic random access memory is connected to the signal ground of the first chip component.

[0022] Optionally, the chip further includes a packaging layer. The first chip component and the second chip component are both disposed within the packaging layer.

[0023] The present disclosure also provides an electronic device.

[0024] The electronic device of the present disclosure includes a circuit board and a chip. The chip is the chip described in any one of the above items, and the chip is connected to the circuit board.

[0025] The chip of the present disclosure connects the integrated passive devices of the second chip component to the processor unit of the first chip component. By taking advantage of the relatively large capacitance density of the integrated passive devices, it provides sufficient capacitance density of decoupling capacitors and a low equivalent inductance value for the processor unit. By connecting the memory of the second chip component to the processing unit of the first chip component, the memory can provide high-capacity and low-latency data reading and storage for the processor unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. is a schematic assembly structure diagram of a first chip component and a second chip component of a chip according to an embodiment of the present disclosure.

[0027] Figure 2 FIG. is a schematic assembly structure diagram of a first chip component and a second chip component of a chip according to another embodiment of the present disclosure.

[0028] Figure 3 FIG. is a schematic assembly structure diagram of a first chip component and a second chip component of a chip according to still another embodiment of the present disclosure.

[0029] Figure 4 FIG. is a schematic assembly structure diagram of a first chip component and a second chip component of a chip according to yet another embodiment of the present disclosure.

[0030] Figure 5 FIG. is a schematic assembly structure diagram of a first chip component and a second chip component of a chip according to yet another embodiment of the present disclosure.

[0031] Figure 6 FIG. is a schematic structure diagram of a chip according to an embodiment of the present disclosure.

[0032] Figure 7 FIG. is a schematic structure diagram of a chip according to another embodiment of the present disclosure.

[0033] Figure 8 FIG. is a manufacturing process diagram of a chip according to an embodiment of the present disclosure.

[0034] REFERENCE SIGNS:

[0035] 1. First chip component; 11. Central processing unit; 111. First part; 112. Second part; 113. First cache unit; 114. Second cache unit; 12. Graphics processing unit; 13. Neural network processor; 14. Interface; 101. First chip layer; 102. Second chip layer; 103. Third chip layer;

[0036] 2. Second chip component; 21. Integrated passive device; 211. First integrated passive device; 212. Second integrated passive device; 22. Dynamic random access memory; 221. Peripheral circuit; 222. Memory cell array; 23. Power gating unit; 24. Computing-in-memory module; 25. Through-silicon via; 201. First integrated unit; 202. Second integrated unit; 203. Third integrated unit;

[0037] 3. Encapsulation layer;

[0038] 4. Substrate;

[0039] 5. LPDDR;

[0040] 6. First pin;

[0041] 7. Second pin;

[0042] 8. Third pin;

[0043] 9. Fourth pin;

[0044] 10. Copper pillar;

[0045] 20. Connection board. Detailed implementation manners

[0046] The embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be construed as a limitation to the present disclosure.

[0047] In the related art, the on-chip heterogeneous processor at least faces the following problems:

[0048] (1) The single-core peak performance of the CPU (Central Processing Unit) requires a higher frequency. With the progress of the process, the power density and PI (Power Integrity) problems are becoming increasingly serious. The transient problems caused by the requirements of low power consumption and fast application response make the PI problem more serious. The capacitance density of the on-chip decoupling capacitor is insufficient, and the cost of MIM / MOM cap (metal-insulator-metal / metal-oxide-metal capacitor) is relatively high.

[0049] (2) The peak bandwidth requirement of the GPU (Graphic Processing Unit) game scenario far exceeds the bandwidth capacity that LPDDR (Low Power Double Data Rate SDRAM) can provide, resulting in an increase in the latency of data storage and reading. Therefore, how to improve the GPU bandwidth and reduce data latency is a technical problem that urgently needs to be solved at present.

[0050] (3) For the NPU (Neural network Processing Unit), the tensor part bears the largest computing and memory access requirements. How to reduce the computing pressure on the tensor part is a technical problem that urgently needs to be solved at present.

[0051] To solve the above problems, the present disclosure proposes a chip and an electronic device to increase the capacitance density of the decoupling capacitor of the chip, reduce the latency of data storage and reading, improve the computing power of the chip, and reduce the power consumption of the chip.

[0052] As Figures 1 to 5 shown, the chip of the present disclosure includes a first chip component 1 and a second chip component 2. The first chip component 1 includes at least one processor unit, and the second chip component 2 includes at least one IPD (Integrated Passive Device, integrated passive device 21) and at least one memory. At least one integrated passive device 21 is connected to at least one processor unit, and at least one memory is connected to at least one processor unit.

[0053] Among them, the first chip component 1 can be an SoC. The processor unit can be a CPU (Central Processing Unit, central processor 11), a GPU (Graphic Processing Unit, graphic processor 12), or an NPU (Neural network Processing Unit, neural network processor 13). The memory can be a DRAM (Dynamic Random Access Memory, dynamic random access memory 22) or an SRAM (Static Random Access Memory, static random access memory). For example, as Figure 2 shown, the central processor 11 is connected to the integrated passive device 21, the graphic processor 12 is connected to the dynamic random access memory 22, and the neural network processor 13 is connected to the integrated passive device 21.

[0054] The chip of the present disclosure connects the integrated passive device 21 of the second chip component 2 to the processor unit of the first chip component 1. By utilizing the characteristic of the integrated passive device 21 having a relatively large capacitance density, it provides a sufficient capacitance density of decoupling capacitors and a low equivalent inductance value for the processor unit; by connecting the memory of the second chip component 2 to the processing unit of the first chip component 1, the memory can provide large-capacity and low-latency data reading and storage for the processor unit.

[0055] As Figures 1 to 4 shown, the first chip component 1 and the second chip component 2 are stacked, and at least one integrated passive device 21 is provided corresponding to at least one processor unit.

[0056] For example, as Figure 1 and Figure 4 shown, the first chip component 1 is disposed on the upper side of the second chip component 2. The first chip component 1 and the second chip component 2 are interconnected through TSV (Through Silicon Via, via 25) and pads. Among them, the up-down direction is as Figures 1 to 4 shown.

[0057] By stacking the first chip component 1 and the second chip component 2, vertical interconnection can be achieved between the integrated passive device 21 and the processor unit, facilitating the connection between the integrated passive device 21 and the processor unit.

[0058] Optionally, as Figure 3 shown, the second chip component 2 includes a power gating unit 23. At least one processor unit is a central processor 11. The power gating unit 23 is provided corresponding to the central processor 11 and is connected to the central processor 11.

[0059] Among them, the power gating unit 23 being provided corresponding to the central processor 11 can be understood as: at least a part of the power gating unit 23 is disposed opposite to at least a part of the central processor 11 in the thickness direction of the chip; or rather, the positive projection of the power gating unit 23 in the direction towards the first chip component 1 covers at least a part of the central processor 11. For example, as Figure 3 shown, at least a part of the power gating unit 23 is disposed directly below the central processor 11.

[0060] By disposing the power gating unit 23 in the second chip component 2, such that the central processing unit 11 and the power gating unit 23 are located on different layers of the chip. On the one hand, the influence of the power gating unit 23 on the utilization rate and current voltage of the central processing unit 11 can be reduced; on the other hand, the number of metal layers of the first chip component 1 can also be reduced, thereby reducing the cost of the first chip component 1. In addition, the power gating unit 23 is disposed corresponding to the central processing unit 11, enabling vertical interconnection between the power gating unit 23 and the central processing unit 11, which facilitates the connection between the power gating unit 23 and the central processing unit 11.

[0061] Optionally, as Figure 3 shown, the central processing unit 11 includes a first part 111 and a second part 112. The power gating unit 23 is disposed corresponding to and connected to the first part 111. At least one integrated passive device 21 is a first integrated passive device 211. The first integrated passive device 211 is disposed corresponding to and connected to the second part 112. The first integrated passive device 211 and the power gating unit 23 are integrated into one body to form a first integrated unit 201.

[0062] By integrating the first integrated passive device 211 and the power gating unit 23 into one body, the volume of the second chip component 2 occupied by the first integrated passive device 211 and the power gating unit 23 can be reduced, and the capacity of the remaining part of the second chip component 2 can be increased.

[0063] Optionally, as Figure 2 and Figure 3 shown, the number of integrated passive devices 21 is multiple. At least one integrated passive device 21 is a second integrated passive device 212. The first chip component 1 includes at least one I / F (Interface, interface 14). The second integrated passive device 212 is disposed corresponding to and connected to the interface 14. Wherein, the interface 14 is used for connecting the chip to an external device.

[0064] Wherein, the second integrated passive device 212 being disposed corresponding to the interface 14 can be understood as: at least a part of the second integrated passive device 212 is disposed opposite to at least a part of the interface 14 in the thickness direction of the chip; or, the orthographic projection of the second integrated passive device 212 in the direction towards the first chip component 1 covers at least a part of the interface 14. For example, as Figure 3 shown, at least a part of the second integrated passive device 212 is disposed directly below the interface 14.

[0065] By setting the interface 14 on the first chip component 1, it is convenient to connect the interface 14 to an external device. By setting the second integrated passive device 212 corresponding to the interface 14 and connecting it to the interface 14, vertical interconnection can be achieved between the second integrated passive device 212 and the interface 14, facilitating the connection between the second integrated passive device 212 and the interface 14.

[0066] Optionally, as Figures 2 to 5 shown, at least one processor unit is the graphics processor 12, and at least one memory is the dynamic random access memory 22, and the dynamic random access memory 22 is connected to the graphics processor 12.

[0067] By connecting the graphics processor 12 to the dynamic random access memory 22, the dynamic random access memory 22 can provide high-capacity and low-latency data reading and storage for the graphics processor 12. The dynamic random access memory 22 exists as heterogeneous memory outside the first chip component 1, meeting the large bandwidth requirements for peak scenario-specific data access.

[0068] Optionally, as Figure 2 and Figure 3 shown, the dynamic random access memory 22 is set corresponding to the graphics processor 12.

[0069] Among them, the dynamic random access memory 22 being set corresponding to the graphics processor 12 can be understood as: at least a part of the dynamic random access memory 22 is set opposite to at least a part of the graphics processor 12 in the thickness direction of the chip; or, the orthographic projection of the dynamic random access memory 22 in the direction towards the first chip component 1 covers at least a part of the graphics processor 12. For example, as Figure 2 and Figure 3 shown, at least a part of the dynamic random access memory 22 is disposed directly below the graphics processor 12.

[0070] The dynamic random access memory 22 being set corresponding to the graphics processor 12 enables vertical interconnection between the dynamic random access memory 22 and the graphics processor 12, facilitating the connection between the dynamic random access memory 22 and the graphics processor 12.

[0071] Optionally, the first chip component 1 is fabricated using Logic process, and the second chip component 2 is fabricated using DRAM process.

[0072] The power gating unit 23 is integrated in the second chip component 2. Although it will increase the number of metal layers of the second chip component 2, since the process cost of the second chip component 2 is lower than that of the first chip component 1, the overall cost of the chip can be reduced.

[0073] Optionally, as Figure 3As shown, at least one processor unit is a neural network processor 13, and the second chip component 2 further includes a PIM (Processing In Memory, in-memory computing module 24). The in-memory computing module 24 is provided corresponding to the neural network processor 13 and is connected to the neural network processor 13.

[0074] By connecting the neural network processor 13 to the in-memory computing module 24, a part of the tensor calculation tasks of the neural network processor 13 can be offloaded to the in-memory computing module 24, thereby reducing the operation pressure of the neural network processor 13 and improving the computing efficiency of the chip.

[0075] Optionally, as Figure 4 shown, the number of the second chip components 2 is multiple. The multiple second chip components 2 are stacked, and the multiple second chip components 2 are arranged on the same side of the first chip component 1 in the thickness direction of the chip.

[0076] Among them, the structures of the multiple second chip components 2 can be the same or different. Two adjacent second chip components 2 can be vertically interconnected, or two non-adjacent second chip components 2 can be vertically interconnected.

[0077] By setting multiple second chip components 2, the multiple second chip components 2 can provide a larger capacity for the processor unit, as well as lower-latency data reading and storage, etc., to meet the applications of multi-scenarios and large models, without integrating LPDDR, saving the chip cost.

[0078] Optionally, the first chip component 1 and the second chip component 2 are connected by hybrid bonding.

[0079] Connecting the first chip component 1 and the second chip component 2 by hybrid bonding can achieve higher density and larger bandwidth.

[0080] Optionally, as Figure 5 shown, the chip includes a first chip layer 101, a second chip layer 102, and a third chip layer 103 that are stacked in sequence. The graphics processor 12 is provided on the first chip layer 101. The dynamic random access memory 22 includes a peripheral circuit 221 (peripheral circuit) and a memory cell array 222 (memory cell array). The peripheral circuit 221 is provided on the second chip layer 102, and the memory cell array 222 and the integrated passive device 21 are both provided on the third chip layer 103. The peripheral circuit 221 is provided corresponding to the graphics processor 12 and is connected to the graphics processor 12. The memory cell array 222 is provided corresponding to the peripheral circuit 221 and is connected to the peripheral circuit 221.

[0081] For example, asFigure 5 As shown, the first chip layer 101 is disposed above the second chip layer 102, and the second chip layer 102 is disposed above the third chip layer 103. Among them, the up-down direction is as Figure 5 shown.

[0082] Among them, the peripheral circuit 221 corresponds to the graphics processor 12. It can be understood that at least a part of the peripheral circuit 221 is disposed opposite to at least a part of the graphics processor 12 in the thickness direction of the chip; or rather, the orthographic projection of the peripheral circuit 221 in the direction towards the first chip layer 101 covers at least a part of the graphics processor 12. For example, as Figure 5 shown, at least a part of the peripheral circuit 221 is disposed directly below the graphics processor 12.

[0083] Among them, the memory cell array 222 corresponds to the peripheral circuit 221. It can be understood that at least a part of the memory cell array 222 is disposed opposite to at least a part of the peripheral circuit 221 in the thickness direction of the chip; or rather, the orthographic projection of the memory cell array 222 in the direction towards the second chip layer 102 covers at least a part of the peripheral circuit 221. For example, as Figure 5 shown, at least a part of the memory cell array 222 is disposed directly below the peripheral circuit 221.

[0084] By separately arranging the peripheral circuit 221 and the memory cell array 222 of the dynamic random access memory 22 on the second chip layer 102 and the third chip layer 103 respectively, the separation of the peripheral circuit 221 and the memory cell array 222 is realized, and the capacity of the dynamic random access memory 22 is improved. Thus, data reading and storage with a larger capacity and lower latency can be provided for the graphics processor 12.

[0085] Optionally, as Figure 5 shown, the central processing unit 11 includes a first cache portion 113 and a second cache portion 114. The first cache portion 113 is disposed on the first chip layer 101, the second cache portion 114 is disposed on the second chip layer 102, and the second cache portion 114 corresponds to the first cache portion 113 and is connected to the second cache portion 114.

[0086] Among them, the second cache portion 114 corresponds to the first cache portion 113. It can be understood that at least a part of the second cache portion 114 is disposed opposite to at least a part of the first cache portion 113 in the thickness direction of the chip; or rather, the orthographic projection of the second cache portion 114 in the direction towards the first chip layer 101 covers at least a part of the first cache portion 113. For example, as Figure 5 shown, at least a part of the second cache portion 114 is disposed directly below the first cache portion 113.

[0087] Among them, the central processing unit 11 includes a first-level memory, a second-level memory, and a third-level memory. The first cache unit 113 may include the first-level memory and the second-level memory, the second cache unit 114 includes the third-level memory, and the third-level memory may be SRAM (Static Random Access Memory).

[0088] By respectively disposing the first cache unit 113 and the second cache unit 114 of the central processing unit 11 on the first chip layer 101 and the second chip layer 102, and separating the second cache unit 114 of the central processing unit 11 into the second chip layer, sufficient space can be provided for the first cache unit 113 of the central processing unit 11. In addition, the process cost of the central processing unit 11 can be reduced, thereby reducing the cost of the chip.

[0089] Optionally, as Figure 5 shown, the second chip component 2 includes a power gating unit 23. The power gating unit 23 is disposed on the third chip layer 103, and the power gating unit 23 is disposed corresponding to the second cache unit 114 and connected to the second cache unit 114.

[0090] Among them, the power gating unit 23 is disposed corresponding to the second cache unit 114, which can be understood as: at least a part of the power gating unit 23 is disposed opposite to at least a part of the second cache unit 114 in the thickness direction of the chip; or, the orthographic projection of the power gating unit 23 in the direction facing the second chip layer 102 covers at least a part of the second cache unit 114. For example, as Figure 5 shown, at least a part of the power gating unit 23 is disposed directly below the second cache unit 114.

[0091] By disposing the power gating unit 23 on the third chip layer 103, the power gating unit 23 and the central processing unit 11 are located on different layers of the chip. On the one hand, the influence of the power gating unit 23 on the utilization rate and current voltage of the central processing unit 11 can be reduced; on the other hand, the number of metal layers of the first chip layer 101 and the second chip layer 102 can be reduced, thereby reducing the cost of the first chip component 1. In addition, the power gating unit 23 is disposed corresponding to the second cache unit 114, so that vertical interconnection can be realized between the power gating unit 23 and the second cache unit 114, which is convenient for the connection between the power gating unit 23 and the central processing unit 11.

[0092] Optionally, as Figure 5As shown, the second cache unit 114 includes a first sub-unit and a second sub-unit. The power gating unit 23 is provided corresponding to the first sub-unit and is connected to the first sub-unit. At least one integrated passive device 21 is the first integrated passive device 211. The first integrated passive device 211 is provided corresponding to the second sub-unit and is connected to the second sub-unit. The first integrated passive device 211 and the power gating unit 23 are integrated into one body to form a second integrated unit 202.

[0093] Among them, the power gating unit 23 is provided corresponding to the first sub-unit, which can be understood as: at least a part of the power gating unit 23 is disposed opposite to at least a part of the first sub-unit in the thickness direction of the chip; or rather, the orthographic projection of the power gating unit 23 in the direction towards the second chip layer 102 covers at least a part of the first sub-unit. For example, as Figure 3 shown, at least a part of the power gating unit 23 is disposed directly below the first sub-unit.

[0094] Among them, the first integrated passive device 211 is provided corresponding to the second sub-unit, which can be understood as: at least a part of the first integrated passive device 211 is disposed opposite to at least a part of the second sub-unit in the thickness direction of the chip; or rather, the orthographic projection of the first integrated passive device 211 in the direction towards the second chip layer 102 covers at least a part of the second sub-unit. For example, as Figure 3 shown, at least a part of the first integrated passive device 211 is disposed directly below the second sub-unit.

[0095] By disposing the power gating unit 23 corresponding to the first sub-unit, vertical interconnection can be achieved between the power gating unit 23 and the first sub-unit; by disposing the first integrated passive device 211 corresponding to the second sub-unit, vertical interconnection can be achieved between the first integrated passive device 211 and the second sub-unit. Thus, it is convenient for the power gating unit 23 and the first integrated passive device 211 to be connected to the central processing unit 11.

[0096] Optionally, as Figure 3 shown, the first chip component 1 includes at least one interface 14. The interface 14 is disposed on the first chip layer 101. At least one integrated passive device 21 is the second integrated passive device 212. The second integrated passive device 212 is provided corresponding to the interface 14 and is connected to the interface 14.

[0097] By disposing the interface 14 on the first chip layer 101, it is convenient for the interface 14 to be connected to an external device.

[0098] Optionally, as Figure 5As shown, at least one processor unit is a neural network processor 13. The neural network processor 13 is disposed on the first chip layer 101. The second chip component 2 further includes a memory - in - computing integrated module 24. The memory - in - computing integrated module 24 is disposed on the second chip layer 102. The memory - in - computing integrated module 24 is arranged corresponding to the neural network processor 13 and is connected to the neural network processor 13. The memory - in - computing integrated module 24 and the peripheral circuit 221 are integrated into one body to form a third integrated unit 203.

[0099] By connecting the neural network processor 13 to the memory - in - computing integrated module 24, a part of the tensor computing tasks of the neural network processor 13 can be offloaded to the memory - in - computing integrated module 24, thereby reducing the operation pressure of the neural network processor 13 and improving the computing efficiency of the chip. In addition, by integrating the memory - in - computing integrated module 24 with the peripheral circuit 221 into one body, the volume of the second chip layer 102 occupied by the integration of the memory - in - computing integrated module 24 and the peripheral circuit 221 can be reduced, and the capacity of the remaining part of the second chip layer 102 can be increased.

[0100] Optionally, the number of the third chip layers 103 is multiple. The multiple third chip layers 103 are stacked, and the multiple third chip layers 103 are disposed on the same side of the second chip layer 102 in the thickness direction of the chip.

[0101] Among them, the structures of the multiple third chip layers 103 can be the same or different. Vertical interconnection can be achieved between two adjacent third chip layers 103, or between two non - adjacent third chip layers 103.

[0102] By setting multiple third chip layers 103, the multiple third chip layers 103 can provide a larger capacity for the processor unit, as well as lower - latency data reading and storage, etc., to meet the applications of multi - scenarios and large models, without the need to integrate LPDDR, saving chip costs.

[0103] Optionally, the first chip layer 101 and the second chip layer 102 are connected by hybrid bonding. The second chip layer 102 and the third chip layer 103 are connected by hybrid bonding.

[0104] The connection between the first chip layer 101 and the second chip layer 102 and the connection between the second chip layer 102 and the third chip layer 103 by hybrid bonding can achieve higher density and larger bandwidth.

[0105] Optionally, the integrated passive device 21 is connected to the power ground of the first chip component 1 to achieve the electrical connection between the integrated passive device 21 and the first chip component 1; the dynamic random - access memory 22 is connected to the signal ground of the first chip component 1 to achieve the signal connection between the dynamic random - access memory 22 and the first chip component 1.

[0106] By connecting the integrated passive device 21 to the power ground of the first chip component 1 and connecting the dynamic random access memory 22 to the signal ground of the first chip component 1, the chip proposed by the present disclosure can provide sufficient capacitance density and a lower equivalent inductance value, ensuring that the central processing unit 11 can operate at a higher frequency; using the dynamic random access memory 22 to store game scenes and rendering intermediate data, improving the bandwidth of the graphics processing unit 12 and reducing data latency; at the same time, the dynamic random access memory 22 exists as heterogeneous memory outside the first chip component 1, further meeting the need for large bandwidth during specific data access in peak scenarios. In addition, it is also possible to reduce the area occupied by decoupling capacitors in the first chip component 1, avoid using relatively expensive MIM / MOM, increase the available area of each processor unit (such as the central processing unit 11, the graphics processing unit 12, etc.) and the interface 14 in the first chip component 1, reduce or eliminate the decoupling capacitors on the package of the first chip component 1, and reduce the cost of the first chip component 1.

[0107] Optionally, as Figure 6 shown, the chip further includes a packaging layer 3, and both the first chip component 1 and the second chip component 2 are disposed within the packaging layer 3. Among them, the packaging layer 3 can be a plastic packaging layer.

[0108] For example, as Figure 6 shown, the chip includes a substrate 4, and both the first chip component 1 and the second chip component 2 are disposed on the same side in the thickness direction of the substrate 4, and the second chip component 2 is connected to the substrate 4. The packaging layer 3 is disposed on the side of the substrate 4 facing the second chip component 2, and the sides of the first chip component 1 and the second chip component 2 are both covered by the packaging layer 3.

[0109] By disposing the first chip component 1 and the second chip component 2 within the packaging layer 3, the packaging layer 3 can be used to protect the first chip component 1 and the second chip component 2, reducing the risk of fracture and breakage when the chip is subjected to external force extrusion during transportation and assembly.

[0110] Optionally, as Figure 6 shown, the chip further includes LPDDR5, and the LPDDR5 is connected to the substrate 4.

[0111] For example, as Figure 6 shown, the first chip component 1 is disposed on the upper side of the second chip component 2, the substrate 4 is disposed on the lower side of the second chip component 2, and the LPDDR5 is disposed on the upper side of the first chip component 1. The substrate 4 is connected to the connection board 20 through copper pillars 10, and the LPDDR5 is connected to the connection board 20 through the first pins 6. Among them, the first pins 6 can be solder bumps, solder balls or copper pillars. Among them, the up and down directions are as Figure 6 shown.

[0112] By setting LPDDR5, the bandwidth of the chip can be further improved to better meet the large bandwidth requirements for specific data access in peak scenarios.

[0113] Optionally, as Figure 6 shown, the chip further includes a second pin 7, and the second pin 7 is connected to the substrate 4. The second pin 7 is used to connect to a circuit board. Among them, the second pin 7 can be a solder ball.

[0114] Optionally, as Figure 7 shown, the chip includes a substrate 4. Both the first chip component 1 and the second chip component 2 are provided on the same side in the thickness direction of the substrate 4, and the second chip component 2 is connected to the substrate 4. On the side of the fourth substrate 4 facing the first chip component 1, there is a plastic encapsulation layer (not shown in the figure). The plastic encapsulation layer includes the sides of the first chip component 1 and the second chip component 2, and the plastic encapsulation layer can also cover the surface of the first chip component 1 facing away from the second chip component 2.

[0115] For example, the first chip component 1 is arranged above the second chip component 2, and the substrate 4 is arranged below the second chip component 2. The second chip component 2 is connected to the substrate 4 through a third pin 8. On the surface of the substrate 4 facing away from the second chip component 2, there is a fourth pin 9, and the fourth pin 9 is used to connect to a circuit board. Among them, the third pin 8 can be a solder bump, a solder ball or a copper pillar; the fourth pin 9 can be a solder ball. Among them, the up and down directions are as Figure 7 shown.

[0116] Next, refer to Figure 8 to describe the manufacturing method of the chip of the present disclosure:

[0117] Provide a first die and a second die, make pads on the first die, and make through-silicon vias 25 and pads on the second die; among them, the first die forms the first chip component 1, and the second die forms the second chip component 2;

[0118] Face-to-face weld the first die and the second die together;

[0119] Grind the second die to expose the through-silicon vias 25 and make necessary pads;

[0120] Repeat the above operations for the stacking of the second layer of dies;

[0121] Grind thin the surface of the stacked first die facing away from the first die and integrate it into the encapsulation layer 3.

[0122] The chip of the present disclosure has the following advantages:

[0123] Provide sufficient capacitance density and extremely low equivalent inductance to ensure the operation at a higher frequency required for the single-core peak performance of the central processing unit 11 under advanced processes;

[0124] The dynamic random access memory 22 is dedicated to storing game scenes and rendering intermediate data, enhancing the peak bandwidth of the game scenes of the graphics processing unit 12;

[0125] Place the key operations of the neural network processor 13 in the dynamic random access memory 22 to improve the computing power and reduce the power consumption;

[0126] The dynamic random access memory 22 exists as heterogeneous memory outside the main memory of the system-on-chip, meeting the need for large bandwidth for peak scenario-specific data access;

[0127] Integrate the power gating unit 23 in the integrated passive device 21 corresponding to the central processing unit 11, solve the influence of the power gating unit 23 on the utilization rate, current and voltage of the central processing unit 11, and reduce the metal layer cost of the system-on-chip;

[0128] Reduce the area of on-chip decoupling capacitors, avoid using relatively expensive MIM / MOM, and increase the available area of the processor unit and interface 14;

[0129] Reduce or eliminate the use of decoupling capacitors at the package and board levels, reduce costs and save area.

[0130] Separate the peripheral circuit 221 and the memory cell array 222 of the dynamic random access memory 22, increase the capacity of the dynamic random access memory 22, and at the same time solve the cost problem of the advanced process of the SRAM of the central processing unit 11;

[0131] Through the stacking of multiple second chip components 2 including the integrated passive device 21 and the dynamic random access memory 22, meet the applications of multiple scenarios and large models, and achieve the need not to integrate LPDDR.

[0132] Adopt the wafer to wafer hybrid bonding stacking process to reduce the stacking cost of the chips.

[0133] The electronic device of the present disclosure includes a circuit board and a chip. The chip is the chip described in any of the above embodiments, and the chip is connected to the circuit board. Among them, the electronic device can be a mobile phone, a tablet computer, a smart wearable device, a smart home device, etc.

[0134] For example, Figure 6 the chip in is soldered to the circuit board through the second pin 7, Figure 7 the chip in is soldered to the circuit board through the fourth pin 9.

[0135] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Any changes, modifications, substitutions, and variations made by those of ordinary skill in the art to the above embodiments are within the protection scope of the present disclosure.

Claims

1. A chip, characterized in that, Comprising: A first chip component, the first chip component including at least one processor unit; A second chip component, the second chip component including at least one integrated passive device and at least one memory, at least one of the at least one integrated passive device being connected to at least one of the at least one processor unit, and at least one of the at least one memory being connected to at least one of the at least one processor unit.

2. The chip according to claim 1, wherein The first chip component and the second chip component are stacked, and at least one of the at least one integrated passive device is disposed corresponding to at least one of the at least one processor unit.

3. The chip according to claim 2, wherein The second chip component includes a power gating unit, at least one of the at least one processor unit being a central processing unit, the power gating unit being disposed corresponding to the central processing unit and connected to the central processing unit.

4. The chip according to claim 3, wherein, The central processing unit includes a first part and a second part, the power gating unit being disposed corresponding to the first part and connected to the first part, at least one of the at least one integrated passive device being a first integrated passive device, the first integrated passive device being disposed corresponding to the second part and connected to the second part; The first integrated passive device and the power gating unit are integrated into one body to form a first integrated unit.

5. The chip according to claim 2, wherein The number of the integrated passive devices is plural, at least one of the at least one integrated passive device being a second integrated passive device, the first chip component including at least one interface, the second integrated passive device being disposed corresponding to the interface and connected to the interface.

6. The chip according to claim 2, wherein At least one of the at least one processor unit is a graphics processing unit, at least one of the at least one memory being a dynamic random access memory, the dynamic random access memory being disposed corresponding to the graphics processing unit and connected to the graphics processing unit; and / or At least one of the at least one processor unit is a neural network processor, the second chip component further including a compute-in-memory module, the compute-in-memory module being disposed corresponding to the neural network processor and connected to the neural network processor.

7. The chip according to any one of claims 2-6, characterized in that, The first chip component and the second chip component are connected by hybrid bonding.

8. The chip according to any one of claims 2-6, characterized in that, The number of the second chip components is plural, and the plural second chip components are disposed on the same side of the first chip component in the thickness direction of the chip, and the plural second chip components are stacked.

9. The chip according to claim 1, characterized in that, At least one of the at least one processor unit is a graphics processing unit, at least one of the at least one memory being a dynamic random access memory, the dynamic random access memory being connected to the graphics processing unit.

10. The chip according to claim 9, characterized in that, The chip includes a first chip layer, a second chip layer, and a third chip layer that are sequentially stacked, the graphics processing unit being disposed in the first chip layer, the dynamic random access memory including a peripheral circuit and a memory cell array, the peripheral circuit being disposed in the second chip layer, and the memory cell array and the integrated passive device being both disposed in the third chip layer; The peripheral circuit is disposed corresponding to the graphics processing unit and connected to the graphics processing unit, and the memory cell array is disposed corresponding to the peripheral circuit and connected to the peripheral circuit.

11. The chip according to claim 10, wherein The number of the processor units is plural, at least one of the at least one processor unit being a central processing unit; The central processing unit includes a first cache unit and a second cache unit. The first cache unit is disposed on the first chip layer, and the second cache unit is disposed on the second chip layer. The second cache unit is arranged corresponding to the first cache unit and is connected to the second cache unit.

12. The chip according to claim 11, characterized in that, The second chip component includes a power gating unit. The power gating unit is disposed on the third chip layer. The power gating unit is arranged corresponding to the second cache unit and is connected to the second cache unit.

13. The chip according to claim 12, characterized in that, The second cache unit includes a first sub-unit and a second sub-unit. The power gating unit is arranged corresponding to the first sub-unit and is connected to the first sub-unit. At least one of the integrated passive devices is a first integrated passive device. The first integrated passive device is arranged corresponding to the second sub-unit and is connected to the second sub-unit. The first integrated passive device and the power gating unit are integrated into one body to form a second integrated unit.

14. The chip according to claim 10, characterized in that, The first chip component includes at least one interface. The interface is disposed on the first chip layer. At least one of the integrated passive devices is a second integrated passive device. The second integrated passive device is arranged corresponding to the interface and is connected to the interface.

15. The chip according to claim 10, characterized in that, The number of the processor units is multiple. At least one of the processor units is a neural network processor. The neural network processor is disposed on the first chip layer. The second chip component further includes a memory and computing integrated module. The memory and computing integrated module is disposed on the second chip layer. The memory and computing integrated module is arranged corresponding to the neural network processor and is connected to the neural network processor. The memory and computing integrated module and the peripheral circuit are integrated into one body to form a third integrated unit.

16. The chip according to claim 10, characterized in that, The number of the third chip layers is multiple. The multiple third chip layers are disposed on the same side of the second chip layer in the thickness direction of the chip, and the multiple third chip layers are stacked.

17. The chip according to any one of claims 10-16, characterized in that, The first chip layer and the second chip layer are connected by hybrid bonding; The second chip layer and the third chip layer are connected by hybrid bonding.

18. The chip according to claim 6 or 9, characterized in that, The integrated passive device is connected to the power ground of the first chip component, and the dynamic random access memory is connected to the signal ground of the first chip component.

19. The chip according to claim 1, wherein The chip further includes a packaging layer. Both the first chip component and the second chip component are disposed within the packaging layer.

20. An electronic device, characterized in that, Including: A circuit board; And A chip, which is the chip according to any one of claims 1-19, and the chip is connected to the circuit board.

Images