Packaging structure of a memory chip and method for manufacturing the same

Abstract

In order to overcome the problems of poor heat dissipation and stress caused by different volume expansion rates among the storage chips in the existing laminated chip packaging structure, the application provides a packaging structure of a storage chip, which comprises a substrate, a control chip, a heat-conducting layer, storage chips, a heat-conducting paste layer and a packaging adhesive layer, the heat-conducting layer is arranged on the surface of the control chip away from the substrate, first and second stepped surfaces are formed on the two sides of the storage chips, respectively, the control chip, the heat-conducting layer and the storage chips are located in the packaging adhesive layer, the heat-conducting paste layer comprises a first heat-conducting paste layer and a second heat-conducting paste layer, the first heat-conducting paste layer covers the second stepped surface, and the second heat-conducting paste layer covers the outer surface of the packaging adhesive layer. Meanwhile, the application also discloses a preparation method of the packaging structure of the storage chip.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of chip packaging, and particularly relates to a packaging structure of a storage chip and a preparation method thereof. BACKGROUND

[0002] In a stacked storage chip packaging structure, a control chip is usually stacked together with a plurality of storage chips. Due to the compact space, the heat dissipation channel is relatively narrow, and the control chip generates a large amount of heat during operation, especially in the case of high frequency and high load operation. However, the design of the stacked packaging makes the air circulation poor, and cannot form an effective convection heat dissipation, at the same time, the heat conduction performance of the packaging material is limited, and the heat generated by the control chip cannot be conducted out in time. This leads to the continuous rise of the temperature of the control chip, which will affect the service life of the control chip in a long-term high-temperature state.

[0003] At the same time, in the stacked storage chip packaging, different storage chips will have different heat generation due to the differences in working frequency, storage capacity, read-write operation and other factors. The storage chip with larger heat generation will generate more heat, resulting in a larger temperature rise. According to the principle of thermal expansion and contraction, the temperature rise will cause the volume of the chip to expand. The volume expansion of the storage chip with smaller heat generation is relatively small. Especially, the temperature of the storage chip in direct contact with the control chip is significantly higher than that of other storage chips, and due to the close stacking of the storage chips, when the volume expansion degrees of the storage chips are different, internal stress will be generated. This internal stress will gradually increase with the accumulation of time, and will have an adverse effect on the connection structure between the chips. The storage chips are electrically connected through lead wires to realize data transmission and signal control. When the volume expansion of the storage chips is different due to different heat generation, the lead wires will be subjected to uneven tension and pressure under the long-term stress, and the metal material of the lead wires will be damaged due to fatigue, eventually leading to the breakage of the lead wires. SUMMARY

[0004] In view of the problems of poor heat dissipation and stress caused by different volume expansion rates between the storage chips in the existing stacked chip packaging structure, the present application provides a packaging structure of a storage chip and a preparation method thereof.

[0005] The technical solution adopted by the present application to solve the above technical problems is as follows:

[0006] In one aspect, the application provides a packaging structure of a memory chip, comprising a substrate, a control chip, a heat-conducting layer, memory chips, a heat-conducting paste layer and a packaging adhesive layer, the control chip is arranged on the surface of the substrate, the heat-conducting layer is arranged on the surface of the control chip away from the substrate and partially extends out of the coverage of the control chip, the number of the memory chips is multiple, the multiple memory chips are arranged in a staggered and stacked manner on the surface of the heat-conducting layer away from the control chip to form a first stepped surface and a second stepped surface on both sides of the multiple memory chips, the positions of the multiple memory chips on the first stepped surface are electrically connected to each other, the memory chips are electrically connected to the control chip, the packaging adhesive layer is arranged on the substrate, the control chip, the heat-conducting layer and the memory chips are located in the packaging adhesive layer, and the heat-conducting layer at least partially extends out of the packaging adhesive layer, the heat-conducting paste layer comprises a first heat-conducting paste layer and a second heat-conducting paste layer, the first heat-conducting paste layer covers the second stepped surface, the second heat-conducting paste layer covers the outer surface of the packaging adhesive layer, the first heat-conducting paste layer and the second heat-conducting paste layer are connected to each other, and the heat-conducting layer and the second heat-conducting paste layer are connected to each other.

[0007] Optionally, at least one first pad is arranged on the memory chip at the position of the first stepped surface, first leads are arranged between the first pads of the adjacent two memory chips to connect the first pads to each other, at least one second pad is arranged on the control chip, and second leads are arranged between at least one of the second pads and at least one of the first pads to connect the second pads to the first pads.

[0008] Optionally, the heat-conducting paste layer further comprises a third heat-conducting paste layer and a fourth heat-conducting paste layer, the third heat-conducting paste layer covers the surface of the heat-conducting layer extending out of the control chip, and the fourth heat-conducting paste layer covers the side surface of the control chip, and the first heat-conducting paste layer, the second heat-conducting paste layer, the third heat-conducting paste layer and the fourth heat-conducting paste layer are connected as a whole.

[0009] Optionally, a first silicone resin layer is arranged between the adjacent memory chips, between the first heat-conducting paste layer and the memory chips, and between the fourth heat-conducting paste layer and the control chip;

[0010] A second silicone resin layer is arranged on the side of the first heat-conducting paste layer away from the memory chip, on the side of the third heat-conducting paste layer away from the heat-conducting layer, and on the side of the fourth heat-conducting paste layer away from the control chip, and the packaging adhesive layer is made of an epoxy resin material;

[0011] The first silicone resin layer and the second silicone resin layer are obtained by curing silicone paste, and the silicone paste comprises the following components by weight:

[0012] The silicone resin is 40-60 parts, the hydrogen-containing silicone oil is 3-10 parts, the catalyst is 0.05-1 part, the filler is 10-20 parts, and the solvent is 10-70 parts.

[0013] Optionally, the thermally conductive paste layer is obtained by curing a thermally conductive paste, and the thermally conductive paste comprises the following components by weight:

[0014] The graphene is 2-11 parts, the tetraethyl orthosilicate is 0.5-4 parts, and the solvent is 81-93 parts.

[0015] Optionally, the thermally conductive layer comprises a metal sheet, an upper insulating layer and a lower insulating layer, the upper insulating layer is located between the metal sheet and the storage chip, the lower insulating layer is located between the metal sheet and the control chip, the thickness of the lower insulating layer is less than the thickness of the upper insulating layer, the end of the metal sheet extends out of the encapsulation adhesive layer and is bent to form a bending portion, and the bending portion is attached to the surface of the second thermally conductive paste layer.

[0016] Optionally, the thermally conductive paste layer further comprises a fifth thermally conductive paste layer, the fifth thermally conductive paste layer is located in the encapsulation adhesive layer, one end of the fifth thermally conductive paste layer is connected to the first thermally conductive paste layer, and the other end of the fifth thermally conductive paste layer is connected to the second thermally conductive paste layer.

[0017] In another aspect, the application provides a preparation method of the packaging structure of the storage chip as described above, comprising the following operation steps:

[0018] The plurality of storage chips are stacked in a stepped staggered manner to obtain a storage chip stack, and the storage chip stack is formed with a first stepped surface and a second stepped surface on two sides thereof;

[0019] The control chip is fixed on the substrate, the thermally conductive layer and the storage chip stack are sequentially placed on the side of the control chip away from the substrate and are pre-fixed, and the storage chip and the control chip are electrically connected by leads at the first stepped surface;

[0020] The control chip, the thermally conductive layer and the storage chip stack are shielded on the side of the second stepped surface, and the control chip, the thermally conductive layer and the storage chip stack on the side of the first stepped surface are pre-packaged by using the encapsulation adhesive;

[0021] The shielding of the control chip, the thermally conductive layer and the storage chip stack on the side of the second stepped surface is removed, the thermally conductive paste is applied to the control chip, the thermally conductive layer and the storage chip stack on the side of the second stepped surface, and then the thermally conductive paste is cured;

[0022] The control chip, the heat conduction layer and the storage chip are laminated on one side of the second stepped surface, and a packaging glue layer is formed outside the control chip, the heat conduction layer and the storage chip, and the heat conduction layer at least partially extends out of the packaging glue layer.

[0023] A heat conduction paste is applied to the outside of the packaging glue layer, and a heat conduction paste layer is formed after solidification.

[0024] Optionally, before the stepped staggered lamination of the storage chip, the bottom surface and one side surface of the storage chip are applied with an organic silicon paste, and solidified; the top surface and one side surface of the control chip are applied with an organic silicon paste, and solidified; and a first organic silicon resin layer is obtained.

[0025] After the heat conduction paste is applied and solidified, before the re-packaging, the control chip, the heat conduction layer and the storage chip laminated on one side of the second stepped surface are applied with an organic silicon paste, and solidified to obtain a second organic silicon resin layer.

[0026] Optionally, after the heat conduction paste layer is formed, the part of the heat conduction layer extending out of the packaging glue layer is bent to adhere to the surface of the heat conduction paste layer.

[0027] According to the packaging structure of the storage chip provided by the application, the first heat conduction paste layer is arranged on the second stepped surface of the storage chip, the heat conduction layer is arranged between the control chip and the storage chip, and the second heat conduction paste layer is arranged outside the packaging glue layer, so that the first heat conduction paste layer, the heat conduction layer and the second heat conduction paste layer are connected. The first heat conduction paste layer on the second stepped surface can improve the temperature consistency among the plurality of storage chips, reduce the stress caused by the different temperature and volume change rates of the storage chips, and is conducive to improving the electrical connection stability of the lead wire. At the same time, through the heat conduction of the first heat conduction paste layer, the heat conduction layer and the second heat conduction paste layer, the heat of the storage chip and the control chip can be directly conducted to the outer surface of the packaging glue layer, so that the heat dissipation efficiency of the packaging structure can be effectively improved, and the heat dissipation through the external heat dissipation structure (heat pipe, etc.) is also conducive to reducing the temperature of the storage chip and the control chip and improving the service life. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a structural schematic diagram of the packaging structure of the storage chip provided by the application;

[0029] Figure 2 is a top view structural schematic diagram of the packaging structure of the storage chip provided by the application;

[0030] Figure 3 is a structural schematic diagram of the first intermediate body of the packaging structure of the storage chip provided by the application;

[0031] Figure 4 is a structural schematic diagram of a second intermediate body of the packaging structure of the storage chip provided by the present application;

[0032] Figure 5 is a structural schematic diagram of a third intermediate body of the packaging structure of the storage chip provided by the present application.

[0033] The reference signs in the drawings of the specification are as follows:

[0034] 1, substrate; 11, solder structure; 2, control chip; 21, second solder pad; 3, heat conduction layer; 31, upper insulating layer; 32, metal sheet; 33, lower insulating layer; 4, storage chip; 41, first solder pad; 42, first lead wire; 43, second lead wire; 5, packaging adhesive layer; 6, first organic silicon resin layer; 7, second organic silicon resin layer; 8, heat conduction paste layer; 81, first heat conduction paste layer; 82, second heat conduction paste layer; 83, third heat conduction paste layer; 84, fourth heat conduction paste layer; 85, fifth heat conduction paste layer; 91, first stepped surface; 92, second stepped surface. DETAILED DESCRIPTION

[0035] In order to make the technical problems solved by the present application, technical solutions and beneficial effects more clearly understood, the present application will be further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application, and are not used to limit the present application.

[0036] Referring to Figure 1 and Figure 2As shown, an embodiment of the present application provides a packaging structure of a storage chip, which comprises a substrate 1, a control chip 2, a heat-conducting layer 3, a storage chip 4, a heat-conducting paste layer 8 and a packaging adhesive layer 5. The control chip 2 is arranged on the surface of the substrate 1. The heat-conducting layer 3 is arranged on the surface of the control chip 2 away from the substrate 1 and partially extends out of the coverage of the control chip 2. The number of the storage chips 4 is multiple. The multiple storage chips 4 are arranged in a stepped staggered manner on the surface of the heat-conducting layer 3 away from the control chip 2 to form a first stepped surface 91 and a second stepped surface 92 on both sides of the multiple storage chips 4 respectively. The multiple storage chips 4 are electrically connected to each other at the position of the first stepped surface 91. The storage chip 4 is electrically connected to the control chip 2. The packaging adhesive layer 5 is arranged on the substrate 1. The control chip 2, the heat-conducting layer 3 and the storage chip 4 are located in the packaging adhesive layer 5. The heat-conducting layer 3 at least partially extends out of the packaging adhesive layer 5. The heat-conducting paste layer 8 comprises a first heat-conducting paste layer 81 and a second heat-conducting paste layer 82. The first heat-conducting paste layer 81 covers the second stepped surface 92. The second heat-conducting paste layer 82 covers the outer surface of the packaging adhesive layer 5. The first heat-conducting paste layer 81 and the second heat-conducting paste layer 82 are connected to each other. The heat-conducting layer 3 and the second heat-conducting paste layer 82 are connected to each other.

[0037] The first heat-conducting paste layer 81 located on the second stepped surface 92 can improve the temperature consistency between the multiple storage chips 4, reduce the stress caused by the different temperature and volume change rates of each storage chip 4, and be beneficial to improving the electrical connection stability of the lead wire. Meanwhile, through the heat conduction of the first heat-conducting paste layer 81, the heat-conducting layer 3 and the second heat-conducting paste layer 82, the heat of the storage chip 4 and the control chip 2 can be directly conducted to the outer surface of the packaging adhesive layer 5, so as to effectively improve the heat dissipation efficiency of the packaging structure and be beneficial to heat dissipation through an external heat dissipation structure (heat pipe, etc.), thereby reducing the temperature of the storage chip 4 and the control chip 2 and improving the service life.

[0038] Furthermore, when the second heat-conducting paste layer 82 adopts graphene paste or metal paste, it has good electromagnetic shielding effect. According to the principle of electromagnetism, due to the high electrical conductivity of graphene paste or metal paste, the free electrons in the conductor will move directionally under the action of electric field force under the action of external electromagnetic signals. An opposite charge distribution to the external electric field is induced on the outer surface of the cage to generate an electromagnetic field opposite to the incident electromagnetic wave, thereby reducing the electromagnetic wave intensity penetrating through the second heat-conducting paste layer 82, realizing the signal shielding effect, reducing the external electromagnetic interference and improving the stability of the operation of the storage chip 4.

[0039] In an embodiment, the memory chip 4 is provided with at least one first pad 41 at the position of the first stepped surface 91, and the first pads 41 of two adjacent memory chips 4 are connected to each other by a first lead 42. The control chip 2 is provided with at least one second pad 21, and the second pad 21 and the first pad 41 are connected to each other by a second lead 43.

[0040] As shown in FIG. 1, the memory chip 4 is provided with at least one first pad 41 at the position of the first stepped surface 91. Specifically, the first pad 41 is located on the surface of the first stepped surface 91 away from the substrate 1, and the first pads 41 of the plurality of memory chips 4 are arranged one by one to form a matrix arrangement structure of multiple rows and multiple columns. The first pads 41 in the same column are sequentially connected by a first lead 42. Correspondingly, the control chip 2 is provided with a plurality of second pads 21 corresponding to the arrangement extension position of the plurality of first pads 41. The second pad 21 on the control chip 2 and the first pad 41 closest to the second pad 21 are connected by a second lead 43. The control chip 2 is responsible for controlling and managing the read-write operation of the memory chip 4. Figure 2 The above arrangement of the first pad 41, the second pad 21, the first lead 42 and the second lead 43 is conducive to reducing the transmission distance of electrical signals, reducing signal attenuation and external interference, enabling the control chip 2 to effectively control and manage the read-write operation of the memory chip 4, and ensuring the normal operation of the entire memory chip 4 system.

[0041] In some embodiments, the first lead 42 and the second lead 43 are metal wires. In other embodiments, the first lead 42 and the second lead 43 can also be replaced by other electrical connection structures.

[0042] In some embodiments, the side of the substrate 1 away from the control chip 2 is provided with a solder structure 11. The first solder structure 11 is used to realize the electrical connection and mechanical fixation between the substrate 1 and other external structures. In a specific embodiment, the solder structure 11 is a solder ball.

[0043] In some embodiments, an electrical connection structure is provided between the control chip 2 and the substrate 1. For example, an electrical connection bump can be provided at the bottom of the control chip 2, and an electrical conduction structure is provided in the substrate 1 to electrically connect the electrical connection bump and the solder structure 11. For another example, a third pad can be provided on the control chip 2, a fourth pad can be provided on the substrate 1, and a lead is provided between the third pad and the fourth pad to electrically connect the fourth pad and the solder structure 11.

[0044]

[0045] ​In some embodiments, lead wires and / or other connecting structures can also be provided to achieve electrical connection between the storage chips 4 and the soldering structure 11.

[0046] In some embodiments, the heat-conducting paste layer 8 further comprises a third heat-conducting paste layer 83 covering the surface of the heat-conducting layer 3 extending out of the control chip 2 and a fourth heat-conducting paste layer 84 covering the side surface of the control chip 2, and the first heat-conducting paste layer 81, the second heat-conducting paste layer 82, the third heat-conducting paste layer 83 and the fourth heat-conducting paste layer 84 are connected as a whole.

[0047] The third heat-conducting paste layer 83 can enhance the heat dissipation capacity of the extending part of the heat-conducting layer 3, so that the heat-conducting layer 3 can more efficiently conduct heat away; the fourth heat-conducting paste layer 84 can increase the heat dissipation area of the side surface of the control chip 2, effectively improving the heat dissipation efficiency of the control chip 2. The heat-conducting paste layers 8 are connected as a whole to form a continuous heat-conducting channel, further optimizing the heat conduction path, so that the heat located inside the packaging structure can be quickly conducted to the surface of the packaging structure, improving the heat dissipation performance of the entire packaging structure.

[0048] In some embodiments, a first organic silicon resin layer 6 is provided between adjacent storage chips 4, between the first heat-conducting paste layer 81 and the storage chips 4, and between the fourth heat-conducting paste layer 84 and the control chip 2.

[0049] The first organic silicon resin layer 6 serves as an adhesive to ensure the bonding and fixation between different storage chips 4, as an insulating layer to prevent electrical short circuit between the storage chips 4, the heat-conducting paste layer 8 and the control chip 2 due to the good insulation of the organic silicon resin and the electrical conductivity of the heat-conducting paste layer 8, and as a buffer layer to adapt to the stress caused by the volume change between the storage chips 4 due to the deformation elasticity of the organic silicon resin layer, ensuring the bonding, improving the stability of the connection between the storage chips 4 and avoiding the generation of cracks caused by stress.

[0050] In some embodiments, a second organic silicon resin layer 7 is provided on the side of the first heat-conducting paste layer 81 away from the storage chips 4, on the side of the third heat-conducting paste layer 83 away from the heat-conducting layer 3, and on the side of the fourth heat-conducting paste layer 84 away from the control chip 2, and the packaging adhesive layer 5 is made of epoxy resin material.

[0051] The epoxy resin material has the advantages of high thermal stability, low water vapor permeability and high curing hardness as the encapsulating adhesive layer 5, and can better avoid the influence of the external environment on the internal storage chip 4 and the control chip 2, but the epoxy resin has shrinkage stress in the curing process, and the influence of the shrinkage stress is small in the traditional packaging structure, but in the present application, since the heat-conducting paste layer 8 is arranged, when the “second packaging” is performed, due to the shrinkage stress between the epoxy resin and the storage chip 4, the heat-conducting layer 3 and the control chip 2, the first heat-conducting paste layer 81, the third heat-conducting paste layer 83 and the fourth heat-conducting paste layer 84 are prone to separate from the surface of the storage chip 4, the heat-conducting layer 3 and the control chip 2, and gaps are formed between the first heat-conducting paste layer 81, the third heat-conducting paste layer 83, the fourth heat-conducting paste layer 84 and the storage chip 4, the heat-conducting layer 3 and the control chip 2, which will affect the heat conduction efficiency between the first heat-conducting paste layer 81, the third heat-conducting paste layer 83, the fourth heat-conducting paste layer 84 and the storage chip 4, the heat-conducting layer 3 and the control chip 2, in order to avoid this situation, the second organic silicon resin layer 7 is arranged, and the deformation buffering effect of the organic silicon resin is utilized to reduce the shrinkage stress generated by the curing of the epoxy resin and directly act on the first heat-conducting paste layer 81, the third heat-conducting paste layer 83 and the fourth heat-conducting paste layer 84, thereby effectively ensuring the contact between the first heat-conducting paste layer 81, the third heat-conducting paste layer 83, the fourth heat-conducting paste layer 84 and the storage chip 4, the heat-conducting layer 3 and the control chip 2, and improving the heat conduction efficiency.

[0052] In some embodiments, the first organic silicon resin layer 6 and the second organic silicon resin layer 7 are both obtained by curing of an organic silicon paste, and the organic silicon paste comprises the following components by weight:

[0053] The organic silicon resin is 40-60 parts, the hydrogen-containing silicone oil is 3-10 parts, the catalyst is 0.05-1 part, the filler is 10-20 parts, and the solvent is 10-70 parts.

[0054] In some embodiments, the heat-conducting paste layer 8 is obtained by curing of a heat-conducting paste, and the heat-conducting paste comprises the following components by weight:

[0055] The graphene is 2-11 parts, the tetraethyl orthosilicate is 0.5-4 parts, and the solvent is 81-93 parts.

[0056] By adding tetraethyl orthosilicate in the graphene paste, since the tetraethyl orthosilicate has multiple siloxane structures, it can hydrolyze and condense with the hydroxyl groups on the surface of the graphene, and can also hydrolyze and condense directly with the organic silicon resin in the first organic silicon resin layer 6 and the second organic silicon resin layer 7, thereby forming a connecting structure between the graphene and the organic silicon resin, improving the connection strength between the heat-conducting paste layer 8 and the first organic silicon resin layer 6 and the second organic silicon resin layer 7, and improving the heat conduction efficiency and structural stability.

[0057] In some embodiments, the heat-conducting layer 3 comprises a metal sheet 32, an upper insulating layer 31 located between the metal sheet 32 and the storage chip 4, and a lower insulating layer 33 located between the metal sheet 32 and the control chip 2, the thickness of the lower insulating layer 33 is less than the thickness of the upper insulating layer 31.

[0058] The upper insulating layer 31 and the lower insulating layer 33 can prevent electrical short circuit between the metal sheet 32 and the storage chip 4 and the control chip 2, and ensure electrical safety.

[0059] In some embodiments, the thickness of the lower insulating layer 33 is 1-10 μm, and the thickness of the upper insulating layer 31 is 15-1000 μm.

[0060] By setting the thickness of the lower insulating layer 33 to be less than the thickness of the upper insulating layer 31, on one hand, the heat conduction efficiency between the metal sheet 32 and the control chip 2 can be improved, and on the other hand, the heat conduction efficiency between the metal sheet 32 and the storage chip 4 can be reduced, so that the heat conduction to the storage chip 4 closest to the control chip 2 can be avoided while the heat dissipation effect on the control chip 2 is ensured.

[0061] In some embodiments, the upper insulating layer 31 and the lower insulating layer 33 are selected from a polyimide layer.

[0062] In some embodiments, the end of the metal sheet 32 extends out of the encapsulation adhesive layer 5 and is bent to form a bent portion, and the bent portion is attached to the surface of the second heat-conducting paste layer 82.

[0063] The bent portion is beneficial to increase the heat conduction area between the heat-conducting layer 3 and the second heat-conducting paste layer 82, and improve the heat dissipation effect.

[0064] In some embodiments, the heat-conducting paste layer 8 further comprises a fifth heat-conducting paste layer 85, the fifth heat-conducting paste layer 85 is located in the encapsulation adhesive layer 5, one end of the fifth heat-conducting paste layer 85 is connected to the first heat-conducting paste layer 81, and the other end of the fifth heat-conducting paste layer 85 is connected to the second heat-conducting paste layer 82.

[0065] The fifth heat-conducting paste layer 85 serves as a heat-conducting intermediate body of the first heat-conducting paste layer 81 and the second heat-conducting paste layer 82, and can improve the heat conduction efficiency of the first heat-conducting paste layer 81 and the second heat-conducting paste layer 82, and further improve the heat dissipation effect on the storage chip 4.

[0066] Another embodiment of the present application provides a preparation method of the packaging structure of the storage chip as described above, comprising the following operation steps:

[0067] Multiple memory chips are stacked in a staggered manner to obtain a memory chip stack, with a first step surface and a second step surface formed on both sides of the memory chip stack.

[0068] The control chip is fixed to the substrate. The thermally conductive layer and the memory chip stack are then placed on the side of the control chip facing away from the substrate and pre-fixed. Lead wires are then electrically connected to the memory chip and the control chip on the first stepped surface, resulting in the following... Figure 3 The first intermediate structure shown;

[0069] The control chip, thermal conductive layer, and memory chip stack are masked on one side of the second step surface. Encapsulating adhesive is then used to pre-encapsulate the control chip, thermal conductive layer, and memory chip stack on the side of the first step surface, resulting in the following... Figure 4 The second intermediate structure shown;

[0070] Remove the shielding on one side of the second step surface of the control chip, thermal conductive layer and memory chip stack, apply thermal conductive paste to one side of the second step surface of the control chip, thermal conductive layer and memory chip stack, and cure.

[0071] Encapsulating adhesive is used to re-encapsulate the control chip, thermal conductive layer, and memory chip laminate on one side of the second step surface. An encapsulating adhesive layer is formed on the exterior of the control chip, the thermal conductive layer, and the memory chip, with the thermal conductive layer at least partially extending beyond the encapsulating adhesive layer, resulting in the following... Figure 5 The third intermediate structure shown;

[0072] A thermally conductive paste is applied to the outside of the encapsulating adhesive layer and cured to form a thermally conductive paste layer.

[0073] In the description of this invention, the application methods for thermally conductive paste and silicone paste can be selected from commonly used existing methods, such as spraying, physical vapor deposition, etc.

[0074] In some embodiments, before performing the staggered stacking of memory chips: applying and curing an organosilicon paste to the bottom surface and one side surface of the memory chip; applying and curing an organosilicon paste to the top surface and one side surface of the control chip; thus obtaining a first organosilicon resin layer.

[0075] After the thermally conductive paste is applied and cured, and before re-encapsulation: an organosilicon paste is applied and cured on one side of the second step surface of the stack of control chip, thermally conductive layer and memory chip to obtain a second organosilicon resin layer.

[0076] In some embodiments, after the thermally conductive paste layer has been cured to form, the portion of the thermally conductive layer extending beyond the encapsulating adhesive layer is bent so that it adheres to the surface of the thermally conductive paste layer.

[0077] The application will be further described by examples.

[0078] Example 1

[0079] The present example is used to illustrate the preparation method of the packaging structure of the storage chip disclosed by the application, which comprises the following operation steps:

[0080] The bottom surface and one side surface of the storage chip are subjected to organic silicon slurry application and solidification; the top surface and one side surface of the control chip are subjected to organic silicon slurry application and solidification; a first organic silicon resin layer is obtained;

[0081] The organic silicon slurry comprises the following components by weight:

[0082] The organic silicon resin is 50 parts, the hydrogen-containing silicone oil is 5 parts, the triethylenediamine is 0.5 parts, the fumed silica is 15 parts, and the toluene is 50 parts.

[0083] The plurality of storage chips are subjected to stepped staggered lamination to obtain a storage chip laminate, and a first stepped surface and a second stepped surface are respectively formed on the two sides of the storage chip laminate;

[0084] The control chip is fixed on the substrate, the heat-conducting layer and the storage chip laminate are sequentially placed on the side of the control chip away from the substrate and are pre-fixed, and the storage chip and the control chip are electrically connected by leads at the first stepped surface; the heat-conducting layer comprises a first polyimide layer, a metal sheet and a second polyimide layer which are sequentially laminated, and the end of the metal sheet is exposed outside the control chip and the storage chip;

[0085] The control chip, the heat-conducting layer and the storage chip laminate are shielded on the side of the second stepped surface, and the control chip, the heat-conducting layer and the storage chip laminate on the side of the first stepped surface are pre-packaged by using packaging glue;

[0086] The shielding of the control chip, the heat-conducting layer and the storage chip laminate on the side of the second stepped surface is removed, and the heat-conducting slurry is applied to the side of the second stepped surface of the control chip, the heat-conducting layer and the storage chip laminate and is solidified;

[0087] The organic silicon slurry is applied to the side of the second stepped surface of the control chip, the heat-conducting layer and the storage chip laminate and is solidified to obtain a second organic silicon resin layer;

[0088] The control chip, the heat-conducting layer and the storage chip laminate on the side of the second stepped surface are packaged again by using packaging glue, and a packaging glue layer is formed outside the control chip, the heat-conducting layer and the storage chip, and the end of the metal sheet extends out of the packaging glue layer;

[0089] A heat-conducting paste is applied to the outside of the encapsulating glue layer, and is cured to form a heat-conducting paste layer; the part of the metal sheet extending out of the encapsulating glue layer is bent to attach to the surface of the heat-conducting paste layer.

[0090] The heat-conducting paste comprises the following components by weight:

[0091] 5 parts of graphene, 2 parts of tetraethyl orthosilicate and 85 parts of water.

[0092] Example 2

[0093] This example is used to illustrate the preparation method of the encapsulating structure of the storage chip disclosed in the present application, which comprises most of the operation steps in Example 1, and the difference lies in that:

[0094] The organic silicon paste comprises the following components by weight:

[0095] 60 parts of organic silicon resin, 3 parts of hydrogen-containing silicone oil, 0.05 parts of triethylenediamine, 20 parts of fumed silica and 40 parts of toluene.

[0096] Example 3

[0097] This example is used to illustrate the preparation method of the encapsulating structure of the storage chip disclosed in the present application, which comprises most of the operation steps in Example 1, and the difference lies in that:

[0098] The heat-conducting paste comprises the following components by weight:

[0099] 5 parts of graphene, 2 parts of polyacrylate and 85 parts of water.

[0100] Example 4

[0101] This example is used to illustrate the preparation method of the encapsulating structure of the storage chip disclosed in the present application, which comprises most of the operation steps in Example 1, and the difference lies in that:

[0102] The operation of applying the second organic silicon resin layer is not performed.

[0103] Example 5

[0104] This example is used to illustrate the preparation method of the encapsulating structure of the storage chip disclosed in the present application, which comprises most of the operation steps in Example 1, and the difference lies in that:

[0105] The bending operation of the heat-conducting layer is not performed.

[0106] Comparative Example 1

[0107] This comparative example is used to compare the preparation method of the encapsulating structure of the storage chip disclosed in the present application, which comprises most of the operation steps in Example 1, and the difference lies in that:

[0108] The application of the heat-conductive paste is not performed on all the storage chips.

[0109] Comparative Example 2

[0110] The present comparative example is used to illustrate the preparation method of the packaging structure of the storage chip disclosed in the present application, which includes most of the operation steps in Example 1, and the difference is that:

[0111] The application of the heat-conductive paste inside the packaging structure is not performed, and the application of the heat-conductive paste outside the packaging structure is performed.

[0112] Comparative Example 3

[0113] The present comparative example is used to illustrate the preparation method of the packaging structure of the storage chip disclosed in the present application, which includes most of the operation steps in Example 1, and the difference is that:

[0114] The heat-conductive layer is not provided, and the storage chip stack is directly stacked on the surface of the control chip.

[0115] Performance test

[0116] The packaging structure of the storage chip prepared above is subjected to the following performance test:

[0117] After the packaged packaging structure is placed in a 100℃ oven for 2h, the packaging structure is taken out and placed on the same glass substrate, and is naturally cooled at room temperature 25℃. After 2min and 4min, the surface temperature is detected by using a non-contact infrared temperature measuring device, and the test results are filled in Table 1.

[0118] Table 1

[0119]

[0120] From the test results in Table 1, it can be seen that the packaging structure provided by the present application can effectively improve the heat conduction efficiency between the internal chip and the external, and further improve the cooling effect of the storage chip and the control chip, thereby avoiding the internal temperature from being too high during work, and being beneficial to prolonging the service life.

[0121] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A package structure of a memory chip, characterized by, The application relates to a packaging structure of a memory chip, which comprises a substrate, a control chip, a heat-conducting layer, a memory chip, a heat-conducting paste layer and a packaging adhesive layer. The heat-conducting paste layer further comprises a third heat-conducting paste layer and a fourth heat-conducting paste layer, the third heat-conducting paste layer covers the surface of the heat-conducting layer extending out of the control chip, and the fourth heat-conducting paste layer covers the side surface of the control chip. The first heat-conducting paste layer, the second heat-conducting paste layer, the third heat-conducting paste layer and the fourth heat-conducting paste layer are connected as a whole. The first heat-conducting paste layer, the second heat-conducting paste layer, the third heat-conducting paste layer and the fourth heat-conducting paste layer are connected as a whole. The first heat-conducting paste layer, the second heat-conducting paste layer, the third heat-conducting paste layer and the fourth heat-conducting paste layer are connected as a whole. The first heat-conducting paste layer, the second heat-conducting paste layer, the third heat-conducting paste layer and the fourth heat-conducting paste layer are connected as a whole.

2. The package structure of memory chips according to claim 1, wherein, The first heat-conducting paste layer, the second heat-conducting paste layer, the third heat-conducting paste layer and the fourth heat-conducting paste layer are connected as a whole.

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The package structure of memory chips according to claim 1, wherein, The heat-conducting layer comprises a metal sheet, an upper insulating layer and a lower insulating layer, the upper insulating layer is located between the metal sheet and the storage chip, the lower insulating layer is located between the metal sheet and the control chip, the thickness of the lower insulating layer is less than the thickness of the upper insulating layer, the end of the metal sheet extends out of the encapsulation adhesive layer and is bent to form a bending part, and the bending part is attached to the surface of the second heat-conducting paste layer.

5. The package structure of memory chips according to claim 1, wherein, The heat-conducting paste layer further comprises a fifth heat-conducting paste layer, the fifth heat-conducting paste layer is located in the encapsulation adhesive layer, and one end of the fifth heat-conducting paste layer is connected to the first heat-conducting paste layer, and the other end of the fifth heat-conducting paste layer is connected to the second heat-conducting paste layer.

6. The method of claim 1 to 5, wherein The method comprises the following operation steps: The bottom surface and one side surface of the storage chip are applied with silicone paste and cured, and the top surface and one side surface of the control chip are applied with silicone paste and cured. A first silicone resin layer is obtained. The plurality of storage chips are stacked in a stepped staggered manner to obtain a storage chip stack, and the two sides of the storage chip stack are formed with a first stepped surface and a second stepped surface, respectively. The control chip is fixed on the substrate, the heat-conducting layer and the storage chip stack are placed on the side of the control chip away from the substrate and are pre-fixed, the storage chip and the control chip are electrically connected by leads at the first stepped surface. The control chip, the heat-conducting layer and the storage chip stack are shielded on the side of the second stepped surface, and the control chip, the heat-conducting layer and the storage chip stack on the side of the first stepped surface are pre-encapsulated by the encapsulation adhesive. The shielding of the control chip, the heat-conducting layer and the storage chip stack on the side of the second stepped surface is removed, the control chip, the heat-conducting layer and the storage chip stack on the side of the second stepped surface are applied with heat-conducting paste and cured, the control chip, the heat-conducting layer and the storage chip stack on the side of the second stepped surface are applied with silicone paste and cured to obtain a second silicone resin layer. The control chip, the heat-conducting layer and the storage chip stack on the side of the second stepped surface are re-encapsulated by the encapsulation adhesive, and an encapsulation adhesive layer is formed outside the control chip, the heat-conducting layer and the storage chip, and the heat-conducting layer at least partially extends out of the encapsulation adhesive layer. Heat-conducting paste is applied to the outside of the encapsulation adhesive layer and cured to form a heat-conducting paste layer.

7. The method of claim 6, wherein the method further comprises: After the heat-conducting paste layer is cured, the part of the heat-conducting layer extending out of the encapsulation adhesive layer is bent to attach to the surface of the heat-conducting paste layer.

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