Ring gate transistor preparation process based on supercritical CO2 assistance

Abstract

The invention discloses a supercritical CO2 assistance-based ring gate transistor preparation process. The process comprises the steps of alternately extending sacrificial layers and channel layers on a substrate to form a periodic laminated structure; a patterned hard mask is deposited on the laminated structure, the laminated structure is etched into at least one periodically distributed fin, the etching depth is larger than the total thickness of the periodic laminated structure, a shallow groove is formed in the substrate, and the shallow groove is filled with a shallow groove isolation layer; depositing a dummy gate structure on the fin, and preparing inner side walls of which the outer walls are aligned with the outer walls of the side walls at the two ends of the fin in the channel region; epitaxially growing a source / drain on two sides of the source / drain forming region; selectively removing the sacrificial layer of the fin in the channel region, and replacing the sacrificial layer with a high-k metal gate; and depositing a second interconnection dielectric layer above the device structure, etching the first interconnection dielectric layer and the second interconnection dielectric layer to form a contact hole communicated with the source / drain electrode and the gate metal, and filling interconnection metal into the hole.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and more particularly, to a preparation process of a gate-all-around transistor assisted by supercritical CO2. Background Art

[0002] A gate-all-around field effect transistor (GAAFET) is a three-dimensional structure device that enhances gate control by surrounding the channel in all directions and is regarded as the mainstream device for 3 nm and below process nodes in the post-Moore era. Compared with the three-sided surrounding channel structure of the previous generation fin field effect transistor (FinFET), the fully surrounded structure of GAAFET can achieve more precise control of the on-state current and significant suppression of the leakage current, but the process complexity also increases accordingly. Taking the vertically stacked Si nanosheet GAAFET as an example, the formation of the fully surrounded gate requires first defining the source / drain on both sides based on a multi-layer Si / SiGe stacked structure, then forming the Si channel by horizontally etching the SiGe sacrificial layer, and finally forming the high-k gate dielectric and the metal gate around the channel. Different from the conventional vertical etching process, the sacrificial SiGe layer requires a highly selective and high-quality etching method to ensure the lossless release of the Si nanosheet channel. After the Si channel is formed, the high-k gate dielectric and the gate metal also need to be conformally deposited and filled around the Si nanosheets. Both of the above processes are carried out in a three-dimensional structure at the nanoscale, so strict requirements are imposed on the etching and deposition processes. Traditional water-based wet etching may cause the collapse of the Si nanosheet structure due to the relatively high surface tension, while dry etching such as atomic layer etching (ALE) has no collapse problem, but the etching rate is slow. Atomic layer deposition (ALD) is a well-known highly conformal deposition process, but its self-limiting reaction mechanism results in a low deposition rate. For the rapid deposition of relatively thick metals, a hybrid method of ALD depositing a seed layer and chemical vapor deposition (CVD) filling can be used, but the applicability of this strategy for nanoscale three-dimensional structures cannot be guaranteed.

[0003] Supercritical carbon dioxide (SC-CO2) is a widely used supercritical fluid with many excellent properties such as a low critical point (Tc = 31.1 °C, pc = 7.38 MPa), liquid-like solubility, gas-like transport behavior, zero surface tension, and reaction inertness. In the field of semiconductor technology, low-temperature processing technologies based on SC-CO2 have been developed, such as SC-CO2-assisted etching, supercritical fluid deposition (SCFD), etc. For SC-CO2-assisted etching, an etchant and a co-solvent are added to the SC-CO2 medium, and the sacrificial layer can be easily etched and the etching residues can be removed by utilizing its transport. For the SCFD of metals, the metal precursor dissolved in SC-CO2 is transported to a specific substrate surface and then reduced to a metal, and due to the continuous transport of SC-CO2 for the precursor and the removal of by-products, a high deposition rate is achieved. The advantage of the above processes is that the zero-tension property of SC-CO2 makes it particularly suitable for the processing of three-dimensional complex structures without causing structural collapse.

[0004] Therefore, the inventors believe that in a three-dimensional structure with a predefined sacrificial layer and non-sacrificial layer, first removing the sacrificial layer by SC-CO2-assisted etching and then achieving conformal filling of the metal by SCFD is a feasible route for preparing high-quality three-dimensional structures. Based on the problems existing in the above prior art and the etching-deposition advantages of SC-CO2, the present invention team proposes a SiGe sacrificial layer etching and gate metal deposition process for GAAFET based on SC-CO2 assistance, which largely makes up for the deficiencies of traditional processes while ensuring process efficiency and quality. Summary of the Invention

[0005] This application solves the problems of deficiencies in the preparation process, efficiency, and quality in the prior art by providing a preparation process for a gate-all-around transistor based on supercritical CO2 assistance.

[0006] This application provides a preparation process for a gate-all-around transistor based on supercritical CO2 assistance, which is characterized by including the following steps: Step 1: Alternately epitaxially grow a sacrificial layer and a channel layer on a substrate to form a periodic laminated structure; Step 2: Deposit a patterned hard mask above the periodic laminated structure, then etch the periodic laminated structure into at least one periodically distributed fin, the etching depth is greater than the total thickness of the periodic laminated structure and a shallow trench is formed on the substrate, and a shallow trench isolation layer is filled into the shallow trench; Step 3: Deposit a dummy gate structure on the fin. The dummy gate structure sequentially includes an interface layer conformally deposited on the surface of the fin, a silicon layer filled above the fin interface layer and the shallow trench isolation layer, and a patterned hard mask layer deposited above the silicon layer. A sidewall is conformally deposited and anisotropically etched on the sidewall surface of the dummy gate structure at the top of the fin. Step 4: Define the part of the fin surrounded by the dummy gate structure laterally as the channel region, and the part not surrounded as the source / drain formation region. Prepare inner sidewall structures at the front and rear ends of the periodic stacked structure of the fin in the channel region, and align the outer walls of the inner sidewall structures with the outer walls of the sidewalls. Step 5: Epitaxially grow the source / drain on both sides of the source / drain formation region. Step 6: Deposit a first interconnect dielectric layer above the source / drain, and remove the dummy gate structure through an etching process. By using a supercritical CO2-assisted etching process, selectively remove the sacrificial layer of the fin in the channel region, and replace the dummy gate structure and the sacrificial layer (2) of the fin in the channel region with a high-k metal gate to form a fully surrounding gate structure. Step 7: Deposit a second interconnect dielectric layer above the device structure, etch the first interconnect dielectric layer and the second interconnect dielectric layer to form contact holes connected to the source / drain and the gate metal, and fill the holes with interconnect metal to complete the preparation of the gate-all-around transistor device.

[0007] Preferably, in Step 1, the sacrificial layer and the channel layer are made of SiGe and Si respectively, and the thickness ratio of the sacrificial layer to the channel layer is controlled within the range of 0.5:1 to 1.5:1.

[0008] Preferably, in Step 2, the shallow trench isolation layer is filled with STI material, then a planarization process is performed, and finally the thickness of the STI material layer is controlled by etching to expose the main structure of the fin. Preferably, the specific steps of Step 3 include: a) Conformally deposit an interface layer on the surface of the fin to protect the dummy gate / fin interface. b) Fill a silicon layer above the fin interface layer and the shallow trench isolation layer as the main body of the dummy gate structure, and perform a planarization process. c) Deposit a patterned hard mask layer above the silicon layer, and then through a selective etching process, etch the silicon layer into a periodic structure spanning the fin, and define the part of the fin surrounded by the dummy gate structure laterally as the channel region, and the part not surrounded as the source / drain formation region. d) Conformally deposit a dielectric material on the sidewall surface of the dummy gate structure, and form a sidewall through an anisotropic etching process.

[0009] Preferably, the specific steps of Step 4 include: Step 4.1: By means of an etching process, remove the source / drain formation regions of the fin, exposing the sidewall surfaces of the channel region not surrounded by the dummy gate structure. Step 4.2: By means of a supercritical CO2-assisted etching process, selectively and locally remove the sacrificial layer of the fin in the channel region to form horizontal grooves with a consistent depth, and the horizontal depth of the grooves is less than or equal to the thickness of the sidewall. Step 4.3: Fill the inner sidewall at the horizontal grooves of the fin in the channel region, and then thin it until it is flush with the two ends of the unetched channel of the fin in the channel region, so as to achieve self-alignment between the outer wall of the inner sidewall and the outer wall of the sidewall.

[0010] Preferably, in step 4.2, the method of the supercritical CO2-assisted etching process is as follows: Place the substrate with the fin whose source / drain formation regions have been removed into the reaction chamber. By introducing CO2 and an etchant into the reaction chamber, make the etchant contact and react with the sacrificial layer of the fin in the channel region to achieve etching of the sacrificial layer; CO2 reaches the supercritical state in the reaction chamber.

[0011] Preferably, step 6 includes: Step 6.1: Deposit a first interconnect dielectric layer above the source / drain, and then thin it by a planarization process until it reaches the patterned hard mask layer of the dummy gate structure. Step 6.2: Remove the dummy gate structure including the interface layer, the silicon layer and the patterned hard mask layer by an etching process, exposing the surrounded fin in the channel region. Step 6.3: By means of a supercritical CO2-assisted etching process, selectively remove the sacrificial layer of the fin in the channel region, thereby completely releasing the channel layer. Step 6.4: By means of atomic layer deposition, conformally deposit a gate stack around the channel layer, and this stack is sequentially deposited by a high-k gate dielectric and a work function layer. Step 6.5: Fill the gate metal by a supercritical fluid deposition process to form a fully surrounding gate structure. Step 6.6: Adopt a planarization process to remove the redundant gate structure on the first interconnect dielectric layer.

[0012] Preferably, step 6.5 includes: Place the device structure with the deposited gate stack into the reaction chamber. By introducing CO2 and a metal precursor into the reaction chamber, make the metal precursor transport to the surface of the work function layer, and introduce a reducing gas into the reaction chamber to reduce the metal precursor to metal on the surface of the work function layer until it is completely filled; wherein, CO2 is in the supercritical state in the reaction chamber. After the supercritical fluid deposition process is completed, continuously introduce supercritical CO2 to remove by-products and redundant metal precursors.

[0013] Preferably, the metal precursor is a metal-organic complex M x Ny , where M is a metal, N is an organic ligand, M is W, Cu, Ru or Co, and N is acetylacetonyl, hexafluoroacetylacetonyl, carbonyl or cyclopentadienyl.

[0014] Preferably, the high-k gate dielectric is a metal oxide such as HfO2, ZrO2 or TiO2; the work function layer is a metal nitride such as TiN or TaN.

[0015] The technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: By using the supercritical CO2-assisted etching process, the etchant is transported to the sacrificial layer of the fin in the channel region through supercritical CO2, which not only realizes the rapid etching of the sacrificial layer but also avoids the damage of the surface tension to the channel layer structure, making up for the deficiencies of the traditional aqueous etching process and atomic layer etching process. On the other hand, by utilizing the significant advantages of the supercritical fluid deposition process in filling complex structures, the layer-by-layer efficient filling of the gate metal of the gate-all-around transistor can be achieved, thereby preparing a high-quality high-k metal gate structure. In addition, due to the solubility of supercritical CO2, the etching and deposition processes based on supercritical CO2 can greatly reduce residues, simplify the manufacturing process of the gate-all-around transistor, and improve the compatibility with other processes. Description of the Drawings

[0016] Figure 1 is a three-dimensional view of the gate-all-around transistor device structure prepared in the embodiment of the present application; Figure 2 is Figure 1 a cross-sectional view of the device in the X-X direction; Figure 3 is a central cross-sectional view of the periodic stacked structure prepared in the embodiment of the present application; Figure 4 is a central cross-sectional view of the fin and shallow trench isolation layer prepared in the embodiment of the present application; Figure 5 is a central cross-sectional view of the steps for preparing the dummy gate structure in the embodiment of the present application; Figure 6 is a central cross-sectional view of the steps for preparing the sidewall in the X-X direction in the embodiment of the present application; Figure 7 is a central cross-sectional view of the steps for preparing the inner sidewall in the X-X direction in the embodiment of the present application; Figure 8 is a central cross-sectional view of the steps for preparing the source / drain in the X-X direction in the embodiment of the present application; Figure 9 is a central cross-sectional view of the steps for preparing the first interconnection dielectric layer in the X-X direction in the embodiment of the present application; Figure 10 is a central cross-sectional view after removing the dummy gate structure in the embodiment of the present application; Figure 11Central cross-sectional view after removing the sacrificial layer in the embodiment of the present application; Figure 12 Central cross-sectional view after depositing the gate stack in the embodiment of the present application; Figure 13 Central cross-sectional view after filling the gate metal in the embodiment of the present application; Figure 14 Central cross-sectional view after removing the redundant gate structure in the embodiment of the present application. Embodiment

[0017] To better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with the accompanying drawings of the specification and specific embodiments. Example

[0018] This embodiment provides a manufacturing process for a gate-all-around transistor based on supercritical CO2 assistance, including the following steps: Step 1: On a semiconductor substrate 1, such as single-crystalline silicon or silicon-on-insulator (SOI), alternately epitaxially grow a SiGe sacrificial layer 2 and a Si channel layer 3 to form a periodic stacked structure. The number of stacking periods of the sacrificial layer 2 and the channel layer 3 determines the number of channel layers in the finally formed gate-all-around transistor device; as Figure 3 shown, only an exemplary stack is drawn in the figure of this embodiment, and the actual number of stacking periods can be adjusted according to design and manufacturing requirements.

[0019] Preferably, the thickness ratio of the sacrificial layer 2 to the channel layer 3 in this embodiment should be controlled within the range of 0.5:1 to 1.5:1, and the specific thickness can be adjusted according to the design performance of the gate-all-around transistor device. For example, when the thickness of the channel layer 3 is 10 nm, the optional range of the thickness of the sacrificial layer 2 is 5 to 15 nm.

[0020] Step 2: Deposit a patterned hard mask (not shown in the figure) above the epitaxial periodic stacked structure, and then through a selective etching process, etch the periodic stacked structure into one or more periodically distributed fins; although only an exemplary fin is drawn in the figure, in the design and manufacturing process, the specific number and distribution of the fins can be adjusted according to actual needs. As Figure 4 shown in Figures (a) and (b) therein, where Figure (a) is the central cross-sectional view in the Y-Y direction, and Figure (b) is the central cross-sectional view in the X-X direction.

[0021] Preferably, the etching depth should be greater than the total thickness of the periodic stack structure to create shallow trenches on the substrate 1; then, the shallow trench isolation layer 4 (STI) is filled into the shallow trenches for electrical isolation of adjacent fins; more specifically, first, the STI material is filled, then a planarization process is performed, and finally, the thickness of the STI material layer is controlled by etching to expose the main structure of the fins; furthermore, the thickness of the STI material layer is generally flush with the interface between the substrate 1 and the stack; Optional materials include SiO2, SiN x etc.

[0022] Step 3: Deposit a dummy gate structure on the fin, which consists of an interface layer 5, a silicon layer 6, a hard mask layer 7, and a spacer 8, etc. As shown in Figures (a) and (b) of Figure 5 , where Figure (a) is the central cross-section in the Y - Y direction and Figure (b) is the central cross-section in the X - X direction; specifically: a) Conformally deposit the interface layer 5 on the fin surface to protect the dummy gate / fin interface. Optional materials include SiO2, SiON, etc.; b) Fill the silicon layer 6 as the main body of the dummy gate structure and perform a planarization process. Optional materials include poly - Si, a - Si, etc.; c) Deposit a patterned hard mask layer 7 above the silicon layer 6, and then through a selective etching process, etch the silicon layer 6 into a periodic structure spanning the fin, and define the part of the fin surrounded laterally by the dummy gate as the channel region, and the part not surrounded as the source / drain formation region; d) Conformally deposit a dielectric material on the sidewall surface of the dummy gate structure and form the spacer 8 through an anisotropic etching process. Optional materials include SiN x , SiO2, SiCN, SiOCN, etc., as shown in Figure 6 shown, Figure 6 which is the central cross-section in the X - X direction.

[0023] Step 4: Form an inner spacer 9 structure on both sides of the fin in the channel region, as shown in Figure 7 shown, specifically: Step 4.1, through an etching process, remove the source / drain formation region of the fin to expose the sidewall surface of the channel region not surrounded by the dummy gate structure; as shown in Figure (a) of Figure 7 shown. Step 4.2: By using a supercritical CO2-assisted etching process, selectively and locally remove the sacrificial layer 2 of the fin in the channel region to form horizontal grooves with a consistent depth, and the horizontal depth of the grooves is less than or equal to the thickness of the sidewall 8. For example, when the thickness of the sidewall 8 is 10 nm, the horizontal depth of the grooves can be 5 - 10 nm; as shown in Figure 7 Figure (b) in

[0024] Furthermore, the steps of the supercritical CO2-assisted etching process include: placing the substrate with the source / drain formation region fins removed into the reaction chamber, introducing CO2 and the etchant into the reaction chamber, making the etchant contact and react with the sacrificial layer 2 of the fin in the channel region to achieve the etching of the sacrificial layer 2. More specifically, CO2 must reach the supercritical state in the reaction chamber, that is, both the temperature and pressure of CO2 are above the critical point (T c = 31.1 °C, p c = 7.38 MPa); the etchant is a mixed solution of a fluorine source, an oxidant, and a buffer. The fluorine source can be selected from HF, NH4F, hexafluorosilicate, the oxidant can be selected from H2O2, HNO3, and the buffer is acetic acid; when necessary, a polar co-solvent can be added to increase the solubility of the etchant in supercritical CO2; the polar co-solvent can be selected from organic solvents such as ethanol, propanol, and acetone; after the etching is completed, supercritical CO2 can be continuously introduced to remove the etching residues and the excess etchant.

[0025] Step 4.3: Fill the horizontal grooves of the fin in the channel region with the inner sidewall 9, and then thin it until it reaches both ends of the unetched channel layer 3 of the fin in the channel region, realizing the self-alignment between the outer wall of the inner sidewall 9 and the outer wall of the sidewall 8. The inner sidewall material can be selected from SiNx, SiO2, SiCN, SiOCN. As shown in Figure 7 Figure (c) in

[0026] Step 5: Epitaxially grow the source / drain 10 on both sides of the fin in the channel region not surrounded by the dummy gate, and simultaneously perform in-situ doping to adjust the carrier concentration of the source / drain 10. The source / drain material can be selected from Si, SiGe. As shown in Figure 8

[0027] Step 6: Replace the dummy gate structure and the sacrificial layer of the fin in the channel region with a high-k metal gate. Specifically, it includes: Step 6.1: Deposit the first interconnection dielectric layer 11 above the source / drain 10, and then thin it by a planarization process until it reaches the hard mask layer 7 of the dummy gate structure, as shown in Figure 9

[0028] Step 6.2: Remove the dummy gate structure including the interface layer 5, the silicon layer 6, and the hard mask layer 7 through an etching process to expose the surrounded fin in the channel region; as shown in Figure 10 ​​As shown, where Figure (a) is a sectional view in the Y-Y direction and Figure (b) is a sectional view in the X-X direction.

[0029] Step 6.3: Selectively remove the sacrificial layer 2 of the fin in the channel region through a supercritical CO2-assisted etching process, thereby completely releasing the channel layer 3; as Figure 11 shown, where Figure (a) is a sectional view in the Y-Y direction and Figure (b) is a sectional view in the X-X direction.

[0030] Step 6.4: Conformally deposit a gate stack 12 around the channel layer 3 through an atomic layer deposition process. This stack is sequentially deposited with a high-k gate dielectric and a work function layer; among them, the high-k gate dielectric can be selected from metal oxides such as HfO2, ZrO2, TiO2, etc.; the work function layer can be selected from metal nitrides such as TiN, TaN, etc. As Figure 12 shown, where Figure (a) is a sectional view in the Y-Y direction and Figure (b) is a sectional view in the X-X direction.

[0031] Step 6.5: Fill the gate metal 13 through a supercritical fluid deposition (SCFD) process to form a fully surrounding gate structure. As Figure 13 shown: where Figure (a) is a sectional view in the Y-Y direction and Figure (b) is a sectional view in the X-X direction.

[0032] The steps of the SCFD process include: placing the device structure with the deposited gate stack 12 into the reaction chamber, introducing CO2 and a metal precursor into the reaction chamber, transporting the metal precursor to the surface of the work function layer, and introducing a reducing gas into the reaction chamber to reduce the metal precursor to metal on the surface of the work function layer until it is completely filled. Among them, CO2 must reach the supercritical state in the reaction chamber, that is, both the temperature and pressure of CO2 are above the critical point (T c = 31.1 °C, p c = 7.38 MPa).

[0033] Preferably, the metal precursor is generally selected from metal-organic complexes (M x N y , where M is a metal and N is an organic ligand), among which M can be selected from W, Cu, Ru, Co, and N can be selected from acetylacetonate (acac), hexafluoroacetylacetonate (hfac), carbonyl (CO), cyclopentadienyl (Cp), etc. Since metal SCFD is driven by surface catalysis, the reduction of the metal precursor only occurs at the solid-supercritical fluid interface between the work function layer and supercritical CO2, avoiding unnecessary random nucleation while performing conformal filling.

[0034] Preferably, the reducing gas is generally selected from H2, and other gases such as NH3 can also be selected.

[0035] Preferably, after the SCFD process, supercritical CO2 can be continuously introduced to remove by-products and excess metal precursors.

[0036] Step 6.6: Perform a planarization process to remove the excess gate structures on the first interconnect dielectric layer 11. As Figure 14 shown, where (a) is a cross-sectional view in the Y-Y direction and (b) is a cross-sectional view in the X-X direction.

[0037] Step 7: Form an interconnect structure above the device structure. Specifically, it includes: depositing a second interconnect dielectric layer 14; etching the first and second interconnect dielectric layers to form contact holes that communicate with the source / drain and gate metals, and filling the holes with interconnect metal 15 to complete the preparation of the gate-all-around transistor device, as Figure 1 、 Figure 2 shown.

[0038] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements can be made, and these improvements should also be regarded as the protection scope of the present invention.

Claims

1. A preparation process of a gate-all-around transistor based on supercritical CO2 assistance, characterized in that It includes the following steps: Step 1: Alternately epitaxially grow a sacrificial layer (2) and a channel layer (3) on a substrate (1) to form a periodic stacked structure; Step 2: Deposit a patterned hard mask above the periodic stacked structure, then etch the periodic stacked structure into at least one periodically distributed fin, the etching depth being greater than the total thickness of the periodic stacked structure and forming a shallow trench on the substrate (1), and fill the shallow trench with a shallow trench isolation layer (4); Step 3: Deposit a dummy gate structure on the fin, the dummy gate structure sequentially including an interface layer (5) conformally deposited on the surface of the fin, a silicon layer (6) filled above the fin interface layer (5) and the shallow trench isolation layer (4), a patterned hard mask layer (7) deposited above the silicon layer (6), and conformally depositing and anisotropically etching on the sidewall surface of the dummy gate structure at the top of the fin to form sidewalls (8); Step 4: Define the part of the fin surrounded by the dummy gate structure laterally as the channel region, and the part not surrounded as the source / drain formation region, and prepare inner sidewall structures (9) at the front and rear ends of the periodic stacked structure of the fin in the channel region, and the outer walls of the inner sidewall structures (9) are aligned with the outer walls of the sidewalls (8); Step 5: Epitaxially grow source / drains (10) on both sides of the source / drain formation region; Step 6: Deposit a first interconnect dielectric layer (11) above the source / drains (10), and remove the dummy gate structure through an etching process. Through a supercritical CO2-assisted etching process, selectively remove the sacrificial layer (2) of the fin in the channel region, and replace the dummy gate structure and the sacrificial layer (2) of the fin in the channel region with a high-k metal gate to form a fully surrounding gate structure; Step 7: Deposit a second interconnect dielectric layer (14) above the device structure, etch the first interconnect dielectric layer (11) and the second interconnect dielectric layer (14) to form contact holes connected to the source / drains and the gate metal, and fill the holes with interconnect metal (15) to complete the preparation of the gate-all-around transistor device.

2. The manufacturing process of the gate-all-around transistor assisted by supercritical CO2 according to claim 1, characterized in that In Step 1, the sacrificial layer (2) and the channel layer (3) are made of SiGe and Si respectively, and the thickness ratio of the sacrificial layer (2) to the channel layer (3) is controlled within the range of 0.5:1 to 1.5:

1.

3. The manufacturing process of the gate-all-around transistor assisted by supercritical CO2 according to claim 1, characterized in that, In Step 2, the shallow trench isolation layer (4) is filled with STI material, then a planarization process is carried out, and finally the thickness of the STI material layer is controlled by etching to expose the main structure of the fin.

4. The preparation process of the gate-all-around transistor based on supercritical CO2 assistance according to claim 1, wherein, The specific steps of Step 3 include: a) Conformally deposit an interface layer (5) on the surface of the fin to protect the dummy gate / fin interface; b) Fill a silicon layer (6) above the fin interface layer (5) and the shallow trench isolation layer (4) as the main body of the dummy gate structure, and carry out a planarization process; c) Deposit a patterned hard mask layer (7) above the silicon layer (6), then through a selective etching process, etch the silicon layer (6) into a periodic structure spanning the fin, and define the part of the fin surrounded by the dummy gate structure laterally as the channel region, and the part not surrounded as the source / drain formation region; d) Conformally deposit a dielectric material on the sidewall surface of the dummy gate structure, and form sidewalls (8) through an anisotropic etching process.

5. The manufacturing process of the gate-all-around transistor based on supercritical CO2 assistance according to claim 4, wherein The specific steps of Step 4 include: Step 4.1: Through an etching process, remove the source / drain formation regions of the fin, exposing the sidewall surfaces of the channel region that are not surrounded by the dummy gate structure. Step 4.2: Through a supercritical CO2-assisted etching process, selectively and locally remove the sacrificial layer (2) of the fin in the channel region to form horizontal grooves with a consistent depth, and the horizontal depth of the grooves is less than or equal to the thickness of the sidewall (8). Step 4.3: Fill the inner sidewall (9) in the horizontal grooves of the fin in the channel region, and then thin it until it is flush with both ends of the unetched channel layer (3) of the fin in the channel region, so as to achieve self-alignment between the outer wall of the inner sidewall (9) and the outer wall of the sidewall (8).

6. The preparation process of the gate-all-around transistor based on supercritical CO2 assistance according to claim 5, wherein, In Step 4.2, the method of the supercritical CO2-assisted etching process is as follows: Place the substrate with the fin from which the source / drain formation region has been removed into the reaction chamber. By introducing CO2 and an etchant into the reaction chamber, the etchant contacts and reacts with the sacrificial layer (2) of the fin in the channel region to achieve etching of the sacrificial layer (2); CO2 reaches the supercritical state in the reaction chamber.

7. The preparation process of the gate-all-around transistor based on supercritical CO2 assistance according to claim 4, wherein Specifically include : Step 6 includes: Step 6.1: Deposit a first interconnect dielectric layer (11) above the source / drain (10), and then thin it by a planarization process until it reaches the patterned hard mask layer (7) of the dummy gate structure. Step 6.2: Remove the dummy gate structure including the interface layer (5), the silicon layer (6), and the patterned hard mask layer (7) through an etching process, exposing the surrounded fin in the channel region. Step 6.3: Through a supercritical CO2-assisted etching process, selectively remove the sacrificial layer (2) of the fin in the channel region, thereby completely releasing the channel layer (3). Step 6.4: Through atomic layer deposition, conformally deposit a gate stack (12) around the channel layer (3), and this stack is sequentially deposited by a high-k gate dielectric and a work function layer. Step 6.5: Fill the gate metal (13) through a supercritical fluid deposition process to form a fully surrounding gate structure. Step 6.6: Adopt a planarization process to remove the excess gate structure on the first interconnect dielectric layer (11).

8. The preparation process of the gate-all-around transistor based on supercritical CO2 assistance according to claim 7, characterized in that, Step 6.5 includes: Place the device structure with the deposited gate stack (12) into the reaction chamber. By introducing CO2 and a metal precursor into the reaction chamber, the metal precursor is transported to the surface of the work function layer, and a reducing gas is introduced into the reaction chamber to reduce the metal precursor to metal on the surface of the work function layer until it is completely filled; wherein, CO2 is in a supercritical state in the reaction chamber. After the supercritical fluid deposition process is completed, continuously introduce supercritical CO2 to remove by-products and excess metal precursors.

9. The preparation process of the gate-all-around transistor based on supercritical CO2 assistance according to claim 8, characterized in that, The metal precursor is a metal-organic complex M x N y , where M is a metal and N is an organic ligand, M is W, Cu, Ru or Co, and N is acetylacetonate, hexafluoroacetylacetonate, carbonyl or cyclopentadienyl.

10. The preparation process of the gate-all-around transistor based on supercritical CO2 assistance according to claim 7, characterized in that, The high-k gate dielectric is a metal oxide such as HfO2, ZrO2, or TiO2, and the work function layer is a metal nitride such as TiN or TaN.

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