Semiconductor device and forming method thereof

Abstract

The invention provides a semiconductor device and a forming method thereof. The semiconductor device includes a substrate, a channel layer, a barrier layer, a gate electrode, a source electrode, and a drain electrode. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate electrode is disposed on the barrier layer. The gate electrode includes a first gate portion and a second gate portion connected to each other. The source electrode is disposed on the barrier layer. The drain electrode is disposed on the barrier layer. Wherein a first threshold voltage of a first gate portion between the source electrode and the drain electrode is less than a second threshold voltage of a second gate portion between the source electrode and the drain electrode.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a semiconductor device including a first gate portion and a second gate portion and a method of forming the same. Background Art

[0002] Due to the wide band-gap and strong polarization effect of gallium nitride materials, gallium nitride materials are widely used. For example, currently, gallium nitride-based semiconductors have been widely used in power devices, such as high electron mobility transistors (HEMTs) including heterojunction structures.

[0003] However, in high electron mobility transistors, there may be problems such as excessive concentration of the electric field distribution, which may generate hot carriers, resulting in non-uniform electric field distribution, insufficient reliability, and deterioration of semiconductor devices. Therefore, although existing semiconductor devices and methods of forming the same have gradually met their intended uses, they still do not fully meet the requirements in all aspects. Therefore, there are still some problems to be overcome regarding semiconductor devices and methods of forming the same. Summary of the Invention

[0004] The present disclosure adjusts the electric field distribution in a semiconductor device by disposing a first gate portion and a second gate portion between a source electrode and a drain electrode. For example, by making the first threshold voltage (Vt1) of the first gate portion less than the second threshold voltage (Vt2) of the second gate portion, hot carriers are avoided from being generated at the second gate portion or the concentration of hot carriers at the second gate portion is reduced. Thus, having two portions in the gate electrode with different threshold voltages can reduce the excessive concentration of the electric field distribution and reduce hot carriers, making the electric field distribution more uniform, improving reliability, and / or avoiding deterioration of the semiconductor device.

[0005] In some embodiments, the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a channel layer, a blocking layer, a gate electrode, a source electrode, and a drain electrode. The channel layer is disposed on the substrate. The blocking layer is disposed on the channel layer. The gate electrode is disposed on the blocking layer. The gate electrode includes a first gate portion and a second gate portion connected to each other. The source electrode is disposed on the blocking layer. The drain electrode is disposed on the blocking layer. Wherein, the first threshold voltage of the first gate portion between the source electrode and the drain electrode is less than the second threshold voltage of the second gate portion between the source electrode and the drain electrode.

[0006] In some embodiments, the present disclosure provides a method of forming a semiconductor device. The method of forming a semiconductor device includes providing a substrate. Forming a channel layer on the substrate. Forming a blocking layer on the channel layer. Forming a gate electrode on the blocking layer, and wherein the gate electrode includes a first gate portion and a second gate portion connected to each other. Forming a source electrode on the blocking layer. Forming a drain electrode on the blocking layer. Wherein, a first threshold voltage of the first gate portion between the source electrode and the drain electrode is less than a second threshold voltage of the second gate portion between the source electrode and the drain electrode.

[0007] The semiconductor device and its forming method according to the present disclosure can be applied to various types of electronic devices and their forming methods. To make the components and advantages of the present disclosure more obvious and understandable, various embodiments are specifically described below in conjunction with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When read in conjunction with the drawings, the present disclosure can be more fully understood from the following detailed description. It should be noted that, in accordance with the standard practice in the industry, the components are not drawn to scale. In fact, for clarity, the dimensions of the components can be arbitrarily enlarged or reduced.

[0009] Figure 1 is a top view schematic diagram of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 2A and Figure 2B are respectively cross-sectional schematic diagrams of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 3A and Figure 3B are respectively cross-sectional schematic diagrams of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 4A and Figure 4B are respectively cross-sectional schematic diagrams of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 5A and Figure 5B are respectively cross-sectional schematic diagrams of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 6A and Figure 6B are respectively cross-sectional schematic diagrams of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 7A and Figure 7B are respectively cross-sectional schematic diagrams of a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 8A andFigure 8B Schematic cross-sectional views of semiconductor devices according to an embodiment of the present disclosure.

[0017] Symbol Explanation

[0018] 1, 2, 3, 4, 5, 6, 7: Semiconductor device

[0019] 100: Substrate

[0020] 200: Buffer layer

[0021] 300: Channel layer

[0022] 301: Two-dimensional electron gas

[0023] 400: Barrier layer

[0024] 500: Gate electrode

[0025] 500a: First gate portion

[0026] 500b: Second gate portion

[0027] 501: First compound semiconductor layer

[0028] 502: First compound semiconductor layer

[0029] 503: Insulating layer

[0030] 520: Source electrode

[0031] 520a: First source portion

[0032] 520b: Second source portion

[0033] 521: Source end

[0034] 540: Drain electrode

[0035] 541: Drain end

[0036] 540a: First drain portion

[0037] 540b: Second drain portion

[0038] A - A’, B - B’: Cross-section

[0039] D1: First direction

[0040] D2: Second direction

[0041] D3: Third direction

[0042] t400, t502: Thickness

[0043] t1: First thickness

[0044] t2: Second thickness Detailed implementation manners

[0045] The semiconductor devices of the embodiments in the present disclosure are described in detail below. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific devices and arrangements described below are only for simply and clearly describing some embodiments of the present disclosure. Of course, these are only for illustration and not for limiting the present disclosure. In addition, similar and / or corresponding device symbols may be used in different embodiments to label similar and / or corresponding devices to clearly describe the present disclosure. However, the use of these similar and / or corresponding device symbols is only for simply and clearly describing some embodiments of the present disclosure, and does not represent any correlation between the different embodiments and / or structures discussed.

[0046] It should be understood that in each embodiment, relative terms may be used, for example, "lower" or "bottom" or "higher" or "top", to describe the relative relationship of one device in the figure to another device. It can be understood that if the device in the figure is flipped so that it is upside down, the device described on the "lower" side will become the device on the "higher" side. The embodiments of the present disclosure can be understood in conjunction with the figures, and the figures of the present disclosure are also regarded as part of the disclosure description.

[0047] Furthermore, when it is mentioned that a first material layer is on or over a second material layer, it may include the case where the first material layer is in direct contact with the second material layer, or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, when the first material layer is directly on the second material layer, it means that the first material layer is in direct contact with the second material layer.

[0048] In addition, it should be understood that the ordinal numbers such as "first", "second", etc. used in the specification and claims are used to modify the devices, and they do not themselves intend to imply that the device (or the plurality of devices) has any previous ordinal number, nor does it represent the order of one device and another device, or the order in the manufacturing method. The use of the plurality of ordinal numbers is only to clearly distinguish a device with a certain name from another device with the same name. The same terms may not be used in the claims and the specification. For example, the first device in the specification may be the second device in the claims.

[0049] In some embodiments of the present disclosure, terms related to joining and connection, such as "connect", "interconnect", "bond", etc., unless specifically defined, may refer to two structures in direct contact, or may also refer to two structures not in direct contact, with other structures disposed therebetween. And these terms related to connection and joining may also include cases where both structures are movable, or both structures are fixed. In addition, the term "electrically connected" or "electrically coupled" includes any direct and indirect means of electrical connection.

[0050] In the text, terms such as "approximate", "about", and "substantially" generally mean within 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% of a given value or range. The given quantity is an approximate quantity, that is, the meaning of "approximate", "about", and "substantially" may still be implied without specific mention of "approximate", "about", and "substantially". The term "ranging from a first value to a second value" or "the first value ~ the second value" means that the range includes the first value, the second value, and other values therebetween. Furthermore, there may be a certain error between any two values or directions being compared. If the first value is equal to the second value, it implies that there may be an error of about 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% between the first value and the second value.

[0051] It should be understood that certain terms are used throughout the specification and claims of the present disclosure to refer to specific devices. Those skilled in the art should understand that electronic device manufacturers may refer to the same device by different names. This document is not intended to distinguish devices with the same function but different names. In the following specification and claims, words such as "comprise", "contain", and "have" are open-ended words, and thus should be interpreted as meaning "including but not limited to...". Therefore, when the description of the present disclosure uses the terms "include", "contain", and / or "have", it specifies the existence of corresponding components, regions, steps, operations, and / or devices, but does not exclude the existence of one or more corresponding components, regions, steps, operations, and / or devices.

[0052] It should be understood that, without departing from the spirit of the present disclosure, components in multiple different embodiments can be replaced, recombined, and combined in the following examples to complete other embodiments. As long as the components between the embodiments do not violate the inventive spirit or conflict with each other, they can be arbitrarily combined and used.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this technology belongs. It is understood that these terms, for example, when defined in a commonly used dictionary, should be interpreted as having a meaning consistent with the relevant technology and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0054] In this disclosure, each direction is not limited to the three axes of the rectangular coordinate system, namely the X-axis, the Y-axis, and the Z-axis, and can be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other, but this is not limiting. For the sake of convenience of description, hereinafter, the X-axis direction is the first direction D1 (length direction), the Y-axis direction is the second direction D2 (width direction), and the Z-axis direction is the third direction D3 (thickness direction). In some embodiments, the top view schematic diagram described herein is a schematic diagram of observing the XY plane (the plane formed by the first direction D1 and the second direction D2), and the cross-sectional schematic diagram described herein is a schematic diagram of observing the XZ plane (the plane formed by the first direction D1 and the third direction D3). In some embodiments, the normal direction of the substrate described herein is the third direction D3.

[0055] Refer to Figure 1 , which is a top view schematic diagram of a semiconductor device 1 according to an embodiment of this disclosure. For the sake of convenience of description, Figure 1 some components may be omitted. As Figure 1 shown, the semiconductor device 1 may include a substrate 100, a gate electrode 500, a source electrode 520, and a drain electrode 540.

[0056] In some embodiments, the gate electrode 500 may include a first gate portion 500a and a second gate portion 500b connected to each other. In some embodiments, when observed in a top view, the gate electrode 500 may have an S-shaped structure. In some embodiments, the gate electrode 500 may include a straight portion and an arc portion. In some embodiments, the first gate portion 500a may include a plurality of straight portions and a plurality of first arc portions, and the second gate portion 500b may include a plurality of second arc portions. In some embodiments, one end of the straight portion may be connected to the first arc portion, and the other end of the straight portion may be connected to the second arc portion. In some embodiments, the radius of curvature of the second arc portion may be greater than the radius of curvature of the first arc portion.

[0057] In some embodiments, the source electrode 520 may include a first source portion 520a and a second source portion 520b connected to each other. In some embodiments, the first source portion 520a may extend along the second direction D2, and the second source portion 520b may extend along a first direction D1 different from the second direction D2. In some embodiments, a plurality of second source portions 520b may be connected to the same side of the first source portion 520a. In some embodiments, the source end portion 521 of the second source portion 520b away from the first source portion 520a may be close to the virtual center of the circle of the first arc portion of the first gate portion 500a. In some embodiments, the source end portion 521 may have an arc-shaped profile to make the electric field distribution more uniform.

[0058] In some embodiments, the drain electrode 540 may include a first drain portion 540a and a second drain portion 540b connected to each other. In some embodiments, the first drain portion 540a may extend along the second direction D2, and the second drain portion 540b may extend along the first direction D1. In some embodiments, the first drain portion 540a may be arranged in parallel with the first source portion 520a, and the gate electrode 500 may be arranged between the first drain portion 540a and the first source portion 520a. In some embodiments, a plurality of second drain portions 540b may be connected to the same side of the first drain portion 540a. In some embodiments, the drain end portion 541 of the second drain portion 540b away from the first drain portion 540a may be close to the virtual center of the circle of the second arc portion of the second gate portion 500b. In some embodiments, the drain end portion 541 may have an arc-shaped profile to make the electric field distribution more uniform. In some embodiments, the source electrode 520 and the drain electrode 540 may be finger electrodes respectively, and the finger portions of the source electrode 520 and the drain electrode 540 may be arranged corresponding to each other.

[0059] In some embodiments, the first gate portion 500a may be located between the second source portion 520b and the second drain portion 540b, and the second gate portion 500b may be located between the first source portion 520a and the second drain portion 540b. Since the gate electrode 500 is used to control whether the semiconductor device is turned on, and the source electrode 520 may be a ground terminal (but this disclosure is not limited thereto, and the drain electrode 540 may also be a ground terminal), the electric field often concentrates excessively at the drain electrode 540. Moreover, since the size of the drain end portion 541 of the drain electrode 540 is small and it is the boundary of the drain electrode 540, the electric field often concentrates excessively at the drain end portion 541 of the second drain portion 540b of the drain electrode 540.

[0060] Accordingly, in the present disclosure, by making the first threshold voltage (Vt1) of the first gate portion 500a less than the second threshold voltage (Vt2) of the second gate portion 500b, the second gate portion 500b is made less likely to be turned - on relative to the first gate portion 500a, thereby avoiding or reducing the generation of hot carriers at the drain end 541 of the second drain portion 540b. That is, the carrier concentration of the two - dimensional electron gas (2DEG) located under the first gate portion 500a is made greater than the carrier concentration of the two - dimensional electron gas located under the second gate portion 500b, and the second gate portion 500b is made less likely to be turned - on relative to the first gate portion 500a.

[0061] In some embodiments, the semiconductor device of the present disclosure may substantially include two high electron mobility transistors (HEMTs) electrically connected to each other. Among them, the two HEMTs may be respectively located in Figure 1 cross - section A - A' and cross - section B - B', and the combination of the two HEMTs may be as shown in Table 1. For example, Figure 1 cross - section A - A' may obtain a cross - section showing the flat region of the semiconductor device, and Figure 1 cross - section B - B' may obtain a cross - section showing the tip region of the semiconductor device.

[0062] Table 1

[0063]

[0064] In some embodiments, the HEMT may include depletion-mode HEMT (D mode HEMT); depletion-mode MIS-HEMT (depletion-mode metal-insulator-semiconductor high electron mobility transistor, D mode MIS-HEMT); enhancement-mode HEMT (E mode HEMT); enhancement-mode MIS-HEMT (enhancement-mode metal-insulator-semiconductor high electron mobility transistor, E mode MIS-HEMT). Among them, the threshold voltages of the depletion-mode HEMT and the depletion-mode MIS-HEMT are both less than 0, and the threshold voltage of the depletion-mode MIS-HEMT is less than that of the depletion-mode HEMT. Among them, the threshold voltages of the enhancement-mode HEMT and the enhancement-mode MIS-HEMT are both greater than 0, and the threshold voltage of the enhancement-mode MIS-HEMT is greater than that of the enhancement-mode HEMT. As shown in Table 1, in the above combination, the semiconductor structure including the first gate portion 500a shown in the cross-section A-A' has a first threshold voltage (Vt1), and the semiconductor structure including the second gate portion 500b shown in the cross-section B-B' has a second threshold voltage (Vt2). Among them, the second threshold voltage (Vt2) is greater than the first threshold voltage (Vt1) to make the electric field evenly distributed.

[0065] In some embodiments, a gate voltage (Vg) may be applied to the first gate portion 500a and the second gate portion 500b. It should be particularly noted that since the first gate portion 500a and the second gate portion 500b may be substantially different parts of the same gate electrode 500, the gate voltage (Vg) applied to the first gate portion 500a is the same as the gate voltage (Vg) applied to the second gate portion 500b. When the gate voltage is greater than or equal to the threshold voltage, the HEMT can be turned on. When the gate voltage is less than the threshold voltage, the HEMT is turned off. In addition, whether the depletion-mode HEMT and the depletion-mode MIS-HEMT are electrically connected to another transistor in the form of cascode or in the form of direct drive, the relationship that the second threshold voltage (Vt2) is greater than the first threshold voltage (Vt1) can be satisfied in both the on state and the off state.

[0066] Furthermore, the enhancement-mode HEMT and the enhancement-mode MIS-HEMT also satisfy the relationship that the second threshold voltage (Vt2) is greater than the first threshold voltage (Vt1) in both the on-state and the off-state. Among them, when the gate voltage (Vg) > the second threshold voltage (Vt2) > the first threshold voltage (Vt1), the hot carriers in the second gate portion 500b can be reduced. Among them, when the second threshold voltage (Vt2) > the gate voltage (Vg) > the first threshold voltage (Vt1), the hot carriers at the drain end 541 can be substantially absent or less.

[0067] For the sake of illustration, hereinafter Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A and Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B show the two-dimensional electron gas distribution when the gate voltage is 0 (Vg = 0).

[0068] Referring to Figure 2A and Figure 2B , which are respectively cross-sectional schematic diagrams of the semiconductor device 1 according to an embodiment of the present disclosure. Among them, the semiconductor device 1 can be regarded as electrically connecting the semiconductor structures shown in the cross-sections A-A' and B-B' to each other to form the overall semiconductor device 1.

[0069] As Figure 2A and Figure 2BAs shown, in some embodiments, a substrate 100 may be provided. In some embodiments, the substrate 100 may include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor-on-insulator substrate includes a semiconductor layer formed on an insulator. For example, the insulating layer may include silicon oxide, silicon nitride, poly-silicon, or a combination thereof, and the semiconductor substrate may include silicon, aluminum nitride (AlN), or the like. The substrate 100 may be an undoped or doped substrate, such as a substrate doped with a p-type or n-type dopant. In some embodiments, the substrate 100 may include a multi-layered substrate or a gradient substrate. In some embodiments, the substrate 100 may include a semiconductor substrate or a ceramic substrate, such as a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, an aluminum nitride substrate, or a sapphire substrate. In some embodiments, the substrate 100 may be a silicon substrate.

[0070] As Figure 2A and Figure 2B shown, in some embodiments, a buffer layer 200 may be formed on the substrate 100 to improve the compatibility between the substrate 100 and other devices disposed on the substrate 100, such as reducing the difference in thermal expansion coefficients and / or reducing the difference in lattice constants. In some embodiments, the buffer layer 200 may include a group III-V compound semiconductor material, such as a group III nitride. For example, the buffer layer 200 may include gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), the like, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the buffer layer 200 may be formed by a deposition process. For example, the deposition process may be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), a similar process, or a combination thereof, but the present disclosure is not limited thereto.

[0071] In some embodiments, a nucleation layer may be further disposed between the substrate 100 and the buffer layer 200 to reduce the lattice difference between the substrate 100 and other layers disposed on the substrate 100, thereby improving the epitaxial quality and reliability. In some embodiments, the nucleation layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), analogs thereof, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the nucleation layer may be formed by a deposition process. In other embodiments, the buffer layer 200 may be omitted.

[0072] As Figure 2A and Figure 2B shown, in some embodiments, a channel layer 300 may be formed on the substrate 100. Specifically, the channel layer 300 may be formed on the buffer layer 200. In some embodiments, the channel layer 300 may include a III-V compound semiconductor material, such as a group III nitride, but the present disclosure is not limited thereto. For example, the channel layer 300 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum gallium nitride (InAlGaN), analogs thereof, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the channel layer 300 may be gallium nitride. In some embodiments, the channel layer 300 may be formed by a deposition process.

[0073] As Figure 2A and Figure 2B shown, in some embodiments, a barrier layer 400 may be formed on the channel layer 300. In some embodiments, the barrier layer 400 may include a III-V compound semiconductor material, such as a group III nitride, but the present disclosure is not limited thereto. For example, the barrier layer may include aluminum nitride (AlN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium aluminum gallium nitride (InAlGaN), analogs thereof, or combinations thereof, but the present disclosure is not limited thereto. In some embodiments, the barrier layer 400 may be aluminum gallium nitride. In some embodiments, the barrier layer 400 may be formed by a deposition process. Since there is a heterointerface between the channel layer 300 and the barrier layer 400, and there is a difference in lattice constant between the channel layer 300 and the barrier layer 400, a two-dimensional electron gas (2DEG) 301 may be formed near the top surface of the channel layer 300 and serve as a current path.

[0074] As Figure 2A and Figure 2BAs shown, in some embodiments, a gate electrode 500 may be formed on a barrier layer 400, and the gate electrode 500 may include a first gate portion 500a and a second gate portion 500b. In some embodiments, the gate electrode 500 may include a conductive material. For example, the conductive material may include a metal, a metal nitride, a semiconductor material, an analog thereof, or a combination thereof, but the present disclosure is not limited thereto. The metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), an analog thereof, or a combination thereof, but the present disclosure is not limited thereto. The semiconductor material may include polysilicon or polycrystalline germanium. The conductive material may be formed by chemical vapor deposition, sputtering, resistance heating evaporation, electron beam evaporation, an analog process, or a combination thereof, but the present disclosure is not limited thereto. In some embodiments, the materials of the first gate portion 500a and the second gate portion 500b are the same as each other and are formed in the same process.

[0075] As Figure 2A and Figure 2B shown, in some embodiments, the first gate portion 500a may be in direct contact with the barrier layer 400, and the second gate portion 500b may also be in direct contact with the barrier layer 400. In some embodiments, the bottom surface of the first gate portion 500a may be flush with the top surface of the barrier layer 400, and the bottom surface of the second gate portion 500b may be lower than the top surface of the barrier layer 400.

[0076] In some embodiments, a source electrode 520 may be formed on the barrier layer 400. The material and formation method of the source electrode 520 may be the same as or different from those of the gate electrode 500. In some embodiments, a drain electrode 540 may be formed on the barrier layer 400. The material and formation method of the drain electrode 540 may be the same as or different from those of the gate electrode 500. Thus, a semiconductor device 1 may be obtained.

[0077] As Figure 2A and Figure 2B shown, in some embodiments, in a third direction D3, the barrier layer 400 may have a thickness t400. In some embodiments, a first thickness t1 of the barrier layer 400 located below the first gate portion 500a may be greater than a second thickness t2 of the barrier layer 400 located below the second gate portion 500b. In some embodiments, the first thickness t1 may be substantially the same as the thickness t400, and the second thickness t2 may be less than the thickness t400. Thus, the two-dimensional electron gas below the first gate portion 500a may be continuous, and the two-dimensional electron gas below the second gate portion 500b may be discontinuous, i.e., depleted.

[0078] Accordingly, in the semiconductor device 1, the semiconductor structure including the first gate portion 500a is a depletion-type HEMT (Vt1 < 0), the semiconductor structure including the second gate portion 500b is an enhancement-type HEMT (Vt2 > 0), and Vt2 > Vt1 is satisfied, so that the electric field distribution is more uniform, the reliability is improved, and / or the deterioration of the semiconductor device is avoided.

[0079] Hereinafter, the same or similar device symbols and descriptions are omitted. In addition, the subsequent Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A respectively show cross-sectional schematic diagrams of the semiconductor devices 2 to 7 obtained along the Figure 1 shown cross-section A-A', and Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B respectively show cross-sectional schematic diagrams of the semiconductor devices 2 to 7 obtained along the Figure 1 shown cross-section B-B'. The semiconductor devices 2 to 7 can be respectively regarded as electrically connecting the semiconductor structures shown in the cross-sections A-A' and B-B' to each other, and as the overall semiconductor devices 2 to 7.

[0080] Referring to Figure 3A and Figure 3B , which are respectively cross-sectional schematic diagrams of the semiconductor device 2 according to an embodiment of the present disclosure. Among them, Figure 3A the shown semiconductor structure can be substantially the same as Figure 2A . As Figure 3A and Figure 3B shown, in some embodiments, the semiconductor device 2 may include an adjustment structure disposed below the second gate portion 500b to adjust the distribution of the two-dimensional electron gas. In some embodiments, when viewed from a top view, the shape of the adjustment structure may correspond to the shape of the second gate portion 500b. In some embodiments, the projection range of the adjustment structure on the substrate 100 may be substantially the same as the projection range of the second gate portion 500b on the substrate 100.

[0081] As Figure 3BAs shown, in some embodiments, the first compound semiconductor layer 501 can serve as an adjustment structure and can be disposed between the second gate portion 500b and the blocking layer 400. In some embodiments, the first compound semiconductor layer 501 can be formed by a deposition process, and the first compound semiconductor layer 501 can be a compound semiconductor material doped with p-type dopants. For example, the first compound semiconductor layer 501 can include p-type doped gallium nitride (p-GaN). Accordingly, since the first compound semiconductor layer 501 can inhibit the formation of the two-dimensional electron gas 301 at the position corresponding to the first compound semiconductor layer 501, the two-dimensional electron gas is depleted. For example, the first compound semiconductor layer 501 can inhibit the two-dimensional electron gas 301 located below (as shown in Figure 3B shown) or above (as shown in Figure 4B shown) the first compound semiconductor layer 501. Therefore, the semiconductor device can be in a normally-off state. In some embodiments, the depletion range of the two-dimensional electron gas 301 can correspond to the projection range of the first compound semiconductor layer 501 on the two-dimensional electron gas 301.

[0082] Accordingly, in the semiconductor device 2, the semiconductor structure including the first gate portion 500a is a depletion-mode HEMT (Vt1 < 0), the semiconductor structure including the second gate portion 500b is an enhancement-mode HEMT (Vt2 > 0), and Vt2 > Vt1 is satisfied, so that the electric field distribution is more uniform, the reliability is improved, and / or the deterioration of the semiconductor device is avoided.

[0083] Referring to Figure 4A and Figure 4B , which are respectively cross-sectional schematic views of a semiconductor device 3 according to an embodiment of the present disclosure. Among them, Figure 4A the shown semiconductor structure can be substantially the same as Figure 2A . As shown in Figure 4A and Figure 4B , in some embodiments, the semiconductor device 3 can include an adjustment structure disposed below the second gate portion 500b to adjust the distribution of the two-dimensional electron gas 301. As shown in Figure 4B , in some embodiments, the first compound semiconductor layer 501 can be disposed in the channel layer 300. Accordingly, in the semiconductor device 3, the semiconductor structure including the first gate portion 500a is a depletion-mode HEMT (Vt1 < 0), the semiconductor structure including the second gate portion 500b is an enhancement-mode HEMT (Vt2 > 0), and Vt2 > Vt1 is satisfied, so that the electric field distribution is more uniform, the reliability is improved, and / or the deterioration of the semiconductor device is avoided.

[0084] Referring to Figure 5A and Figure 5B, which are respectively cross-sectional schematic diagrams of a semiconductor device 4 according to an embodiment of the present disclosure. Among them, Figure 5A The semiconductor structure shown may be substantially the same as Figure 2A the same. As Figure 5A and Figure 5B shown, in some embodiments, the semiconductor device 4 may include an adjustment structure disposed below the second gate portion 500b to adjust the distribution of the two-dimensional electron gas. As Figure 5B shown, in some embodiments, the second compound semiconductor layer 502 may serve as the adjustment structure and may be disposed between the second gate portion 500b and the barrier layer 400. In some embodiments, the second compound semiconductor layer 502 may be disposed at the top surface of the barrier layer 400. In some embodiments, the second compound semiconductor layer 502 may include halogen-doped compound semiconductors. In some embodiments, the halogen element may include fluorine (F), chlorine (Cl), bromine (Br), iodine (I), or a combination thereof. In some embodiments, the second compound semiconductor layer 502 may be a fluorine-doped compound semiconductor. In some embodiments, since the barrier layer 400 may include aluminum gallium nitride, the second compound semiconductor layer 502 may include fluorine-doped aluminum gallium nitride (F doped AlGaN).

[0085] In some embodiments, in the third direction D3, the second compound semiconductor layer 502 may have a thickness t502. In some embodiments, the thickness t502 may be greater than 0 and less than or equal to the thickness t400. In other words, the second compound semiconductor layer 502 may penetrate the barrier layer 400 to contact the channel layer 300, or the second compound semiconductor layer 502 may not penetrate the barrier layer 400 and be spaced apart from the channel layer 300.

[0086] Since the second compound semiconductor layer 502 can provide holes and the carriers in the channel region are electrons (i.e., the electrons in the two-dimensional electron gas 301), the electrons in the channel region can be neutralized by the holes provided by the second compound semiconductor layer 502, thereby depleting the carriers in the channel region. Therefore, the electric field distribution can be made more uniform by providing a material that provides holes.

[0087] Accordingly, in the semiconductor device 4, the semiconductor structure including the first gate portion 500a is a depletion-type HEMT (Vt1 < 0), the semiconductor structure including the second gate portion 500b is an enhancement-type HEMT (Vt2 > 0), and Vt2 > Vt1 is satisfied, thereby making the electric field distribution more uniform, improving the reliability, and / or avoiding the deterioration of the semiconductor device.

[0088] Referring to Figure 6A andFigure 6B , which are respectively cross-sectional schematic diagrams of a semiconductor device 5 according to an embodiment of the present disclosure. As Figure 6A and Figure 6B shown, in some embodiments, an insulating layer 503 may be disposed between the barrier layer 400 and the first gate portion 500a to adjust the distance between the conduction band and the Fermi level. In some embodiments, the insulating layer 503 is not disposed between the barrier layer 400 and the second gate portion 500b. In some embodiments, the bottom surface of the first gate portion 500a may be higher than the top surface of the barrier layer 400. In some embodiments, the second gate portion 500b may be in direct contact with the barrier layer 400.

[0089] Accordingly, in the semiconductor device 5, the semiconductor structure including the first gate portion 500a is a depletion-type MIS-HEMT (Vt1 < 0), the semiconductor structure including the second gate portion 500b is a depletion-type HEMT (Vt2 < 0), and Vt2 > Vt1 is satisfied, so that the electric field distribution is more uniform, the reliability is improved, and / or the deterioration of the semiconductor device is avoided.

[0090] Referring to Figure 7A and Figure 7B , which are respectively cross-sectional schematic diagrams of a semiconductor device 6 according to an embodiment of the present disclosure. As Figure 7A and Figure 7B shown, in some embodiments, in the third direction D3, the barrier layer 400 may have a thickness t400. In some embodiments, a first thickness t1 of the barrier layer 400 under the first gate portion 500a may be greater than a second thickness t2 of the barrier layer 400 under the second gate portion 500b. In some embodiments, the thickness t400 may be greater than the first thickness t1 and the second thickness t2. Therefore, when the two-dimensional electron gas 301 under the first gate portion 500a and the second gate portion 500b are both discontinuous, the carrier concentration of the two-dimensional electron gas 301 under the first gate portion 500a can still be greater than the carrier concentration of the two-dimensional electron gas 301 under the second gate portion 500b.

[0091] Accordingly, in the semiconductor device 6, the semiconductor structure including the first gate portion 500a is an enhancement-type HEMT (Vt1 > 0), the semiconductor structure including the second gate portion 500b is an enhancement-type HEMT (Vt2 > 0), and Vt2 > Vt1 is satisfied, so that the electric field distribution is more uniform, the reliability is improved, and / or the deterioration of the semiconductor device is avoided.

[0092] Referring to Figure 8A and Figure 8B , which are respectively cross-sectional schematic diagrams of a semiconductor device 7 according to an embodiment of the present disclosure. AsFigure 8A and Figure 8B As shown in Figure 8B , in some embodiments, the insulating layer 503 may be disposed between the blocking layer 400 and the second gate portion 500b. In some embodiments, the bottom surface of the first gate portion 500a and the bottom surface of the second gate portion 500b may be lower than the top surface of the blocking layer 400. In some embodiments, the insulating layer 503 may not be disposed between the blocking layer 400 and the first gate portion 500a.

[0093] Accordingly, in the semiconductor device 7, the semiconductor structure including the first gate portion 500a is an enhancement-mode HEMT (Vt1>0), the semiconductor structure including the second gate portion 500b is an enhancement-mode MIS-HEMT (Vt2>0), and Vt2>Vt1 is satisfied, so that the electric field distribution is more uniform, the reliability is improved, and / or the deterioration of the semiconductor device is avoided.

[0094] In some embodiments, a further process may be performed on any one of the semiconductor devices 1-7 to form a power device array. In some embodiments, the semiconductor devices 1-7 disclosed herein may be used in any combination. In some embodiments, the top view of the semiconductor device may be combined with the cross-sectional view of the semiconductor device arbitrarily.

[0095] Accordingly, the present disclosure adjusts the electric field distribution in the semiconductor device by making the first threshold voltage of the first gate portion less than the second threshold voltage of the second gate portion. For example, in the top view, there is a problem that the electric field intensity is too high and overly concentrated at the tip of the drain electrode (for example, the second drain portion), resulting in an overly high concentration of hot carriers at the tip of the drain electrode. Therefore, the present disclosure enables two portions in the gate electrode to have different threshold voltages, which can reduce the over-concentration of the electric field distribution and reduce hot carriers, making the electric field distribution more uniform, improving the reliability, and / or avoiding the deterioration of the semiconductor device.

[0096] Specifically, in the case where the first gate portion may be disposed between the second source portion and the second drain portion, and the second gate portion may be disposed between the first source portion and the second drain portion, the threshold voltage may be adjusted by adjusting the two-dimensional electron gas concentration below the first gate portion and below the second gate portion. For example, the threshold voltages of the first gate portion and the second gate portion may be adjusted by adjusting the combination of the types of HEMTs (depletion-mode HEMT, depletion-mode MIS-HEMT, enhancement-mode HEMT, enhancement-mode MIS-HEMT). For example, the types of HEMTs may be adjusted by adjusting the blocking layer thickness, providing an adjustment structure, providing an insulating layer, etc.

[0097] The protection scope of the present disclosure is not limited to the processes, machines, manufactures, compositions of matter, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand from the disclosure content of the present disclosure the processes, machines, manufactures, compositions of matter, devices, methods and steps developed currently or in the future. As long as they can implement substantially the same functions or achieve substantially the same results in the embodiments described herein, they can be used according to the present disclosure. Therefore, the protection scope of the present disclosure includes the aforementioned processes, machines, manufactures, compositions of matter, devices, methods and steps. Any embodiment or claim of the present disclosure does not have to achieve all the purposes, advantages and / or features described in the present disclosure.

[0098] The above outlines several embodiments so that those skilled in the art to which the present disclosure pertains can better understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure pertains should understand that they can design or modify other processes and structures based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments herein. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and replacements without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A channel layer disposed on the substrate; A blocking layer disposed on the channel layer; A gate electrode disposed on the blocking layer and including a first gate portion and a second gate portion connected to each other; A source electrode disposed on the blocking layer; and A drain electrode disposed on the blocking layer, wherein a first threshold voltage of the first gate portion between the source electrode and the drain electrode is less than a second threshold voltage of the second gate portion between the source electrode and the drain electrode.

2. The semiconductor device according to claim 1, wherein, The carrier concentration of the two-dimensional electron gas below the first gate portion is greater than the carrier concentration of the two-dimensional electron gas below the second gate portion.

3. The semiconductor device according to claim 1, characterized in that, The source electrode includes: A first source portion extending along a first direction; and A second source portion connected to the first source portion and extending along a second direction different from the first direction, and The first gate portion is located between the second source portion and the drain electrode, and The second gate portion is located between the first source portion and the gate electrode.

4. The semiconductor device according to claim 3, wherein, The drain electrode includes: A first drain portion extending along the first direction; and A second drain portion connected to the first drain portion and extending along the second direction, and The first gate portion is located between the second source portion and the second drain portion, and The second gate portion is located between the first source portion and the second drain portion.

5. The semiconductor device according to claim 1, wherein, A first thickness of the blocking layer below the first gate portion is greater than a second thickness of the blocking layer below the second gate portion.

6. The semiconductor device according to claim 1, wherein, Further comprising: An adjustment structure disposed below the second gate portion and including a P-type doped compound semiconductor or a halogen-doped compound semiconductor, wherein the first gate portion contacts the blocking layer.

7. The semiconductor device according to claim 1, characterized in that, Further comprising: An insulating layer disposed between the blocking layer and the first gate portion, wherein the second gate portion contacts the blocking layer.

8. The semiconductor device according to claim 7, wherein, The bottom surface of the first gate portion is higher than the top surface of the blocking layer.

9. The semiconductor device according to claim 1, wherein, Further comprising: An insulating layer disposed between the blocking layer and the second gate portion, wherein the bottom surface of the first gate portion is lower than the top surface of the blocking layer.

10. A method for forming a semiconductor device, characterized in that Comprising: Providing a substrate; Forming a channel layer on the substrate; Forming a blocking layer on the channel layer; Forming a gate electrode on the blocking layer, and wherein the gate electrode includes a first gate portion and a second gate portion connected to each other; Forming a source electrode on the blocking layer; and Forming a drain electrode on the blocking layer, wherein a first threshold voltage of the first gate portion between the source electrode and the drain electrode is less than a second threshold voltage of the second gate portion between the source electrode and the drain electrode.

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